Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a semiconductor layer and a gate structure located on the upper surface of the semiconductor layer, the gate structure comprises a gate dielectric layer and a gate electrode which are sequentially arranged in a stacked mode, the semiconductor layer comprises a drift region extending into the semiconductor layer from the upper surface of the semiconductor layer, and the drift region is of a first doping type; a well region is arranged in the drift region, the well region extends into the drift region from the upper surface of the drift region, and the well region has a second doping type opposite to the first doping type; a first doped region is arranged in the well region, the first doped region extends into the well region from the upper surface of the well region, and the first doped region has a first doping type; the semiconductor structure further comprises a dummy gate structure, and the dummy gate structure is at least partially located in the well region and comprises a dummy gate which is equipotential with the gate; and the dummy gate dielectric layer wraps the dummy gate to at least isolate the dummy gate from the well region. The on resistance or saturation voltage drop of the semiconductor structure is reduced by arranging the dummy gate structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] The on-resistance (RDSon) is the resistance between the drain D and the source S of the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) in the on state, and its size directly affects the conduction loss and efficiency of the MOSFET. The saturation voltage drop (VCESAT) is the voltage difference between the collector C and the emitter E of the IGBT (Insulated Gate Bipolar Transistor) in the on state. For application scenarios that require high efficiency and low loss, MOSFETs with low on-resistance and IGBTs with low saturation voltage drop are required to ensure the efficiency and reliability of power electronic equipment. To this end, how to reduce the on-resistance of MOSFET and the saturation voltage drop of IGBT has always been the focus of research and development in the industry.

[0003] For planar gate MOSFET, refer to Figure 1A A planar gate MOSFET refers to a MOSFET in which the gate 140 is a planar structure and is located on the surface of the semiconductor layer 120 (specifically, the upper surface of the drift region 122). Figure 1A In the example of a vertically conductive planar gate MOSFET, the current flows vertically upward from the bottom of the wafer, passing through the drain 110, the substrate 121, the drift region 122, the channel region located in the well region 123, and the source region 124 to reach the source 130. Accordingly, Figure 1B As shown, along the direction of current flow, the on-resistance RDSon of the planar gate MOSFET includes the drain contact resistance R CD , substrate resistance R SUB , drift region resistance R D , JFET region resistance R JFET , accumulation resistance R A , channel resistance R CH , source resistance R N+ And the source contact resistance R CS Among them, the drift region resistance R D and the JFET region resistance R JFET The proportion of the on-resistance RDSon is as high as more than 90%, so the purpose of reducing the on-resistance RDSon can be achieved by reducing at least one of the two resistances.

[0004] Both theory and practice show that the drift region resistance R of a planar gate MOSFETD and the JFET region resistance R JFET The reduction of on-resistance can be achieved by changing the doping concentration of the corresponding area. However, the change of doping concentration in the drift region will cause the source-drain voltage to change, and the degree of change of on-resistance by adjusting the doping concentration in the JFET region is limited. Both methods are difficult to achieve effective reduction of on-resistance. Similarly, for planar gate IGBTs, it is also difficult to achieve effective reduction of saturation voltage drop by simply adjusting the doping concentration.

[0005] Therefore, a new semiconductor structure is still needed to effectively reduce the on-resistance RDSon of the planar gate MOSFET or the saturation voltage drop VCESAT of the planar gate IGBT.

[0006] Invention

[0007] In view of the above problems, an object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which can effectively reduce the on-resistance or saturation voltage drop of the semiconductor structure.

[0008] According to one aspect of the present invention, a semiconductor structure is provided, comprising: a semiconductor layer and a gate structure located on the upper surface of the semiconductor layer, the gate structure comprising a gate dielectric layer and a gate electrode stacked in sequence on the upper surface of the semiconductor layer, the semiconductor layer comprising a drift region extending from the upper surface of the semiconductor layer to the semiconductor layer, the drift region having a first doping type; a well region is provided in the drift region, the well region extends from the upper surface of the drift region to the drift region, the well region has a second doping type opposite to the first doping type; a first doping region is provided in the well region, the first doping region extends from the upper surface of the well region to the well region, the first doping region has the first doping type; wherein the semiconductor structure further comprises a dummy gate structure, the dummy gate structure is at least partially located in the well region, and comprises: a dummy gate having the same potential as the gate electrode; and a dummy gate dielectric layer wrapping the dummy gate to at least isolate the dummy gate from the well region.

[0009] Optionally, the pseudo-gate structure includes a first part and a second part that are connected, wherein: the first part extends downward from the upper surface of the well region into the well region, the first doped region is provided on the outside of the first part, the second part is located below the first part and extends laterally to between the lower surface of the first doped region and the lower surface of the well region, and the second part is not in direct contact with the lower surface of the well region.

[0010] Optionally, an edge of the second portion extending in the lateral direction exceeds an edge of the first doped region thereover and does not exceed a space charge region of the well region.

[0011] Optionally, the second portion extends laterally to between the first doped region above it and the adjacent edges of the well region; or, the second portion extends laterally to directly contact the edge of the adjacent well region and does not extend beyond the well region; or, the second portion extends laterally to beyond the well region but does not extend beyond the space charge region of the well region.

[0012] Optionally, the gate is electrically connected to the dummy gate; and / or the withstand voltage of the gate dielectric layer is less than or equal to the withstand voltage of the dummy gate dielectric layer.

[0013] Optionally, it also includes a second doping region, which extends from the upper surface of the semiconductor layer to the well region, and the second doping region is located between the first doping region and the pseudo-gate structure, the second doping region has the second doping type, and the doping concentration of the second doping region is greater than the doping concentration of the well region.

[0014] Optionally, the semiconductor structure is a planar gate metal oxide semiconductor field effect transistor, and the first doped region is a source region; the semiconductor layer also includes a substrate stacked with the drift region, and the substrate has the same doping type as the drift region; or, the semiconductor structure is a planar gate insulated gate bipolar transistor, the first doped region is an emitter region, and the semiconductor layer also includes a collector region stacked with the drift region, and the collector region has the second doping type.

[0015] According to another aspect of the present invention, a method for preparing a semiconductor structure is provided, comprising: forming a well region in a drift region of a semiconductor layer, wherein the drift region extends from the upper surface of the semiconductor layer into the semiconductor layer, the drift region has a first doping type, the well region extends from the upper surface of the drift region into the drift region, and the well region has a second doping type opposite to the doping type of the drift region; forming a first doping region in the well region, the first doping region extends from the upper surface of the well region into the well region, and the first doping region has the first doping type; forming a dummy gate structure, the dummy gate structure is at least partially located in the well region, the dummy gate structure includes a dummy gate and a dummy gate dielectric layer, wherein the dummy gate dielectric layer wraps the dummy gate to at least isolate the dummy gate from the well region; forming a gate structure on the upper surface of the semiconductor layer, the gate structure includes a gate dielectric layer and a gate arranged in a stacked manner, and the gate and the dummy gate have the same potential.

[0016] Optionally, the step of forming the pseudo gate structure includes: forming a first trench in the well region, the first trench extending downward from the upper surface of the well region into the well region, and the depth of the first trench is greater than the depth of the first doped region; the outer side of the first trench is the first doped region; forming a second trench at the bottom of the first trench, the second trench extending laterally to between the lower surface of the first doped region and the lower surface of the well region, and not directly contacting the lower surface of the first doped region, the first trench and the second trench forming a trench; forming a first insulating material layer inside the trench, and making the first insulating material A layer covers the upper surface of the drift region; a conductive material layer is filled in the groove, and the conductive material layer covers the first insulating material layer located on the upper surface of the drift region; the conductive material layer is patterned so that the conductive material layer in the groove forms the pseudo gate, and the conductive material layer located on the upper surface of the drift region forms the gate, wherein at least a portion of the upper surface of the pseudo gate is lower than the upper surface of the semiconductor layer; and a second insulating material layer is formed to cover the upper surface of the conductive material layer in the groove, and the first insulating material layer and the second insulating material layer located in the groove form the pseudo gate dielectric layer.

[0017] Optionally, an edge of the second trench extending in the lateral direction exceeds an edge of the first doped region thereover and does not exceed a space charge region of the well region.

[0018] Optionally, the second trench extends laterally to between the first doped region and the adjacent edges of the well region above it; or, the second trench extends laterally to directly contact the edge of the adjacent well region and does not extend beyond the well region; or, the second trench extends laterally to exceed the well region but does not extend beyond the space charge region of the well region.

[0019] Optionally, the graphic processing also forms an ion implantation window, and the ion implantation window corresponds to a portion of the upper surface of the semiconductor layer located between the first doping region and the groove. The preparation method also includes: performing ion implantation through the ion implantation window to form a second doping region between the first doping region and the groove, the second doping region having the second doping type, and the doping concentration of the second doping region is higher than the doping concentration of the well region.

[0020] Optionally, the conductive material layer is patterned so that part of the surface of the conductive material layer located in the groove is lower than the upper surface of the semiconductor layer, and another part of the surface is higher than the upper surface of the semiconductor layer, so as to maintain connection with the conductive material layer located on the upper surface of the drift region, thereby realizing electrical connection between the gate and the dummy gate.

[0021] According to the semiconductor structure and preparation method thereof provided by the present invention, a dummy gate structure is added in the well region, wherein the dummy gate has the same potential as the gate. Thus, when voltage is applied to the gate and the dummy gate at the same time, the dummy gate forms a capacitor with the JFET region and induces a large number of carriers, thereby reducing the resistance of the JFET region, thereby reducing the on-resistance RDSon or the saturation voltage drop VCESAT of the semiconductor structure.

[0022] Furthermore, by controlling the position and size of the pseudo-gate structure, especially the relative position relationship between the pseudo-gate structure and the edge of the well region, it is possible to further reduce the on-resistance or saturation voltage drop while avoiding affecting other electrical parameters of the semiconductor device using this structure, which is more conducive to adapting to high-efficiency, low-loss application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the description of the embodiments of the present invention with reference to the following drawings, in which:

[0024] Figure 1A The schematic structure diagram of the existing planar gate MOSFET and the current flow direction when the device is turned on are shown;

[0025] Figure 1B Shows Figure 1A The schematic diagram of the equivalent resistance structure of the planar gate MOSFET is shown;

[0026] Figure 2A A schematic structural diagram showing a semiconductor structure according to a first embodiment of the present invention;

[0027] Figure 2B A schematic structural diagram showing a well region in a semiconductor structure according to a first embodiment of the present invention;

[0028] Figure 3A A schematic structural diagram showing a semiconductor structure according to a second embodiment of the present invention;

[0029] Figure 3B A schematic structural diagram showing a well region in a semiconductor structure according to a second embodiment of the present invention;

[0030] Figure 4A A schematic structural diagram showing a semiconductor structure according to a third embodiment of the present invention;

[0031] Figure 4B A schematic structural diagram showing a well region in a semiconductor structure according to a third embodiment of the present invention;

[0032] Figure 5 The simulated volt-ampere characteristic curves of different embodiments of the present invention are shown;

[0033] 6A to 6HThe cross-sectional views at various stages of the method for preparing the semiconductor structure of the present invention are shown. DETAILED DESCRIPTION

[0034] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements, components and regions are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0035] In addition, it should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations, nor do they represent the number of entities or operations. Unless otherwise specified, "contact" in this article can be direct contact or indirect contact.

[0036] An embodiment of the present invention provides a semiconductor structure, which includes a semiconductor layer and a gate structure. The semiconductor layer includes a relative upper surface (commonly known as the "front side" in the industry) and a lower surface (commonly known as the "back side" in the industry). The gate structure is located on the upper surface of the semiconductor layer, wherein the gate structure includes a gate dielectric layer located on the upper surface of the semiconductor layer and a gate located on the gate dielectric layer. That is, the semiconductor structure provided by the embodiment of the present invention is a planar gate semiconductor structure. For ease of description below, the upper and lower surfaces of other parts of the semiconductor structure or each region in the semiconductor layer will be determined according to the relative positional relationship between the upper and lower surfaces of the semiconductor layer, and will not be specifically explained below.

[0037] The semiconductor layer includes a drift region, which extends from the upper surface of the semiconductor layer into the semiconductor layer and has a first doping type. A well region is provided in the drift region, which extends from the upper surface of the drift region into the drift region and has a second doping type. A first doping region is provided in the well region, which extends from the upper surface of the well region into the well region and has a first doping type. The first doping type is opposite to the second doping type, specifically, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.

[0038] It should be understood that the semiconductor structure provided in the embodiment of the present invention can eventually form a planar gate MOSFET device such as a vertical conductive MOSFET, a super junction MOSFET, or a planar gate IGBT device.

[0039] For a planar gate MOSFET, the first doped region is a source region, the semiconductor layer further includes a substrate stacked with the drift region, and the lower surface of the substrate is the lower surface of the semiconductor layer. The drift region may be an epitaxial layer formed on the surface of the substrate, that is, the semiconductor layer includes the substrate and the epitaxial layer. In practice, the semiconductor layer may be an epitaxial wafer. The substrate has a first doping type, and generally the doping concentration of the substrate is higher than the doping concentration of the drift region.

[0040] For a planar gate IGBT, the first doped region is an emitter region. The semiconductor layer also includes a collector region stacked with the drift region, and the lower surface of the collector region is the lower surface of the semiconductor layer. The collector region has a second doping type. The collector region can be a semiconductor substrate that meets the conductive requirements, or it can be formed by inverting ion implantation on the lower surface of the semiconductor layer. In addition, it is also possible to choose whether to set a buffer zone between the collector region and the drift region according to the product requirements of the IGBT.

[0041] The semiconductor structure provided by the embodiment of the present invention also includes a dummy gate structure, and the dummy gate structure can be partially or completely located in the well region. The dummy gate structure specifically includes a dummy gate having a potential equal to that of the gate and a dummy gate dielectric layer wrapping the dummy gate. By setting the dummy gate structure, the on-resistance RDSon of the planar gate MOSFET or the saturation voltage drop VCESAT of the planar gate IGBT is effectively reduced.

[0042] To facilitate understanding of the semiconductor structure and the pseudo-gate structure in the semiconductor structure provided by the present invention, a vertical conductive planar gate MOSFET (VDMOSFET) is taken as an example for further explanation. In order to more clearly indicate the relative positional relationship between the regions, in the following description, the X direction or the opposite direction of the X direction in each cross-sectional view is referred to as the horizontal direction, and the Y direction or the opposite direction of the Y direction is referred to as the vertical direction. Among them, in each embodiment of the present invention, the arrangement direction of multiple well regions in the semiconductor structure is the above-mentioned horizontal direction, and the direction between the upper and lower surfaces of any region is the above-mentioned vertical direction.

[0043] Figure 2A A schematic structural diagram of a semiconductor structure according to a first embodiment of the present invention is shown. Figure 2A The semiconductor structure of the first embodiment of the present invention includes: a semiconductor layer 200, a gate structure 10, a source metal layer (not shown in the figure) and a drain metal layer (not shown in the figure).

[0044] The gate structure 10 is located on the upper surface of the semiconductor layer 200, and includes a gate 11 and a gate dielectric layer 12 isolating the gate 11 from the semiconductor layer 200. The gate 11 is a conductive material, such as doped polysilicon or metal. The gate dielectric layer 12 is an insulating material, such as silicon oxide or silicon nitride. In addition, the gate dielectric layer 12 can be a single-layer structure or a multi-layer structure. It should be understood that the gate structure 10 can be any planar gate structure in the prior art, and the present invention does not make too many restrictions, and the gate structure will not be explained and restricted in detail below.

[0045] Continue to refer Figure 2A The semiconductor layer 200 includes a substrate 210 and a drift region 220 , wherein a plurality of well regions 230 are disposed in the drift region 220 , and a first doped region, namely a source region 231 , is disposed in the well region 230 .

[0046] Specifically, the lower surface of the substrate 210 is the lower surface of the semiconductor layer 200, and the upper surface of the drift region 220 is the upper surface of the semiconductor layer 200. The substrate 210 can be a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, and in particular a semiconductor substrate for preparing a semiconductor power device. The drift region 220 is, for example, an epitaxial layer formed on the upper surface of the substrate 210 by an epitaxial process. Both the substrate 210 and the drift region 220 have a first doping type, and generally the doping concentration of the substrate 210 is greater than the doping concentration of the drift region 220.

[0047] The well region 230 extends from the upper surface of the drift region 220 into the drift region 220 and has a second doping type opposite to the first doping type. The semiconductor layer 200 includes a plurality of well regions 230 (in Figure 2A In the example of two well regions 230, each well region 230 is arranged in a lateral spacing in the drift region 220. The drift region 220 between adjacent well regions 230 is a JFET region. It should be understood that the JFET region is located below the gate structure 10.

[0048] The source region 231 extends from the upper surface of the well region 230 into the well region 230 and has a first doping type. Figure 2A In the cross-sectional view, each well region 230 includes two source regions 231. However, it should be understood that the source region 231 in the same well region 230 can generally be a square ring, that is, the upper surface of the source region 231 is a square ring, so Figure 2A The two parts of the source region 231 in each well region 230 are actually different regions of the same source region. Different parts of the upper surface of the same source region 231 are in contact with the gate structure 10 and the source metal layer respectively, that is, there is an overlapping area between a part of the upper surface of the source region 231 and the projection of the gate structure 10 on the upper surface of the drift region 220, and a source metal layer is provided on another part of the upper surface of the source region 231, so as to lead out the source region 231.

[0049] In order to reduce the on-resistance RDSon, the semiconductor structure 200 provided by the present invention also includes a dummy gate structure 232, which includes a dummy gate 232a and a dummy gate dielectric layer 232b, wherein the dummy gate 232a has the same potential as the gate 11 in the gate structure 10. In some embodiments, for example, the gate 11 and the dummy gate 232a are electrically connected to achieve the same potential between the two, or the same voltage is applied after the two are respectively led out. The dummy gate dielectric layer 232b wraps the dummy gate 232a to at least isolate the dummy gate 232a from the well region 230. Of course, it can be understood that the dummy gate dielectric layer 232b does not completely wrap the entire periphery of the dummy gate 232a, but an area not wrapped by the dummy gate dielectric layer 232b is provided on the upper surface of the dummy gate 232a, so as to facilitate the dummy gate 232a to be led out, so as to achieve electrical connection with the gate 11.

[0050] The pseudo gate 232a is a conductive material, and in particular, can be a material commonly used for gates; the pseudo gate dielectric layer 232b is an insulating material. In a preferred embodiment, in order to facilitate preparation and control production costs, the pseudo gate 232a is made of the same material as the gate 11, and the pseudo gate dielectric layer 232b is made of the same material as the gate dielectric layer 12. Similarly, the pseudo gate dielectric layer 232b can be a single-layer structure or a stacked structure of multiple dielectric layers. In each embodiment of the present invention, the pseudo gate dielectric layer 232b is taken as an example as a single-layer structure.

[0051] Furthermore, in order to ensure that there is no abnormality in the gate-source reverse leakage current, the withstand voltage of the gate dielectric layer 12 is less than or equal to the withstand voltage of the pseudo gate dielectric layer 232b, so as to avoid structural failure caused by the pseudo gate dielectric layer 232b being broken down earlier than the gate dielectric layer 12 when the gate 11 and the pseudo gate 232a are applied with the same potential. In the specific implementation process, the above-mentioned withstand voltage requirement can be met by selecting a suitable insulating material or controlling the thickness of the two. Of course, if the pseudo gate dielectric layer 232b is made of the same material as the gate dielectric layer 12, especially if the pseudo gate dielectric layer 232b located on the upper surface of the pseudo gate 232a is made of the same material as the gate dielectric layer 12, the above-mentioned withstand voltage requirement can be achieved by controlling the thickness of the pseudo gate dielectric layer 232b of this part to be greater than or equal to the thickness of the gate dielectric layer 12.

[0052] According to the semiconductor structure provided by the present invention, the gate 11 and the pseudo gate 232a can be electrically connected to make the gate 11 and the pseudo gate 232a have the same potential. When a voltage is applied to the gate 11 and the pseudo gate 232a, the pseudo gate 232a and the JFET region form a capacitor. Specifically, the pseudo gate 232a is equivalent to the upper plate of the capacitor, and the JFET region is equivalent to the lower plate of the capacitor, and the two are isolated by the pseudo gate dielectric layer 232b.

[0053] The following formula (1) shows the calculation formula of the JFET region resistance:

[0054] (I)

[0055] Among them, R JFET is the resistance of the JFET region; ρ JFET is the resistivity of the JFET region; X JP is the well depth; W G is the gate width; X is the JFET region width; W0 is the width of the space charge region outside the well region.

[0056] Taking the NMOS structure as an example, when the gate 11 and the pseudo gate 232a are connected to a positive potential, a large number of carriers (electrons in the NMOS structure) are induced in the JFET region, and the doping type of the drift region 220 is N-type, so the resistivity of the JFET region decreases. Combined with the above formula (I), when other conditions remain unchanged, due to the decrease in the resistivity of the JFET region, the resistance of the JFET region will also decrease, thereby reducing the on-resistance RDSon of the VDMOSFET. Similarly, for PMOS devices or other types of planar gate MOSFETs, RDSon can also be reduced, and for planar gate IGBTs, the saturation voltage drop VCESAT can be reduced, which will not be explained here one by one.

[0057] Figure 2B A schematic structural diagram of a well region in a semiconductor structure according to a first embodiment of the present invention is shown below. Figure 2B The pseudo gate structure 232 is further described. Figure 2B In the figure, the dummy gate structure 232 is regarded as a whole, and the division of the dummy gate and the dummy gate dielectric layer is ignored, so as to more clearly illustrate the structure of the dummy gate structure 232.

[0058] refer to Figure 2B , the longitudinal cross-section of the pseudo gate structure 232 is an inverted "T" shape. Specifically, the pseudo gate structure 232 includes two parts, which are distinguished by different patterns. Among them, the first part 2321 extends from the upper surface of the well region 230 to the well region 230. The source region 231 in the same well region 230 is distributed outside the first part 2321 and is separated by the first part 2321. For example, if the source region 231 is in a square ring shape on the upper surface of the semiconductor structure 200, the first part 2321 is located in the middle of the square ring, that is, the first part 2321 is surrounded by the source region 231.

[0059] The second portion 2322 of the dummy gate structure 232 is located below the first portion 2321 and connected to the first portion 2321 , and the second portion 2322 extends laterally to between the lower surface of the source region 231 and the lower surface of the well region 230 .

[0060] The longitudinal extension depth h1 of the first portion 2321 in the well region 230 is greater than the longitudinal extension depth h2 of the source region 231 in the well region 230, so that the upper surface of the second portion 2322 is spaced from the lower surface of the source region 231 by a first preset distance h3 (h3= h1-h2, h3>0), that is, the upper surface of the second portion 2322 is not in direct contact with the lower surface of the source region 231. In this way, the current in the semiconductor structure 200 can flow to the source metal layer along the well region 230 located above the pseudo-gate structure 232, especially the second portion 2322, without flowing through the source region 231, thereby ensuring normal avalanche breakdown.

[0061] In order to further improve the avalanche breakdown resistance, the semiconductor structure 200 further includes a second doped region, namely a contact region 233. The contact region 233 extends from the upper surface of the well region 230 to the well region 230 and is located between the source region 231 and the dummy gate structure 232. Figure 2B In the illustrated embodiment, the contact region 233 is separated from the dummy gate structure 232 by the well region 230, that is, there is a gap between the lower surface of the contact region 233 and the upper surface of the second portion 2322. However, it should be understood that in some other embodiments, the contact region 233 may also be in direct contact with the dummy gate structure 232, that is, the lower surface of the contact region 233 is in direct contact with the upper surface of the second portion 2322. The contact region 233 has the same second doping type as the well region 230, and its doping concentration is greater than the doping concentration of the well region 230, so as to reduce the lateral contact resistance Rb, thereby meeting the single pulse avalanche breakdown energy (EAS) requirement.

[0062] exist Figure 2B In the embodiment shown, the second portion 2322 is completely located in the well region 230. That is, the second portion 2322 extends in the lateral direction and does not extend beyond the well region 230. More specifically, the second portion 2322 extends in the lateral direction to extend beyond the edge of the source region 231 above it and does not extend beyond the edge of the well region 230. In other words, Figure 2B In the X direction or the opposite direction of the X direction shown in FIG. 2 , the distance d2 between the second portion 2322 and the adjacent edge of the well region 230 should be less than the distance d1 between the source region 231 above it and the adjacent edge of the well region 230 (i.e., d1>d2). In other words, the distance between the edge of the second portion 2322 and the edge of the adjacent JFET region is greater than 0. In this way, although the well region 230 is divided into two parts, the upper and lower parts, and the space charge regions of the two parts are still connected, so that the on-resistance RDSon is maintained at a low level while satisfying the drain-source voltage and the drain-source leakage current.

[0063] In some embodiments, the lower surface of the second portion 2322 has a second preset distance h4 from the lower surface of the well region 230, h4>0, that is, the lower surface of the second portion 2322 is not in direct contact with the lower surface of the well region 230, ensuring that the space charge region of the well region 230 is located below the pseudo gate structure 230, further reducing the change in drain-source voltage.

[0064] Figure 3A A schematic structural diagram showing a semiconductor structure according to a second embodiment of the present invention; Figure 3B A schematic structural diagram of a well region in a semiconductor structure according to a second embodiment of the present invention is shown.

[0065] refer to Figure 3A and Figure 3B In the second embodiment of the present invention, the relative positional relationship between the gate structure 10 and the semiconductor layer 300, as well as the arrangement of the substrate 310, the drift region 320, the well region 330, the source region 331, the contact region 333 and the first portion 3321 of the dummy gate structure 332 in the semiconductor layer 300 and the relative positional relationship between any two regions are the same as those in the first embodiment and are not described in detail herein. Figure 3B The division of the pseudo gate and the pseudo gate dielectric layer is also ignored.

[0066] In the second embodiment, although the dummy gate structure 332 is also completely located in the well region, that is, the second portion 3322 of the dummy gate structure 332 extends in the lateral direction and does not exceed the well region 330. However, unlike the first embodiment, along the X direction in the figure and the opposite direction of the X direction, the second portion 3322 of the dummy gate structure 332 in the second embodiment extends to the edge of the well region 330 and directly contacts the edge of the well region 330, that is, the edge of the second portion 3322 is flush with or tangent to the edge of the well region 330. In other words, the distance between the second portion 3322 and the JET region is 0. Therefore, the second embodiment of the present invention can also maintain the on-resistance RDSon at a low level while satisfying the drain-source voltage and drain-source leakage current.

[0067] Figure 4A A schematic structural diagram showing a semiconductor structure according to a third embodiment of the present invention; Figure 4B A schematic structural diagram showing a well region in a semiconductor structure according to a third embodiment of the present invention.

[0068] refer to Figure 4A and Figure 4BIn the third embodiment of the present invention, the relative positional relationship between the gate structure 10 and the semiconductor layer 400, as well as the arrangement of the substrate 410, the drift region 420, the well region 430, the source region 431, the contact region 433 and the first portion 4321 of the dummy gate structure 432 in the semiconductor layer 400 and the relative positional relationship between any two regions are the same as those in the first / second embodiment, and will not be described in detail here. At the same time, in order to more clearly illustrate the relative positional relationship between the second portion 4322 of the dummy gate structure 432 and the well region 430, Figure 4B The division of the pseudo gate and the pseudo gate dielectric layer is also ignored.

[0069] The third embodiment of the present invention is different from the first / second embodiment of the present invention in that the second portion 4322 of the pseudo gate structure 432 extends laterally beyond the well region 430 and into the drift region 420, that is, most of the pseudo gate structure 432 is located in the well region, and a small portion of the pseudo gate structure 432 is located in the JFET region. At this time, the pseudo gate dielectric layer is also used to isolate the pseudo gate and the drift region 420. Further, the width of the second portion extending to the drift region 420 is less than the width of the space charge region (shown by a dotted line in the figure) outside the well region 430. In other words, the second portion 4322 extends laterally into the JFET and does not exceed the space charge region outside the well region, that is, the distance between the edge of the second portion 4322 and the edge of the adjacent JFET region can be regarded as a negative value. Therefore, the space charge region outside the entire well region 430 remains continuous, and the third embodiment of the present invention can also maintain the on-resistance RDSon at a low level while satisfying the drain-source voltage and drain-source leakage current.

[0070] It should be understood that reference Figure 4A and Figure 4B Since the second portion 4322 of the pseudo gate structure 432 enters the drift region 420, the space charge region corresponding to the second portion 4322 will be concave, that is, the lateral width w1 of the space charge region corresponding to the second portion 4322 is smaller than the lateral width w2 of the space charge region outside other edges of the well region 430 (w1<w2).

[0071] It should be noted that, in the semiconductor structures shown in the first to third embodiments above, the second part of the pseudo-gate structure extends to the same or substantially the same extent on both sides in the lateral direction, but the present invention is not limited thereto. In some other embodiments, the extent of extension on both sides of the second part may also be different. For example, in the fourth embodiment, one side of the second part extends laterally beyond the source region above it and does not exceed the edge of the adjacent well region, and the other side extends laterally beyond the well region and into the JFET region; in the fifth embodiment, one side of the second part extends laterally to directly contact the edge of the adjacent well region, and the other side extends laterally beyond the well region and into the JFET region; in the sixth embodiment, one side of the second part extends laterally beyond the source region above it and does not exceed the edge of the adjacent well region, and the other side extends laterally to directly contact the edge of the adjacent well region. Due to limited space, they will not be listed.

[0072] Figure 5 The simulated volt-ampere characteristic curves of different embodiments of the present invention are shown. Figure 5 As shown, under the condition that other parameters are the same and only the lateral extension of the second part of the dummy gate structure is different, the relationship between the on-resistance RDSon of the semiconductor structure in each embodiment is:

[0073] The semiconductor structure of the third embodiment is less than the semiconductor structure of the second embodiment and less than the semiconductor structure of the first embodiment and less than the conventional planar gate type semiconductor structure (i.e., not including the dummy gate structure, refer to Figure 1A ).

[0074] According to Figure 5 It can be seen from the volt-ampere characteristic curve shown that, compared with the existing planar MOSFETs such as VDMOSFET, the on-resistance RDSon can be reduced by setting a pseudo-gate structure in the well region by adopting the technical solution of the above embodiment. Further comparison with the simulated volt-ampere characteristic curve corresponding to the above embodiment shows that as the second part of the pseudo-gate structure extends laterally closer to the JFET region, the on-resistance RDSon shows a downward trend, especially when the second part extends laterally to the edge of the well region (which can be regarded as the distance between the second part and the JFET region is 0, that is, the technical solution of the second embodiment) or even when the second part extends laterally into the JFET region (which can be regarded as the distance between the second part and the JFET region is a negative value, that is, the technical solution of the third embodiment), the on-resistance RDSon decreases more significantly; and in comparison, the on-resistance RDSon is reduced most significantly by adopting the technical solution of the third embodiment.

[0075] Similarly, for the planar gate IGBT, the saturation voltage drop can be effectively reduced by setting a pseudo gate structure in the well region, and the saturation voltage drop is most significantly reduced when the second part of the pseudo gate structure extends laterally into the JFET region, which will not be elaborated here.

[0076] 6A to 6HThe cross-sectional views of the method for preparing the semiconductor structure provided by the present invention at multiple stages are shown. 6A to 6H In the present invention, the preparation of the semiconductor structure provided in the third embodiment of the present invention is taken as an example, but it should be understood that the preparation method provided by the present invention is also applicable to the preparation of the semiconductor structure in other embodiments of the present invention. In addition, by adjusting the doping type of the corresponding region, the preparation method is also applicable to the preparation of the corresponding planar gate IGBT. At the same time, in order to more clearly show the changes of the semiconductor structure as the preparation steps proceed, the filling pattern of the same region may be different in different drawings.

[0077] refer to Fig. 6A , a drift region 420 is formed on the substrate 410, for example, by an epitaxial process, to obtain a semiconductor layer. The substrate 410 may be a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, and in particular, a semiconductor substrate that can be used for power semiconductor devices. The substrate 410 and the drift region 420 both have a first doping type, and generally, the doping concentration of the substrate 410 is greater than the doping concentration of the drift region 420.

[0078] It should be additionally explained that the above steps are performed as optional steps. In some embodiments, an epitaxial wafer that meets the requirements can be directly selected as the semiconductor layer, that is, the subsequent steps can be directly implemented on the existing semiconductor layer without performing the above steps.

[0079] Further references Fig. 6A , a well region 430 is formed in the drift region 420, and the well region 430 has a second doping type. Specifically, for example, a patterned first mask layer 21 is formed on the upper surface of the semiconductor layer, and then a plurality of well regions 430 are formed in the drift region 420 by, for example, ion implantation and push junction.

[0080] It should be noted that Fig. 6A Only one well region 430 is shown in the figure. In actual products, multiple well regions 430 are formed in the drift region 420. The well regions 430 are spaced apart in the drift region 420 along the lateral direction (i.e., the X direction in the figure and the opposite direction of the X direction). The drift region 420 between adjacent well regions 430 is a JFET region (not marked in the figure).

[0081] refer to Figure 6B , a source region 431 is formed in each well region 430, and the source region 431 has a first doping type. Exemplarily, the upper surface of the source region 431 is in a square ring shape, so that Figure 6B The longitudinal cross section shown includes two parts of the source region 431. The process of forming the source region 431 includes ion implantation and thermal process junction driving.

[0082] refer to Figure 6C, a first trench A1 is formed in the well region 430. The first trench A1 extends from the upper surface of the well region 430 to the well region 430 and is surrounded by the source region 431 (at Figure 6C 4. In FIG. 4, the first trench A1 is shown as being located between two portions of the source region 431. The etching depth y2 of the first trench A1 is greater than the depth y1 of the source region 431 and less than the depth y3 of the well region 430 (y1<y2<y3).

[0083] For example, the first trench A1 may be formed by referring to the following steps: a patterned second mask layer 22 is formed on the upper surface of the drift region 420 to expose the upper surface of the well region 430 (i.e., the semiconductor layer) between the adjacent source regions 431. The exposed well region 430 is then etched to form the first trench A1 in the well region 430.

[0084] refer to Fig.6D , forming a protective layer on the sidewall of the first trench. Specifically, a barrier layer B may be deposited to at least cover the bottom and sidewall of the first trench. Thereafter, the barrier layer B is patterned to remove the B1 portion of the barrier layer at the bottom of the first trench and retain the B2 portion of the barrier layer on the sidewall of the first trench, thereby forming a protective layer (i.e., the barrier layer of the B2 portion). Fig.6D In the structure shown, for ease of operation, the protection layer covers both the sidewalls of the first trench and the sidewalls of the second mask layer 22 .

[0085] refer to Fig. 6E , isotropic etching is performed at the bottom of the first trench A1 to obtain a second trench A2, and the second trench A2 is located between the lower surface of the source region 431 and the lower surface of the well region 430. The trench A finally formed is roughly in an inverted "T" shape, including a first trench A1 extending from the upper surface of the well region 430 to the well region 430 and a second trench A2 located between the lower surface of the source region 431 and the lower surface of the well region 430, and the first trench A1 and the second trench A2 are connected. Among them, the upper surface of the second trench A2 is a first preset distance from the lower surface of the source region 431, and the lower surface of the second trench A2 is a second preset distance from the lower surface of the well region 430, and the first preset distance and the second preset distance are both greater than zero. Fig. 6E As shown, due to the isotropic etching, after the etching is completed, the distance between the upper surface of the second trench A2 and the upper surface of the well region 430 will be slightly smaller than the etching depth of the first trench A1 ( Figure 6C y2 in .

[0086] For the semiconductor structure of the third embodiment of the present invention, in the lateral direction, that is, along the X direction in the figure or the opposite direction of the X direction, the second trench A2 extends toward the edge of the well region 430 and enters the drift region 420. It should be understood that, for the lateral dimension of the second trench A2, the second trench A2 may extend to directly contact the edge of the well region but not exceed the well region, thereby forming the semiconductor structure of the second embodiment described above; or, the second trench A2 may extend to exceed the source region above it and not exceed the adjacent edge of the well region, thereby forming the semiconductor structure of the first embodiment described above.

[0087] The above-mentioned isotropic etching method can specifically be wet etching or gas etching, or wet etching combined with gas etching. It is understandable that, in practice, the morphology of the second groove A2, especially the specific dimensions of the second groove A2 in the longitudinal and transverse directions, can be controlled by adjusting the process conditions during the isotropic etching process. In addition, due to the different crystal phases in different areas at the bottom of the first groove A1, the etching rates in different directions are also different. On this basis, the etching rates in different directions can also be controlled by adjusting the composition and ratio of the liquid used for wet etching, thereby obtaining an ideal morphology.

[0088] Thereafter, a dummy gate and a dummy gate dielectric layer are formed. Specifically, first, a first insulating material layer is filled in trench A to cover the inner wall of trench A; then, a conductive material layer is filled in trench A and patterned so that at least part of the upper surface of the conductive material layer is lower than the upper surface of the semiconductor layer; then, a second insulating material layer is continuously filled to cover the upper surface of the conductive material layer in trench A (the first insulating material layer and the second insulating material layer may be made of the same material). Among them, the conductive material layer in trench A is the dummy gate finally formed; the first insulating material layer and the second insulating material layer that wrap the dummy gate are the dummy gate dielectric layer finally formed.

[0089] However, it should be understood that in a preferred embodiment, in order to further simplify the process, the gate and the dummy gate are made of the same material, and the dummy gate dielectric layer and at least a portion of the gate dielectric layer are made of the same material, so that the gate and the dummy gate as well as the dummy gate dielectric layer and a portion of the gate dielectric layer can be formed simultaneously. The following takes the preferred embodiment as an example to continue to introduce the preparation method provided by the embodiment of the present invention.

[0090] refer to Fig. 6F After removing the second mask layer and the protective layer, a first insulating material layer 23 and a conductive material layer 24 are formed in sequence.

[0091] In some embodiments, the first insulating material layer 23 covers the inner wall of the trench and the exposed upper surface of the semiconductor layer, and then the conductive material layer 24 is formed to fill the trench and cover the first insulating material layer 23 on the upper surface of the semiconductor layer. In the subsequent preparation process, the first insulating material layer 23 is used to form a part of the dummy gate dielectric layer and the gate dielectric layer; the conductive material layer 24 is used to form the dummy gate and the gate. It should be noted that in Fig. 6F In the illustrated embodiment, in order to control costs and reduce processing difficulty, the first insulating material layer is a material layer of a single material, thereby forming a pseudo gate dielectric layer of a single-layer structure; in some embodiments, the first insulating material layer may include material layers of multiple materials, thereby forming a multi-layer pseudo gate dielectric layer.

[0092] Furthermore, in some embodiments, the conductive material layer 24 is planarized to avoid the influence of the uneven surface of the conductive material layer 24 on the yield of the semiconductor structure. The planarization process includes, for example, chemical mechanical polishing (CMP).

[0093] refer to Figure 6G , the conductive material layer is patterned so that the upper surface of the conductive material layer in the groove is lower than the upper surface of the semiconductor layer, thereby completely separating the conductive material layer in the groove and the conductive material layer on the upper surface of the semiconductor layer. Among them, the conductive material layer in the groove eventually forms a pseudo gate 432a, and the first insulating material layer covering the inner wall of the groove eventually forms a part of the pseudo gate dielectric layer. The first insulating material layer covering the upper surface of the semiconductor layer eventually forms a gate dielectric layer, and the conductive material layer stacked with the first insulating material layer on the upper surface of the semiconductor layer eventually forms a gate 11. Of course, in order to ensure that the conductive material layer is completely etched, a certain degree of over-etching can also be performed to reduce the thickness of the first insulating material layer between the gate 11 and the groove to the process requirements.

[0094] As described above, since the conductive material layer in the groove is completely separated from the conductive material layer on the upper surface of the semiconductor layer, the gate and the dummy gate can be electrically connected in subsequent steps by, for example, electrode extraction to ensure that the two have the same potential. The electrode extraction can be carried out by any method in the prior art and will not be described in detail in the present invention.

[0095] In some other embodiments, during the above-mentioned patterning process, the conductive material layer located on the upper surface of the semiconductor layer and the conductive material layer located in the groove are not completely separated. That is, for each groove, by patterning the conductive material in a partial area, the conductive material layer in the partial area of ​​the groove is etched to a certain depth, so that the upper surface of the conductive material layer in the area is lower than the upper surface of the semiconductor layer (see Figure 6G), the conductive material layer in another part of the area is retained, and the conductive material layer in this area is still connected to the conductive material layer on the upper surface of the semiconductor layer. The structure of the conductive material layer in this area can be similar to that of Fig. 6F The dummy gate 432 a is electrically connected to the gate 11 through the conductive material layer that is not completely separated.

[0096] Furthermore, during the patterning process, an ion implantation window C is formed. The ion implantation window C corresponds to the upper surface of the semiconductor layer between the source region 431 and the trench. Figure 6G and Figure 6H , ions are implanted into the well region 430 through the ion implantation window C to form a contact region 433 having the same doping type as the well region 430 and a higher doping concentration. The contact region 433 is located between the source region 431 and the dummy gate structure.

[0097] In some embodiments, the ion implantation window C exposes the corresponding area of ​​the upper surface of the semiconductor layer. In a preferred embodiment, the first insulating material layer located on the upper surface of the semiconductor layer in the corresponding area of ​​the ion implantation window C is retained, and when the conductive material layer is patterned, over-etching is performed to sufficiently reduce the thickness of the first insulating material layer in the corresponding area of ​​the ion implantation window, so as to serve as a shielding layer when ions are implanted, thereby facilitating the reduction of the channel effect.

[0098] Then, a second insulating material layer is deposited. The second insulating material layer covers the exposed conductive material layer (including the conductive material layer located on the upper surface of the semiconductor layer to form the gate 11 and the conductive material layer located in the groove to form the dummy gate 432a) and the upper surface of the first insulating material layer and / or the semiconductor layer exposed by the ion implantation window C. The second insulating material layer covering the conductive material layer in the groove and the first insulating material layer covering the inner wall of the groove together form a dummy gate dielectric layer that wraps the conductive material layer in the groove (i.e., the dummy gate 432a).

[0099] In the present invention, there are no restrictions on the materials and formation processes of the first insulating material layer and the second insulating material layer. For example, the materials of the first insulating material layer and the second insulating material layer can be the same or different (in Figure 6H In the example, the first insulating material layer and the second insulating material layer are made of the same material, so the two insulating material layers are not clearly distinguished); when the first insulating material layer and the second insulating material layer are made of the same material, their formation processes may also be different. For example, when the conductive material layer is doped polysilicon, the first insulating material layer and the second insulating material layer may both be silicon oxide. And the first insulating material layer may be formed by vapor deposition, and the second insulating material layer may be formed by low-temperature oxidation growth.

[0100] Since the upper surface of the conductive material layer in at least part of the groove is lower than the upper surface of the semiconductor layer, the thickness of the second insulating material layer in at least this part of the groove is greater than the thickness of the first insulating material layer. Therefore, the thickness of the pseudo gate dielectric layer can be greater than or equal to the thickness of the gate dielectric layer, thereby making the withstand voltage of the pseudo gate dielectric layer greater than or equal to the withstand voltage of the gate dielectric layer, thereby improving the reliability of the device.

[0101] Finally, the electrode is led out. For a vertically conductive planar gate MOSFET, an isolation layer can be first formed and patterned to expose part of the source region and the gate (and possible pseudo gate), and then a first metal layer is formed and patterned to lead out the source region and the gate (and possible pseudo gate) respectively; then the lower surface of the semiconductor layer is ground to reduce its overall thickness, and a second metal layer is deposited on the lower surface of the semiconductor layer as a drain metal layer. For a planar gate IGBT, the first metal layer is located on the upper surface of the semiconductor layer, including an emitter metal layer electrically in contact with the emitter region and a gate metal layer electrically in contact with the gate (and possible pseudo gate), and the second metal layer is located on the lower surface of the semiconductor layer to serve as a collector together with the collector region.

[0102] According to the semiconductor structure prepared by the preparation method provided by the present invention, a pseudo-gate structure is prepared in the well region, wherein the pseudo-gate has the same potential as the gate, so that when voltage is applied to the gate and the pseudo-gate at the same time, the pseudo-gate forms a capacitor with the JFET region and induces a large number of carriers, thereby reducing the resistance of the JFET region, thereby reducing the on-resistance RDSon or the saturation voltage drop VCESAT of the semiconductor structure.

[0103] Furthermore, by controlling the position and size of the pseudo-gate structure, especially the relative position relationship between the pseudo-gate structure and the edge of the well region, it is possible to further reduce the on-resistance or saturation voltage drop while avoiding affecting other electrical parameters of the semiconductor device using this structure. Therefore, it is particularly suitable for application scenarios with higher requirements on performance and loss.

[0104] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the present invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A semiconductor layer and a gate structure located on the upper surface of the semiconductor layer, wherein the gate structure comprises a gate dielectric layer and a gate layer stacked in sequence on the upper surface of the semiconductor layer, The semiconductor layer comprises a drift region extending from the upper surface of the semiconductor layer into the semiconductor layer, the drift region having a first doping type; a well region is provided in the drift region, the well region extends from the upper surface of the drift region into the drift region, the well region has a second doping type opposite to the first doping type; a first doping region is provided in the well region, the first doping region extends from the upper surface of the well region into the well region, the first doping region has the first doping type; Wherein, the semiconductor structure further includes a dummy gate structure, and the dummy gate structure is at least partially located in the well region, including: a dummy gate having the same potential as the gate; and A dummy gate dielectric layer wraps the dummy gate to at least isolate the dummy gate from the well region.

2. The semiconductor structure according to claim 1, characterized in that: The dummy gate structure comprises a first portion and a second portion connected to each other, wherein: The first portion extends downward from the upper surface of the well region into the well region, and the first doping region is disposed outside the first portion. The second portion is located below the first portion and extends laterally to between the lower surface of the first doped region and the lower surface of the well region, and the second portion is not in direct contact with the lower surface of the well region.

3. The semiconductor structure according to claim 2, characterized in that: The edge of the second portion extending in the lateral direction exceeds the edge of the first doped region above the second portion and does not exceed the space charge region of the well region.

4. The semiconductor structure according to claim 3, characterized in that: The second portion extends laterally to between the first doped region and the adjacent edge of the well region above the second portion; Alternatively, the second portion extends in the lateral direction to directly contact the edge of the well region adjacent to the second portion and does not extend beyond the well region; Alternatively, the second portion extends in the lateral direction beyond the well region but does not extend beyond the space charge region of the well region.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The gate is electrically connected to the dummy gate; and / or the withstand voltage of the gate dielectric layer is less than or equal to the withstand voltage of the dummy gate dielectric layer.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that: It also includes a second doping region, which extends from the upper surface of the semiconductor layer to the well region, and is located between the first doping region and the pseudo-gate structure. The second doping region has the second doping type, and the doping concentration of the second doping region is greater than the doping concentration of the well region.

7. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The semiconductor structure is a planar gate metal oxide semiconductor field effect transistor, the first doped region is a source region; the semiconductor layer further comprises a substrate stacked with the drift region, the substrate and the drift region have the same doping type; Alternatively, the semiconductor structure is a planar gate insulated gate bipolar transistor, the first doped region is an emitter region, the semiconductor layer further includes a collector region stacked with the drift region, and the collector region has the second doping type.

8. A method for preparing a semiconductor structure, characterized in that: include: forming a well region in a drift region of a semiconductor layer, wherein the drift region extends from an upper surface of the semiconductor layer into the semiconductor layer, the drift region has a first doping type, the well region extends from an upper surface of the drift region into the drift region, and the well region has a second doping type opposite to the doping type of the drift region; forming a first doped region in the well region, wherein the first doped region extends from an upper surface of the well region into the well region, and the first doped region has the first doping type; forming a dummy gate structure, wherein the dummy gate structure is at least partially located in the well region, and the dummy gate structure comprises a dummy gate and a dummy gate dielectric layer, wherein the dummy gate dielectric layer wraps the dummy gate to at least isolate the dummy gate from the well region; as well as A gate structure is formed on the upper surface of the semiconductor layer. The gate structure includes a gate dielectric layer and a gate electrode which are stacked, and the gate electrode and the dummy gate electrode are at the same potential.

9. The preparation method according to claim 8, characterized in that: The steps of forming the dummy gate structure include: forming a first trench in the well region, wherein the first trench extends downward from the upper surface of the well region into the well region, and the depth of the first trench is greater than the depth of the first doped region; the outer side of the first trench is the first doped region; A second trench is formed at the bottom of the first trench, the second trench extends in a lateral direction to between the lower surface of the first doped region and the lower surface of the well region, and is not in direct contact with the lower surface of the first doped region, the first trench and the second trench forming a trench; forming a first insulating material layer inside the trench, and making the first insulating material layer cover the upper surface of the drift region; Filling a conductive material layer in the trench, and making the conductive material layer cover a first insulating material layer located on an upper surface of the drift region; Patterning the conductive material layer so that the conductive material layer in the trench forms the dummy gate, and the conductive material layer on the upper surface of the drift region forms the gate, wherein at least a portion of the upper surface of the dummy gate is lower than the upper surface of the semiconductor layer; and A second insulating material layer is formed to cover the upper surface of the conductive material layer in the trench, and the first insulating material layer and the second insulating material layer in the trench form the dummy gate dielectric layer.

10. The preparation method according to claim 9, characterized in that: The edge of the second trench extending in the lateral direction exceeds the edge of the first doped region thereover and does not exceed the space charge region of the well region.

11. The preparation method according to claim 10, characterized in that: The second trench extends laterally to between the first doped region and the adjacent edges of the well region above the second trench; Alternatively, the second trench extends in the lateral direction to directly contact the edge of the well region adjacent to the second trench and does not exceed the well region; Alternatively, the second trench extends in a lateral direction beyond the well region but does not extend beyond a space charge region of the well region.

12. The preparation method according to claim 10, characterized in that: The patterning process further forms an ion implantation window, wherein the ion implantation window corresponds to a portion of the upper surface of the semiconductor layer located between the first doping region and the trench. The preparation method further includes: performing ion implantation through an ion implantation window to form a second doping region between the first doping region and the groove, wherein the second doping region has the second doping type and a doping concentration of the second doping region is higher than a doping concentration of the well region.

13. The preparation method according to claim 10 or 12, characterized in that: The conductive material layer is patterned so that part of the surface of the conductive material layer in the groove is lower than the upper surface of the semiconductor layer, and another part of the surface is higher than the upper surface of the semiconductor layer to maintain connection with the conductive material layer on the upper surface of the drift region.

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