Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to realize manufacturing of a ring gate transistor with a thicker gate dielectric layer and other ring gate transistors in the semiconductor device and / or an integrated circuit on the same semiconductor substrate and reduce the integration difficulty of the two kinds of ring gate transistors. The semiconductor device includes a semiconductor substrate, a first gate-all-around transistor and a second gate-all-around transistor. The first gate-all-around transistor and the second gate-all-around transistor are arranged on the semiconductor substrate in a spaced mode in the direction parallel to the surface of the semiconductor substrate. Wherein in the thickness direction of the semiconductor substrate, the number of layers of the first nanostructures included in the first gate-all-around transistor is smaller than the number of layers of the second nanostructures included in the second gate-all-around transistor. Each layer of first nano-structure comprises a first semiconductor material part, and each layer of first semiconductor material part and the corresponding layer of second nano-structure are integrally formed and are aligned in the thickness direction of the semiconductor substrate. The first spacing is greater than the second spacing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Compared with planar transistors and fin field effect transistors, ring-gate transistors have advantages such as higher gate control capability. Therefore, when each transistor included in a semiconductor device and / or an integrated circuit adopts a ring-gate transistor, the operating performance of the semiconductor device and the integrated circuit can be improved.

[0003] However, when a portion of the all-around gate transistors in a semiconductor device and / or integrated circuit has a thicker gate dielectric layer than another portion of the all-around gate transistors, it is difficult to manufacture the above two all-around gate transistors using existing manufacturing methods. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which are used to realize the manufacture of a ring-gate transistor with a thicker gate dielectric layer and other ring-gate transistors in a semiconductor device and / or an integrated circuit on the same semiconductor substrate, thereby reducing the integration difficulty of the above two types of ring-gate transistors.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a semiconductor device, which includes: a semiconductor substrate, a first ring-gate transistor and a second ring-gate transistor. The first ring-gate transistor and the second ring-gate transistor are arranged on the semiconductor substrate at intervals in a direction parallel to the surface of the semiconductor substrate. Wherein, along the thickness direction of the semiconductor substrate, the number of layers of the first nanostructure included in the first ring-gate transistor is less than the number of layers of the second nanostructure included in the second ring-gate transistor. Each layer of the first nanostructure includes a first semiconductor material portion, and each layer of the first semiconductor material portion is integrally formed with the corresponding layer of the second nanostructure and aligned along the thickness direction of the semiconductor substrate. Any layer of the first nanostructure has a first spacing with the adjacent first structure, and the first structure is the semiconductor substrate and / or the adjacent layer of the first nanostructure. Any layer of the second nanostructure has a second spacing with the adjacent second structure, and the second structure is the semiconductor substrate and / or the adjacent layer of the second nanostructure, and the first spacing is greater than the second spacing. The thickness of the gate dielectric layer included in the first ring-gate transistor is greater than the thickness of the gate dielectric layer included in the second ring-gate transistor.

[0006] In the case of adopting the above technical solution, in the semiconductor device provided by the present invention, the number of layers of the first nanostructure included in the first ring gate transistor is less than the number of layers of the second nanostructure included in the second ring gate transistor. In addition, any layer of the first nanostructure included in the first ring gate transistor has a first spacing with the adjacent first structure. Any layer of the second nanostructure included in the second ring gate transistor has a second spacing with the adjacent second structure. The above first spacing is greater than the second spacing. Based on this, because the gate dielectric layer and the gate included in the first ring gate transistor at least surround the periphery of the first nanostructure in sequence, and the gate dielectric layer and the gate included in the second ring gate transistor at least surround the periphery of the second nanostructure in sequence, in the case where the first spacing is greater than the second spacing, even if the thickness of the gate dielectric layer included in the first ring gate transistor is greater than the thickness of the gate dielectric layer included in the second ring gate transistor, when manufacturing the first ring gate transistor and the second ring gate transistor on the same semiconductor substrate, the problem that the gate dielectric layer included in the first ring gate transistor is too large, resulting in the spacing between the first nanostructure and the semiconductor substrate, and the spacing between the two adjacent layers of the first nanostructure are too small, resulting in the gate dielectric layer included in the subsequent first ring gate transistor can only be partially filled and / or the gate included in the first ring gate transistor cannot be filled or can only be partially filled. Furthermore, each layer of the first nanostructure includes a first semiconductor material portion, and each layer of the first semiconductor material portion is integrally formed with the corresponding layer of the second nanostructure and aligned along the thickness direction of the semiconductor substrate. Based on this, in the actual manufacturing process, the manufacturing of the ring-gate transistor with a thicker gate dielectric layer and the remaining ring-gate transistors can be realized on the same semiconductor substrate and based on the same first semiconductor material layer (used to manufacture the first semiconductor material portion and the second nanostructure), ensuring that the thickness of the gate dielectric layer and gate included in the first ring-gate transistor, and the gate dielectric layer and gate included in the second ring-gate transistor can meet the working requirements, improving the yield and manufacturing efficiency of the above two ring-gate transistors, while also reducing the integration difficulty of the above two ring-gate transistors.

[0007] In one example, among all the first nanostructures in the same first all-around gate transistor, at least the first nanostructure at the top layer further includes a second semiconductor material portion surrounding the first semiconductor material portion. The carrier mobility of the second semiconductor material portion is greater than that of the first semiconductor material portion.

[0008] In one example, when at least two layers of the first nanostructure further include the second semiconductor material portion, in all layers of the first nanostructure including the second semiconductor material portion, the thickness of the different second semiconductor material portions included in different layers of the first nanostructure gradually increases along the direction away from the semiconductor substrate. The materials of the different second semiconductor material portions included in the different layers of the first nanostructure are the same; or, the materials of some of the different second semiconductor material portions included in the different layers of the first nanostructure are different.

[0009] In one example, the materials of the first semiconductor material portion and the second semiconductor material portion include silicon, silicon germanium or germanium, wherein the germanium content in the second semiconductor material portion is at least 20% higher than the germanium content in the first semiconductor material portion.

[0010] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising: first, providing a semiconductor substrate. Next, forming a first ring-gate transistor and a second ring-gate transistor on the semiconductor substrate. The first ring-gate transistor and the second ring-gate transistor are arranged on the semiconductor substrate in a direction parallel to the surface of the semiconductor substrate. Wherein, along the thickness direction of the semiconductor substrate, the number of layers of the first nanostructure included in the first ring-gate transistor is less than the number of layers of the second nanostructure included in the second ring-gate transistor. Each layer of the first nanostructure includes a first semiconductor material portion, and each layer of the first semiconductor material portion is integrally formed with the corresponding layer of the second nanostructure and aligned along the thickness direction of the semiconductor substrate. Any layer of the first nanostructure has a first spacing with the adjacent first structure, and the first structure is the semiconductor substrate and / or the adjacent layer of the first nanostructure. Any layer of the second nanostructure has a second spacing with the adjacent second structure, and the second structure is the semiconductor substrate and / or the adjacent layer of the second nanostructure, and the first spacing is greater than the second spacing. The thickness of the gate dielectric layer included in the first ring-gate transistor is greater than the thickness of the gate dielectric layer included in the second ring-gate transistor.

[0011] In one example, a first ring-gate transistor and a second ring-gate transistor are formed on a semiconductor substrate, including: forming a first active structure and a second active structure distributed at intervals on the semiconductor substrate. The first active structure includes at least two layers of a first semiconductor material portion, and a first source / drain region included in the first ring-gate transistor disposed on both sides of the at least two layers of the first semiconductor material portion along the length direction. The second active structure includes at least two layers of a first semiconductor material portion, and a second source / drain region included in the second ring-gate transistor disposed on both sides of the at least two layers of the first semiconductor material portion along the length direction. The first active structure and the second active structure include the same number of layers of the first semiconductor material portion and are integrally formed. The spacing between two adjacent layers of the first semiconductor material portion in the first active structure is equal to the spacing between two adjacent layers of the first semiconductor material portion in the second active structure. Next, a first dielectric layer covering the periphery of the first active structure including at least two layers of the first semiconductor material portion, and a second dielectric layer surrounding the periphery of the first dielectric layer are formed. The materials of the first dielectric layer and the second dielectric layer are different, and the top of the second dielectric layer is flush with the top of the first dielectric layer. Next, under the protection of the mask structure, the second dielectric layer and the first dielectric layer are etched respectively by an etching process to process the at least two layers of the first semiconductor material portion included in the first active structure exposed layer by layer, and obtain the first nanostructure included in the first ring-gate transistor. The mask structure covers the periphery of the at least two layers of the first semiconductor material portion included in the second active structure.

[0012] In one example, under the protection of the mask structure, the second dielectric layer and the first dielectric layer are etched respectively by an etching process to process at least two layers of the first semiconductor material portion included in the first active structure exposed layer by layer, including: under the protection of the mask structure, the second dielectric layer is subjected to a first back-etching process until the pre-reserved layer located above the top layer to be removed is completely exposed. The top height of the second dielectric layer after the first back-etching process is not higher than the minimum bottom height of the exposed pre-reserved layer, and is not lower than M / N of the thickness of the top layer to be removed. The pre-reserved layer is the first semiconductor material portion overlapping the position of the corresponding first nanostructure. The layer to be removed is the first semiconductor material portion that does not form at least part of the first nanostructure correspondingly. N is a positive integer greater than 1, M is a positive integer greater than or equal to 1, and M>N. Next, at least the portion of the first dielectric layer exposed outside the second dielectric layer along the thickness direction of the semiconductor substrate is removed. Next, a deposition process is used to form a second semiconductor material portion on the periphery of the exposed structure, so that the exposed pre-reserved layer forms at least part of the corresponding first nanostructure. The carrier mobility of the second semiconductor material portion is greater than the carrier mobility of the first semiconductor material portion. Next, the second dielectric layer is subjected to a second back-etching process until the layer to be removed located on the top layer is exposed. The top height of the second dielectric layer after the second back-etching process is not higher than the bottom height of the layer to be removed located on the top layer, and is not lower than the top height of the remaining pre-reserved layer. Next, at least the portion of the first dielectric layer exposed outside the second dielectric layer along the thickness direction of the semiconductor substrate is removed. And the exposed layer to be removed is removed. Next, the above operation is repeated until a second semiconductor material portion is formed on the periphery of the pre-reserved layer located on the bottom layer. Next, the remaining portion of the second dielectric layer and the remaining portion of the first dielectric layer are removed. Next, the remaining layer to be removed is removed to obtain the first nanostructure included in the first ring-gate transistor.

[0013] In one example, M of N is greater than or equal to 1 / 5 and less than or equal to 2 / 3.

[0014] In one example, the first dielectric layer is formed by atomic layer deposition or selective oxidation process.

[0015] In one example, before a second semiconductor material portion is formed on the periphery of the exposed structure using a deposition process, when the top height of the first dielectric layer is lower than the top height of the layer to be removed located on the top layer, the exposed layer to be removed is removed while removing the portion of the second semiconductor material portion located on the layer to be removed.

[0016] In one example, before forming the second semiconductor material portion on the periphery of the exposed structure by a deposition process, the top height of the first dielectric layer is not less than Q of P of the thickness of the layer to be removed at the top layer. Q of P is greater than or equal to 1 / 5 and less than or equal to 2 / 3.

[0017] In one example, the material of the first dielectric layer includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0018] In one example, the material of the second dielectric layer includes at least one of SiCO, SiCON and SiO2-SiF4.

[0019] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0021] Figure 1 It is a schematic diagram of the structure of a semiconductor device in the related art;

[0022] Figure 2 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 1 ;

[0023] Figure 3 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 ;

[0024] Figure 4 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 ;

[0025] Figure 5 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 4 ;

[0026] Figure 6 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 5 ;

[0027] Figure 7 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 6 ;

[0028] Figure 8 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 7 ;

[0029] Fig. 9 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 8 ;

[0030] Fig.10 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 9 ;

[0031] Fig.11 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 ;

[0032] Fig.12 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 one;

[0033] Fig.13 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 two;

[0034] Fig.14 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 three;

[0035] Fig.15 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 Four;

[0036] Fig.16 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 five;

[0037] Fig.17 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 six;

[0038] Fig.18 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 seven;

[0039] Fig.19 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 eight;

[0040] Fig. 20 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 10 Nine;

[0041] Fig.21 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 ten;

[0042] Fig. 22 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 eleven;

[0043] Fig.23 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 twelve;

[0044] Fig.24 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 Thirteen;

[0045] Fig.25 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 fourteen;

[0046] Fig.26 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 fifteen;

[0047] Fig. 27 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 sixteen;

[0048] Fig.28 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 XVII;

[0049] Fig.29 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 eighteen;

[0050] Fig.30 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 2 nineteen;

[0051] Fig.31 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 ten;

[0052] Fig.32 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 eleven;

[0053] Fig.33 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 twelve;

[0054] Fig.34A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 Thirteen;

[0055] Fig.35 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 fourteen;

[0056] Fig.36 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention Figure 3 fifteen.

[0057] Figure numerals: 11 is a semiconductor substrate, 12 is a first all-around gate transistor, 13 is a second all-around gate transistor, 14 is a first nanostructure, 15 is a second nanostructure, 16 is a first semiconductor material portion, 17 is a gate dielectric layer, 18 is a gate, 19 is a second semiconductor material portion, 20 is a shallow trench isolation structure, 21 is a gate sidewall, 22 is an interlayer dielectric layer, 23 is a first source / drain region, 24 is a second source / drain region, 25 is a first dielectric layer, 26 is a second dielectric layer, 27 is a mask structure, 28 is a pre-reserved layer, 29 is a layer to be removed, 30 is a sacrificial gate, and 31 is a sacrificial layer. DETAILED DESCRIPTION

[0058] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0059] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0060] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0062] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0063] The gate-all-around transistor has advantages such as higher gate control capability compared to planar transistors and fin field effect transistors, so when the transistors included in the semiconductor device and / or integrated circuit adopt the gate-all-around transistor, the working performance of the semiconductor device and the integrated circuit can be improved. However, when a portion of the gate-all-around transistors in the semiconductor device and / or integrated circuit has a thicker gate dielectric layer than another portion of the gate-all-around transistors, it is difficult to use the existing manufacturing method to realize the manufacturing of the above two types of gate-all-around transistors.

[0064] Specifically, the input / output (IO) transistors and core (Core) transistors of an integrated circuit are taken as examples to illustrate that it is difficult to manufacture the two types of ring-gate transistors when the gate dielectric layer of some of the above-mentioned ring-gate transistors is thicker. Among them, because the above-mentioned input / output transistors need to withstand a higher operating voltage (usually 1.8V, 2.5V, 3.3V or 5V, etc.), the gate dielectric layer of the input / output transistor is thicker. However, there are a large number of core transistors inside the chip, so in order to achieve the purpose of saving power and faster computing speed at the same time, the core transistors often use a lower operating voltage (usually 1.0V or 1.2V, etc.). Correspondingly, the gate dielectric layer of the core transistor is smaller. In the actual manufacturing process, when the core transistors and input / output transistors whose device structures are all ring-gate transistors are manufactured on the same semiconductor substrate, such as Figure 1 As shown, after a gate dielectric layer 17 (the thickness of the gate dielectric layer 17 is relatively small) is formed on the Core device region of the semiconductor substrate 11 to surround the outer periphery of the channel of the core transistor, and a gate dielectric layer 17 (the thickness of the gate dielectric layer 17 is relatively large) is formed to surround the outer periphery of the channel of the input / output transistor on the IO device region, because the distance between adjacent nanostructures only meets the structural requirements of the core transistor, relative to the input / output transistor, after the thicker gate dielectric layer 17 is formed, the gate dielectric layer 17 has filled the gaps between the smaller nanostructures or only a smaller gate forming space remains between the nanostructures, and subsequently, a metal gate of the input / output transistor that meets the working requirements cannot be formed in the above-mentioned gaps or smaller gate spaces, thereby causing a "pinch-off" phenomenon between adjacent nanostructures on the IO device region, thereby affecting the electrical performance of the input / output transistor formed on the IO device region, that is, it is difficult to realize the integration of the core transistor and the input / output transistor whose device structures are all ring-gate transistors, and the working performance of the input / output transistor is reduced.

[0065] In addition, in semiconductor devices, two ring-gate transistors are often provided with gate dielectric layers of different thicknesses to achieve different threshold voltages for the two ring-gate transistors. As mentioned above, when the two ring-gate transistors are manufactured on the same semiconductor substrate, since the distance between adjacent nanostructures only meets the structural requirements of the ring-gate transistor with a thinner gate dielectric layer, it is impossible to manufacture a thicker gate dielectric layer between adjacent nanostructures with a smaller spacing, resulting in the threshold voltage corresponding to the ring-gate transistor with a thicker gate dielectric layer being difficult to meet the requirements of the preset scheme, thereby reducing the yield and working performance of the semiconductor device.

[0066] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. Among them, in the semiconductor device provided by the embodiment of the present invention, the number of layers of the first nanostructure included in the first ring-gate transistor is less than the number of layers of the second nanostructure included in the second ring-gate transistor. In addition, the first spacing is greater than the second spacing, which solves the problem that the gate dielectric layer included in the first ring-gate transistor can only be partially filled and / or the gate included in the first ring-gate transistor cannot be filled or can only be partially filled because the thickness of the gate dielectric layer included in the first ring-gate transistor is greater than the thickness of the gate dielectric layer included in the second ring-gate transistor.

[0067] First, as Fig.35 and Fig.36 As shown, the semiconductor device provided by the embodiment of the present invention includes: a semiconductor substrate 11, a first all-round gate transistor 12 and a second all-round gate transistor 13. The first all-round gate transistor 12 and the second all-round gate transistor 13 are arranged on the semiconductor substrate 11 in a direction parallel to the surface of the semiconductor substrate 11. Among them, along the thickness direction of the semiconductor substrate 11, the number of layers of the first nanostructure 14 included in the first all-round gate transistor 12 is less than the number of layers of the second nanostructure 15 included in the second all-round gate transistor 13. Each layer of the first nanostructure 14 includes a first semiconductor material portion 16, and each layer of the first semiconductor material portion 16 is integrally formed with the corresponding layer of the second nanostructure 15 and aligned along the thickness direction of the semiconductor substrate 11. Any layer of the first nanostructure 14 has a first spacing with the adjacent first structure, and the first structure is the semiconductor substrate 11 and / or the adjacent layer of the first nanostructure 14. Any layer of the second nanostructure 15 has a second spacing with the adjacent second structure, and the second structure is the semiconductor substrate 11 and / or the adjacent layer of the second nanostructure 15, and the first spacing is greater than the second spacing. The thickness of the gate dielectric layer 17 included in the first all-around gate transistor 12 is greater than the thickness of the gate dielectric layer 17 included in the second all-around gate transistor 13 .

[0068] When the above technical solution is adopted, in the semiconductor device provided by the embodiment of the present invention, Fig.35 and Fig.36As shown, the number of layers of the first nanostructure 14 included in the first all-around gate transistor 12 is less than the number of layers of the second nanostructure 15 included in the second all-around gate transistor 13. In addition, any layer of the first nanostructure 14 included in the first all-around gate transistor 12 has a first spacing with an adjacent first structure. Any layer of the second nanostructure 15 included in the second all-around gate transistor 13 has a second spacing with an adjacent second structure. The above-mentioned first spacing is greater than the second spacing. Based on this, since the gate dielectric layer 17 and the gate 18 included in the first all-round gate transistor 12 at least sequentially surround the outer periphery of the first nanostructure 14, and the gate dielectric layer 17 and the gate 18 included in the second all-round gate transistor 13 at least sequentially surround the outer periphery of the second nanostructure 15, when the first spacing is greater than the second spacing, even if the thickness of the gate dielectric layer 17 included in the first all-round gate transistor 12 is greater than the thickness of the gate dielectric layer 17 included in the second all-round gate transistor 13, when the first all-round gate transistor 12 and the second all-round gate transistor 13 are manufactured on the same semiconductor substrate 11, the problem that the thickness of the gate dielectric layer 17 included in the first all-round gate transistor 12 is larger, resulting in the spacing between the first nanostructure 14 and the semiconductor substrate 11 and the spacing between two adjacent layers of the first nanostructure 14 being too small, resulting in the gate dielectric layer 17 included in the subsequent first all-round gate transistor 12 can only be partially filled and / or the gate 18 included in the first all-round gate transistor 12 cannot be filled or can only be partially filled will not occur. Furthermore, each layer of the first nanostructure 14 includes a first semiconductor material portion 16, and each layer of the first semiconductor material portion 16 is integrally formed with the corresponding layer of the second nanostructure 15 and aligned along the thickness direction of the semiconductor substrate 11. Based on this, in the actual manufacturing process, the manufacturing of the ring-gate transistor with a thicker gate dielectric layer 17 and the remaining ring-gate transistors can be realized on the same semiconductor substrate 11 and based on the same first semiconductor material layer (used to manufacture the first semiconductor material portion 16 and the second nanostructure 15), ensuring that the thickness of the gate dielectric layer 17 and the gate 18 included in the first ring-gate transistor 12, and the gate dielectric layer 17 and the gate 18 included in the second ring-gate transistor 13 can meet the working requirements, improving the yield and manufacturing efficiency of the above two ring-gate transistors, and reducing the integration difficulty of the above two ring-gate transistors.

[0069] In actual application, the embodiment of the present invention does not specifically limit the material of the semiconductor substrate. For example, the semiconductor substrate can be a substrate made of any semiconductor material such as a silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate or a germanium substrate.

[0070] For the first gate-all-around transistor and the second gate-all-around transistor, in terms of conductivity type, the conductivity type of the first gate-all-around transistor and the second gate-all-around transistor can be the same; for example, the conductivity type of the first gate-all-around transistor and the second gate-all-around transistor can both be P-type or N-type. Alternatively, the conductivity types of the first gate-all-around transistor and the second gate-all-around transistor can also be opposite; for example, the conductivity type of the first gate-all-around transistor can be P-type, and the conductivity type of the second gate-all-around transistor is N-type; for another example, the conductivity type of the first gate-all-around transistor can be N-type, and the conductivity type of the second gate-all-around transistor is P-type.

[0071] From the distribution perspective, the embodiment of the present invention does not specifically limit the distribution positions of the first ring-gate transistor and the second ring-gate transistor on the semiconductor substrate, as long as the first ring-gate transistor and the second ring-gate transistor are arranged on the semiconductor substrate at intervals in a direction parallel to the surface of the semiconductor substrate.

[0072] From a structural perspective, Figure 8 , Fig.35 and Fig.36 As shown, the first all-around gate transistor 12 may include a first source / drain region 23, a first nanostructure 14, a gate dielectric layer 17 and a gate 18. The first source / drain region 23 is respectively arranged on both sides of the first nanostructure 14 along the length direction, and is respectively in contact with the first nanostructure 14. The gate dielectric layer 17 included in the first all-around gate transistor 12 at least surrounds the periphery of each layer of the first nanostructure 14. The gate 18 included in the first all-around gate transistor 12 is formed on the gate dielectric layer 17.

[0073] The number of layers of the first nanostructure included in the first ring-gate transistor may be only one layer, or may be multiple layers spaced apart along the thickness direction of the semiconductor substrate. The embodiment of the present invention does not specifically limit the number of layers of the first nanostructure included in the first ring-gate transistor, as long as the number of layers of the first nanostructure included in the first ring-gate transistor is less than the number of layers of the second nanostructure included in the second ring-gate transistor, and the first spacing is greater than the second spacing.

[0074] In addition, the first structures adjacent to any layer of the first nanostructures have different first structures corresponding thereto according to the number of layers where the first nanostructures are located. Fig.30 As shown, in the case where the first gate-all-around transistor includes only one layer of the first nanostructure 14, the first structure adjacent to the first nanostructure 14 is only the semiconductor substrate 11. Fig.35 and Fig.36As shown, in the case where the first ring-gate transistor 12 includes at least two layers of the first nanostructure 14, the number of layers of the first nanostructure 14 included in the first ring-gate transistor 12 is defined in sequence from bottom to top (the number of layers of each object is also defined in this way below). Among them, the first structures adjacent to the first layer of the first nanostructure 14 are the semiconductor substrate 11 and the second layer of the first nanostructure 14. The first structures adjacent to any layer of the first nanostructure 14 except the first nanostructure 14 located at the bottom and top layers are other first nanostructures 14 located at the upper and lower layers of the first nanostructure 14. The first structures adjacent to the first nanostructure 14 located at the top layer are only other first nanostructures 14 located at the upper layer of the first nanostructure 14.

[0075] For the above-mentioned first spacing, the size of the first spacing can be set according to the requirements for the thickness of the gate dielectric layer and the gate electrode included in the first all-around gate transistor in the actual application scenario. Specifically, when the first all-around gate transistor has at least two layers of first nanostructures, except for the first nanostructure located at the top layer, the two first spacings corresponding to any layer of the first nanostructure and the two adjacent first structures can be the same or different. For example: Fig.35 and Fig.36 As shown, the first spacing between the first layer of first nanostructures 14 and the semiconductor substrate 11 may be equal to or may not be equal to the first spacing between the first layer of first nanostructures 14 and the second layer of first nanostructures 14. For example, Fig.36 As shown, in the case where the first ring-gate transistor 12 has at least two layers of first nanostructures 14, except for the first nanostructure 14 located at the top layer, at least one layer of the first nanostructure 14 is not equal to the two first spacings corresponding to the two adjacent first structures. At this time, in the process of manufacturing the semiconductor device, it is not necessary to strictly require the number of layers of the first semiconductor material portion 16 to be etched in order to keep the two first spacings corresponding to the first nanostructure 14 located in the middle layer equal to each other, so that the manufacturing method of the semiconductor device provided by the embodiment of the present invention is diversified and the applicability of the semiconductor device to different application scenarios is improved.

[0076] In addition, when the first ring-gate transistor has at least two layers of first nanostructures, the first spacing corresponding to any layer of first nanostructures may be equal to or unequal to the first spacings corresponding to other layers of first nanostructures. For example, the first spacing between the first layer of nanostructures and the semiconductor substrate may be equal to or unequal to the first spacing between the second layer of first nanostructures and the third layer of first nanostructures. For example, Fig.36As shown, in the case where the first all-around gate transistor 12 has at least two layers of first nanostructures 14, the first spacing corresponding to at least one layer of the first nanostructures 14 is not equal to the different first spacings corresponding to another first nanostructure 14. At this time, in the process of manufacturing the semiconductor device, it is not necessary to strictly require the number of layers of the first semiconductor material portion 16 to be etched in order to keep the different first spacings corresponding to the first nanostructures 14 located at different layers equal to each other, so that the manufacturing method of the semiconductor device provided by the embodiment of the present invention is diversified and the applicability of the semiconductor device to different application scenarios is improved.

[0077] As for the second ring-gate transistor, Fig.35 and Fig.36 As shown, the second all-around gate transistor 13 may include a second source / drain region 24, a second nanostructure 15, a gate dielectric layer 17 and a gate 18. The second source / drain region 24 is respectively arranged on both sides of the second nanostructure 15 along the length direction, and is respectively in contact with the second nanostructure 15. The gate dielectric layer 17 included in the second all-around gate transistor 13 at least surrounds the outer periphery of each layer of the second nanostructure 15. The gate 18 included in the second all-around gate transistor 13 is formed on the gate dielectric layer 17.

[0078] The second gate-all-around transistor includes a plurality of layers of the second nanostructure that are spaced apart along the thickness direction of the semiconductor substrate. The embodiment of the present invention does not specifically limit the number of layers of the second nanostructure included in the second gate-all-around transistor, as long as it can be applied to the semiconductor device provided in the embodiment of the present invention.

[0079] As for the second spacing, the specific situation of the second structure adjacent to each layer of the second nanostructure can refer to the situation of the first structure adjacent to each layer of the first nanostructure described above, and will not be repeated here. The size of the second spacing can be set according to the thickness requirements of the gate dielectric layer and the gate included in the second ring-gate transistor in the actual application scenario. Specifically, Fig.35 and Fig.36 As shown, except for the second nanostructure 15 located at the top layer, each layer of the second nanostructure 15 has a second spacing with two adjacent second structures. The two second spacings can be equal or unequal. For example: Fig.35 and Fig.36 As shown, the second spacing between the second nanostructure 15 of the second layer and the second nanostructure 15 of the first layer may be equal to or may not be equal to the second spacing between the second nanostructure 15 of the second layer and the second nanostructure 15 of the third layer. Fig.35 and Fig.36 As shown, except for the second nanostructure 15 located at the top layer, at least one layer of the second nanostructure 15 has two second spacings corresponding to two adjacent second structures that are equal. Figures 2 to 36 As shown, the thickness of at least two adjacent sacrificial layers 31 in different stacks (each stack includes a sacrificial layer 31 and a first semiconductor material layer located on the sacrificial layer 31; the first semiconductor material layer is used to manufacture the first semiconductor material portion 16) of the second nanostructure 15 can be the same. Based on this, in the process of removing the sacrificial layer 31 corresponding to the second ring-gate transistor 13 to release the first semiconductor material portion 16 included in the second active structure, it is helpful to solve the problem of difficulty in controlling the etching time due to the different progress of etching different sacrificial layers 31 under the same etching time due to the different thicknesses of each sacrificial layer 31. In addition, it is also helpful to solve the problem of etching a part of the reserved first semiconductor material portion 16 due to the long etching time to ensure that the thickest sacrificial layer 31 is completely etched, thereby improving the yield of the second ring-gate transistor 13.

[0080] In addition, the second spacing corresponding to any layer of the second nanostructures may be equal to or different from the second spacing corresponding to other layers of the second nanostructures. Fig.35 and Fig.36 As shown, the second distance between the first layer of second nanostructures 15 and the semiconductor substrate 11 may be equal to or may not be equal to the second distance between the second layer of second nanostructures 15 and the third layer of second nanostructures 15. For example, Fig.35 and Fig.36 As shown, the second spacing corresponding to at least one layer of the second nanostructure 15 is equal to the different second spacing corresponding to another second nanostructure 15. The application principle of the corresponding beneficial effect in this case can refer to the application principle of the beneficial effect of the two second spacings corresponding to the same second nanostructure 15 being equal as described above, which will not be repeated here.

[0081] As for the difference between the first spacing and the second spacing, it can be determined according to the difference in thickness of the gate dielectric layer included in the first all-around gate transistor and the second all-around gate transistor, and the formation process of the first nanostructure and the second nanostructure. Figures 2 to 24 As shown, when only the odd-numbered layers of the first semiconductor material portion 16 corresponding to the first ring-gate transistor 12 (for example, the first layer of the first semiconductor material portion 16, the third layer of the first semiconductor material portion 16, etc.) are removed, the above-mentioned first spacing is equal to the sum of the thickness of the first semiconductor material portion 16 and twice the second spacing.

[0082] As for the materials and thicknesses of the first nanostructure and the second nanostructure, they can be set according to the actual application scenario. Among them, because the first semiconductor material included in the first nanostructure and the second nanostructure are integrally formed and flush along the thickness direction of the semiconductor substrate, the first semiconductor material included in the first nanostructure and the second nanostructure have the same material and thickness. For example: the materials of the first semiconductor material included in the first nanostructure and the second nanostructure can both be Si 1- x Ge x ; Wherein, 0≤x≤1. For example, the first semiconductor material included in the first nanostructure and the material of the second nanostructure can both be Si or Si 0.5 Ge 0.5 wait.

[0083] In addition, if Fig.35 and Fig.36 As shown, each layer of the first nanostructure 14 may include only the first semiconductor material portion 16. Alternatively, as shown in FIG. Fig.33 and Fig.34 As shown, among all the layers of first nanostructures 14 included in the same first all-around gate transistor 12, at least the first nanostructure 14 located at the top layer also includes a second semiconductor material portion 19 surrounding the periphery of the first semiconductor material portion 16. Moreover, the carrier mobility of the second semiconductor material portion 19 is greater than the carrier mobility of the first semiconductor material portion 16. In this case, it can be understood that the number of layers of the first nanostructure 14 included in the first all-around gate transistor 12 is less than the number of layers of the second nanostructure 15 included in the second all-around gate transistor 13. At this time, the operation of removing part of the layers of the first semiconductor material portion 16 to make the first spacing greater than the second spacing will cause the driving performance of the first all-around gate transistor 12 to be reduced. However, because among all the layers of first nanostructures 14 included in the same first ring-gate transistor 12, at least the first nanostructure 14 located at the top layer also includes a second semiconductor material portion 19 surrounding the outer periphery of the first semiconductor material portion 16, and the second semiconductor material portion 19 also has a relatively high carrier mobility, the conduction characteristics of the first nanostructure 14 including the second semiconductor material portion 19 can be improved, and the problem of reduced driving capability caused by the reduction in the number of layers of the first nanostructure 14 can be alleviated, thereby ensuring that the first ring-gate transistor 12 has relatively high electrical performance.

[0084] Specifically, in the case where the first ring-gate transistor has at least two layers of the first nanostructure, there may be only one layer of the first nanostructure including the above-mentioned first semiconductor material portion and the second semiconductor material portion. Alternatively, at least two layers of the first nanostructure may include the above-mentioned first semiconductor material portion and the second semiconductor material portion. Of course, each layer of the first nanostructure may also include the second semiconductor material portion. As for the specific material type of the second semiconductor material portion, it can be set according to actual needs, as long as the carrier mobility of the second semiconductor material portion is greater than the carrier mobility of the first semiconductor material portion.

[0085] For example, the materials of the first semiconductor material part and the second semiconductor material part may include silicon, silicon germanium or germanium. The germanium content in the second semiconductor material part is at least 20% higher than the germanium content in the first semiconductor material part. 0.1 Ge 0.9 、Si 0.2 Ge 0.8 、Si 0.3 Ge 0.7 、Si 0.4 Ge 0.6 or Si 0.5 Ge 0.5 The material of the first semiconductor material part may include Si, Si 0.9 Ge 0.1 、Si 0.8 Ge 0.2 、Si 0.3 Ge 0.7 or Si 0.4 Ge 0.6 As for the difference between the germanium content in the second semiconductor material portion and the germanium content in the first semiconductor material portion, it can be determined based on the number of layers of the first nanostructure included in the first all-around gate transistor and the requirements for the driving performance of the first all-around gate transistor, and is not specifically limited here.

[0086] In addition, in the actual manufacturing process, Figures 2 to 23 As shown, when the first nanostructure 14 and the second nanostructure 15 are manufactured by the same stack, and after the first nanostructure 14 is formed, all or part of the second semiconductor material portion 19 surrounding the periphery of each layer of the first nanostructure 14 is retained, the materials of the first nanostructure 15 are not completely the same.

[0087] Furthermore, when the first gate-all-around transistor has at least two layers of the first nanostructure, and the at least two layers of the first nanostructure include a first semiconductor material portion and a second semiconductor material portion, the materials of the second semiconductor material portions included in different first nanostructures may be the same or may not be completely the same. Fig.33 As shown, in the case where at least two layers of the first nanostructure 14 further include the second semiconductor material portion 19, in all layers of the first nanostructure 14 including the second semiconductor material portion 19, the thickness of the different second semiconductor material portions 19 included in different layers of the first nanostructure 14 gradually increases along the direction away from the semiconductor substrate 11. The materials of the different second semiconductor material portions 19 included in the different layers of the first nanostructure 14 are the same; or, the materials of some of the different second semiconductor material portions 19 included in the different layers of the first nanostructure 14 are different.

[0088] like Figures 2 to 36 As shown, the first semiconductor material portion 16 included in the first active structure is processed by a deposition and etching process to obtain a first nanostructure 14. The purpose of the above deposition process is to form a second semiconductor material portion 19 on the periphery of the first semiconductor material portion 16 that is reserved. In this way, in the process of removing the layer 29 to be removed, the second semiconductor material portion 19 can protect the reserved layer 28. As can be seen from the above content, a layer of the second semiconductor material portion 19 is deposited on the exposed structure each time. Based on this, if the material of the second semiconductor material portion 19 deposited each time is the same, the material of the first nanostructure 14 of different layers obtained is the same. If the material of the second semiconductor material portion 19 deposited at least once is different from that of the second semiconductor material portion 19 deposited in the remaining steps, and the second semiconductor material portion 19 is not removed, the material of the second semiconductor material portion 19 included in different first nanostructures 14 will be different. In addition, it can be understood that the first nanostructure 14 with a larger number of layers includes more layers of the second semiconductor material portion 19, so that its thickness is also greater. Specifically, the material, number of layers and thickness of the second semiconductor material portion 19 included in the first nanostructure 14 can be set according to the actual application scenario, and are not specifically limited here.

[0089] As for the materials of the above-mentioned first source / drain region, the second source / drain region, the gate dielectric layer and the gate, the material of the first source / drain region and / or the second source / drain region may include any semiconductor material such as silicon, silicon germanium or germanium. Specifically, the materials of the above-mentioned first source / drain region and the second source / drain region may be the same as or different from each other. The materials of the gate dielectric layer included in the above-mentioned first ring-gate transistor and the gate dielectric layer included in the second ring-gate transistor may be insulating materials with lower dielectric constants such as silicon oxide or silicon nitride, or may be insulating materials with higher dielectric constants such as HfO2, ZrO2, TiO2 or Al2O3. The materials and thicknesses of the gate dielectric layer included in the first ring-gate transistor and the gate dielectric layer included in the second ring-gate transistor may be the same or different. Specifically, the materials and thicknesses of the gate dielectric layer included in the above-mentioned first ring-gate transistor and the gate dielectric layer included in the second ring-gate transistor may be set according to the actual application scenario.

[0090] In actual application, the working performances of the first gate-all-around transistor and the second gate-all-around transistor are different according to the different thicknesses of the gate dielectric layer included in the first gate-all-around transistor and the gate dielectric layer included in the second gate-all-around transistor. Figure 33 to Figure 36 As shown, the thickness of the gate dielectric layer 17 included in the first ring-gate transistor 12 is greater than the thickness of the gate dielectric layer 17 included in the second ring-gate transistor 13. At this time, the absolute value of the operating voltage of the first ring-gate transistor 12 is greater than that of the second ring-gate transistor 13. Based on this, the problem of "pinch-off" of the ring-gate transistor with a thicker gate dielectric layer 17 caused by the integration of two ring-gate transistors with different absolute values ​​of operating voltages in the prior art can be solved. Accordingly, in this case, the thickness and working type of the gate dielectric layer 17 of the two ring-gate transistors can be set according to the requirements for the operating voltage of the two ring-gate transistors in the actual application scenario. For example: Figure 33 to Figure 36 As shown, the first gate-all-around transistor 12 may be an input / output transistor, and the second gate-all-around transistor 13 may be a core transistor. Of course, the first gate-all-around transistor 12 may also be other types of transistors with relatively high operating voltages in the integrated circuit. The second gate-all-around transistor 13 may also be other types of transistors with relatively low operating voltages in the integrated circuit.

[0091] In addition, the gate dielectric layer included in the first all-around gate transistor and the gate dielectric layer included in the second all-around gate transistor may be a single-layer structure or a stacked structure consisting of at least two insulating layers. The specific structures of the gate dielectric layer included in the first all-around gate transistor and the gate dielectric layer included in the second all-around gate transistor may be set according to the actual application scenario, for example, Figure 33 to Figure 36 As shown, in the case where the first ring-gate transistor 12 is an input / output transistor, the gate dielectric layer 17 included in the first ring-gate transistor 12 may be a stacked structure. Specifically, the gate dielectric layer 17 included in the first ring-gate transistor 12 includes a gate oxide layer and a gate insulating layer located on the gate oxide layer. The gate oxide layer is formed at least on the periphery of the first nanostructure 14. Among them, the material of the gate oxide layer may be silicon oxide, silicon oxynitride, etc. The gate insulating layer may be the above-mentioned insulating material with a higher dielectric constant. The thickness of the two can be set according to the operating voltage of the first ring-gate transistor 12, and is not specifically limited here.

[0092] As for the material and thickness of the gate included in the first ring-gate transistor and the gate included in the second ring-gate transistor, they can be set according to the actual application scenario. For example, the material of the gate included in the first ring-gate transistor and the gate included in the second ring-gate transistor can be a conductive material such as TiN, TaN or TiSiN. Among them, the material and thickness of the gate included in the first ring-gate transistor and the gate included in the second ring-gate transistor can be the same or different. Exemplarily, the thickness of the gate included in the first ring-gate transistor included in the first ring-gate transistor can be greater than the thickness of the gate included in the second ring-gate transistor included in the second ring-gate transistor. At this time, the problem of "pinch-off" of the ring-gate transistor with a thicker gate caused by the integration of two ring-gate transistors with gates of different thicknesses in the prior art can be solved.

[0093] In some cases, such as Figure 33 to Figure 36 As shown, a shallow trench isolation structure 20 for defining an active area is also formed on the semiconductor substrate 11. The material of the shallow trench isolation structure 20 can be an insulating material such as SiN, Si3N4, SiO2 or SiCO.

[0094] In some cases, such as Figures 8 to 36 As shown, the first all-around gate transistor 12 and the second all-around gate transistor 13 may also have a gate sidewall 21 and an interlayer dielectric layer 22. The interlayer dielectric layer 22 covers the semiconductor substrate 11. In addition, the top of the interlayer dielectric layer 22 is flush with the top of the gate 18 included in the first all-around gate transistor 12 and the second all-around gate transistor 13. It should be understood that in the process of manufacturing the semiconductor device provided by the embodiment of the present invention, as Figures 8 to 36 As shown, the presence of the interlayer dielectric layer 22 can protect the first source / drain region 23 and the second source / drain region 24 from being affected by operations such as etching and cleaning when etching the sacrificial gate 30 and the sacrificial layer 31. Specifically, the material of the interlayer dielectric layer 22 can be an insulating material such as SiO2 or SiN.

[0095] For the above-mentioned gate sidewall, Figures 8 to 36 As shown, the gate sidewall 21 included in the first ring-gate transistor 12 can be formed between the interlayer dielectric layer 22 and the gate dielectric layer 17 and the gate 18 included in the first ring-gate transistor 12. The gate sidewall 21 included in the second ring-gate transistor 13 can be formed at least between the interlayer dielectric layer 22 and the gate dielectric layer 17 and the gate 18 included in the second ring-gate transistor 13. The presence of the above-mentioned gate sidewall 21 facilitates the formation of the gate stack included in the first ring-gate transistor 12 and the second ring-gate transistor 13, and isolates the gate stack from the conductive structure formed subsequently. The material of the above-mentioned gate sidewall 21 is an insulating material. Specifically, the material of the above-mentioned gate sidewall 21 and the thickness of the gate sidewall 21 can be designed according to the actual application scenario, and are not specifically limited here.

[0096] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 2 to 36 The manufacturing process is described in detail with reference to the cross-sectional view or stereoscopic view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0097] First, a semiconductor substrate is provided. Specifically, the material of the semiconductor substrate can be referred to above and will not be described in detail here.

[0098] Next, if Figures 2 to 36 As shown, a first all-around gate transistor 12 and a second all-around gate transistor 13 are formed on a semiconductor substrate 11. The first all-around gate transistor 12 and the second all-around gate transistor 13 are arranged on the semiconductor substrate 11 in a direction parallel to the surface of the semiconductor substrate 11. In which, along the thickness direction of the semiconductor substrate 11, the number of layers of the first nanostructure 14 included in the first all-around gate transistor 12 is less than the number of layers of the second nanostructure 15 included in the second all-around gate transistor 13. Each layer of the first nanostructure 14 includes a first semiconductor material portion 16, and each layer of the first semiconductor material portion 16 is integrally formed with the corresponding layer of the second nanostructure 15 and aligned along the thickness direction of the semiconductor substrate 11. Any layer of the first nanostructure 14 has a first spacing with the adjacent first structure, and the first structure is the semiconductor substrate 11 and / or the adjacent layer of the first nanostructure 14. Any layer of the second nanostructure 15 has a second spacing with the adjacent second structure, and the second structure is the semiconductor substrate 11 and / or the adjacent layer of the second nanostructure 15, and the first spacing is greater than the second spacing. The thickness of the gate dielectric layer 17 included in the first all-around gate transistor 12 is greater than the thickness of the gate dielectric layer 17 included in the second all-around gate transistor 13 .

[0099] Specifically, the various structures included in the above-mentioned first ring-gate transistor and the second ring-gate transistor, as well as the information such as the materials and specifications of each structure can be referred to the previous text, and will not be repeated here. In addition, the formation order of the different structures in the above-mentioned first ring-gate transistor and the second ring-gate transistor on the semiconductor substrate can be set according to the actual application scenario. Among them, the first semiconductor material part included in the first ring-gate transistor and the second nanostructure of the second ring-gate transistor are formed at the same time. The first source / drain region, gate dielectric layer and gate included in the first ring-gate transistor can be formed on the substrate before the second source / drain region, gate dielectric layer and gate included in the second ring-gate transistor; or, the second source / drain region, gate dielectric layer and gate included in the second ring-gate transistor can be formed on the substrate before the first source / drain region, gate dielectric layer and gate included in the first ring-gate transistor.

[0100] In one example, forming a first gate-all-around transistor and a second gate-all-around transistor on a semiconductor substrate may include the steps of:

[0101] like Figures 2 to 10As shown, a first active structure and a second active structure are formed on a semiconductor substrate 11 and are distributed at intervals. The first active structure includes at least two layers of first semiconductor material parts 16, and a first source / drain region 23 included in a first ring-gate transistor 12 arranged on both sides of the at least two layers of first semiconductor material parts 16 along the length direction. The second active structure includes at least two layers of first semiconductor material parts 16, and a second source / drain region 24 included in a second ring-gate transistor 13 arranged on both sides of the at least two layers of first semiconductor material parts 16 along the length direction. The first active structure and the second active structure include the same number of layers of the first semiconductor material parts 16 and are integrally formed. The spacing between two adjacent layers of the first semiconductor material parts 16 in the first active structure is equal to the spacing between two adjacent layers of the first semiconductor material parts 16 in the second active structure.

[0102] Specifically, the at least two layers of the first semiconductor material portion include at least one pre-reserved layer and at least one layer to be removed. Among them, the pre-reserved layer refers to the first semiconductor material portion in the first active structure that will subsequently form at least part of the first nanostructure. The layer to be removed refers to the first semiconductor material portion in the first active structure that does not subsequently form the first nanostructure. In addition, the manufacturing method of the semiconductor device provided by the embodiment of the present invention is to obtain a first nanostructure with a larger first spacing by pre-forming at least two layers of first semiconductor material portions with a smaller spacing on a semiconductor substrate, and removing the layers to be removed included therein. Based on this, the spacing between adjacent first semiconductor material portions in the first active structure and the second active structure, and the spacing between the first semiconductor material portion and the semiconductor substrate located at the bottom layer can be set with reference to the size of the second spacing described above, as well as actual needs.

[0103] In the actual manufacturing process, Figure 2 As shown, epitaxy or other processes can be used to form at least two stacked layers for manufacturing the first active structure and the second active structure on the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11. Each stacked layer includes a sacrificial layer 31 and a first semiconductor material layer located on the sacrificial layer 31. The first semiconductor material layer is used to manufacture the first semiconductor material portion 16 included in the first active structure and the second active structure, so the first semiconductor material layer included in the stacked layer can be set according to the material, thickness and number of layers of the first semiconductor material portion 16. In addition, the material of the sacrificial layer 31 can be any semiconductor material different from the first semiconductor material layer. The thickness of the sacrificial layer 31 can be set according to the size of the second spacing. Next, as Figure 3 As shown, the stack and part of the semiconductor substrate 11 can be etched from top to bottom by photolithography and etching processes to form a first fin structure and a second fin structure. The depth of the semiconductor substrate 11 etched is greater than or equal to the thickness of the shallow trench isolation structure 20 and less than the thickness of the semiconductor substrate 11. Next, as Figure 4 As shown, a shallow trench isolation structure 20 is formed on the portion of the semiconductor substrate 11 exposed outside the first fin structure and the second fin structure by using processes such as deposition and etching. The material of the shallow trench isolation structure 20 can be referred to in the previous text and will not be repeated here. The portion of the first fin structure exposed outside the shallow trench isolation structure 20 is the first fin. The portion of the second fin structure exposed outside the shallow trench isolation structure 20 is the second fin. Figure 5 and Figure 6 As shown, a sacrificial gate 30 and a gate sidewall 21 spanning the first fin and the second fin can be formed by deposition and selective etching. The length extension direction of the sacrificial gate 30 is different from the length extension direction of the first fin and the second fin. The gate sidewall 21 is formed at least on both sides of the sacrificial gate 30 along its own length direction. By using wet etching or dry etching, the exposed portions of the first fin and the second fin are removed under the masking effect of the sacrificial gate 30 and the gate sidewall 21. Figure 7 As shown, then, the first source / drain region 23 and the second source / drain region 24 are formed simultaneously or step by step by using epitaxial processes. Figure 8 As shown, deposition and chemical mechanical polishing processes can be used to form an interlayer dielectric layer 22 covering the semiconductor substrate 11. The top of the interlayer dielectric layer 22 is flush with the top of the sacrificial gate 30. Finally, as shown in FIG. Fig. 9 As shown, a dry or wet etching process can be used to remove the sacrificial gate and the remaining sacrificial layer, and the remaining first semiconductor material layer in the first fin and the formed first source / drain region 23 form a first active structure, and the remaining second semiconductor material layer in the second fin and the formed second source / drain region 24 form a second active structure.

[0104] It should be noted that the first active structure and the second active structure can be formed in a variety of ways. How to form the above structure is not the main feature of the present invention, so in this specification, only a brief introduction is given so that ordinary technicians in the field can easily implement the present invention. Ordinary technicians in the field can completely imagine other ways to make the above first active structure and the second active structure.

[0105] Next, if Fig.11 and Fig.12 As shown, a first dielectric layer 25 covering the periphery of the first active structure including at least two layers of the first semiconductor material portion 16 and a second dielectric layer 26 surrounding the periphery of the first dielectric layer 25 are formed. The first dielectric layer 25 and the second dielectric layer 26 are made of different materials, and the top of the second dielectric layer 26 is flush with the top of the first dielectric layer 25.

[0106] Specifically, the embodiment of the present invention will subsequently achieve the purpose of protecting the second dielectric layer of the first semiconductor material part located below and of the same material by selectively etching the first dielectric layer and the second dielectric layer in different steps when releasing the pre-reserved layer and the layer to be removed layer by layer, so as to make the lateral etching rate greater than the longitudinal etching rate, so as to meet the requirement that the width of the nanostructure included in the ring-gate transistor is greater than the thickness of the nanostructure in the actual application scenario. Among them, because the width of the nanostructure included in the ring-gate transistor is greater than the thickness of the nanostructure, the etching depth of the second dielectric layer along the thickness direction of the nanostructure is small, and the width of the nanostructure is usually large. In order to completely remove the second dielectric layer under the nanostructure, a larger lateral etching length is required. Based on this, the manufacturing method provided by the embodiment of the present invention etches the first dielectric layer first by setting the first dielectric layer and the second dielectric layer of different materials, so that at least the pre-reserved layer or the layer to be removed to be operated is exposed along the thickness direction of the semiconductor substrate. Then, under the protection of the first dielectric layer, only the part of the second dielectric layer exposed outside the first dielectric layer along the thickness direction of the semiconductor substrate can be removed (or a part can be etched downward more), so as to achieve the purpose of making the lateral etching rate of the second dielectric layer that protects the first semiconductor material part located below and of the same material greater than the longitudinal etching rate, and prevent the pre-reserved layer to be operated or the layer to be removed from being not completely exposed to the outside (or other first semiconductor material parts located below are not exposed to the outside according to the preset scheme) due to the longitudinal etching rate being greater than or equal to the lateral etching rate, thereby reducing the difficulty of manufacturing work and improving the yield of the manufactured semiconductor device. In the above case, the material types of the first dielectric layer and the second dielectric layer can be determined according to the requirements of the etching selectivity ratio of the two in the actual application scenario, as long as they can be applied to the manufacturing method provided in the embodiment of the present invention.

[0107] Exemplarily, the material of the first dielectric layer may include at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0108] Exemplarily, the material of the second dielectric layer may include at least one of SiCO, SiCON and SiO2-SiF4.

[0109] In the actual manufacturing process, the first dielectric layer can be formed by atomic layer deposition or selective oxidation. Then, a deposition process can be used to form a second dielectric layer covering the periphery of the first dielectric layer, and then the second dielectric layer can be processed by chemical mechanical polishing or other processes so that the top of the remaining part of the second dielectric layer is flush with the top of the first dielectric layer.

[0110] Next, if Figures 13 to 32As shown, under the protection of the mask structure 27, the second dielectric layer 26 and the first dielectric layer 25 are etched respectively by an etching process to process the at least two layers of the first semiconductor material portion 16 included in the first active structure exposed layer by layer, and obtain the first nanostructure 14 included in the first all-around gate transistor 12. The mask structure 27 covers the periphery of the at least two layers of the first semiconductor material portion 16 included in the second active structure.

[0111] Specifically, in the actual manufacturing process, such as Fig.11 As shown, deposition and selective etching processes can be used to form a mask structure 27 covering the periphery of at least two layers of the first semiconductor material portion 16 included in the second active structure. The material of the mask structure 27 can include a material that has a protective effect and is easy to remove, such as photoresist or spin-on carbon. Then, as shown in FIG. Fig.13 As shown, the second dielectric layer 26 can be firstly subjected to a first back-etching process by dry etching or wet etching under the protection of the mask structure 27, until the pre-reserved layer 28 above the top layer to be removed 29 is completely exposed. Moreover, the top height of the second dielectric layer 26 after the first back-etching process is not higher than the minimum bottom height of the exposed pre-reserved layer 28, and is not lower than M of N of the thickness of the top layer to be removed 29. The pre-reserved layer 28 is the first semiconductor material portion 16 that overlaps with the position of the corresponding first nanostructure 14. The layer to be removed 29 is the first semiconductor material portion 16 that does not form at least a portion of the first nanostructure 14. N is a positive integer greater than 1, M is a positive integer greater than or equal to 1, and M>N.

[0112] Among them, after the first back-etching process, the top height of the second dielectric layer is not higher than the minimum bottom height of the exposed pre-reserved layer. Relative to the layer to be removed located at the top layer, the top height of the second dielectric layer can be higher than the top height of the layer to be removed located at the top layer, or lower than the top height of the layer to be removed. Because the second semiconductor material portion will be formed on the periphery of the exposed pre-reserved layer later, in the process of removing the layer to be removed later, the pre-reserved layer will be protected from being removed at the same time. When the top height of the second dielectric layer is lower than the top height of the layer to be removed, the second semiconductor material portion will be formed on the layer to be removed later. At this time, if the difference between the top height of the second dielectric layer and the top height of the layer to be removed is large, the formation range of the second semiconductor material portion on the layer to be removed is also large, which is not conducive to removing the layer to be removed. Therefore, the size of the above-mentioned M of N can be determined according to the etching requirements of the layer to be removed in the actual application scenario. Exemplarily, M of N can be greater than or equal to 1 / 5 and less than or equal to 2 / 3. In this case, there is no need to strictly control the etching accuracy in order to make the top height of the second dielectric layer must be higher than the top height of the layer to be removed located at the top layer, thereby reducing the difficulty of the etching process.

[0113] Next, if Fig.15 and Fig.16 As shown, at least the portion of the first dielectric layer 25 exposed outside the second dielectric layer 26 along the thickness direction of the semiconductor substrate 11 is removed.

[0114] In the actual manufacturing process, Fig.15 As shown, wet etching or dry etching can be used, and under the protection of the second dielectric layer 26, only the portion of the first dielectric layer 25 exposed outside the second dielectric layer 26 along the thickness direction of the semiconductor substrate 11 can be removed. Fig.16 As shown, after the selective etching operation, the top height of the first dielectric layer 25 may also be lower than the top height of the layer to be removed 29 located at the top layer. In this case, there is no need to strictly control the etching accuracy in order to make the top height of the first dielectric layer 25 higher than the top height of the layer to be removed 29 located at the top layer, thereby reducing the difficulty of the etching process. As for the top height of the first dielectric layer 25 after selective etching, it can be determined according to the etching requirements of the layer to be removed 29 in the actual application scenario, and is not specifically limited here. Exemplarily, the top height of the first dielectric layer 25 is not less than Q of P of the thickness of the layer to be removed 29 located at the top layer. Q of P may be greater than or equal to 1 / 5 and less than or equal to 2 / 3.

[0115] Next, if Fig.17 and Fig.18 As shown, a second semiconductor material portion 19 is formed on the periphery of the exposed structure by a deposition process, so that the exposed pre-reserved layer 28 forms at least a portion of the corresponding first nanostructure 14. The carrier mobility of the second semiconductor material portion 19 is greater than that of the first semiconductor material portion 16.

[0116] In the actual manufacturing process, the second semiconductor material portion can be formed by epitaxy or other processes. The material and thickness of the second semiconductor material portion can be referred to above. Fig.18 As shown, before depositing the second semiconductor material portion 19, if the top height of the first dielectric layer 25 is lower than the top height of the layer to be removed 29 located on the top layer, then when the second semiconductor material portion 19 is formed, the second semiconductor material portion 19 will not only be located at the periphery of the exposed pre-reserved layer 28, but will also be formed on the exposed portion of the layer to be removed 29.

[0117] Next, if Fig.19 As shown, a dry etching or wet etching process is used to perform a second etching back process on the second dielectric layer 26 until the to-be-removed layer 29 located at the top layer is exposed. The top height of the second dielectric layer 26 after the second etching back process is not higher than the bottom height of the to-be-removed layer 29 located at the top layer, and is not lower than the top height of the remaining pre-reserved layer 28, so that the to-be-removed layer 29 located at the top layer is exposed to the outside, so as to facilitate its removal.

[0118] Next, if Fig.19 and Fig. 20 As shown, at least the portion of the first dielectric layer 25 exposed outside the second dielectric layer 26 along the thickness direction of the semiconductor substrate 11 is removed; and the exposed layer to be removed 29 is removed.

[0119] In the actual manufacturing process, a dry etching or wet etching process can be used, and the first dielectric layer is exposed outside the second dielectric layer along the thickness direction of the semiconductor substrate. Then, the exposed layer to be removed is removed. It can be understood that if a part of the layer to be removed is also exposed when the second semiconductor material portion is formed, then when the exposed layer to be removed is removed, the part of the second semiconductor material portion located on the layer to be removed will be removed due to lack of support.

[0120] Next, if Fig.21 As shown, the above operation is repeated until a second semiconductor material portion is formed at the periphery of the pre-reserved layer at the bottom. Specifically, the number of cycles of the above operation can be determined according to the number of layers of the first semiconductor material portion included in the first active structure and the number of layers of the first nanostructure included in the first all-around gate transistor.

[0121] Next, if Fig. 22 As shown, the remaining portion of the second dielectric layer 26 and the remaining portion of the first dielectric layer are removed.

[0122] Next, if Fig. 22 As shown, the remaining layer to be removed is removed to obtain the first nanostructure 14 included in the first all-around gate transistor 12 .

[0123] It should be noted that, from the above-mentioned contents, the at least two layers of the first semiconductor material portion include at least one layer of pre-reserved layer and at least one layer of to-be-removed layer. After at least two layers of the first semiconductor material portion are formed on the semiconductor substrate, an etching process is required to remove the layers to be removed that are exposed layer by layer. A deposition process is used to form a second semiconductor material portion on the periphery of the structure that is exposed layer by layer and includes the pre-reserved layer to protect the exposed structure. The above-mentioned layer-by-layer exposure is layer-by-layer exposure in a broad sense. In other words, depending on the number of layers, only one layer of the first semiconductor material portion can be exposed from top to bottom at a time. And the first semiconductor material portion is deposited or etched according to whether the first semiconductor material portion is a pre-reserved layer or a to-be-removed layer. In the case where at least two layers of the to-be-removed layers are adjacent to each other, the adjacent layers of the to-be-removed layers can also be exposed at the same time to remove the layers of the to-be-removed layers at the same time, thereby improving manufacturing efficiency and reducing manufacturing costs. It can be imagined that the order of execution of the above-mentioned etching and deposition processes is different depending on the position of the first nanostructure located on the top layer relative to the first semiconductor material portion located on the top layer. Specifically, as Figures 12 to 30 As shown, when the first nanostructure 14 at the top layer is lower than the first semiconductor material portion 16 at the top layer in the first active structure, the etching operation needs to be performed first to remove the layer to be removed 29 at the top layer, and then the second semiconductor material portion 19 is deposited on the exposed reserved layer 28. When the first nanostructure 14 at the top layer is flush with the first semiconductor material portion 16 at the top layer in the first active structure, the deposition operation needs to be performed first to deposit the second semiconductor material portion 19 on the exposed reserved layer 28. The exposed layer to be removed 29 at the top layer is then removed by etching.

[0124] Then, if 31 to Fig.36 As shown, the gate dielectric layer 17 and the gate 18 included in the first all-around gate transistor 12 may be formed by processes such as atomic layer deposition. Then, a dry etching or wet etching process may be used to remove the mask structure to expose the first semiconductor material portion 16 included in the second active structure to form the second nanostructure 15 included in the second all-around gate transistor 13. Next, the gate dielectric layer 17 and the gate 18 included in the second all-around gate transistor 13 may be formed by processes such as atomic layer deposition.

[0125] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0126] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0127] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, a first gate-all-around transistor and a second gate-all-around transistor; The first gate-all-around transistor and the second gate-all-around transistor are arranged on the semiconductor substrate at intervals in a direction parallel to the surface of the semiconductor substrate; Wherein, along the thickness direction of the semiconductor substrate, the number of layers of the first nanostructure included in the first all-around gate transistor is less than the number of layers of the second nanostructure included in the second all-around gate transistor; each layer of the first nanostructure includes a first semiconductor material portion, and each layer of the first semiconductor material portion is integrally formed with the corresponding layer of the second nanostructure and is aligned along the thickness direction of the semiconductor substrate; The first nanostructure in any layer has a first spacing with an adjacent first structure, and the first structure is the semiconductor substrate and / or the first nanostructure in an adjacent layer; the second nanostructure in any layer has a second spacing with an adjacent second structure, and the second structure is the semiconductor substrate and / or the second nanostructure in an adjacent layer, and the first spacing is greater than the second spacing; the thickness of the gate dielectric layer included in the first ring-gate transistor is greater than the thickness of the gate dielectric layer included in the second ring-gate transistor.

2. The semiconductor device according to claim 1, wherein: Among all the first nanostructures in the same first ring-gate transistor, at least the first nanostructure at the top layer also includes a second semiconductor material portion surrounding the first semiconductor material portion; the carrier mobility of the second semiconductor material portion is greater than the carrier mobility of the first semiconductor material portion.

3. The semiconductor device according to claim 2, characterized in that When at least two layers of the first nanostructures further include the second semiconductor material portion, in all layers of the first nanostructures including the second semiconductor material portion, the thicknesses of different second semiconductor material portions included in different layers of the first nanostructures gradually increase along a direction away from the semiconductor substrate; The materials of different second semiconductor material parts included in different layers of the first nanostructures are the same; or, the materials of different second semiconductor material parts included in different layers of the first nanostructures are partially different.

4. The semiconductor device according to claim 2, characterized in that The materials of the first semiconductor material portion and the second semiconductor material portion include silicon, silicon germanium or germanium; The germanium content in the second semiconductor material portion is at least 20% higher than the germanium content in the first semiconductor material portion.

5. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate; forming a first all-around gate transistor and a second all-around gate transistor on the semiconductor substrate; The first ring-gate transistor and the second ring-gate transistor are arranged on the semiconductor substrate at intervals along a direction parallel to the surface of the semiconductor substrate; wherein, along the thickness direction of the semiconductor substrate, the number of layers of the first nanostructure included in the first ring-gate transistor is less than the number of layers of the second nanostructure included in the second ring-gate transistor; each layer of the first nanostructure includes a first semiconductor material portion, and each layer of the first semiconductor material portion is integrally formed with the corresponding layer of the second nanostructure and aligned along the thickness direction of the semiconductor substrate; any layer of the first nanostructure has a first spacing with an adjacent first structure, and the first structure is the semiconductor substrate and / or the first nanostructure of the adjacent layer; any layer of the second nanostructure has a second spacing with an adjacent second structure, and the second structure is the semiconductor substrate and / or the second nanostructure of the adjacent layer, and the first spacing is greater than the second spacing; the thickness of the gate dielectric layer included in the first ring-gate transistor is greater than the thickness of the gate dielectric layer included in the second ring-gate transistor.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The step of forming a first gate-all-around transistor and a second gate-all-around transistor on the semiconductor substrate comprises: A first active structure and a second active structure are formed on the semiconductor substrate, which are spaced apart from each other; the first active structure comprises at least two layers of first semiconductor material parts, and first source / drain regions included in a first all-around gate transistor disposed on both sides of the at least two layers of first semiconductor material parts along a length direction; the second active structure comprises at least two layers of first semiconductor material parts, and second source / drain regions included in a second all-around gate transistor disposed on both sides of the at least two layers of first semiconductor material parts along a length direction; the first active structure and the second active structure comprise the same number of first semiconductor material parts and are integrally formed; the spacing between two adjacent layers of first semiconductor material parts in the first active structure is equal to the spacing between two adjacent layers of first semiconductor material parts in the second active structure; Forming a first dielectric layer covering the periphery of the first active structure including at least two layers of first semiconductor material portion, and a second dielectric layer surrounding the periphery of the first dielectric layer; the first dielectric layer and the second dielectric layer are made of different materials, and the top of the second dielectric layer is flush with the top of the first dielectric layer; Under the protection of the mask structure, the second dielectric layer and the first dielectric layer are etched respectively by an etching process to process the at least two layers of the first semiconductor material parts included in the first active structure exposed layer by layer, so as to obtain the first nanostructure included in the first ring-gate transistor; the mask structure covers the periphery of the at least two layers of the first semiconductor material parts included in the second active structure.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The step of etching the second dielectric layer and the first dielectric layer respectively under the protection of the mask structure to process the at least two layers of the first semiconductor material portion included in the first active structure exposed layer by layer comprises: Under the protection of the mask structure, the second dielectric layer is subjected to a first back-etching process until the pre-reserved layer located above the top layer to be removed is completely exposed; the top height of the second dielectric layer after the first back-etching process is not higher than the minimum bottom height of the exposed pre-reserved layer, and is not lower than M / N of the thickness of the top layer to be removed; the pre-reserved layer is the first semiconductor material portion overlapping with the position where the corresponding first nanostructure is located; the layer to be removed is the first semiconductor material portion that does not form at least a portion of the first nanostructure correspondingly; N is a positive integer greater than 1, M is a positive integer greater than or equal to 1, and M>N; removing at least a portion of the first dielectric layer that is exposed outside the second dielectric layer along a thickness direction of the semiconductor substrate; A second semiconductor material portion is formed on the periphery of the exposed structure by a deposition process, so that the exposed pre-reserved layer forms at least a portion of the first nanostructure corresponding thereto; the carrier mobility of the second semiconductor material portion is greater than the carrier mobility of the first semiconductor material portion; Performing a second back-etching process on the second dielectric layer until the to-be-removed layer located on the top layer is exposed; the top height of the second dielectric layer after the second back-etching process is not higher than the bottom height of the to-be-removed layer located on the top layer, and is not lower than the top height of the remaining pre-reserved layer; At least the portion of the first dielectric layer exposed outside the second dielectric layer along the thickness direction of the semiconductor substrate is removed; and the exposed layer to be removed is removed; Repeat the above operation until the second semiconductor material portion is formed on the periphery of the pre-reserved layer located at the bottom layer; removing a remaining portion of the second dielectric layer and a remaining portion of the first dielectric layer; The remaining layer to be removed is removed to obtain a first nanostructure included in the first all-around gate transistor.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: M of N is greater than or equal to 1 / 5 and less than or equal to 2 / 3; And / or, the first dielectric layer is formed by atomic layer deposition or selective oxidation process.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: Before forming the second semiconductor material portion on the periphery of the exposed structure by a deposition process, when the top height of the first dielectric layer is lower than the top height of the layer to be removed located at the top layer, the exposed layer to be removed is removed while removing the portion of the second semiconductor material portion located on the layer to be removed; And / or, before forming the second semiconductor material portion on the periphery of the exposed structure using a deposition process, the top height of the first dielectric layer is not less than Q / P of the thickness of the layer to be removed on the top layer; Q / P is greater than or equal to 1 / 5 and less than or equal to 2 / 3.

10. The method for manufacturing a semiconductor device according to any one of claims 5 to 9, characterized in that: The material of the first dielectric layer includes: at least one of silicon oxide, silicon nitride and silicon oxynitride; And / or, the material of the second dielectric layer includes: at least one of SiCO, SiCON and SiO2-SiF4.

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