Ferroelectric field effect transistor based on gate stack optimization and preparation method thereof

Abstract

The invention discloses a ferroelectric field effect transistor based on gate stack optimization and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The gate laminated structure optimized by the FeFET comprises an aluminum oxide channel interface layer, a double-layer hafnium zirconium oxide ferroelectric layer, an aluminum oxide gate interface layer and a gate metal electrode which are sequentially stacked on top silicon of a substrate, the double-layer hafnium-zirconium-oxide ferroelectric layer comprises an upper hafnium-zirconium-oxide ferroelectric layer and a lower hafnium-zirconium-oxide ferroelectric layer which are consistent in thickness, and an aluminum oxide middle interface layer between the two hafnium-zirconium-oxide ferroelectric layers. According to the novel FeFET gate stack structure design, through collaborative optimization between the ferroelectric layers and the interface layers, MW is increased, meanwhile, the stress of the interface layers is reduced, durability is optimized in a multi-bit storage FeFET unit, D2D fluctuation is restrained in a FeFET with the reduced size, the limitation of the tradeoff effect is successfully broken through, and the performance of the device is improved. And comprehensive improvement of the storage density and reliability of the FeFET is realized. The size of the prepared FeFET is reduced by adopting the electron beam lithography technology, so that the integration density of the FeFET is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of micro-nanoelectronics, and in particular relates to a novel high storage density and high reliability ferroelectric field effect transistor (FeFET) based on gate stack optimization and a preparation method thereof. Background Art

[0002] Modern memory architecture mainly includes cache represented by CPU register unit and static random access memory (SRAM), main memory represented by dynamic random access memory (DRAM), and external storage represented by flash memory (Flash) and hard disk drive (HDD). In the memory hierarchy, the access speed of memory increases from bottom to top, but the capacity decreases and the cost increases. There is a large difference in access speed and capacity between main memory and external storage, and this performance gap limits the efficiency of information transmission between different memories. In order to fill this gap, the academic community has proposed the concept of storage-class memory (SCM), which mainly includes spin transfer torque-magnetic random access memory (STT-MRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), ferroelectric random access memory (FeRAM) and ferroelectric field effect transistor (FeFET).

[0003] Among many candidates, hafnium oxide-based ferroelectric field-effect transistors (FeFETs) are considered to be one of the most promising storage-class memories due to their unique three-terminal structure, miniaturization, high speed, and ultra-low power consumption. They can be used in advanced three-dimensional memories and new in-memory computing architectures. However, to date, the further development and large-scale application of FeFETs are still limited by their low storage density and reliability, and the trade-off between the two is the core challenge facing device optimization. For example, when the size of FeFETs is scaled down to increase the integration density, the reduction in the number of grains caused by the reduction in size will cause serious device-to-device (D2D) fluctuations due to the coexistence of polycrystalline and multiphase ferroelectric layers; and when the storage window (MW) of FeFETs is increased to increase the number of bits per storage unit, the huge electric field stress at the interface of the FeFET gate stack will cause serious durability degradation. Therefore, in the current study, the existing FeFETs can optimize these indicators to a size of less than 100nm, more than 3 bits per unit storage, or a durability of more than 10 6 However, it is very difficult to achieve these ideal storage performances at the same time. Therefore, it is necessary to further study the optimization methods of FeFET devices to synergistically improve storage density and reliability and break through the limitations of the above trade-off effects. Summary of the invention

[0004] In view of the problems existing in the above-mentioned prior art, the present invention proposes a ferroelectric field effect transistor (FeFET) based on gate stack optimization and a preparation method thereof. The optimized gate stack structure includes a double-layer hafnium zirconium oxide ferroelectric layer and a three-layer aluminum oxide interface layer, which can reduce the size of the FeFET and simultaneously optimize the storage density and reliability of the FeFET.

[0005] The technical solution of the present invention is as follows:

[0006] A ferroelectric field effect transistor (FeFET) based on gate stack optimization, comprising a silicon substrate, a source, a drain, a gate stack structure and a gate metal electrode, wherein the silicon substrate comprises a bottom silicon, a buried oxide layer and a top silicon from bottom to top, a gate stack structure is arranged on the top silicon, a source region and a drain region are arranged on the substrate buried oxide layer on both sides of the top silicon below the gate stack structure, a gate metal electrode is arranged on the gate stack structure, and the space outside each component region on the substrate buried oxide layer is filled with a passivation layer material, and through holes for contacting the gate metal electrode, the source and the drain are reserved in the passivation layer, and the contact metal electrode is provided. The metal fills the through hole and covers the passivation layer; the characteristic is that the gate stack structure is: an aluminum oxide channel interface layer is arranged on the top silicon layer, a double-layer hafnium zirconium oxide ferroelectric layer is arranged on the aluminum oxide channel interface layer, the double-layer hafnium zirconium oxide ferroelectric layer includes a lower hafnium zirconium oxide ferroelectric layer, an aluminum oxide intermediate interface layer and an upper hafnium zirconium oxide ferroelectric layer from bottom to top, the thickness of the lower hafnium zirconium oxide ferroelectric layer is consistent with the thickness of the upper hafnium zirconium oxide ferroelectric layer, an aluminum oxide gate interface layer is arranged on the double-layer hafnium zirconium oxide ferroelectric layer, and the gate metal electrode is arranged on the aluminum oxide gate interface layer.

[0007] Furthermore, the silicon substrate adopts a fully depleted SOI wafer as a substrate; for n-type FeFET, the silicon substrate selects an n-type silicon substrate, and for p-type FeFET, the silicon substrate selects a p-type silicon substrate; the p-type silicon substrate can adopt a silicon substrate doped with lower concentration of boron, etc., and the n-type silicon substrate can adopt a silicon substrate doped with lower concentration of arsenic or phosphorus, etc.

[0008] Furthermore, in the silicon substrate, the thickness of the top silicon layer is 10-15 nm, the thickness of the buried oxide layer of the silicon dioxide substrate below the top silicon layer is 15-30 nm, and the thickness of the entire silicon substrate is 500 μm.

[0009] Furthermore, the thickness of the aluminum oxide channel interface layer is 1 to 3 nm.

[0010] Furthermore, the upper and lower hafnium zirconium oxide ferroelectric layers in the double-layer hafnium zirconium oxide ferroelectric layer have the same thickness, each layer has a thickness of 6-10 nm, and the ratio of hafnium atoms to zirconium atoms in the hafnium zirconium oxide material is 1:1.

[0011] Furthermore, the aluminum oxide intermediate interface layer in the double-layer hafnium zirconium oxide ferroelectric layer is a thin aluminum oxide layer with a thickness of 1 to 2 nm.

[0012] Furthermore, the aluminum oxide gate interface layer is a thin aluminum oxide layer with a thickness of 2 to 6 nm.

[0013] Furthermore, the passivation layer is made of silicon dioxide with a thickness of 300-700 nm.

[0014] Furthermore, the material of the gate metal electrode is selected from metallic materials such as TiN, TaN or W; the gate metal electrode should have a small resistivity to reduce the contact resistance; in addition, the gate metal electrode also needs to have a certain thermal stability and mechanical strength, and needs to form a certain stress relative to the ferroelectric layer to induce stable ferroelectricity in the ferroelectric layer; at the same time, the selected gate metal electrode should have a suitable work function, and form a suitable electron and hole barrier height between the aluminum oxide gate interface layer, thereby facilitating the tunneling and capture of electrons and holes.

[0015] Furthermore, the source, drain and gate contact metal materials include but are not limited to Al, Pt, Cr, Cu, Au, Ti and the like; the contact metal should have a low resistivity and form a good ohmic contact with the source and drain to reduce the contact resistance.

[0016] The present invention also provides a method for preparing the ferroelectric field effect transistor based on gate stack optimization, comprising the following steps:

[0017] (1) Define the active area on the SOI silicon substrate, then use the photoresist as a barrier layer to etch away the top silicon of the non-active area, leak out the buried oxide layer underneath and form device isolation, and then remove the photoresist;

[0018] (2) removing the natural oxide layer on the top silicon surface of the active area silicon substrate;

[0019] (3) growing an aluminum oxide channel interface layer by atomic layer deposition on the top silicon layer of the active area;

[0020] (4) growing a double layer of hafnium zirconium oxide ferroelectric layer on the aluminum oxide channel interface layer by atomic layer deposition, first depositing a lower hafnium zirconium oxide HZO ferroelectric layer, then an aluminum oxide middle interface layer, and finally depositing an upper hafnium zirconium oxide HZO ferroelectric layer;

[0021] (5) growing an aluminum oxide gate interface layer on the upper hafnium zirconium oxide (HZO) ferroelectric layer by atomic layer deposition;

[0022] (6) growing a gate metal electrode material on the aluminum oxide gate interface layer by physical vapor deposition (PVD);

[0023] (7) defining the gate region by electron beam lithography, using electron beam photoresist as a barrier layer, and then dry etching to remove the gate metal electrode material, the aluminum oxide gate interface layer, the double-layer hafnium zirconium oxide ferroelectric layer and the aluminum oxide channel interface layer in the non-gate region;

[0024] (8) using photoresist and gate region as barrier layers, forming source and drain regions on the top silicon layer of the substrate on both sides of the gate region by self-aligned ion implantation, with the middle of the source and drain regions being the channel region;

[0025] (9) Rapid thermal annealing (RTP) is performed on the entire chip to simultaneously activate the ferroelectricity of the mixed ferroelectric layer and the ions injected into the source and drain regions;

[0026] (10) growing a silicon dioxide passivation layer over the entire wafer by chemical vapor deposition (CVD);

[0027] (11) Then, the contact hole patterns of the gate, source, and drain regions are defined by ultraviolet lithography, and the photoresist is used as a barrier layer. The silicon dioxide passivation layer in the contact hole region is removed by dry etching and wet etching to form a through hole, and then the photoresist is removed;

[0028] (12) depositing source, drain, and gate contact metals on the entire wafer by sputtering, evaporation, or other physical vapor deposition methods, wherein the contact metals fill the contact holes and cover the surface above the silicon dioxide passivation layer;

[0029] (13) defining the pattern of the contact metal electrodes of the gate, source, and drain by ultraviolet lithography, using the photoresist as a barrier layer, and removing the contact metal in the remaining area by dry etching to ensure that the etching is carried through to the silicon dioxide passivation layer, and then removing the photoresist;

[0030] (14) Finally, the alloy is annealed to form an ohmic contact between the contact metal and the source and drain.

[0031] Furthermore, in step (2), a diluted hydrofluoric acid solution or a hydrofluoric acid buffered etching solution BHF is used to remove the natural oxide layer on the top silicon surface of the active area.

[0032] Furthermore, in the steps (3), (4) and (5), the aluminum oxide interface layer and the double-layer hafnium zirconium oxide ferroelectric layer are preferably grown by atomic layer deposition (ALD), and trimethylaluminum (TMA), tetrakis(dimethylamino)hafnium (TDMAHf), tetrakis(dimethylamino)zirconium (TDMAZr) and water are used as precursors of aluminum, hafnium, zirconium and oxygen, respectively.

[0033] Furthermore, the atomic layer deposition (ALD) aluminum oxide interface layer and the double hafnium zirconium oxide ferroelectric layer of steps (3), (4) and (5) can be deposited in the same atomic layer deposition (ALD) step, and the growth order of the material can be controlled by setting the pulse sequence of different components in the program, thereby simplifying the process steps.

[0034] Furthermore, the two hafnium zirconium oxide ferroelectric layers in the double hafnium zirconium oxide ferroelectric layer in step (4) are grown by atomic layer deposition. During the atomic layer deposition cycle, the ratio of the doped atoms is controlled by controlling the cycle ratio of hafnium oxide and zirconium oxide. The ratio of hafnium atoms to zirconium atoms in the finally formed hafnium zirconium oxide solid solution layer is 1:1, thereby ensuring good ferroelectricity.

[0035] Furthermore, in step (6), gate metal electrode material is deposited by evaporation, sputtering or other physical vapor deposition (PVD) methods.

[0036] Furthermore, in the self-aligned ion implantation of step (8), ion implantation is performed on the entire wafer using appropriate energy and dosage to ensure that a source and a drain with a low resistivity can be formed without damaging other structures.

[0037] Furthermore, the temperature and time of the rapid thermal annealing process in step (9) need to simultaneously meet the conditions for mixed ferroelectric layer activation and source-drain activation, and need to be flexibly adjusted according to the ferroelectric layer material, gate material, implanted ion type and dosage, and the approximate range is: annealing temperature is 500-900°C, and annealing time is 10-120s.

[0038] Furthermore, in step (14), the alloy annealing temperature is 400-450° C. and the time is about 30 minutes.

[0039] The technical effects of the present invention are as follows:

[0040] 1. By introducing an aluminum oxide gate interface layer into the FeFET gate stack structure, when the FeFET is programmed and erased, charges tunnel from the gate metal layer to the gate interface layer, and their type is consistent with the ferroelectric polarization charge, thereby increasing the influence of ferroelectric polarization on the FeFET channel and increasing the storage window, which helps to store multi-bit data in a single FeFET storage unit and increase the storage density.

[0041] In the present invention, a thin layer of aluminum oxide of about 3nm is inserted between the ferroelectric layer and the gate metal electrode as a gate interface layer, and charge capture on one side of the gate metal electrode is introduced. Different from the channel interface layer structure in the conventional FeFET, the captured charge of the gate interface layer is of the same type as the ferroelectric polarization charge, which is equivalent to increasing the influence of the ferroelectric polarization on the channel, so that the storage window can be increased. For example, when a positive voltage is applied to the FeFET gate for programming, the polarization direction in the ferroelectric layer is directed from the electrode to the channel, and under the action of the positive voltage, the holes of the gate metal electrode cross the gate interface layer barrier, tunnel to the gate interface layer and the ferroelectric layer and are captured, and after the voltage is removed, they stay in place due to the blocking part of the barrier layer. The holes staying between the gate interface layer and the ferroelectric layer tend to induce negative charges in the channel, which is consistent with the induced charge caused by the ferroelectric polarization. Therefore, the effect of the captured holes on the channel is the same as that of the ferroelectric polarization on the channel, which is equivalent to enhancing the modulation effect of the ferroelectric polarization on the FeFET channel, and the threshold voltage shift is larger. Similarly, when a negative voltage is applied to the FeFET gate for erasure, the electrons tunneling from the gate electrode to the gate interface layer also equivalently enhance the effect of the ferroelectric polarization in the ferroelectric layer from the channel to the gate metal electrode, further increasing the threshold voltage offset. Therefore, under the action of the captured charge in the gate interface layer, the difference between the threshold voltages of the programming and erased states of the FeFET, that is, the storage window, increases. By comparing the prepared gate stack optimized FeFET with an aluminum oxide gate interface layer with a conventional structure FeFET without a gate interface layer, under the same other conditions, the storage window of the conventional structure FeFET is 1.7V, while the storage window of the gate stack optimized FeFET is 4.3V, achieving more than a two-fold increase in the storage window. This proves that after the introduction of the gate interface layer, the charge capture on the gate metal electrode side has a boosting effect on the storage window.

[0042] Second, by inserting a thin layer of aluminum oxide (aluminum oxide intermediate interface layer) into the hafnium zirconium oxide ferroelectric layer to form a double-layer hafnium zirconium oxide ferroelectric structure, the grain size in the ferroelectric layer can be reduced. After the FeFET size is reduced, it can ensure that there are still a sufficient number of ferroelectric grains in the ferroelectric layer, thereby suppressing the D2D fluctuations caused by different ferroelectric phase components and structures.

[0043] Due to the coexistence of polycrystalline and multiphase in the ferroelectric layer, when the size of FeFET is reduced, the number of grains in the ferroelectric layer decreases, resulting in the composition ratio of the ferroelectric phase to the non-ferroelectric phase, the grain orientation, etc. being more affected by the randomness of a single grain. Therefore, the polarization intensity of the ferroelectric layer and the threshold voltage fluctuation related to it are larger, that is, the D2D fluctuation increases. After inserting a thin layer of aluminum oxide of about 1nm in the middle of the hafnium zirconium oxide ferroelectric layer, the aluminum oxide thin layer separates the hafnium zirconium oxide layer into two parts, upper and lower. During ferroelectric annealing and crystallization, the continuous growth of ferroelectric grains in the upper and lower hafnium zirconium oxide layers will be hindered by the aluminum oxide thin layer in the middle. Therefore, compared with the single-layer hafnium zirconium oxide ferroelectric layer of the same thickness, the size of the ferroelectric grains in the double-layer hafnium zirconium oxide ferroelectric layer is smaller. Therefore, when the size of FeFET is reduced, there are still enough ferroelectric grains in the double-layer hafnium zirconium oxide ferroelectric layer, and the influence of the randomness of a single grain is reduced, thereby suppressing the fluctuation of FeFET under size miniaturization. By comparing the single-layer hafnium zirconium oxide ferroelectric layer with the double-layer hafnium zirconium oxide ferroelectric layer, it was extracted that the grain size of the single-layer hafnium zirconium oxide ferroelectric layer is 10.24nm, while the grain size of the double-layer hafnium zirconium oxide ferroelectric layer is 8.69nm. The prepared single-layer hafnium zirconium oxide ferroelectric layer FeFET was compared with the double-layer hafnium zirconium oxide ferroelectric layer FeFET with optimized gate stack. When the channel length of FeFET is 500nm, the average standard deviation of the threshold voltage of the single-layer hafnium zirconium oxide FeFET and the double-layer hafnium zirconium oxide FeFET are 77.1mV and 62.1mV respectively; when the channel length is reduced to 100nm, the average standard deviation of the single-layer hafnium zirconium oxide FeFET is 125mV, while the average standard deviation of the double-layer hafnium zirconium oxide FeFET is only 82.8mV. This result proves that the thin aluminum oxide layer inserted into the double-layer hafnium zirconium oxide ferroelectric layer can effectively reduce the size of ferroelectric grains and suppress the D2D fluctuation caused by the miniaturization of FeFET.

[0044] It is precisely because of the larger storage window and smaller D2D fluctuation of the gate stack optimized FeFET compared to the conventional gate stack structure FeFET that the gate stack optimized FeFET can store 3 bits of information per cell and there is no overlap between each storage state, while the conventional gate stack structure can only store 2 bits of information per cell. Therefore, the gate stack optimized FeFET increases the storage density compared to the conventional gate stack structure FeFET, and also increases the reliability of each storage state.

[0045] 3. The gate interface layer, the intermediate interface layer and the channel interface layer of the present invention are all made of high-quality aluminum oxide materials with high relative dielectric constant, thereby reducing the electric field strength in each interface layer, suppressing the breakdown of the interface layer, and improving the durability of the FeFET. In addition, compared with the conventional gate stack structure without a gate interface layer and an intermediate interface layer, the present invention optimizes the intermediate gate interface layer and the intermediate interface layer of the gate stack structure, introduces an additional voltage divider relationship, reduces the electric field strength of the channel interface layer, suppresses charge capture from the channel to the gate stack, and further improves the durability of the FeFET.

[0046] Compared with silicon dioxide with a relative dielectric constant of 3.9 commonly used in conventional FeFET gate stack structures, each interface layer in the present invention uses an aluminum oxide material with a relative dielectric constant of about 9. The increase in the relative dielectric constant leads to a decrease in the electric field strength of each interface layer, thereby delaying the breakdown of the dielectric layer caused by the electric field stress and increasing durability. In addition, the aluminum oxide materials used for each interface layer in the present invention are grown by atomic layer deposition. Compared with the film formed by conventional chemical vapor deposition, this material deposition method is denser, has a smaller trap density, and is of higher quality, and also suppresses the breakdown of the interface layer caused by stress. In conventional gate stack structure FeFETs, the charge accumulated at the channel interface layer with the number of cycles is the main reason for the durable degradation of FeFETs. In the gate stack optimized FeFET of the present invention, the additional gate interface layer and the intermediate interface layer will also form a partial pressure, resulting in a further reduction in the electric field strength of the channel interface layer, thereby reducing the charge tunneling and charge capture from the channel to the gate stack, suppressing the durable cycle degradation of FeFETs, and improving durability. By comparing the prepared conventional gate stack structure FeFET with the FeFET with optimized gate stack structure, the conventional gate stack structure FeFET was 6 After 10 cycles, the storage window gradually decreases and 6 After the cycle, the storage performance fails. However, the FeFET with optimized gate stack structure in the present invention has a high storage performance of more than 5×10 6 After the first cycle, the storage window still remained above 2V without breakdown. The improvement in durability verifies that the FeFET with optimized gate stack structure has better reliability.

[0047] Fourth, the electron beam lithography technology used in the present invention reduces the size of the prepared FeFET, thereby improving the integration density of the FeFET. Compared with the conventional ultraviolet lithography technology, the electron beam lithography technology used in the present invention can break through the size limitation of the ultraviolet lithography technology and reduce the channel length of the FeFET to less than 100nm, so that more FeFET storage units can be integrated in the same area, further increasing the storage density of the FeFET.

[0048] Finally, the FeFET based on the gate stack structure optimization of the present invention simultaneously achieves a size reduction below 100nm, a storage window of 4.3V, a storage of three bits per cell, and a durability of more than 5×10 6 Cycle times and other indicators. Compared with the conventional gate stack structure FeFET, the FeFET based on the gate stack structure optimization of the present invention realizes an increase in storage window, a decrease in D2D fluctuations, an increase in the number of storage bits per unit and an improvement in durability, while optimizing the storage density and reliability of FeFET, breaking through the constraints of the trade-off between the two. In addition, most of the materials, equipment and techniques used in the preparation process of the present invention have been widely used in advanced CMOS nodes, so the preparation process is fully compatible with advanced node CMOS processes, and the gate stack structure optimized FeFET design of the present invention is expected to be applied to large-scale integrated circuit manufacturing. In addition, the FeFET gate stack structure design can also be extended to the vertical channel FeFET, and applied to the field of three-dimensional memory with high storage density and high reliability.

[0049] The novel FeFET gate stack structure design of the present invention increases the MW while reducing the stress of the interface layer through the coordinated optimization between the ferroelectric layers and the interface layer, optimizes the durability in the FeFET unit of multi-bit storage, and suppresses the D2D fluctuation in the FeFET with reduced size, successfully breaking through the limitation of the trade-off effect and realizing the comprehensive improvement of the storage density and reliability of FeFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a cross-sectional schematic diagram of a FeFET based on gate stack structure optimization prepared in an embodiment of the present invention;

[0051] Figure 2 Schematic diagram of the steps of preparing FeFET based on gate stack structure optimization according to an embodiment of the present invention, wherein:

[0052] (a) is a cross-sectional view of a SOI substrate after the active area pattern is first defined by UV lithography and then the top silicon of the non-active area is removed by dry etching;

[0053] (b) is a cross-sectional view after three layers of aluminum oxide interface layer and two layers of hafnium zirconium oxide ferroelectric layer are grown by atomic layer deposition (ALD) on the basis of (a);

[0054] (c) is a cross-sectional view after the gate metal electrode is grown by physical vapor deposition (PVD) such as sputtering on the basis of (b);

[0055] (d) is a cross-sectional view after the gate area pattern is defined by electron beam lithography based on (c), and the gate metal and gate dielectric layer (double hafnium zirconium oxide ferroelectric layer and three-layer aluminum oxide interface layer) in the non-gate area are removed by dry etching;

[0056] (e) is a cross-sectional view after forming source and drain regions by self-aligned ion implantation based on (d) using photoresist and gate region as barrier layers and annealing;

[0057] (f) is a cross-sectional view after a silicon dioxide passivation layer is grown by chemical vapor deposition (CVD) on the basis of (e);

[0058] (g) is a cross-sectional view of the process of (f) in which the contact hole pattern is first defined by UV lithography, the silicon dioxide in the contact hole is removed by dry etching and wet etching, and then the contact metal is grown by physical vapor deposition (PVD) such as sputtering and evaporation;

[0059] (h) is a cross-sectional view after the contact metal electrode pattern is defined by UV lithography and the contact metal in the remaining area is removed by dry etching based on (g);

[0060] Figure 1 and Figure 2 middle:

[0061] 1——The bottom silicon of SOI substrate 2——The buried oxide layer of SOI substrate

[0062] 3——Top silicon of SOI substrate 4——Aluminum oxide channel interface layer

[0063] 5——Lower hafnium zirconium oxide ferroelectric layer 6——Aluminum oxide intermediate interface layer

[0064] 7——Upper hafnium zirconium oxide ferroelectric layer 8——Aluminum oxide gate interface layer

[0065] 9——Gate metal electrode 10——Source

[0066] 11——leakage 12——silicon dioxide passivation layer

[0067] 13——Contact with metal electrode

[0068] Figure 3 The conventional gate stack structure FeFET prepared in the example of the present invention and the FeFET with optimized gate stack structure after programming and erasing are shown in FIG. d -V g curve;

[0069] Figure 4are the grazing-incidence X-ray diffraction results of a single-layer hafnium zirconium oxide HZO ferroelectric layer with equal total thickness and a double-layer hafnium zirconium oxide HZO+HZO ferroelectric layer with a thin layer of aluminum oxide inserted therein, prepared in the embodiment of the present invention, wherein (b) is an enlarged view of the 30.5° peak corresponding to the ferroelectric phase grains in (a);

[0070] Figure 5 1 is a threshold voltage distribution diagram of each storage state of a FeFET with a conventional gate stack structure and a FeFET with an optimized gate stack structure prepared in an embodiment of the present invention;

[0071] Figure 6 The relationship between the threshold voltage of the programming and erasing states of the conventional stacked structure FeFET and the FeFET with optimized gate stack structure prepared in the embodiment of the present invention and the number of cycles. DETAILED DESCRIPTION

[0072] The present invention will be further described below through specific embodiments in conjunction with the accompanying drawings.

[0073] like Figure 1 As shown, the high storage density and high reliability FeFET based on gate stack optimization prepared in this embodiment includes a bottom silicon layer 1 of a SOI substrate, a buried oxide layer 2 of a SOI substrate, a top silicon layer 3 of a SOI substrate, an aluminum oxide channel interface layer 4, a lower hafnium zirconium oxide ferroelectric layer 5, an aluminum oxide intermediate interface layer 6, an upper hafnium zirconium oxide ferroelectric layer 7, an aluminum oxide gate interface layer 8, a gate metal electrode 9, a source 10, a drain 11, a silicon dioxide passivation layer 12 and a contact metal electrode 13. Among them, the aluminum oxide channel interface layer 4 is located on the top silicon 3, the lower hafnium zirconium oxide ferroelectric layer 5 is located on the aluminum oxide channel interface layer 4, the aluminum oxide intermediate interface layer 6 is located between the lower hafnium zirconium oxide ferroelectric layer 5 and the upper hafnium zirconium oxide ferroelectric layer 7, the aluminum oxide gate interface layer 8 is located on the upper hafnium zirconium oxide ferroelectric layer 7, the gate metal electrode 9 is located on the aluminum oxide gate interface layer 8, the source 10 and the drain 11 are located on both sides below the gate stack structure in the top silicon 3 of the SOI substrate, and the gate, source and drain contact metal electrodes 13 are connected to the gate metal electrode 9, the source 10 and the drain 11 respectively.

[0074] The process steps of the FeFET preparation method are as follows: Figure 2 As shown, specifically including:

[0075] 1) Define the pattern of the active area on the SOI substrate by UV lithography, then use the photoresist as a barrier layer, and use dry etching to remove the top silicon 3 (thickness of about 12nm) of the non-active area, ensuring appropriate over-etching to expose the buried oxide layer 2 (thickness of about 20nm) underneath, so as to achieve isolation between different FeFETs, and finally remove the photoresist, such as Figure 2 As shown in (a);

[0076] 2) Use a diluted hydrofluoric acid solution or a hydrofluoric acid buffered etching solution BHF to remove the natural oxide layer on the surface of the top silicon 3 in the active area. Pay attention to controlling the etching time to avoid etching the exposed buried oxide layer in the non-active area.

[0077] 3) Then, a 2 nm thick aluminum oxide channel interface layer 4 is deposited on the top silicon layer of the active area by atomic layer deposition (ALD);

[0078] 4) Depositing an 8 nm thick lower hafnium zirconium oxide ferroelectric layer 5, a 1 nm thick aluminum oxide middle interface layer 6, and an 8 nm thick upper hafnium zirconium oxide ferroelectric layer 7 on the aluminum oxide channel interface layer by atomic layer deposition (ALD), wherein the atomic ratio of hafnium atoms to zirconium atoms in the two hafnium zirconium oxide ferroelectric layers 5 and 7 is 1:1, as shown in FIG. Figure 2 As shown in (b);

[0079] 5) depositing a 3 nm thick aluminum oxide gate interface layer 8 on the upper hafnium zirconium oxide HZO ferroelectric layer by atomic layer deposition (ALD);

[0080] 6) A 50 nm thick gate metal electrode 9 is grown on the aluminum oxide gate interface layer by physical vapor deposition (PVD) such as evaporation or sputtering. Figure 2 As shown in (c);

[0081] 7) Define the gate region by electron beam lithography, then use electron beam photoresist as a barrier layer, and use dry etching to remove the gate metal electrode 9 and the underlying gate stack structure in the non-gate region, such as Figure 2 As shown in (d);

[0082] 8) According to the n-type or p-type FeFET, select appropriate ions to implant the whole wafer with an energy of 5 keV and a surface dose of 10 14 cm -2 In the gate region, due to the blocking of the photoresist and the gate stack structure, the ions will not be injected into the gate structure, and the ions on both sides of the gate stack structure are injected into the top silicon 3 to form the source 10 and drain 11 regions, and the middle of the source and drain regions is the channel region. For n-type FeFET, high-concentration arsenic or phosphorus and other elements can be used to form n-type sources and drains, and for p-type FeFET, high-concentration boron and other elements can be used to form p-type sources and drains.

[0083] 9) Then the whole chip is subjected to rapid thermal annealing treatment, the annealing temperature is 700-900℃, the annealing time is 10-60s, the annealing conditions need to be flexibly adjusted according to the doping ratio of the ferroelectric layer, the gate type and the type, concentration and dosage of the implanted ions, etc., and it is necessary to ensure that the ferroelectricity of the ferroelectric layer and the implanted ions in the source and drain regions are activated at the same time, such as Figure 2 As shown in (e);

[0084] 10) A thick silicon dioxide passivation layer 12 (about 500 nm) is grown on the entire wafer by chemical vapor deposition (CVD). Figure 2 As shown in (f);

[0085] 11) Define the through-hole pattern of the gate metal electrode 9, source 10, and drain 11 regions by ultraviolet lithography, and form through-holes in the silicon dioxide passivation layer 12 by combining dry etching and wet etching, ensuring over-etching to expose the gate metal electrode 9, source 10, and drain 11 regions, and then remove the photoresist.

[0086] 12) Then, source, drain, and gate contact metal electrodes 13 (about 1 μm) are grown on the entire wafer by physical vapor deposition (PVD) methods such as sputtering and evaporation. The contact metal fills the through holes and covers the surface of the silicon dioxide passivation layer 12. Figure 2 As shown in (g);

[0087] 13) Define the pattern of the contact metal electrode 13 by ultraviolet lithography, use the photoresist as a barrier layer, and use dry etching to remove the contact metal in the remaining area, ensuring that the etching reaches the silicon dioxide passivation layer 12, and then remove the photoresist, such as Figure 2 As shown in (h);

[0088] 14) Finally, alloy annealing is performed to form ohmic contact between the contact metal and the source and drain. The alloy annealing temperature is 400-450° C. and the time is about 30 minutes.

[0089] At this point, the high storage density and high reliability FeFET based on gate stack optimization can be obtained.

[0090] A similar method was used to prepare a comparative device, namely a FeFET with a conventional gate stack structure. Compared with the FeFET with optimized gate stack, it lacks the aluminum oxide gate interface layer and the intermediate interface layer. Its ferroelectric layer is a single-layer hafnium zirconium oxide ferroelectric layer with a thickness of 16 nm. The other steps are the same.

[0091] Figure 3 The conventional gate stack structure FeFET prepared by the example of the present invention and the FeFET with optimized gate stack structure after programming and erasing are shown in FIG. d -V g Curve. By setting the fixed current to 10 -3 The threshold voltage is extracted at μA / μm. The storage window of conventional structure FeFET is about 1.7V, while the storage window of FeFET based on gate stack structure optimization is about 4.3V.

[0092] Figure 4It is the grazing-incidence X-ray diffraction result of a single-layer hafnium zirconium oxide HZO ferroelectric layer of equal total thickness and a double-layer hafnium zirconium oxide HZO+HZO ferroelectric layer with a thin layer of aluminum oxide inserted in the middle, prepared in the embodiment of the present invention. Among them, (b) is an enlarged view of the 30.5° peak corresponding to the ferroelectric phase grains in (a). Using the grain size calculation formula in Figure (b), the average grain size in the single-layer hafnium zirconium oxide and the double-layer hafnium zirconium oxide ferroelectric layer is calculated based on the half-peak width of the 30.5° peak of the single-layer hafnium zirconium oxide and the double-layer hafnium zirconium oxide ferroelectric layer. Among them, the average grain size in the single-layer hafnium zirconium oxide ferroelectric layer is 10.24nm, while the average grain size in the double-layer hafnium zirconium oxide ferroelectric layer is 8.69nm. Therefore, the thin layer of aluminum oxide inserted in the double-layer hafnium zirconium oxide ferroelectric layer can effectively reduce the ferroelectric grain size.

[0093] Figure 5 This is a threshold voltage distribution diagram of each storage state of the FeFET with a conventional gate stack structure and the FeFET with an optimized gate stack structure prepared in the embodiment of the present invention. The threshold voltages of 20 devices of each of the two FeFETs with channel lengths of 500nm and 100nm were extracted for comparison. The average standard deviation of the threshold voltage of the FeFET with a conventional gate stack structure is 77.1mV and 125mV when the channel length is 500nm and 100nm, respectively, while the average standard deviation of the threshold voltage of the FeFET with an optimized gate stack structure is 62.1mV and 82.8mV when the channel length is 500nm and 100nm, respectively, which is smaller than that of the conventional gate stack structure FeFET, that is, the D2D fluctuation is smaller. In addition, since the storage window of the optimized gate stack structure FeFET is larger than that of the conventional gate stack structure FeFET, and the D2D fluctuation is also smaller, 3-bit storage can be achieved in the FeFET with an optimized gate stack structure, and there is no overlap between each storage state. In contrast, conventional gate stack structure FeFETs can only store 2 bits per cell, so the storage density of FeFETs with optimized gate stack structures is higher.

[0094] Figure 6 The relationship between the threshold voltage of the programming and erasing states of the conventional stacked structure FeFET and the optimized gate stacked structure FeFET prepared in the embodiment of the present invention and the cycle number. The storage window of the conventional gate stacked structure FeFET gradually decreases with the increase of the cycle number. 6 After 10 cycles, the voltage is less than 0.5V and the 6 After 10 cycles, the device breaks down and fails. 6 After the first cycle, the storage window still remained above 2V, and no breakdown occurred. Therefore, the durability of FeFET with optimized gate stack structure was improved compared with that of FeFET with conventional stack structure.

[0095] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A FeFET device based on gate stack optimization, comprising a silicon substrate, a source, a drain, a gate stack structure and a gate metal electrode, wherein the silicon substrate comprises a bottom silicon, a buried oxide layer and a top silicon from bottom to top, a gate stack structure is arranged on the top silicon, a source region and a drain region are arranged on the substrate buried oxide layer on both sides of the top silicon below the gate stack structure, a gate metal electrode is arranged on the gate stack structure, and the space outside each component region on the substrate buried oxide layer is filled with a passivation layer material, and through holes for contacting metal electrodes of the gate metal electrode, source and drain are reserved in the passivation layer, and the contact metal fills the through holes and covers the passivation layer; characterized in that The gate stack structure is as follows: an aluminum oxide channel interface layer is arranged on the top silicon layer, a double-layer hafnium zirconium oxide ferroelectric layer is arranged on the aluminum oxide channel interface layer, the double-layer hafnium zirconium oxide ferroelectric layer includes, from bottom to top, a lower hafnium zirconium oxide ferroelectric layer, an aluminum oxide intermediate interface layer and an upper hafnium zirconium oxide ferroelectric layer, the thickness of the lower hafnium zirconium oxide ferroelectric layer is consistent with the thickness of the upper hafnium zirconium oxide ferroelectric layer, an aluminum oxide gate interface layer is arranged on the double-layer hafnium zirconium oxide ferroelectric layer, and the gate metal electrode is arranged on the aluminum oxide gate interface layer.

2. The FeFET device based on gate stack optimization according to claim 1, characterized in that: The thickness of the aluminum oxide channel interface layer is 1-3 nm.

3. The FeFET device based on gate stack optimization according to claim 1, characterized in that: The upper and lower hafnium zirconium oxide ferroelectric layers in the double-layer hafnium zirconium oxide ferroelectric layer have the same thickness, each layer has a thickness of 6-10 nm, and the ratio of hafnium atoms to zirconium atoms in the hafnium zirconium oxide material is 1:

1.

4. The FeFET device based on gate stack optimization according to claim 1, characterized in that: The aluminum oxide intermediate interface layer in the double-layer hafnium zirconium oxide ferroelectric layer is a thin aluminum oxide layer with a thickness of 1 to 2 nm.

5. The FeFET device based on gate stack optimization according to claim 1, characterized in that: The aluminum oxide gate interface layer is a thin aluminum oxide layer with a thickness of 2 to 6 nm.

6. A method for preparing a FeFET device based on gate stack optimization as claimed in claim 1, characterized in that: The following steps are involved: (1) Define the active area on the SOI silicon substrate, then use the photoresist as a barrier layer to etch away the top silicon of the non-active area, leak out the buried oxide layer underneath and form device isolation, and then remove the photoresist; (2) removing the natural oxide layer on the top silicon surface of the active area silicon substrate; (3) growing an aluminum oxide channel interface layer by atomic layer deposition on the top silicon layer of the active area; (4) growing a double layer of hafnium zirconium oxide ferroelectric layer on the aluminum oxide channel interface layer by atomic layer deposition, first depositing a lower hafnium zirconium oxide HZO ferroelectric layer, then an aluminum oxide middle interface layer, and finally depositing an upper hafnium zirconium oxide HZO ferroelectric layer; (5) growing an aluminum oxide gate interface layer on the upper hafnium zirconium oxide (HZO) ferroelectric layer by atomic layer deposition; (6) growing a gate metal electrode material on the aluminum oxide gate interface layer by physical vapor deposition; (7) defining the gate region by electron beam lithography, using electron beam photoresist as a barrier layer, and then dry etching to remove the gate metal electrode material, the aluminum oxide gate interface layer, the double-layer hafnium zirconium oxide ferroelectric layer and the aluminum oxide channel interface layer in the non-gate region; (8) using photoresist and gate region as barrier layers, forming source and drain regions on the top silicon layer of the substrate on both sides of the gate region by self-aligned ion implantation, with the middle of the source and drain regions being the channel region; (9) subjecting the entire wafer to rapid thermal annealing to simultaneously activate the ferroelectricity of the mixed ferroelectric layer and the ions injected into the source and drain regions; (10) growing a silicon dioxide passivation layer on the entire wafer by chemical vapor deposition; (11) Then, the contact hole patterns of the gate, source, and drain regions are defined by ultraviolet lithography, and the photoresist is used as a barrier layer. The silicon dioxide passivation layer in the contact hole region is removed by dry etching and wet etching to form a through hole, and then the photoresist is removed; (12) depositing source, drain, and gate contact metals on the entire wafer by sputtering, evaporation, or other physical vapor deposition methods, wherein the contact metals fill the contact holes and cover the surface above the silicon dioxide passivation layer; (13) defining the pattern of the contact metal electrodes of the gate, source, and drain by ultraviolet lithography, using the photoresist as a barrier layer, and removing the contact metal in the remaining area by dry etching to ensure that the etching is carried through to the silicon dioxide passivation layer, and then removing the photoresist; (14) Finally, the alloy is annealed to form an ohmic contact between the contact metal and the source and drain.

7. The preparation method according to claim 6, characterized in that: In the steps (3), (4) and (5), an atomic layer deposition method is used to grow an aluminum oxide interface layer and a double-layer hafnium zirconium oxide ferroelectric layer, and trimethylaluminum (TMA), tetrakis(dimethylamino)hafnium (TDMAHf), tetrakis(dimethylamino)zirconium (TDMAZr) and water are used as precursors of aluminum, hafnium, zirconium and oxygen, respectively.

8. The preparation method according to claim 6, characterized in that: The atomic layer deposition aluminum oxide interface layer and the double hafnium zirconium oxide ferroelectric layer in step (3), step (4) and step (5) are deposited in the same atomic layer deposition step. The growth sequence of the material is controlled by setting the pulse sequence of different components in the program, thereby simplifying the process steps.

9. The preparation method according to claim 6, characterized in that: The two hafnium zirconium oxide ferroelectric layers in the double hafnium zirconium oxide ferroelectric layer in step (4) are grown by atomic layer deposition. During the atomic layer deposition cycle, the ratio of the number of cycles of hafnium oxide and zirconium oxide is controlled to control the ratio of the doped atoms. The ratio of hafnium atoms to zirconium atoms in the finally formed hafnium zirconium oxide solid solution layer is 1:1, thereby ensuring good ferroelectricity.

10. The preparation method according to claim 6, characterized in that: The temperature and time of the rapid thermal annealing process in step (9) are as follows: the annealing temperature is 500-900°C and the annealing time is 10-120s; the alloy annealing temperature in step (14) is 400-450°C and the time is 30 minutes.

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