Preparation method of semiconductor structure, semiconductor structure, device and equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. The method comprises the following steps: forming an active structure; forming a first pseudo gate structure of the first transistor based on the first active structure; reversing the wafer and thinning the substrate; forming a second pseudo gate structure of the second transistor based on the second active structure; etching a second interlayer dielectric layer with a preset height in a second source-drain region of the second transistor to form a first groove; depositing a first mask material in the first groove to form a first hard mask; exposing a first active structure in a first gate region of the first transistor and a second active structure in a second gate region of the second transistor; forming a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor; forming a second gate structure and a second metal interconnection layer of a second transistor; reversing and exposing the first active structure; and forming a first gate structure and a first metal interconnection layer of the first transistor.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] Currently, the consistency of gate dielectrics in the fabrication process of stacked transistors remains an urgent problem to be solved. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus to solve the problem of gate dielectric consistency during the processing of flip-chip stacked transistors.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, wherein the semiconductor structure includes a first transistor and a second transistor arranged in a stacked manner; the method includes: forming an active structure on a substrate; the active structure includes a first active structure and a second active structure arranged in a stacked manner; based on the first active structure, forming a first dummy gate structure, a first spacer, a first interlayer dielectric layer and a first source-drain structure of the first transistor; flipping the wafer and thinning the substrate; based on the second active structure, forming a second dummy gate structure, a second spacer, a second interlayer dielectric layer and a second source-drain structure of the second transistor; etching the second interlayer dielectric layer in a second source-drain region of the second transistor to a preset height to form a first groove; A first mask material is deposited in the groove to form a first hard mask; under the masking action of the first hard mask, the second dummy gate structure and the first dummy gate structure are removed to expose the first active structure located in the first gate region of the first transistor and the second active structure located in the second gate region of the second transistor; an insulating material is deposited on the surface of the first active structure and the second active structure to form a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor; the first gate dielectric layer and the second gate dielectric layer are integrally formed; a second gate structure and a second metal interconnection layer of the second transistor are formed; the first active structure is flipped and exposed; and a first gate structure and a first metal interconnection layer of the first transistor are formed.

[0006] In some possible embodiments, after forming an active structure on the substrate, the method further includes: depositing a second mask material on the first active structure to form a second hard mask; the second hard mask covers the first surface of the first active structure; the first surface is a surface of the first active structure away from the second active structure; depositing a third mask material on the surface of the active structure and the substrate to form a third hard mask; depositing oxide on the active structure and the substrate to form a first shallow trench isolation structure; the first shallow trench isolation structure wraps the active structure.

[0007] In some possible embodiments, before forming a first pseudo-gate structure, a first spacer, a first interlayer dielectric layer and a first source-drain structure of a first transistor based on the first active structure, the above method further includes: removing a portion of the first shallow trench isolation structure that wraps the first active structure to expose the first active structure; removing the second hard mask to expose the first surface of the first active structure.

[0008] In some possible embodiments, after inverting and thinning the substrate, the method further includes: etching a second active structure of a preset height to form a second groove; depositing a second mask material in the second groove to form a fourth hard mask; the fourth hard mask covers a second surface of the second active structure, the second surface being a surface of the second active structure away from the first active structure; and removing a portion of the first shallow trench isolation structure that wraps the second active structure to expose the second active structure.

[0009] In some possible embodiments, before depositing an insulating material on the surface of the first active structure and the second active structure to form a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor, the method further includes: removing a fourth hard mask and a third hard mask located in the first gate region and the second gate region to expose the first active structure located in the first gate region and the second active structure in the second gate region.

[0010] In some possible embodiments, after depositing insulating material on the surfaces of the first active structure and the second active structure to form a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor, the method further includes: depositing oxide on the first gate region and the second gate region to form a second shallow trench isolation structure; removing a portion of the second shallow trench isolation structure that wraps the second active structure to expose the second active structure.

[0011] In some possible embodiments, after inverting and exposing the first active structure, the process includes: etching the first interlayer dielectric layer located in the first source and drain region of the first transistor to a preset height to form a third groove; depositing a first mask material in the third groove to form a fifth hard mask; and under the masking action of the fifth hard mask, removing the second shallow trench isolation structure located in the first gate region to expose the first gate region.

[0012] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared using a method as described in the first aspect, and the semiconductor structure includes: a first transistor; a second transistor; the first transistor and the second transistor are stacked; wherein the first gate dielectric layer in the first transistor and the second gate dielectric layer in the second transistor are integrally formed.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, under the masking action of the first hard mask, the first dummy gate structure and the second dummy gate structure are removed to expose the first active structure located in the first gate region and the second active structure located in the second gate region; then, insulating material is simultaneously deposited on the surfaces of the first active structure and the second active structure to form a first gate dielectric layer and a second gate dielectric layer; the first gate dielectric layer and the second gate dielectric layer formed in the same process can solve the problem of gate dielectric consistency in the processing of flip-chip stacked transistors.

[0016] Furthermore, the integrally formed gate dielectric can also avoid process and position deviation of the gate dielectric between the first transistor and the second transistor, thereby improving the gate control capability of the semiconductor structure.

[0017] Furthermore, the method for preparing the semiconductor structure described in the present application has a weaker requirement for the operation intensity of the aspect ratio process, has stronger operability, and a simpler process.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0020] Figure 1A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of a semiconductor structure in an embodiment of the present application;

[0022] FIG. 3A to FIG. 3M A schematic diagram of a process for preparing a semiconductor structure in an embodiment of the present application;

[0023] The above pictures:

[0024] 10. semiconductor structure; 11. first transistor; 111. first fin structure; 112. first source-drain structure; 113. first spacer; 114. first interlayer dielectric layer; 115. first gate dielectric layer; 116. first gate structure; 117. first source-drain metal; 118. first metal interconnect layer; 12. second transistor; 121. second fin structure; 122. second source-drain structure; 123. second spacer; 124. second interlayer dielectric layer; 125. second gate dielectric layer; 126. second gate structure; 127. second source-drain metal; 128. second metal interconnect layer ; 13. shallow trench isolation layer; 14. second insulating layer; 15. second carrier wafer; 21. substrate; 22. pad oxide layer; 23. second hard mask; 24. third hard mask; 25. first shallow trench isolation structure; 261. first pseudo gate structure; 262. second pseudo gate structure; 27. second groove; 281. first initial hard mask; 28. fourth hard mask; 29. ​​first semiconductor material layer; 31. first insulating layer; 32. first carrier wafer; 33. second source and drain grooves; 34. first groove; 35. first hard mask; 36. second shallow trench isolation structure; 37. fifth hard mask. DETAILED DESCRIPTION

[0025] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0026] As Moore's Law continues to deepen, after the gate-all-around (GAA) technology node, continuing to promote transistor size miniaturization is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space by stacking three-dimensional transistors, which helps to further improve transistor integration density and circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0027] However, in the process flow of stacked transistors, the gate dielectric of the front transistor and the gate dielectric of the back transistor are formed in two steps, which results in differences in gate control capabilities between the front transistor and the back transistor and a problem of gate dielectric consistency.

[0028] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a semiconductor structure to solve the problem of gate dielectric consistency during the processing of flip-chip stacked transistors.

[0029] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0030] In some embodiments, the semiconductor structure includes: a first transistor; a second transistor; the first transistor and the second transistor are stacked; wherein the first gate dielectric layer in the first transistor and the second gate dielectric layer in the second transistor are integrally formed.

[0031] It can be understood that in the semiconductor structure, the first transistor and the second transistor are stacked, and in the stacking direction of the first transistor and the second transistor, the first transistor and the second transistor are self-aligned. In the semiconductor structure, the first gate dielectric layer in the first transistor and the second gate dielectric layer in the second transistor are integrally formed, that is, the first gate dielectric layer and the second gate dielectric layer are formed by the same process.

[0032] In an embodiment of the present application, the first transistor and the second transistor in the semiconductor structure can be transistors of the same type, such as any one of the following: a fin field effect transistor (FinFET), a nanosheet field effect transistor (NSFET), a planar transistor, a vertical transistor, and a complementary field effect transistor (CFET), etc.

[0033] Figure 2 The semiconductor structure composed of fin field effect transistors is combined below Figure 2 The schematic diagram of the semiconductor structure shown illustrates the method for preparing the semiconductor structure provided in the embodiment of the present application.

[0034] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application. In some embodiments, the semiconductor structure includes a first transistor and a second transistor that are stacked. Figure 1As shown, the method for preparing the semiconductor structure may include:

[0035] S101, forming an active structure on a substrate, wherein the active structure includes a first active structure and a second active structure stacked together.

[0036] It can be understood that by forming a hard mask on the substrate, the active structure is patterned, and under the masking effect of the hard mask, the substrate is etched to form the active structure. The active structure includes a first active structure and a second active structure, and the first active structure and the second active structure are formed by the same process, so that the active area of ​​the first transistor and the active area of ​​the second transistor are self-aligned, and further, the self-alignment of the active area makes the first transistor and the second transistor self-aligned.

[0037] In some embodiments, before S101, the method for preparing the semiconductor structure may further include: providing a substrate. Selecting a suitable substrate according to the type of the first transistor and the second transistor. For example, when the first transistor and the second transistor are fin-type field effect transistors, a silicon (Si) substrate may be selected; when the first transistor and the second transistor are nanosheet field effect transistors, a stacked layer formed by stacking silicon and silicon germanium (SiGe) in sequence may be selected as the substrate.

[0038] In some embodiments, the shape of the active structure formed is different depending on the type of the first transistor and the second transistor. For example, when the first transistor and the second transistor are fin-type field effect transistors, the active structure is a fin-shaped structure; when the first transistor and the second transistor are nanosheet field effect transistors, the active structure is a plurality of parallel nanosheet structures or a plurality of parallel nanowire structures.

[0039] It should be noted that, in the process of forming the active structure by etching, a substrate with a preset height needs to be retained, and the retained substrate can play a role in supporting the active structure.

[0040] S102 , based on the first active structure, forming a first dummy gate structure, a first spacer, a first interlayer dielectric layer and a first source-drain structure of a first transistor.

[0041] It is understandable that, according to a standard process for manufacturing transistors, other structures in the first transistor, such as a first dummy gate structure, a first spacer, a first interlayer dielectric layer and a first source-drain structure, can be formed based on the first active structure.

[0042] In some embodiments, the above S102 may include: photolithography to open the first gate region of the first transistor; depositing polysilicon in the first gate region to form a first dummy gate structure; depositing insulating material on the sidewalls of the first dummy gate structure to form a first spacer; depositing dielectric material in other regions of the first transistor except the first gate region to form a first interlayer dielectric layer; removing the first interlayer dielectric layer; performing source and drain epitaxial growth in the first source and drain region of the first transistor to form a first source and drain structure; and re-depositing dielectric material to form a first interlayer dielectric layer.

[0043] S103, flipping the wafer and thinning the substrate.

[0044] It can be understood that after forming the first dummy gate structure, the first spacer, the first interlayer dielectric layer and the first source-drain structure, the first transistor and the wafer can be flipped so that the substrate is placed upward, and then the substrate is thinned until the second active structure is exposed.

[0045] In some embodiments, the substrate may be thinned by a chemical-mechanical planarization (CMP) process.

[0046] In some possible implementations, before the above S103, the method for preparing the above semiconductor structure may further include: depositing an insulating material on a surface of the first transistor away from the second active structure to form a first insulating layer; and bonding the first insulating layer to the first carrier wafer.

[0047] In the embodiment of the present application, the bonded first carrier wafer can provide physical support for the flipped first transistor after inversion, thereby effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

[0048] It should be noted that the insulating material forming the first insulating layer can be selected according to actual needs, and the embodiments of the present application do not specifically limit this.

[0049] S104 , based on the second active structure, forming a second dummy gate structure, a second spacer, a second interlayer dielectric layer and a second source-drain structure of the second transistor.

[0050] It is understandable that, according to a standard process for manufacturing transistors, other structures in the second transistor, such as a second dummy gate structure, a second spacer, a second interlayer dielectric layer and a second source-drain structure, can be formed based on the second active structure.

[0051] In the embodiments of the present application, the first source-drain structure represents the source and / or drain in the first transistor. Accordingly, other expressions related to "source and drain" in the embodiments of the present application are all used to represent "source and / or drain", such as: the second source-drain structure, the first source-drain region and the second source-drain region, etc.

[0052] In some embodiments, the above S104 may include: photolithography to open the second gate region of the second transistor; depositing polysilicon in the second gate region to form a second dummy gate structure; depositing insulating material on the sidewalls of the second dummy gate structure to form a second spacer; depositing dielectric material in other regions of the second transistor except the second gate region to form a second interlayer dielectric layer; removing the second interlayer dielectric layer; performing source and drain epitaxial growth in the second source and drain region of the second transistor to form a second source and drain structure; and re-depositing dielectric material to form a second interlayer dielectric layer.

[0053] S105 , etching the second interlayer dielectric layer in the second source / drain region of the second transistor to a preset height to form a first groove.

[0054] It can be understood that the second interlayer dielectric layer wraps the second active structure and the second source and drain structure in the second source and drain region of the second transistor. By selectively etching back the second interlayer dielectric layer to a preset height, a first groove is formed on the retained (ie, unetched) second interlayer dielectric layer.

[0055] S106 , depositing a first mask material in the first groove to form a first hard mask.

[0056] It can be understood that depositing the first mask material in the first groove can form a first hard mask, the first hard mask is located on the first interlayer dielectric layer, and the height of the first hard mask in the horizontal direction is the same as the height of the second dummy gate structure in the horizontal direction.

[0057] In some embodiments, the above S106 may include depositing a first mask material on the first groove and the second dummy gate structure at the same time until the first groove is filled; at this time, since the heights of the first groove and the second dummy gate structure are different in the horizontal direction, the deposited first mask material has a different height in the horizontal direction, and the first mask material located on the second dummy gate structure is removed by chemical mechanical planarization, so that the second dummy gate structure is exposed, and the first mask material retained in the first groove forms a first hard mask.

[0058] S107 , under the masking effect of the first hard mask, removing the second dummy gate structure and the first dummy gate structure to expose the first active structure located in the first gate region of the first transistor and the second active structure located in the second gate region of the second transistor.

[0059] It can be understood that the first hard mask is located in the second source and drain region, and the first hard mask is used to limit the etching region. Then, the second dummy gate structure and the first dummy gate structure can be removed by selective etching. After removing the second dummy gate structure and the first dummy gate structure, the first active structure located in the first gate region and the second active structure located in the second gate region are exposed.

[0060] S108, depositing insulating material on the surfaces of the first active structure and the second active structure to form a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor, wherein the first gate dielectric layer and the second gate dielectric layer are integrally formed.

[0061] It can be understood that in the first gate region and the second gate region, an insulating material is deposited on the surface of the active structure (i.e., the first active structure and the second active structure) to form a gate dielectric layer (i.e., the first gate dielectric layer and the second gate dielectric layer). The gate dielectric layer is formed by one process, that is, the first gate dielectric layer and the second gate dielectric layer are integrally formed.

[0062] S109, forming a second gate structure and a second metal interconnection layer of a second transistor.

[0063] It can be understood that metal material is deposited in the second gate region to form a second gate structure; then, under the action of a pre-set hard mask, a portion of the second interlayer dielectric layer is etched to form a second source-drain metal groove; metal material is filled in the second source-drain metal groove to form a second source-drain metal, and the second source-drain metal is in contact with the second source-drain structure; and post-processing is performed on the second gate structure and the second source-drain metal to form a second metal interconnection layer.

[0064] In some embodiments, since the second transistor is formed based on the second active structure after flipping the first transistor, the second transistor and the first transistor are stacked “back to back” and are self-aligned.

[0065] S110 , flipping the wafer and exposing the first active structure.

[0066] It can be understood that after the second transistor is formed, the second transistor can be flipped over so that the first carrier wafer is placed facing upward, and then the first carrier wafer and the first insulating layer are removed by chemical mechanical planarization.

[0067] In some embodiments, before the above S110, the method for preparing the above semiconductor structure may further include: depositing an insulating material on a surface of the second transistor away from the first active structure to form a second insulating layer; and bonding the second insulating layer to a second carrier wafer.

[0068] In the embodiment of the present application, the bonded second carrier wafer can provide physical support for the flipped second transistor after inversion, thereby effectively preventing the second transistor from being broken by external force during the preparation of the first transistor.

[0069] It should be noted that the insulating material forming the second insulating layer can be selected according to actual needs, and the embodiments of the present application do not specifically limit this.

[0070] S111 , forming a first gate structure and a first metal interconnection layer of a first transistor.

[0071] It can be understood that a metal material is deposited in the first gate region to form a first gate structure; then, under the action of a pre-set hard mask, a portion of the first interlayer dielectric layer is etched to form a first source-drain metal groove; a metal material is filled in the first source-drain metal groove to form a first source-drain metal, and the first source-drain metal is in contact with the first source-drain structure; and a back-end interconnection process is performed on the first gate structure and the first source-drain metal to form a first metal interconnection layer.

[0072] In some possible embodiments, after the above S101, the preparation method of the above semiconductor structure may further include: depositing a second mask material on the first active structure to form a second hard mask; the second hard mask covers the first surface of the first active structure; the first surface is a surface of the first active structure away from the second active structure; depositing a third mask material on the surface of the active structure and the substrate to form a third hard mask; depositing oxide on the active structure and the substrate to form a first shallow trench isolation structure; the first shallow trench isolation structure wraps the active structure.

[0073] It can be understood that a second mask material of a preset height is deposited on the first surface of the first active structure to form a second hard mask covering the first surface. Then, a third mask material is deposited on the surface of the active structure and the substrate by an atomic layer deposition (ALD) process to form a third hard mask, and the third hard mask covers the surface of the active structure and the substrate. Through deposition and filling processes, a first shallow trench isolation (STI) structure is formed on the active structure and the substrate. The first shallow trench isolation (STI) structure is formed of oxide. The height of the first shallow trench isolation structure is greater than the height of the active structure, and the first shallow trench isolation structure can wrap the active structure.

[0074] In some embodiments, the oxide forming the first shallow trench isolation structure may include any of the following: silicon dioxide (SiO 2), silicon carbide (SiCO), etc. Other oxides may also be selected according to actual needs, which is not specifically limited in the embodiments of the present application.

[0075] In some embodiments, after providing the substrate and before forming the active structure, the method for preparing the semiconductor structure may further include: depositing an oxide with a preset height on the substrate to form a pad oxide layer. The pad oxide layer can provide a buffer for the substrate and reduce the stress effect on the substrate.

[0076] In some possible implementations, before the above S102, the method for preparing the above semiconductor structure may further include: removing a portion of the first shallow trench isolation structure that wraps the first active structure to expose the first active structure; and removing the second hard mask to expose the first surface of the first active structure.

[0077] It is understandable that before forming the first dummy gate structure, the first spacer, the first interlayer dielectric layer and the first source-drain structure based on the first active structure, the first active structure needs to be exposed, that is, the portion of the first shallow trench isolation structure that wraps the first active structure and the second hard mask are removed.

[0078] In some possible embodiments, after S103 above, the method for preparing the semiconductor structure may further include: etching a second active structure of a preset height to form a second groove; depositing a second mask material in the second groove to form a fourth hard mask; the fourth hard mask covers a second surface of the second active structure, and the second surface is a surface of the second active structure away from the first active structure; and removing a portion of the first shallow trench isolation structure that wraps the second active structure to expose the second active structure.

[0079] It can be understood that a portion of the second active structure is etched, and the height of the etched second active structure is lower than the height of the first shallow trench isolation structure, forming a second groove. The second groove is filled with a second mask material to form a fourth hard mask. Next, the portion of the first shallow trench isolation structure that wraps the second active structure is removed by etching to expose the second active structure. At this time, the fourth hard mask protects the second active structure and prevents the second active structure from being etched.

[0080] In some embodiments, the process of forming the fourth hard mask may include: depositing a second mask material on the second groove and the first shallow trench isolation structure, and due to the height difference between the second groove and the first shallow trench isolation structure, the height of the second mask material on the first shallow trench isolation structure is greater than the height of the second mask material in the second groove. Then, by a chemical mechanical planarization process, the second mask material on the first shallow trench isolation structure is removed, and the second mask material remaining in the second groove is formed to form a fourth hard mask.

[0081] In some possible embodiments, before the above S108, the method for preparing the above semiconductor structure may further include: removing the fourth hard mask and the third hard mask located in the first gate region and the second gate region to expose the first active structure located in the first gate region and the second active structure located in the second gate region.

[0082] It can be understood that the third hard mask wrapping the active structure in the first gate region and the second gate region is removed by selective isotropic etching, and then the fourth hard mask is removed by selective anisotropic etching, so that the active structure in the gate region is exposed.

[0083] In some possible embodiments, after S108 above, the method for preparing the semiconductor structure may further include: depositing oxide in the first gate region and the second gate region to form a second shallow trench isolation structure; removing a portion of the second shallow trench isolation structure that wraps the second active structure to expose the second active structure.

[0084] It can be understood that the removal of the first dummy gate structure and the second dummy gate structure exposes the first gate region and the second gate region; then, oxide is deposited in the first gate region and the second gate region to form a second shallow trench isolation structure; then, a portion of the second shallow trench isolation structure is removed by back etching to expose the second active structure.

[0085] It should be noted that the oxide used to prepare the second shallow trench isolation structure and the oxide used to prepare the first shallow trench isolation structure may be the same oxide.

[0086] In some possible embodiments, after the above S110, the method for preparing the above semiconductor structure may further include: etching the first interlayer dielectric layer located in the first source and drain region of the first transistor to a preset height to form a third groove; depositing a first mask material in the third groove to form a fifth hard mask; under the masking action of the fifth hard mask, removing the second shallow trench isolation structure located in the first gate region to expose the first gate region.

[0087] It can be understood that the first interlayer dielectric layer wraps the first active structure and the first source-drain structure in the first source-drain region of the first transistor. By selectively etching back the first interlayer dielectric layer of a preset height, a third groove is formed on the retained (i.e., unetched) first interlayer dielectric layer. A first mask material is deposited in the third groove to form a fifth hard mask, which is located on the first interlayer dielectric layer, and the height of the fifth hard mask in the horizontal direction is the same as the height of the second shallow trench isolation structure in the horizontal direction. The second shallow trench isolation structure of a preset height is etched back so that the first active structure located in the first gate region and the first active structure located in the first gate region are exposed.

[0088] In some embodiments, the above-mentioned formation of the fifth hard mask may include simultaneously depositing a first mask material on the third groove and the second shallow trench isolation structure until the third groove is filled; at this time, since the heights of the third groove and the second shallow trench isolation structure in the horizontal direction are different, the heights of the deposited first mask material in the horizontal direction are also different, and the first mask material located on the second shallow trench isolation structure is removed by chemical mechanical planarization, so that the second shallow trench isolation structure is exposed, and the first mask material retained in the third groove forms the fifth hard mask.

[0089] In some embodiments, during the process of etching a portion of the second shallow trench isolation structure to expose the first active structure, the second shallow trench isolation structure of a preset height is retained, and the retained portion serves as a shallow trench isolation layer, which is used to isolate the first transistor from the second transistor.

[0090] In the embodiment of the present application, in order to achieve selective etching, the first mask material, the second mask material and the third mask material are different materials. The specific materials used can be set according to actual needs, and the embodiment of the present application does not make specific limitations on this.

[0091] Below, the semiconductor structure provided in the embodiment of the present application is described by taking the first transistor and the second transistor as fin-type field effect transistors as an example. Figure 2 This is a schematic diagram of a semiconductor structure in an embodiment of the present application. Figure 2 (a) is the design layout of the semiconductor structure. It should be noted that, for ease of understanding, only the fin structure, gate structure and source-drain structure are shown in the design layout; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction); (d) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the fin structure (i.e., CC' direction).

[0092] See also Figure 2 As shown, the semiconductor structure 10 includes: a first transistor 11 and a second transistor 12. The first transistor 11 and the second transistor 12 are stacked "back to back"; the first gate dielectric layer in the first transistor and the second gate dielectric layer in the second transistor are integrally formed.

[0093] Figure 2 The semiconductor structure 10 shown may be FIG. 3A to FIG. 3M The process shown is prepared FIG. 3A to FIG. 3M A schematic diagram of the preparation process of the semiconductor structure in an embodiment of the present application.

[0094] In one example, the preparation process of the semiconductor structure 10 may include the following steps:

[0095] Step 1: Provide a substrate 21 (see Figure 3A (a)). The substrate 21 is a silicon substrate.

[0096] Step 2: Deposit oxide on the substrate 21 to form a pad oxide layer 22 (see Figure 3A (b)).

[0097] Step 3: Form a fin structure according to a standard process for manufacturing transistors. The fin structure includes a first fin structure 111 and a second fin structure 121. Next, a second mask material is deposited on the first fin structure 111 to form a second hard mask 23 (see Figure 3A (c)).

[0098] In some embodiments, since the fin structures in the two transistors (i.e., the first fin structure 111 and the second fin structure 121) are formed in the same etching process, a larger etching depth can be selected during the etching process so that the height of the fin structure is sufficient to prepare the two transistors. In one example, the height of the fin structure can be greater than 100 nanometers (nm).

[0099] Step 4: Deposit a layer of third mask material on the surface of the first fin structure 111 and the upper surface of the substrate 21 by an atomic layer deposition process to form a third hard mask 24 (see Figure 3B (a)).

[0100] Step 5: Deposit and fill oxide on the substrate 21 and the fin structure to form a first shallow trench isolation structure 25. Next, a portion of the first shallow trench isolation structure 25 is etched back until the upper surface of the second hard mask 23 is exposed, so that the height of the second hard mask 23 in the horizontal direction is the same as the height of the first shallow trench isolation structure 25 after the etch back (see Figure 3B (b)).

[0101] Step 6: Etch the portion of the first shallow trench isolation structure 25 that wraps the first fin structure 111 to expose the first fin structure 111 (see Figure 3B (c)).

[0102] Step 7: epitaxially grow source and drain in the first source and drain region of the first transistor 11 to form a first source and drain structure 112; then, deposit polysilicon in the first gate region to form a first dummy gate structure 261; deposit insulating material on the sidewall of the first dummy gate structure 261 to form a first spacer 113; deposit an interlayer dielectric in the first source and drain region to form a first interlayer dielectric layer 114 (see Figure 3C (a)).

[0103] Step 8: Deposit insulating material on the first interlayer dielectric layer 114 and the first dummy gate structure 261 to form a first insulating layer 31; then, bond the first carrier wafer 32 and the first insulating layer 31 together; perform a flip process on the first transistor 11 that has not yet been formed, so that the substrate 21 is placed upward (see Figure 3C (b)).

[0104] Step 9: Remove the substrate 21 by wafer thinning process and perform chemical mechanical planarization until the first shallow trench isolation structure 25 is exposed (see Figure 3C (c)).

[0105] Step 10: Etch the second fin structure 121 to a preset height to form a second groove 27 (see Figure 3D (a)).

[0106] Step 11: Deposit a second mask material in the second groove 27 and on the first shallow trench isolation structure 25 to form a first initial hard mask 281 (see Figure 3D (b)).

[0107] Step 12: Through a chemical mechanical planarization process, the first initial hard mask 281 located on the first shallow trench isolation structure 25 is polished flat, and only the second mask material in the second groove 27 is retained to form a fourth hard mask 28 (see Figure 3D (c)).

[0108] Step 13: Etch the first shallow trench isolation structure 25 of a preset height to expose the first fin structure 111. Retain the first shallow trench isolation structure 25 of a preset height to form a shallow trench isolation layer 13 (see Figure 3E (a)).

[0109] Step 14: Deposit polysilicon on the shallow trench isolation layer 13 to form a first semiconductor material layer 29 (see Figure 3E (b)).

[0110] Step 15: Remove the first semiconductor material layer 29 in the second source and drain region by photolithography, and only retain the first semiconductor material layer 29 in the second gate region to form a second dummy gate structure 262 (see Figure 3E (c)).

[0111] Step 16: Deposit an insulating material on the sidewalls of the second dummy gate structure 262 to form a second spacer 123 (see Figure 3F (a)).

[0112] Step 17: Etch down the fourth hard mask 28 located in the second source / drain region and etch the second fin structure 121 located in the second source / drain region to a predetermined height to form a second source / drain groove 33 (see Figure 3F (b)).

[0113] Step 18: Perform source-drain epitaxial growth in the second source-drain groove 33 to form a second source-drain structure 122 (see Figure 3F (c)).

[0114] Step 19: Deposit dielectric material in the second source / drain region by flowable chemical vapor deposition (FCVD), and perform chemical mechanical planarization to form a second interlayer dielectric layer 124 (see Figure 3G (a)).

[0115] Step 20: Selectively etch back the second interlayer dielectric layer 124 to a preset height to form a first groove 34 (see Figure 3G (b)).

[0116] Step 21: Deposit a first mask material in the first groove 34 to form a first hard mask 35 (see Figure 3G (c)).

[0117] Step 22: Under the restriction of the shallow trench isolation layer 13 and the first hard mask 35, the second dummy gate structure 262 is selectively removed (see Figure 3H (a)).

[0118] Step 23: Remove the shallow trench isolation layer 13 located in the gate region by anisotropic etching (see Figure 3H (b)).

[0119] Step 24: Remove the first dummy gate structure 261 by selective isotropic etching (see Figure 3H (c)).

[0120] Step 25: Remove the third hard mask 24 (see Fig. 3I (a)).

[0121] Step 26: Remove the exposed fourth hard mask 28 by selective anisotropic etching (see Fig. 3I (b)).

[0122] Step 27: Deposit insulating material on the surfaces of the first fin structure 111 and the second fin structure 121 to form a first gate dielectric layer 115 and a second gate dielectric layer 125 (see Fig. 3I(c)).

[0123] Step 28: Deposit oxide in the gate region to fill the gate region and form a second shallow trench isolation structure 36 (see Figure 3J (a)).

[0124] Step 29: Etch back the second shallow trench isolation structure 36 to a preset height to expose the second gate region (see Figure 3J (b)).

[0125] Step 30: Deposit a metal material in the second gate region to form a second gate structure 126 (see Figure 3J (c)).

[0126] Step 31: Remove the first hard mask 35 located in the second source / drain region (see Figure 3K (a)).

[0127] Step 32: A second source-drain metal groove is formed by etching a portion of the second interlayer dielectric layer; then, a metal material is deposited in the second source-drain metal groove to form a second source-drain metal 127 (see Figure 3K (b)).

[0128] Step 33: Perform a back-end process on the second gate structure 126 and the second source-drain metal 127 to form a second metal interconnection layer 128 (see Figure 3K (c)).

[0129] Step 34: Deposit insulating material on the second metal interconnect layer 128 to form a second insulating layer 14, and bond the preset second carrier wafer 15 to the second insulating layer 14; then, flip the second transistor 12 so that the first carrier wafer 32 is placed upward (see Figure 3L (a)).

[0130] Step 35: Remove the first carrier wafer 32 and the first insulating layer 31 by chemical mechanical planarization. The chemical mechanical planarization process stops at the second shallow trench isolation structure 36 (see Figure 3L (b)).

[0131] Step 36: Etch back the first interlayer dielectric layer 114 to a preset height to form a third groove; deposit the first mask material in the third groove to form a fifth hard mask 37 (see Figure 3L (c)).

[0132] Step 37: Under the masking effect of the fifth hard mask 37, the second shallow trench isolation structure 36 located in the first gate region is etched, and the second shallow trench isolation structure 36 with a preset height is retained as the shallow trench isolation layer 13 (see Figure 3M (a)).

[0133] Step 38: Deposit a metal material in the first gate region to form a first gate structure 116 (see Figure 3M (b)).

[0134] Step 39: A first source-drain metal groove is formed by etching a portion of the first interlayer dielectric layer; then, a metal material is deposited in the first source-drain metal groove to form a first source-drain metal 117 (see Figure 3M (c)).

[0135] Step 40: Perform a back-end process on the first gate structure 116 and the first source / drain metal 117 to form a first metal interconnect layer 118 (see Figure 2 ).

[0136] At this point, the semiconductor structure 10 is manufactured according to the above manufacturing method.

[0137] It should be noted that the preparation method of the semiconductor structure described in the embodiment of the present application is also applicable to different types of transistors such as nanosheet field effect transistors, planar transistors, vertical transistors and complementary field effect transistors. The above method only takes fin-type field effect transistors as an example and is not used to limit the transistor type of the semiconductor structure of the embodiment of the present application.

[0138] In an embodiment of the present application, under the masking action of the first hard mask, the first dummy gate structure and the second dummy gate structure are removed to expose the first active structure located in the first gate region and the second active structure located in the second gate region; then, insulating material is simultaneously deposited on the surfaces of the first active structure and the second active structure to form a first gate dielectric layer and a second gate dielectric layer; the first gate dielectric layer and the second gate dielectric layer formed in the same process can solve the problem of gate dielectric consistency in the processing of flip-chip stacked transistors.

[0139] Furthermore, the integrally formed gate dielectric can also avoid process and position deviation of the gate dielectric between the first transistor and the second transistor, thereby improving the gate control capability of the semiconductor structure.

[0140] Furthermore, the method for preparing the semiconductor structure described in the embodiment of the present application has a weaker requirement on the operation intensity of the aspect ratio process, has stronger operability, and a simpler process.

[0141] Furthermore, the semiconductor structure provided in the embodiment of the present application can be detected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the semiconductor structure provided in the embodiment of the present application can be detected by TEM slicing. For example, the first gate dielectric layer and the second gate dielectric layer can be observed on the surface of the first active structure and the second active structure; in the AA' direction, it can be observed that there is no gate dielectric layer between the shallow trench isolation structure and the first gate structure, and there is no gate dielectric layer between the shallow trench isolation structure and the second gate structure; further indicating that the first gate dielectric layer and the second gate dielectric layer are integrally formed.

[0142] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 2 The semiconductor structure shown will not be described in detail here.

[0143] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 2 , I will not go into details here.

[0144] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0145] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The semiconductor structure includes a first transistor and a second transistor that are stacked; the method includes: An active structure is formed on a substrate; the active structure comprises a first active structure and a second active structure which are stacked; Based on the first active structure, a first dummy gate structure, a first spacer, a first interlayer dielectric layer and a first source-drain structure of the first transistor are formed; Flipping and thinning the substrate; Based on the second active structure, forming a second dummy gate structure, a second spacer, a second interlayer dielectric layer and a second source-drain structure of a second transistor; Etching the second interlayer dielectric layer in the second source / drain region of the second transistor to a preset height to form a first groove; depositing a first mask material in the first recess to form a first hard mask; Under the masking effect of the first hard mask, removing the second dummy gate structure and the first dummy gate structure to expose the first active structure located in the first gate region of the first transistor and the second active structure located in the second gate region of the second transistor; Depositing insulating material on the surfaces of the first active structure and the second active structure to form a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor; the first gate dielectric layer and the second gate dielectric layer are integrally formed; forming a second gate structure and a second metal interconnect layer for a second transistor; Flipping the wafer and exposing the first active structure; A first gate structure and a first metal interconnect layer of a first transistor are formed.

2. The method according to claim 1, characterized in that After forming the active structure on the substrate, the method further comprises: Depositing a second mask material on the first active structure to form a second hard mask; the second hard mask covers a first surface of the first active structure; the first surface is a surface of the first active structure away from the second active structure; depositing a third mask material on the surface of the active structure and the substrate to form a third hard mask; Oxide is deposited on the active structure and the substrate to form a first shallow trench isolation structure; the first shallow trench isolation structure wraps the active structure.

3. The method according to claim 2, characterized in that Before forming a first dummy gate structure, a first spacer, a first interlayer dielectric layer, and a first source-drain structure of a first transistor based on the first active structure, the method further includes: removing a portion of the first shallow trench isolation structure that wraps the first active structure to expose the first active structure; The second hard mask is removed to expose the first surface of the first active structure.

4. The method according to claim 3, characterized in that After flipping the wafer and thinning the substrate, the method further includes: Etching the second active structure to a preset height to form a second groove; Depositing a second mask material in the second groove to form a fourth hard mask; the fourth hard mask covers a second surface of the second active structure, the second surface being a surface of the second active structure away from the first active structure; A portion of the first shallow trench isolation structure that surrounds the second active structure is removed to expose the second active structure.

5. The method according to claim 4, characterized in that Before depositing insulating material on the surfaces of the first active structure and the second active structure to form a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor, the method further includes: The fourth hard mask and the third hard mask located in the first gate region and the second gate region are removed to expose the first active structure located in the first gate region and the second active structure located in the second gate region.

6. The method according to claim 1, characterized in that After depositing insulating material on the surfaces of the first active structure and the second active structure to form a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor, the method further includes: Depositing oxide on the first gate region and the second gate region to form a second shallow trench isolation structure; A portion of the second shallow trench isolation structure that surrounds the second active structure is removed to expose the second active structure.

7. The method according to claim 6, characterized in that After flipping the wafer and exposing the first active structure, the method further comprises: Etching the first interlayer dielectric layer in the first source and drain region of the first transistor to a preset height to form a third groove; depositing a first mask material in the third recess to form a fifth hard mask; Under the masking effect of the fifth hard mask, the second shallow trench isolation structure located in the first gate region is removed to expose the first gate region.

8. A semiconductor structure, characterized in that: Prepared by the method according to any one of claims 1 to 7, the semiconductor structure comprises: a first transistor; a second transistor; the first transistor and the second transistor are stacked; The first gate dielectric layer in the first transistor and the second gate dielectric layer in the second transistor are integrally formed.

9. A semiconductor device, characterized in that: include: The semiconductor structure as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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