Method of fabricating a semiconductor structure, semiconductor structure, device and apparatus

Abstract

The application provides a semiconductor structure preparation method, a semiconductor structure, a device and equipment. The method comprises the following steps: forming an active structure; forming a first dummy gate structure of a first transistor based on the first active structure; peeling and thinning a substrate; forming a second dummy gate structure of a second transistor based on a second active structure; etching a second interlayer dielectric layer in a second source / drain region of the second transistor to a preset height to form a first recess; depositing a first mask material in the first recess to form a first hard mask; exposing the first active structure in a first gate region of the first transistor and the second active structure in a second gate region of the second transistor; forming a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor; forming a second gate structure of the second transistor and a second metal interconnection layer; peeling and exposing the first active structure; and forming a first gate structure of the first transistor and a first metal interconnection layer.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a method for preparing a semiconductor structure, a semiconductor structure, a device, and an apparatus. Background Technology

[0002] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacking transistors, by integrating two or more layers of transistors in a vertical space, further increases transistor integration density and has become one of the important technologies for continuing the miniaturization of integrated circuits.

[0003] Currently, ensuring the consistency of the gate dielectric during the fabrication process of stacked transistors remains a problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, a device, and an apparatus to solve the problem of gate dielectric consistency during the fabrication process of flip-chip stacked transistors.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, the semiconductor structure including a first transistor and a second transistor stacked together; the method includes: forming an active structure on a substrate; the active structure including a first active structure and a second active structure stacked together; forming a first dummy gate structure, a first spacer, a first interlayer dielectric layer, and a first source / drain structure of the first transistor based on the first active structure; washing and thinning the substrate; forming a second dummy gate structure, a second spacer, a second interlayer dielectric layer, and a second source / drain structure of the second transistor based on the second active structure; etching the second interlayer dielectric layer at a predetermined height located in the second source / drain region of the second transistor to form a first groove; in the first A first mask material is deposited in a groove to form a first hard mask; under the masking action of the first hard mask, a second dummy gate structure and a first dummy gate structure are removed to expose a first active structure located in the first gate region of the first transistor and a second active structure located in the second gate region of the second transistor; an insulating material is deposited on the surfaces of the first active structure and the second active structure to form a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor; the first gate dielectric layer and the second gate dielectric layer are integrally formed; a second gate structure and a second metal interconnect layer of the second transistor are formed; the first active structure is flipped and exposed; a first gate structure and a first metal interconnect layer of the first transistor are formed.

[0006] In some possible implementations, after forming the active structure on the substrate, the method further includes: depositing a second mask material on the first active structure to form a second hard mask; the second hard mask covering a first surface of the first active structure; the first surface being a surface of the first active structure that is away from the second active structure; depositing a third mask material on the surface of the active structure and the substrate to form a third hard mask; depositing an oxide on the active structure and the substrate to form a first shallow trench isolation structure; the first shallow trench isolation structure enclosing the active structure.

[0007] In some possible implementations, prior to forming the first pseudo-gate structure, first spacer wall, first interlayer dielectric layer, and first source / drain structure of the first transistor based on the first active structure, the above method further includes: removing the portion of the first active structure enclosing the first active structure in the first shallow trench isolation structure to expose the first active structure; and removing the second hard mask to expose the first surface of the first active structure.

[0008] In some possible implementations, after wafer fabrication and substrate thinning, the method further includes: etching a second active structure to a predetermined height to form a second groove; depositing a second mask material in the second groove to form a fourth hard mask; the fourth hard mask covering a second surface of the second active structure, the second surface being the surface of the second active structure that is away from the first active structure; and removing the portion of the first shallow trench isolation structure that encloses the second active structure to expose the second active structure.

[0009] In some possible implementations, before depositing insulating material on the surfaces of the first active structure and the second active structure to form the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor, the method further includes: removing a fourth hard mask and a third hard mask located in the first gate region and the second gate region to expose the first active structure located in the first gate region and the second active structure located in the second gate region.

[0010] In some possible implementations, after depositing insulating material on the surfaces of the first active structure and the second active structure to form the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor, the method further includes: depositing oxide in the first gate region and the second gate region to form a second shallow trench isolation structure; and removing the portion of the second shallow trench isolation structure that encloses the second active structure to expose the second active structure.

[0011] In some possible implementations, after flipping the wafer and exposing the first active structure, the process includes: etching a first interlayer dielectric layer at a predetermined height in the first source / drain region of the first transistor to form a third groove; depositing a first mask material in the third groove to form a fifth hard mask; and removing a second shallow trench isolation structure in the first gate region under the masking action of the fifth hard mask to expose the first gate region.

[0012] In a second aspect, embodiments of this application provide a semiconductor structure fabricated using the method described in the first aspect. The semiconductor structure includes: a first transistor; a second transistor; and the first transistor and the second transistor stacked together; wherein the first gate dielectric layer in the first transistor and the second gate dielectric layer in the second transistor are integrally formed.

[0013] Thirdly, embodiments of this application provide a semiconductor device, which includes the semiconductor structure as described in the second aspect above.

[0014] Fourthly, embodiments of this application provide an electronic device, which includes: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is disposed on the circuit board.

[0015] In this application, under the masking action of a first hard mask, the first dummy gate structure and the second dummy gate structure are removed to expose the first active structure located in the first gate region and the second active structure located in the second gate region. Then, insulating material is deposited on the surfaces of the first active structure and the second active structure simultaneously to form a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer formed in the same process can solve the problem of gate dielectric consistency in the processing of flip-chip stacked transistors.

[0016] Furthermore, the integrally molded gate dielectric can also avoid process and positional deviations in the gate dielectric between the first and second transistors, thereby improving the gate control capability of the semiconductor structure.

[0017] Furthermore, the semiconductor structure fabrication method described in this application has a lower requirement for the operational strength of the aspect ratio process, making it more operable and simpler.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] Figure 1This is a schematic diagram of an implementation process of the semiconductor structure fabrication method in this application.

[0021] Figure 2 This is a schematic diagram of a semiconductor structure in one embodiment of this application;

[0022] Figures 3A to 3M This is a schematic diagram of the semiconductor structure fabrication process in an embodiment of this application;

[0023] The above images:

[0024] 10. Semiconductor structure; 11. First transistor; 111. First fin structure; 112. First source / drain structure; 113. First spacer; 114. First interlayer dielectric layer; 115. First gate dielectric layer; 116. First gate structure; 117. First source / drain metal; 118. First metal interconnect layer; 12. Second transistor; 121. Second fin structure; 122. Second source / drain structure; 123. Second spacer; 124. Second interlayer dielectric layer; 125. Second gate dielectric layer; 126. Second gate structure; 127. Second source / drain metal; 128. Second metal interconnect layer ; 13. Shallow trench isolation layer; 14. Second insulating layer; 15. Second carrier wafer; 21. Substrate; 22. Pad oxide layer; 23. Second hard mask; 24. Third hard mask; 25. First shallow trench isolation structure; 261. First pseudo-gate structure; 262. Second pseudo-gate structure; 27. Second groove; 281. First initial hard mask; 28. Fourth hard mask; 29. ​​First semiconductor material layer; 31. First insulating layer; 32. First carrier wafer; 33. Second source / drain groove; 34. First groove; 35. First hard mask; 36. Second shallow trench isolation structure; 37. Fifth hard mask. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0026] With Moore's Law continuously evolving, and following the gate-all-around (GAA) technology node, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, by stacking three-dimensional transistors, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. This technology is considered one of the key technologies for continuing the miniaturization of integrated circuits.

[0027] However, in the stacked transistor process, the gate dielectric of the front transistor and the gate dielectric of the back transistor are formed in two steps, which results in differences in the gate control capability of the front transistor and the back transistor, and causes a gate dielectric consistency problem.

[0028] To address the aforementioned technical problems, this application provides a method for fabricating a semiconductor structure to solve the issue of gate dielectric consistency during the fabrication of flip-chip stacked transistors.

[0029] In the embodiments of this application, the above-described semiconductor structure can be applied to semiconductor devices such as memory and processors.

[0030] In some embodiments, the semiconductor structure includes: a first transistor; a second transistor; the first transistor and the second transistor are stacked; wherein the first gate dielectric layer in the first transistor and the second gate dielectric layer in the second transistor are integrally formed.

[0031] Understandably, in a semiconductor structure, a first transistor and a second transistor are stacked, and the first and second transistors are self-aligned in the stacking direction. In the semiconductor structure, the first gate dielectric layer in the first transistor and the second gate dielectric layer in the second transistor are integrally formed, that is, the first gate dielectric layer and the second gate dielectric layer are formed through the same process.

[0032] In the embodiments of this application, the first transistor and the second transistor in the semiconductor structure can be transistors of the same type, such as any of the following: fin field effect transistor (FinFET), nanosheet field effect transistor (NSFET), planar transistor, vertical transistor, and complementary field effect transistor (CFET), etc.

[0033] Figure 2 The semiconductor structure is composed of fin field-effect transistors, which will be discussed below. Figure 2 The schematic diagram of the semiconductor structure shown illustrates the method for fabricating the semiconductor structure provided in the embodiments of this application.

[0034] Figure 1 This is a schematic diagram illustrating one implementation process of a semiconductor structure fabrication method according to an embodiment of this application. In some embodiments, the semiconductor structure includes a first transistor and a second transistor stacked together. See also Figure 1As shown, the method for fabricating the above-mentioned semiconductor structure may include:

[0035] S101, an active structure is formed on the substrate. The active structure includes a first active structure and a second active structure stacked together.

[0036] Understandably, active structures are patterned by forming a hard mask on a substrate, and the substrate is etched under the masking effect of the hard mask to form the active structures. The active structures include a first active structure and a second active structure, which are formed through the same process, enabling self-alignment of the active regions of the first and second transistors. Furthermore, the self-alignment of the active regions enables self-alignment of the first and second transistors.

[0037] In some embodiments, prior to S101, the method for fabricating the semiconductor structure may further include: providing a substrate. A suitable substrate is selected based on the type of the first transistor and the second transistor. For example, if the first transistor and the second transistor are fin field-effect transistors, a silicon (Si) substrate may be used; if the first transistor and the second transistor are nanosheet field-effect transistors, a stack formed by sequentially stacking silicon and silicon-germanium (SiGe) may be used as the substrate.

[0038] In some embodiments, the shape of the active structure varies depending on the type of the first transistor and the second transistor. For example, if the first transistor and the second transistor are fin field-effect transistors, the active structure is a fin-shaped structure; if the first transistor and the second transistor are nanosheet field-effect transistors, the active structure is a plurality of parallel nanosheet structures or a plurality of parallel nanowire structures.

[0039] It should be noted that during the process of forming an active structure through etching, a substrate of a predetermined height needs to be retained. The retained substrate can serve to support the active structure.

[0040] S102, based on the first active structure, a first pseudo-gate structure, a first spacer, a first interlayer dielectric layer, and a first source / drain structure are formed for the first transistor.

[0041] Understandably, according to the standard process for manufacturing transistors, other structures in the first transistor can be formed based on the first active structure, such as the first pseudo-gate structure, the first spacer, the first interlayer dielectric layer, and the first source / drain structure.

[0042] In some embodiments, S102 may include: photolithographically opening the first gate region of the first transistor; depositing polysilicon in the first gate region to form a first dummy gate structure; depositing insulating material on the sidewalls of the first dummy gate structure to form a first spacer wall; depositing dielectric material in other regions of the first transistor besides the first gate region to form a first interlayer dielectric layer; removing the first interlayer dielectric layer; performing source-drain epitaxial growth in the first source-drain region of the first transistor to form a first source-drain structure; and redepositing dielectric material to form the first interlayer dielectric layer.

[0043] S103, wafer pouring and substrate thinning.

[0044] Understandably, after forming the first pseudo-gate structure, the first spacer wall, the first interlayer dielectric layer, and the first source / drain structure, the first transistor and the wafer can be flipped so that the substrate faces upwards. Then, the substrate is thinned until the second active structure is exposed.

[0045] In some embodiments, the substrate can be thinned using a chemical-mechanical planarization (CMP) process.

[0046] In some possible implementations, prior to S103 above, the method for fabricating the semiconductor structure may further include: depositing an insulating material on the surface of the first transistor away from the second active structure to form a first insulating layer; and bonding the first insulating layer to a first carrier wafer.

[0047] In this embodiment, the bonded first carrier wafer can provide physical support for the flipped first transistor after the wafer is flipped, effectively preventing the first transistor from being broken by external force during the fabrication of the second transistor.

[0048] It should be noted that the insulating material forming the first insulating layer can be selected according to actual needs, and the embodiments of this application do not impose specific limitations on it.

[0049] S104, based on the second active structure, forms the second pseudo-gate structure, the second spacer, the second interlayer dielectric layer, and the second source / drain structure of the second transistor.

[0050] Understandably, following standard transistor fabrication processes, other structures in the second transistor can be formed based on the second active structure, such as a second pseudo-gate structure, a second spacer, a second interlayer dielectric layer, and a second source / drain structure.

[0051] In the embodiments of this application, the first source-drain structure represents the source and / or drain in the first transistor. Correspondingly, other expressions related to "source-drain" in the embodiments of this application are used to represent "source and / or drain", such as: second source-drain structure, first source-drain region and second source-drain region, etc.

[0052] In some embodiments, S104 may include: photolithographically opening the second gate region of the second transistor; depositing polysilicon in the second gate region to form a second dummy gate structure; depositing insulating material on the sidewalls of the second dummy gate structure to form a second spacer wall; depositing dielectric material in other regions of the second transistor besides the second gate region to form a second interlayer dielectric layer; removing the second interlayer dielectric layer; performing source / drain epitaxial growth in the second source / drain region of the second transistor to form a second source / drain structure; and redepositing dielectric material to form the second interlayer dielectric layer.

[0053] S105, etch the second interlayer dielectric layer at a preset height located in the second source / drain region of the second transistor to form a first groove.

[0054] Understandably, the second interlayer dielectric layer encapsulates the second active structure and the second source / drain structure in the second source / drain region of the second transistor. By selectively etching back the second interlayer dielectric layer to a predetermined height, a first groove is formed on the retained (i.e., unetched) portion of the second interlayer dielectric layer.

[0055] S106, deposit the first mask material in the first groove to form the first hard mask.

[0056] It is understandable that depositing the first mask material in the first groove can form a first hard mask. The first hard mask is located on the first interlayer dielectric layer, and the height of the first hard mask in the horizontal direction is the same as the height of the second pseudo-gate structure in the horizontal direction.

[0057] In some embodiments, S106 may include simultaneously depositing a first mask material on the first groove and the second pseudo-gate structure until the first groove is filled; at this time, since the first groove and the second pseudo-gate structure are at different heights in the horizontal direction, the deposited first mask material is at different heights in the horizontal direction, and the first mask material located on the second pseudo-gate structure is removed by chemical mechanical planarization, so that the second pseudo-gate structure is exposed, and the first mask material remaining in the first groove forms a first hard mask.

[0058] S107, under the masking action of the first hard mask, the second pseudo-gate structure and the first pseudo-gate structure are removed to expose the first active structure located in the first gate region of the first transistor and the second active structure located in the second gate region of the second transistor.

[0059] Understandably, the first hard mask is located in the second source / drain region and is used to limit the etched area. Then, the second dummy gate structure and the first dummy gate structure can be removed by selective etching. After removing the second dummy gate structure and the first dummy gate structure, the first active structure located in the first gate region and the second active structure located in the second gate region are exposed.

[0060] S108, an insulating material is deposited on the surfaces of the first active structure and the second active structure to form a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor. The first gate dielectric layer and the second gate dielectric layer are integrally formed.

[0061] Understandably, in the first gate region and the second gate region, insulating material is deposited on the surface of the active structure (i.e., the first active structure and the second active structure) to form a gate dielectric layer (i.e., the first gate dielectric layer and the second gate dielectric layer). The gate dielectric layer is formed in one process, that is, the first gate dielectric layer and the second gate dielectric layer are integrally formed.

[0062] S109 forms the second gate structure and the second metal interconnect layer of the second transistor.

[0063] Understandably, a metal material is deposited in the second gate region to form a second gate structure; then, under the action of a pre-set hard mask, a portion of the second interlayer dielectric layer is etched to form a second source / drain metal trench; a metal material is filled in the second source / drain metal trench to form a second source / drain metal, which contacts the second source / drain structure; and a back-end interconnect process is performed on the second gate structure and the second source / drain metal to form a second metal interconnect layer.

[0064] In some embodiments, since the second transistor is formed based on the second active structure after the first transistor is flipped, the second transistor and the first transistor are stacked back to back and self-aligned.

[0065] S110, rewind and expose the first active structure.

[0066] Understandably, after the second transistor is formed, it can be flipped so that the first carrier wafer is placed facing upwards. Then, the first carrier wafer and the first insulating layer are removed by chemical mechanical planarization.

[0067] In some embodiments, prior to S110, the method for fabricating the semiconductor structure may further include: depositing an insulating material on the surface of the second transistor away from the first active structure to form a second insulating layer; and bonding the second insulating layer to a second carrier wafer.

[0068] In this embodiment, the bonded second carrier wafer can provide physical support for the flipped second transistor after the wafer is flipped, effectively preventing the second transistor from being broken by external force during the fabrication of the first transistor.

[0069] It should be noted that the insulating material forming the second insulating layer can be selected according to actual needs, and the embodiments of this application do not impose specific limitations on it.

[0070] S111, forming the first gate structure and the first metal interconnect layer of the first transistor.

[0071] Understandably, a metal material is deposited in the first gate region to form a first gate structure; then, under the action of a pre-set hard mask, a portion of the first interlayer dielectric layer is etched to form a first source / drain metal trench; a metal material is filled in the first source / drain metal trench to form a first source / drain metal, which contacts the first source / drain structure; and a back-end interconnect process is performed on the first gate structure and the first source / drain metal to form a first metal interconnect layer.

[0072] In some possible implementations, after S101 above, the method for fabricating the semiconductor structure may further include: depositing a second mask material on the first active structure to form a second hard mask; the second hard mask covering a first surface of the first active structure; the first surface being a surface of the first active structure that is far from the second active structure; depositing a third mask material on the surface of the active structure and a substrate to form a third hard mask; depositing an oxide on the active structure and the substrate to form a first shallow trench isolation structure; the first shallow trench isolation structure enclosing the active structure.

[0073] Understandably, a second mask material of a predetermined height is deposited on the first surface of the first active structure to form a second hard mask covering the first surface. Next, a third mask material is deposited on the surface of the active structure and the substrate using atomic layer deposition (ALD) to form a third hard mask, which covers the surfaces of the active structure and the substrate. Through deposition and filling processes, a first shallow trench isolation (STI) structure is formed on the active structure and the substrate. The first shallow trench isolation (STI) structure is formed of oxide. The height of the first shallow trench isolation structure is greater than the height of the active structure, and the first shallow trench isolation structure can enclose the active structure.

[0074] In some embodiments, the oxide forming the first shallow trench isolation structure may include any of the following: silicon dioxide (SiO2), silicon oxycarbonate (SiCO), etc., and other oxides may be selected according to actual needs. This application embodiment does not specifically limit this.

[0075] In some embodiments, after providing the substrate and before forming the active structure, the method for fabricating the semiconductor structure may further include: depositing an oxide layer of a predetermined height on the substrate to form a pad oxide layer. The pad oxide layer can provide a buffer effect for the substrate and reduce the stress impact on the substrate.

[0076] In some possible implementations, prior to S102 above, the method for fabricating the semiconductor structure may further include: removing the portion of the first active structure encapsulated in the first shallow trench isolation structure to expose the first active structure; and removing the second hard mask to expose the first surface of the first active structure.

[0077] Understandably, before forming the first pseudo-gate structure, the first gap wall, the first interlayer dielectric layer, and the first source / drain structure based on the first active structure, it is necessary to expose the first active structure first, that is, to remove the part of the first shallow trench isolation structure that encloses the first active structure and the second hard mask.

[0078] In some possible implementations, after S103, the method for fabricating the semiconductor structure may further include: etching a second active structure at a predetermined height to form a second groove; depositing a second mask material in the second groove to form a fourth hard mask; the fourth hard mask covering a second surface of the second active structure, the second surface being the surface of the second active structure that is away from the first active structure; and removing the portion of the first shallow trench isolation structure that encloses the second active structure to expose the second active structure.

[0079] Understandably, a portion of the second active structure is etched, and the height of the etched second active structure is lower than the height of the first shallow trench isolation structure, forming a second groove. A second mask material is filled into the second groove to form a fourth hard mask. Next, the portion of the first shallow trench isolation structure that encloses the second active structure is removed by etching to expose the second active structure. At this point, the fourth hard mask protects the second active structure, preventing it from being etched.

[0080] In some embodiments, the process of forming the fourth hard mask described above may include: depositing a second mask material on the second groove and the first shallow trench isolation structure, wherein the height of the second mask material on the first shallow trench isolation structure is greater than the height of the second mask material in the second groove due to the height difference between the second groove and the first shallow trench isolation structure. Then, the second mask material on the first shallow trench isolation structure is removed by a chemical mechanical planarization process, leaving the second mask material in the second groove, thus forming the fourth hard mask.

[0081] In some possible implementations, prior to S108, the method for fabricating the semiconductor structure may further include: removing a fourth hard mask and a third hard mask located in the first gate region and the second gate region to expose a first active structure located in the first gate region and a second active structure located in the second gate region.

[0082] Understandably, by selective isotropic etching, the third hard mask encapsulating the active structure in the first gate region and the second gate region is removed, and then by selective anisotropic etching, the fourth hard mask is removed, thereby exposing the active structure in the gate region.

[0083] In some possible implementations, after S108, the method for fabricating the semiconductor structure may further include: depositing oxides in the first gate region and the second gate region to form a second shallow trench isolation structure; and removing the portion of the second shallow trench isolation structure that encloses the second active structure to expose the second active structure.

[0084] Understandably, the removal of the first and second dummy gate structures exposes the first and second gate regions; then, oxide is deposited in the first and second gate regions to form a second shallow trench isolation structure; then, a portion of the second shallow trench isolation structure is removed by etch-back to expose the second active structure.

[0085] It should be noted that the oxide used to prepare the second shallow trench isolation structure and the oxide used to prepare the first shallow trench isolation structure can be the same oxide.

[0086] In some possible implementations, after S110, the method for fabricating the semiconductor structure may further include: etching a first interlayer dielectric layer at a predetermined height in the first source / drain region of the first transistor to form a third groove; depositing a first mask material in the third groove to form a fifth hard mask; and removing a second shallow trench isolation structure in the first gate region under the masking action of the fifth hard mask to expose the first gate region.

[0087] Understandably, the first interlayer dielectric layer encapsulates the first active structure and the first source / drain structure in the first source / drain region of the first transistor. By selectively etching back the first interlayer dielectric layer to a predetermined height, a third groove is formed on the retained (i.e., unetched) portion of the first interlayer dielectric layer. Depositing a first mask material in the third groove forms a fifth hard mask, which is located on the first interlayer dielectric layer. The horizontal height of the fifth hard mask is the same as the horizontal height of the second shallow trench isolation structure. Idling back the second shallow trench isolation structure to a predetermined height exposes the first gate region and the first active structure located in the first gate region.

[0088] In some embodiments, the formation of the fifth hard mask may include simultaneously depositing a first mask material on the third groove and the second shallow trench isolation structure until the third groove is filled; at this time, since the third groove and the second shallow trench isolation structure are at different heights in the horizontal direction, the deposited first mask material is also at different heights in the horizontal direction. The first mask material located on the second shallow trench isolation structure is removed by chemical mechanical planarization, so that the second shallow trench isolation structure is exposed, and the first mask material remaining in the third groove forms the fifth hard mask.

[0089] In some embodiments, during the process of etching a portion of the second shallow trench isolation structure to expose the first active structure, the second shallow trench isolation structure with a predetermined height is retained, and the retained portion serves as a shallow trench isolation layer, which is used to isolate the first transistor and the second transistor.

[0090] In this embodiment, in order to achieve selective etching, the first mask material, the second mask material and the third mask material are different materials. The specific materials used can be set according to actual needs, and this embodiment does not make specific limitations on this.

[0091] The following description uses fin field-effect transistors as examples of the first and second transistors to illustrate the semiconductor structure provided in the embodiments of this application. Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of this application. Wherein, Figure 2 (a) is the design layout of the semiconductor structure. It should be noted that, for ease of understanding, only the fin structure, gate structure, and source / drain structure are shown in the design layout; (b) is a cross-sectional view of the semiconductor structure taken along the tangential direction of the gate structure (i.e., the AA' direction); (c) is a cross-sectional view of the semiconductor structure taken along the tangential direction of the source / drain structure (i.e., the BB' direction); and (d) is a cross-sectional view of the semiconductor structure taken along the tangential direction of the fin structure (i.e., the CC' direction).

[0092] See Figure 2As shown, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12. The first transistor 11 and the second transistor 12 are stacked back-to-back; the first gate dielectric layer in the first transistor and the second gate dielectric layer in the second transistor are integrally formed.

[0093] Figure 2 The semiconductor structure 10 shown can be used to... Figures 3A to 3M The process shown is used for preparation. Figures 3A to 3M This is a schematic diagram of the semiconductor structure fabrication process in an embodiment of this application.

[0094] In one example, the fabrication process of the semiconductor structure 10 may include the following steps:

[0095] Step 1: Provide a substrate 21 (see...) Figure 3A (a)). Substrate 21 is a silicon substrate.

[0096] Step 2: Deposit oxide on substrate 21 to form pad oxide layer 22 (see...) Figure 3A (b)

[0097] Step 3: A fin structure is formed according to the standard process for fabricating transistors. The fin structure includes a first fin structure 111 and a second fin structure 121. Next, a second mask material is deposited on the first fin structure 111 to form a second hard mask 23 (see...). Figure 3A (c)).

[0098] In some embodiments, since the fin structures in the two transistors (i.e., the first fin structure 111 and the second fin structure 121) are formed in the same etching process, a larger etching depth can be selected during the etching process, so that the height of the fin structure is sufficient to fabricate two transistors. In one example, the height of the fin structure can be greater than 100 nanometers (nm).

[0099] Step 4: Deposit a third mask material on the surface of the first fin structure 111 and the upper surface of the substrate 21 using atomic layer deposition (ALD) to form a third hard mask 24 (see Figure 3B (a)

[0100] Step 5: Deposit and fill oxide on substrate 21 and fin structure to form first shallow trench isolation structure 25. Next, etch back a portion of the first shallow trench isolation structure 25 until the upper surface of the second hard mask 23 is exposed, such that the horizontal height of the second hard mask 23 is the same as the horizontal height of the etched first shallow trench isolation structure 25 (see...). Figure 3B (b)

[0101] Step 6: Etch the portion of the first shallow trench isolation structure 25 that encloses the first fin structure 111 to expose the first fin structure 111 (see...). Figure 3B (c)).

[0102] Step 7: Perform epitaxial growth of the source / drain in the first source / drain region of the first transistor 11 to form a first source / drain structure 112; then, deposit polysilicon in the first gate region to form a first dummy gate structure 261; deposit insulating material on the sidewalls of the first dummy gate structure 261 to form a first spacer 113; deposit interlayer dielectric in the first source / drain region to form a first interlayer dielectric layer 114 (see...). Figure 3C (a)

[0103] Step 8: Deposit insulating material on the first interlayer dielectric layer 114 and the first dummy gate structure 261 to form the first insulating layer 31; then, bond the pre-set first carrier wafer 32 and the first insulating layer 31 together; perform a flipping process on the unformed first transistor 11 so that the substrate 21 faces upward (see...). Figure 3C (b)

[0104] Step 9: Remove the substrate 21 using a wafer thinning process and perform chemical mechanical planarization until the first shallow trench isolation structure 25 is exposed (see...). Figure 3C (c)).

[0105] Step 10: Etch the second fin structure 121 to a predetermined height to form the second groove 27 (see...) Figure 3D (a)

[0106] Step 11: Deposit a second mask material in the second groove 27 and on the first shallow trench isolation structure 25 to form a first initial hard mask 281 (see...) Figure 3D (b)

[0107] Step 12: Using a chemical mechanical planarization process, the first initial hard mask 281 located on the first shallow trench isolation structure 25 is ground flat, leaving only the second mask material in the second groove 27, forming the fourth hard mask 28 (see...). Figure 3D (c)).

[0108] Step 13: Etch the first shallow trench isolation structure 25 to a predetermined height, exposing the first fin structure 111. Retain the first shallow trench isolation structure 25 at the predetermined height to form the shallow trench isolation layer 13 (see...). Figure 3E (a)

[0109] Step 14: Deposit polysilicon on the shallow trench isolation layer 13 to form the first semiconductor material layer 29 (see...) Figure 3E (b)

[0110] Step 15: Using photolithography, remove the first semiconductor material layer 29 in the second source / drain region, leaving only the first semiconductor material layer 29 in the second gate region, forming the second dummy gate structure 262 (see...). Figure 3E (c)).

[0111] Step 16: Deposit insulating material on the sidewalls of the second pseudo-gate structure 262 to form the second spacer wall 123 (see...) Figure 3F (a)

[0112] Step 17: Etch downwards the fourth hard mask 28 located in the second source / drain region and etch the second fin structure 121 located at a predetermined height in the second source / drain region to form the second source / drain groove 33 (see...). Figure 3F (b)

[0113] Step 18: Perform epitaxial growth of the source / drain in the second source / drain groove 33 to form the second source / drain structure 122 (see...). Figure 3F (c)).

[0114] Step 19: Deposit dielectric material in the second source / drain region by flowable chemical vapor deposition (FCVD) and perform chemical mechanical planarization to form the second interlayer dielectric layer 124 (see...). Figure 3G (a)

[0115] Step 20: Selectively etch back the second interlayer dielectric layer 124 to a preset height to form the first groove 34 (see...) Figure 3G (b)

[0116] Step 21: Deposit the first mask material in the first groove 34 to form the first hard mask 35 (see...) Figure 3G (c)).

[0117] Step 22: Under the constraint of the shallow trench isolation layer 13 and the first hard mask 35, selectively remove the second pseudo-gate structure 262 (see...). Figure 3H (a)

[0118] Step 23: Remove the shallow trench isolation layer 13 located in the gate region by anisotropic etching (see...) Figure 3H (b)

[0119] Step 24: Remove the first pseudo-gate structure 261 by selective isotropic etching (see...) Figure 3H (c)).

[0120] Step 25: Remove the third hard mask 24 encapsulating the fin-like structure in the gate region by selective isotropic etching (see...). Figure 3I (a)

[0121] Step 26: Remove the exposed fourth hard mask 28 by selective anisotropic etching (see...) Figure 3I (b)

[0122] Step 27: Simultaneously deposit insulating material on the surfaces of the first fin structure 111 and the second fin structure 121 to form the first gate dielectric layer 115 and the second gate dielectric layer 125 (see...). Figure 3I (c)).

[0123] Step 28: Deposit oxide in the gate region to fill the gate region, forming the second shallow trench isolation structure 36 (see...). Figure 3J (a)

[0124] Step 29: Idle the second shallow trench isolation structure 36 back to the preset height to expose the second gate region (see...). Figure 3J (b)

[0125] Step 30: Deposit metal material in the second gate region to form the second gate structure 126 (see...) Figure 3J (c)).

[0126] Step 31: Remove the first hard mask 35 located in the second source / drain region (see...) Figure 3K (a)

[0127] Step 32: Form a second source / drain metal trench by etching a portion of the second interlayer dielectric layer; then, deposit metal material in the second source / drain metal trench to form the second source / drain metal 127 (see...). Figure 3K (b)

[0128] Step 33: Perform subsequent processing on the second gate structure 126 and the second source / drain metal 127 to form the second metal interconnect layer 128 (see...). Figure 3K (c)).

[0129] Step 34: Deposit insulating material on the second metal interconnect layer 128 to form the second insulating layer 14, and bond the pre-set second carrier wafer 15 to the second insulating layer 14; then, perform a flipping process on the second transistor 12 so that the first carrier wafer 32 is placed facing upwards (see...). Figure 3L (a)

[0130] Step 35: Remove the first carrier wafer 32 and the first insulating layer 31 by chemical mechanical planarization. The chemical mechanical planarization process stops at the second shallow trench isolation structure 36 (see...). Figure 3L (b)

[0131] Step 36: Etch back the first interlayer dielectric layer 114 to a predetermined height to form a third groove; deposit the first mask material in the third groove to form a fifth hard mask 37 (see...). Figure 3L (c)).

[0132] Step 37: Under the masking action of the fifth hard mask 37, the second shallow trench isolation structure 36 located in the first gate region is etched, and the second shallow trench isolation structure 36 with a preset height is retained as the shallow trench isolation layer 13 (see...). Figure 3M (a)

[0133] Step 38: Deposit metal material in the first gate region to form the first gate structure 116 (see...) Figure 3M (b)

[0134] Step 39: Form a first source / drain metal trench by etching a portion of the first interlayer dielectric layer; then, deposit metal material in the first source / drain metal trench to form the first source / drain metal 117 (see...). Figure 3M (c)).

[0135] Step 40: Perform subsequent processing on the first gate structure 116 and the first source / drain metal 117 to form the first metal interconnect layer 118 (see...). Figure 2 ).

[0136] Thus, the semiconductor structure 10 was successfully prepared according to the above preparation method.

[0137] It should be noted that the semiconductor structure fabrication method described in the embodiments of this application is also applicable to different types of transistors such as nanosheet field-effect transistors, planar transistors, vertical transistors, and complementary field-effect transistors. The above method is only used as an example of a fin field-effect transistor and is not intended to limit the type of transistor in the semiconductor structure of the embodiments of this application.

[0138] In this embodiment, under the masking action of the first hard mask, the first dummy gate structure and the second dummy gate structure are removed to expose the first active structure located in the first gate region and the second active structure located in the second gate region. Then, insulating material is deposited on the surfaces of the first active structure and the second active structure to form the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer formed in the same process can solve the problem of gate dielectric consistency in the process of flip-chip stacked transistors.

[0139] Furthermore, the integrally molded gate dielectric can also avoid process and positional deviations in the gate dielectric between the first and second transistors, thereby improving the gate control capability of the semiconductor structure.

[0140] Furthermore, the semiconductor structure fabrication method described in this application has a lower requirement for the operational intensity of the aspect ratio process, making it more operable and simpler.

[0141] Furthermore, the semiconductor structure provided in this application embodiment can be inspected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, the semiconductor structure provided in this application embodiment can be inspected by TEM slicing. For example, a first gate dielectric layer and a second gate dielectric layer can be observed on the surfaces of the first active structure and the second active structure; in the AA' direction, it can be observed that there is no gate dielectric layer between the shallow trench isolation structure and the first gate structure, and no gate dielectric layer between the shallow trench isolation structure and the second gate structure; furthermore, the first gate dielectric layer and the second gate dielectric layer are integrally formed.

[0142] This application provides a semiconductor device, including the semiconductor structure as described in the above embodiments. Specific limitations of the semiconductor structure can be found above. Figure 2 The semiconductor structure shown will not be described in detail here.

[0143] This application provides an electronic device, including a circuit board and a semiconductor device as described in the above embodiments, wherein the semiconductor device is disposed on the circuit board. The semiconductor device includes the semiconductor structure described above. Specific limitations of the semiconductor structure can be found above. Figure 2 This will not be elaborated upon here.

[0144] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0145] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The semiconductor structure includes a first transistor and a second transistor stacked together; the method includes: An active structure is formed on a substrate; the active structure includes a first active structure and a second active structure stacked together. Based on the first active structure, a first pseudo-gate structure, a first spacer, a first interlayer dielectric layer, and a first source / drain structure are formed for the first transistor. The substrate is then poured and thinned. Based on the second active structure, a second pseudo-gate structure, a second spacer wall, a second interlayer dielectric layer, and a second source / drain structure are formed for the second transistor. The second interlayer dielectric layer located in the second source / drain region of the second transistor at a predetermined height is etched to form a first groove; A first mask material is deposited in the first groove to form a first hard mask; Under the masking action of the first hard mask, the second pseudo-gate structure and the first pseudo-gate structure are removed to expose the first active structure located in the first gate region of the first transistor and the second active structure located in the second gate region of the second transistor. An insulating material is deposited on the surfaces of the first active structure and the second active structure to form a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor; the first gate dielectric layer and the second gate dielectric layer are integrally formed. A second gate structure and a second metal interconnect layer are formed to form the second transistor; The film is then rewound to expose the first active structure; The first gate structure and the first metal interconnect layer of the first transistor are formed.

2. The method according to claim 1, characterized in that, After forming the active structure on the substrate, the method further includes: A second mask material is deposited on the first active structure to form a second hard mask; the second hard mask covers a first surface of the first active structure; the first surface is the surface of the first active structure that is away from the second active structure; A third mask material is deposited on the surface of the active structure and the substrate to form a third hard mask; An oxide is deposited on the active structure and the substrate to form a first shallow trench isolation structure; the first shallow trench isolation structure encapsulates the active structure.

3. The method according to claim 2, characterized in that, Before forming the first pseudo-gate structure, first spacer wall, first interlayer dielectric layer, and first source / drain structure of the first transistor based on the first active structure, the method further includes: Remove the portion of the first active structure that encloses the first shallow trench isolation structure to expose the first active structure; Remove the second hard mask to expose the first surface of the first active structure.

4. The method according to claim 3, characterized in that, After the wafer is poured and the substrate is thinned, the method further includes: The second active structure at a predetermined height is etched to form the second groove; A second mask material is deposited in the second groove to form a fourth hard mask; the fourth hard mask covers a second surface of the second active structure, the second surface being the surface of the second active structure that is away from the first active structure; Remove the portion of the first shallow trench isolation structure that encloses the second active structure to expose the second active structure.

5. The method according to claim 4, characterized in that, Before depositing insulating material on the surfaces of the first active structure and the second active structure to form the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor, the method further includes: Remove the fourth hard mask and the third hard mask located in the first gate region and the second gate region to expose the first active structure located in the first gate region and the second active structure located in the second gate region.

6. The method according to claim 1, characterized in that, After depositing insulating material on the surfaces of the first active structure and the second active structure to form the first gate dielectric layer of the first transistor and the second gate dielectric layer of the second transistor, the method further includes: Oxides are deposited in the first gate region and the second gate region to form a second shallow trench isolation structure; Remove the portion of the second shallow trench isolation structure that encloses the second active structure to expose the second active structure.

7. The method according to claim 6, characterized in that, After the wafer is poured and the first active structure is exposed, the process includes: The first interlayer dielectric layer located in the first source / drain region of the first transistor at a predetermined height is etched to form a third groove; A first mask material is deposited in the third groove to form a fifth hard mask; Under the masking action of the fifth hard mask, the second shallow trench isolation structure located in the first gate region is removed to expose the first gate region.

8. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method according to any one of claims 1 to 7, wherein the semiconductor structure comprises: First transistor; The second transistor; the first transistor and the second transistor are stacked; The first gate dielectric layer in the first transistor and the second gate dielectric layer in the second transistor are integrally formed.

9. A semiconductor device, characterized in that, include: The semiconductor structure as described in claim 8.

10. An electronic device, characterized in that, include: The circuit board and the semiconductor device as described in claim 9, wherein the semiconductor device is disposed on the circuit board.

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