Split-gate light-emitting display with piezoresistive sensing function and manufacturing method of split-gate light-emitting display

Abstract

The invention relates to the technical field of display manufacturing, in particular to a split-gate light-emitting display with a piezoresistive sensing function and a manufacturing method of the split-gate light-emitting display. The split-gate light-emitting display with the piezoresistive sensing function comprises a plurality of pixels, wherein each pixel comprises a red light-emitting sub-pixel R, a green light-emitting sub-pixel G, a blue light-emitting sub-pixel B and a pressure sensing sub-pixel S; the driving backboard is provided with a plurality of via holes which are regularly arranged, and the driving backboard bears a plurality of pixels, drives the red light-emitting sub-pixels R, the green light-emitting sub-pixels G and the blue light-emitting sub-pixels to emit light and drives the pressure sensing sub-pixels S to receive pressure information. According to the split-gate module prepared by using a semiconductor process, the display functions of high resolution, high brightness, high contrast and low response time can be realized, external pressure information can be received in real time, and a feasible scheme is provided for single-chip integration of touch interactive display.

Description

Technical Field

[0001] The present invention relates to the technical field of display manufacturing, and in particular to a split-grid type light-emitting display equipped with a piezoresistive sensing function and a manufacturing method thereof. Background Art

[0002] As consumers pursue a better visual experience, high-definition display products are becoming more and more popular, which has driven display technology to develop in the direction of higher resolution, higher brightness, higher contrast and lower response time. However, if the display of the existing technology wants to receive external pressure information in real time, it needs to be equipped with a pressure sensor device, and the pixel arrangement of the existing display needs to be optimized.

[0003] If the piezoresistive sensor is formed in the manufacturing process of the semiconductor display, it can provide a practical solution for the single-chip integration of interactive display. Summary of the invention

[0004] The technical problem to be solved by the present invention is: in order to solve the problems existing in the prior art in the above-mentioned background technology, a split-gate type light-emitting display equipped with a piezoresistive sensing function is provided.

[0005] The technical solution adopted by the present invention to solve the technical problem is: a split-grid type light-emitting display equipped with a piezoresistive sensing function, comprising: A plurality of pixels, each of which includes a red light-emitting sub-pixel R, a green light-emitting sub-pixel G, a blue light-emitting sub-pixel B and a pressure sensing sub-pixel S; A driving backplane, wherein a plurality of regularly arranged via holes are provided on the driving backplane, wherein the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B or the pressure sensing sub-pixel S covers at least one via hole, and the driving backplane carries a plurality of pixels and drives the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel to emit light and drives the pressure sensing sub-pixel S to receive pressure information; The red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B and the pressure sensing sub-pixel S all include an anode, a semiconductor device, an ITO thin film layer and an Al layer. The anode is arranged on a driving backplane and covers at least one via hole. The semiconductor device is located on a side of the anode away from the driving backplane, the ITO thin film layer is located on a side of the semiconductor device away from the driving backplane, and the Al layer is arranged on the ITO thin film layer.

[0006] Furthermore, the semiconductor device includes an N-type highly doped region, an N-type epitaxial layer, a gate, a P-region, an N+ region, a P+ region and a metal layer, wherein the N-type highly doped region is located on the side of the anode away from the driving backplane, an N-type epitaxial layer is formed on the N-type highly doped region, the gate is arranged in the N-type epitaxial layer and is divided into two sections, the P-region is arranged on the upper surface of the N-type epitaxial layer avoiding the gate, the N+ region is arranged on the upper surface of the P+ region, an oxide layer is arranged on the N+ region, a through hole is arranged on the oxide layer, the P+ region is arranged in the P-region below the through hole, a metal layer is arranged on the oxide layer, and the metal layer has a metal connector extending into the through hole and connected to the P+ region.

[0007] Furthermore, the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B each include a P-pad layer, a P-GaN layer, an MQW layer, an n-GaN layer and an N-pad layer which are sequentially arranged on the Al layer.

[0008] Furthermore, a Si layer with a hollow structure is provided on the Al layer in the pressure sensing sub-pixel S, a SiO2 layer is provided on the Si layer, a P-type silicon is provided on the SiO2 layer, a P-type single crystal silicon sensing film with a piezoresistive electrode is connected to the P-type silicon, a through hole is provided from the upper surface of the P-type silicon to the lower bottom surface of the Si layer, and tungsten connecting the P-type single crystal silicon sensing film and the Al layer is provided in the through hole.

[0009] Furthermore, it also includes an interlayer dielectric layer and a common cathode, the interlayer dielectric layer is produced and filled between the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B and the pressure sensing sub-pixel S, and the interlayer dielectric layers corresponding to the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B are all provided with electrode grooves, the common cathode is arranged on the side of the interlayer dielectric layer away from the driving backplane and covers the electrode grooves, and the common cathode is in contact with the upper surfaces of the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B through the electrode grooves, and in the pressure sensing sub-pixel S, the common cathode is connected to the piezoresistive electrode of the P-type single crystal silicon sensing film.

[0010] Furthermore, it also includes a thin film encapsulation layer, which is located on a side of the common cathode away from the driving backplane and covers the common cathode.

[0011] A method for manufacturing a split-grid type light-emitting display equipped with a piezoresistive sensing function is also mentioned, comprising the following steps: S1, forming a number of regularly arranged via holes on the driving backplane, and filling the via holes with conductive material, and then forming a number of anodes on the upper surface of the driving backplane, and each anode covers at least one via hole; S2, sequentially growing an N-type highly doped region, an N-type epitaxial layer and an oxide layer on the driving back plate and the anode to form a semiconductor layer; S3, patterning the semiconductor layer, filling the removed portion with the interlayer dielectric layer, and smoothing the interlayer dielectric layer using a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the oxide layer; S4, etching the trench structure and growing a gate oxide layer, and depositing a polysilicon gate in the trench; S5, grinding the polysilicon layer using a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the N-type epitaxial layer, and then partially etching the polysilicon gate to form a gate; S6, growing an oxide layer on the polysilicon gate, depositing polysilicon again to form another gate section, and then coating an oxide film to form a split-gate structure; S7, forming a P- region and an N+ region in sequence by ion implantation on the N-type epitaxial layer avoiding the split gate structure; S8, after depositing an oxide layer on the upper surface of the N+ region, etching a through hole, forming a P+ region on the upper part of the P- region by ion implantation through the through hole, depositing a metal layer on the oxide layer, and the metal layer passes through the through hole to contact the P+ region; S9, plating an ITO thin film layer and an Al layer on the metal layer, producing an interlayer dielectric layer again, and grinding the interlayer dielectric layer by a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the Al layer; S10, connecting the RGB LED chips in the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, and the blue light-emitting sub-pixel B to the driving backplane using mass transfer and vacuum bonding technology; S11, depositing a Si layer on the Al layer of the pressure sensing sub-pixel S and patterning it to form a hollow structure, sequentially growing a thin SiO2 layer and a P-type silicon layer on the top of the Si layer of the hollow structure, and then performing deep silicon etching and drilling, depositing tungsten in the hole by a CVD process, and then bonding a P-type single crystal silicon sensing film with a piezoresistive electrode by a bonding process; S12. Finally, grow a common cathode and a thin film encapsulation layer.

[0012] Another method for manufacturing a split-gate type light-emitting display equipped with a piezoresistive sensing function is also mentioned, comprising the following steps: Sa, forming a number of regularly arranged via holes on the driving backplane, and filling the via holes with a conductive material, and then forming a number of anodes on the upper surface of the driving backplane, and each anode covers at least one via hole; Sb, sequentially growing an N-type highly doped region, an N-type epitaxial layer and an oxide layer on the driving back plate and the anode to form a semiconductor layer; Sc, patterning the semiconductor layer, filling the removed portion with an interlayer dielectric layer, and smoothing the interlayer dielectric layer using a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the oxide layer; Sd, etching the trench structure and growing the gate oxide layer, and depositing the polysilicon gate in the trench; Se, using a chemical mechanical polishing process to polish the polysilicon layer so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the N-type epitaxial layer, and then partially etching the polysilicon gate to form a section of the gate; Sf, an oxide layer is grown on the surface of the polysilicon gate and the N-type epitaxial layer above it, polysilicon is deposited again to form another gate section, and then an oxide film is plated on it to form a split-gate structure; Sg, ion implantation is performed on the N-type epitaxial layer avoiding the split gate structure to form a P- region and an N+ region in sequence; Sh, after depositing an oxide layer on the upper surface of the N+ region, etching a through hole, forming a P+ region on the upper part of the P- region by ion implantation through the through hole, depositing a metal layer on the oxide layer, and the metal layer passes through the through hole to contact the P+ region; Si, plating an ITO thin film layer and an Al layer on the metal layer, producing an interlayer dielectric layer again, and grinding the interlayer dielectric layer by a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the Al layer; Sj, using mass transfer and vacuum bonding technology to connect the RGB LED chips in the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, and the blue light-emitting sub-pixel B to the driving backplane; Sk, depositing a Si layer on the Al layer of the pressure sensing sub-pixel S and patterning it to form a hollow structure, sequentially growing a thin SiO2 layer and a P-type silicon layer on top of the Si layer of the hollow structure, and then performing deep silicon etching and drilling, depositing tungsten in the hole using a CVD process, and then bonding a P-type single crystal silicon sensing film with a piezoresistive electrode through a bonding process; S1. Finally, grow the common cathode and thin film encapsulation layers.

[0013] Beneficial effects of the present invention: The split-gate module prepared by the present invention using semiconductor technology can not only realize the display functions of high resolution, high brightness, high contrast and low response time, but also can receive external pressure information in real time, providing a practical solution for the single-chip integration of touch interactive display. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0015] Figure 1 It is a structural diagram of embodiment 1 of the present invention.

[0016] Figure 2 It is a schematic diagram of step 1 of embodiment 1 of the present invention.

[0017] Figure 3 It is a schematic diagram of step 2 of embodiment 1 of the present invention.

[0018] Figure 4 It is a schematic diagram of step 3 of embodiment 1 of the present invention.

[0019] Figure 5 It is a schematic diagram of step 4 of embodiment 1 of the present invention.

[0020] Figure 6 It is a schematic diagram of step 5 of embodiment 1 of the present invention.

[0021] Figure 7 It is a schematic diagram of step 6 of embodiment 1 of the present invention.

[0022] Figure 8 It is a schematic diagram of step 7 of embodiment 1 of the present invention.

[0023] Fig. 9 It is a schematic diagram of step 8 of embodiment 1 of the present invention.

[0024] Fig.10 It is a schematic diagram of step 9 of embodiment 1 of the present invention.

[0025] Fig.11 It is a schematic diagram of step 10 of the first embodiment of the present invention.

[0026] Fig.12 It is a schematic diagram of step 11 of the first embodiment of the present invention.

[0027] Fig.13 It is a schematic diagram of step 12 of the first embodiment of the present invention.

[0028] Fig.14 It is a structural diagram of embodiment 2 of the present invention.

[0029] Fig.15 It is a schematic diagram of step a of embodiment 2 of the present invention.

[0030] Fig.16 It is a schematic diagram of step b of embodiment 2 of the present invention.

[0031] Fig.17 It is a schematic diagram of step c of embodiment 2 of the present invention.

[0032] Fig.18 It is a schematic diagram of step d of embodiment 2 of the present invention.

[0033] Fig.19 It is a schematic diagram of step e of embodiment 2 of the present invention.

[0034] Fig. 20 It is a schematic diagram of step f of embodiment 2 of the present invention.

[0035] Fig.21 It is a schematic diagram of step g of embodiment 2 of the present invention.

[0036] Fig. 22 It is a schematic diagram of step h of embodiment 2 of the present invention.

[0037] Fig.23 It is a schematic diagram of step i of embodiment 2 of the present invention.

[0038] Fig.24 It is a schematic diagram of step j of embodiment 2 of the present invention.

[0039] Fig.25 It is a schematic diagram of step k of embodiment 2 of the present invention.

[0040] Fig.26 It is a schematic diagram of step 1 of embodiment 2 of the present invention.

[0041] Fig. 27 It is a diagram of the optimized pixel arrangement scheme of Embodiment 1 and Embodiment 2 of the present invention.

[0042] Fig.28 1 is a driving circuit diagram of Embodiment 1 and Embodiment 2 of the present invention.

[0043] In the figure: 1. driving backplane; 2. via; 3. anode; 4. semiconductor device; 41. N-type highly doped region; 42. N-type epitaxial layer; 43. gate; 44. P-region; 45. N+ region; 46. P+ region; 47. metal layer; 48. oxide layer; 5. ITO thin film layer; 6. Al layer; 7. interlayer dielectric layer; 8. common cathode; 9. thin film encapsulation layer; 10. P-pad layer; 11. P-GaN layer; 12. MQW layer; 13. n-GaN layer; 14. N-pad layer; 15. Si layer; 16. SiO2 layer; 17. P-type silicon; 18. P-type single crystal silicon sensing film; 19. tungsten. DETAILED DESCRIPTION

[0044] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0045] Embodiment 1 like Figure 1As shown, a split-gate light-emitting display equipped with a piezoresistive sensing function comprises: a plurality of pixels, each pixel comprising a red light-emitting sub-pixel R, a green light-emitting sub-pixel G, a blue light-emitting sub-pixel B and a pressure sensing sub-pixel S; a driving backplane 1, a plurality of regularly arranged via holes 2 are provided on the driving backplane 1, the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B or the pressure sensing sub-pixel S covers at least one via hole 2, the driving backplane 1 carries a plurality of pixels, and drives the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel to emit light and drives the pressure sensing sub-pixel S to receive pressure information respectively; the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B and the pressure sensing sub-pixel S all comprise an anode 3, a semiconductor device 4, an ITO film layer 5 and an Al layer 6, the anode 3 is arranged on the driving backplane 1 and covers at least one via hole 2, the semiconductor device 4 is located on a side of the anode 3 away from the driving backplane 1, the ITO film layer 5 is located on a side of the semiconductor device 4 away from the driving backplane 1, and the Al layer 6 is arranged on the ITO film layer 5.

[0046] It also includes an interlayer dielectric layer 7 and a common cathode 8. The interlayer dielectric layer 7 is produced and filled between the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B and the pressure sensing sub-pixel S. The interlayer dielectric layer 7 corresponding to the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B is provided with an electrode groove. The common cathode 8 is arranged on the side of the interlayer dielectric layer 7 away from the driving backplane 1 and covers the electrode groove. The common cathode 8 is in contact with the upper surfaces of the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B through the electrode groove. In the pressure sensing sub-pixel S, the common cathode 8 is connected to the piezoresistive electrode of the P-type single crystal silicon sensing film.

[0047] It also includes a thin film encapsulation layer 9 , which is located on a side of the common cathode 8 away from the driving backplane 1 and covers the common cathode 8 .

[0048] Among them, the semiconductor device 4 includes an N-type highly doped region 41, an N-type epitaxial layer 42, a gate 43, a P-region 44, an N+ region 45, a P+ region 46 and a metal layer 47. The N-type highly doped region 41 is located on the side of the anode 3 away from the driving backplane 1, an N-type epitaxial layer 42 is formed on the N-type highly doped region 41, the gate 43 is arranged in the N-type epitaxial layer 42 and is divided into two sections, the P-region 44 is arranged on the upper surface of the N-type epitaxial layer 4 avoiding the gate 43, the N+ region 45 is arranged on the upper surface of the P+ region 46, an oxide layer 48 is arranged on the N+ region 45, and a through hole is arranged on the oxide layer 48, the P+ region 46 is arranged in the P-44 below the through hole, and a metal layer 47 is arranged on the oxide layer 48, and the metal layer 47 has a metal connector extending into the through hole and connected to the P+ region 46.

[0049] The red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B all include a P-pad layer 10, a P-GaN layer 11, an MQW layer 12, an n-GaN layer 13 and an N-pad layer 14 arranged in sequence on the Al layer 6. The Al layer 6 in the pressure sensing sub-pixel S is provided with a Si layer 15 with a hollow structure, a SiO2 layer 16 is provided on the Si layer 15, a P-type silicon 17 is provided on the SiO2 layer 16, a P-type single crystal silicon sensing film 18 with a piezoresistive electrode is connected to the P-type silicon 17, a through hole is provided from the upper surface of the P-type silicon 17 to the lower bottom surface of the Si layer 15, and a tungsten 19 connecting the P-type single crystal silicon sensing film 18 and the Al layer 6 is provided in the through hole.

[0050] The manufacturing method of the split-gate type light-emitting display equipped with a piezoresistive sensing function of the first embodiment is specifically as follows: Step 1: If Figure 2 As shown, a plurality of regularly arranged via holes 2 are formed on the driving back plate 1, and a conductive material is filled in the via holes 2, and then a plurality of anodes 3 are formed on the upper surface of the driving back plate 1, and each anode 3 covers at least one via hole 2; Step 2: If Figure 3 As shown, an N-type highly doped region 41, an N-type epitaxial layer 42 and an oxide layer 48 are sequentially grown on the driving backplane 1 and the anode 3 to form a semiconductor layer; Step 3: If Figure 4 As shown, the patterned semiconductor layer is filled with the removed portion through the interlayer dielectric layer 7, and the interlayer dielectric layer 7 is polished by a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the oxide layer 48; Step 4: Figure 5 As shown, a trench structure is etched and a gate oxide layer 48 is grown, and a polysilicon gate 43 is deposited in the trench; Step 5: Figure 6 As shown, the polysilicon layer is polished using a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the N-type epitaxial layer 42, and then the polysilicon gate 43 is partially etched to form a gate; Step 6: Figure 7 As shown, an oxide layer 48 is grown on the polysilicon gate 43, polysilicon is deposited again to form another gate segment, and then an oxide film is plated to form a split-gate structure; Step 7: Figure 8 As shown, ion implantation is performed on the N-type epitaxial layer 42 avoiding the split gate structure to form a P- region 44 and an N+ region 45 in sequence; Step 8: Fig. 9 As shown, an oxide layer 48 is deposited on the upper surface of the N+ region 45 and then a through hole is etched. A P+ region 46 is formed on the upper part of the P- region 44 by ion implantation through the through hole. A metal layer 47 is deposited on the oxide layer 48. The metal layer 47 passes through the through hole and contacts the P+ region 46. Step 9: Fig.10 As shown, an ITO thin film layer 5 and an Al layer 6 are plated on the metal layer 47, and an interlayer dielectric layer 7 is produced again, and the interlayer dielectric layer 7 is polished by a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the Al layer 6; Step 10: Fig.11 As shown, the RGB LED chips (including the P-pad layer 10, the P-GaN layer 11, the MQW layer 12, the n-GaN layer 13 and the N-pad layer 14 arranged in sequence) in the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B are connected to the driving backplane 1 using mass transfer and vacuum bonding technology; Step 11: Fig.12 As shown, a Si layer 15 is deposited on the Al layer 6 of the pressure sensing sub-pixel S and patterned to form a hollow structure, a thin SiO2 layer 16 and a P-type silicon 17 are sequentially grown on the top of the Si layer 15 of the hollow structure, and then deep silicon etching is performed to drill holes, and tungsten 19 is deposited in the holes by a CVD process, and then a P-type single crystal silicon sensing film 18 with a piezoresistive electrode is bonded by a bonding process; Step 12: Fig.13 As shown, finally, a common cathode 8 and a thin film encapsulation layer 9 are grown, and the current flow is shown by the red arrow in the semiconductor device 4.

[0051] Embodiment 2 The difference from the first embodiment is that: Fig.14 As shown, a section of the gate at the bottom of the trench is longer than that in the first embodiment, and the oxide layer 48 grown on the section is at a different position. The oxide layer 48 grows on the surface of the section of the gate and the N-type epitaxial layer 42 above it.

[0052] The manufacturing method of the split-gate type light-emitting display equipped with a piezoresistive sensing function of the second embodiment is specifically as follows: Step a: Fig.15 As shown, a plurality of regularly arranged via holes 2 are formed on the driving back plate 1, and a conductive material is filled in the via holes 2, and then a plurality of anodes 3 are formed on the upper surface of the driving back plate 1, and each anode 3 covers at least one via hole 2; Step b: Fig.16 As shown, an N-type highly doped region 41, an N-type epitaxial layer 42 and an oxide layer 48 are sequentially grown on the driving backplane 1 and the anode 3 to form a semiconductor layer; Step c: Fig.17 As shown, the patterned semiconductor layer is filled with the removed portion through the interlayer dielectric layer 7, and the interlayer dielectric layer 7 is polished by a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the oxide layer 48; Step d: Fig.18As shown, a trench structure is etched and a gate oxide layer 48 is grown, and a polysilicon gate 43 is deposited in the trench; Step e: Fig.19 As shown, the polysilicon layer is polished using a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the N-type epitaxial layer 42, and then the polysilicon gate 43 is partially etched to form a gate; Step f: Fig. 20 As shown, an oxide layer 48 is regrown on the surface of the polysilicon gate 43 and the N-type epitaxial layer 42 thereon, polysilicon is deposited again to form another gate section, and then an oxide film is plated on it to form a split-gate structure; Step g: Fig.21 As shown, ion implantation is performed on the N-type epitaxial layer 42 avoiding the split gate structure to form a P- region 44 and an N+ region 45 in sequence; Step h: Fig. 22 As shown, an oxide layer 48 is deposited on the upper surface of the N+ region 45 and then a through hole is etched. A P+ region 46 is formed on the upper part of the P- region 44 by ion implantation through the through hole. A metal layer 47 is deposited on the oxide layer. The metal layer 47 passes through the through hole and contacts the P+ region 46. Step i: Fig.23 As shown, an ITO thin film layer 5 and an Al layer 6 are plated on the metal layer 47, and an interlayer dielectric layer 7 is produced again, and the interlayer dielectric layer 7 is polished by a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer 7 is flush with the upper surface of the Al layer 6; Step j: Fig.24 As shown, the RGB LED chips (including the P-pad layer 10, the P-GaN layer 11, the MQW layer 12, the n-GaN layer 13 and the N-pad layer 14 arranged in sequence) in the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B are connected to the driving backplane 1 using mass transfer and vacuum bonding technology; Step k: Fig.25 As shown, a Si layer 15 is deposited on the Al layer 6 of the pressure sensing sub-pixel S and patterned to form a hollow structure, a thin SiO2 layer 16 and a P-type silicon 17 are sequentially grown on the top of the Si layer 15 of the hollow structure, and then deep silicon etching is performed to drill holes, and tungsten 19 is deposited in the holes by a CVD process, and then a P-type single crystal silicon sensing film 18 with a piezoresistive electrode is bonded by a bonding process; Step 1: Fig.26 As shown, finally, a common cathode 8 and a thin film encapsulation layer 9 are grown, and the current flow is shown by the red arrow in the semiconductor device 4.

[0053] The optimized pixel arrangement schemes of the first and second embodiments are as follows: Fig. 27As shown, a pixel includes a red light-emitting sub-pixel R, a green light-emitting sub-pixel G, a blue light-emitting sub-pixel B, and a pressure sensing sub-pixel S. In terms of spatial distribution, the four vertices of a square include the pressure sensing sub-pixel S and the blue light-emitting sub-pixel B at the two diagonal vertices and the red light-emitting sub-pixel R and the green light-emitting sub-pixel G at the remaining two vertices, and the side length of the square is equal to the pixel width. Four concentrated red light-emitting sub-pixels R, green light-emitting sub-pixels G, blue light-emitting sub-pixels B or pressure sensing sub-pixels S are grouped together and share a mask opening.

[0054] Embodiment 1 and embodiment 2 adopt Fig. 27 The pixel optimization arrangement scheme shown in combination with the high-resolution driving backplane 1 can break through the physical limit of the existing high-resolution metal mask FMM, achieving high-resolution, high-brightness, high-contrast display with low response time.

[0055] Embodiment 1 and embodiment 2 are matched as follows Fig.28 The driving circuit shown can improve the performance and reliability of the display, and has the beneficial effects of high integration, low power consumption, high speed and good stability, so that it has a wide range of applications.

[0056] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A split-gate type light-emitting display equipped with a piezoresistive sensing function, characterized in that: include: A plurality of pixels, each of which includes a red light-emitting sub-pixel R, a green light-emitting sub-pixel G, a blue light-emitting sub-pixel B and a pressure sensing sub-pixel S; A driving backplane (1), wherein a plurality of regularly arranged via holes (2) are provided on the driving backplane (1), wherein the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B or the pressure sensing sub-pixel S covers at least one via hole (2), and the driving backplane (1) carries a plurality of pixels and respectively drives the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel to emit light and drives the pressure sensing sub-pixel S to receive pressure information; The red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B and the pressure sensing sub-pixel S all comprise an anode (3), a semiconductor device (4), an ITO thin film layer (5) and an Al layer (6); the anode (3) is arranged on the driving backplane (1) and covers at least one via hole (2); the semiconductor device (4) is located on a side of the anode (3) away from the driving backplane (1); the ITO thin film layer (5) is located on a side of the semiconductor device (4) away from the driving backplane (1); and the Al layer (6) is arranged on the ITO thin film layer (5).

2. The split-gate type light-emitting display equipped with a piezoresistive sensing function according to claim 1, characterized in that: The semiconductor device (4) comprises an N-type highly doped region (41), an N-type epitaxial layer (42), a gate (43), a P- region (44), an N+ region (45), a P+ region (46) and a metal layer (47); the N-type highly doped region (41) is located on a side of the anode (3) away from the driving backplane (1); an N-type epitaxial layer (42) is formed on the N-type highly doped region (41); the gate (43) is arranged in the N-type epitaxial layer (42) and is divided into two sections; the P- The region (44) is arranged on the upper surface of the N-type epitaxial layer (42) avoiding the gate (43), the N+ region (45) is arranged on the upper surface of the P+ region (46), an oxide layer (48) is arranged on the N+ region (45), a through hole is arranged on the oxide layer (49), the P+ region (46) is arranged in the P- region (44) below the through hole, a metal layer (47) is arranged on the oxide layer (19), and the metal layer (47) has a metal connector extending into the through hole and connected to the P+ region (46).

3. The split-gate type light-emitting display equipped with a piezoresistive sensing function according to claim 1, characterized in that: The red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B each comprise a P-pad layer (10), a P-GaN layer (11), an MQW layer (12), an n-GaN layer (13) and an N-pad layer (14) which are sequentially arranged on the Al layer (6).

4. The split-gate type light-emitting display with piezoresistive sensing function according to claim 1, characterized in that: A Si layer (15) with a hollow structure is provided on the Al layer (6) in the pressure sensing sub-pixel S, a SiO2 layer (16) is provided on the Si layer (15), a P-type silicon (17) is provided on the SiO2 layer (16), a P-type single crystal silicon sensing film (18) with a piezoresistive electrode is connected to the P-type silicon (17), a through hole is provided from the upper surface of the P-type silicon (17) to the lower bottom surface of the Si layer (15), and tungsten (19) connecting the P-type single crystal silicon sensing film (18) and the Al layer (6) is provided in the through hole.

5. The split-gate type light-emitting display equipped with a piezoresistive sensing function according to claim 4, characterized in that: It also includes an interlayer dielectric layer (7) and a common cathode (8), wherein the interlayer dielectric layer (7) is produced and filled between the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, the blue light-emitting sub-pixel B and the pressure sensing sub-pixel S, and the interlayer dielectric layer (7) corresponding to the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B is provided with an electrode groove, and the common cathode (8) is arranged on a side of the interlayer dielectric layer (7) away from the driving backplane (1) and covers the electrode groove, and the common cathode (8) is in contact with the upper surface of the red light-emitting sub-pixel R, the green light-emitting sub-pixel G and the blue light-emitting sub-pixel B through the electrode groove, and in the pressure sensing sub-pixel S, the common cathode (8) is connected to the piezoresistive electrode of the P-type single crystal silicon sensing film (18).

6. The split-gate type light-emitting display equipped with a piezoresistive sensing function according to claim 5, characterized in that: It also comprises a thin film encapsulation layer (9), wherein the thin film encapsulation layer (9) is located on a side of the common cathode (8) away from the driving backplane (1) and covers the common cathode (8).

7. A method for manufacturing a split-gate type light-emitting display equipped with a piezoresistive sensing function according to any one of claims 1 to 6, characterized in that: The steps include: S1, forming a plurality of regularly arranged via holes (2) on a driving back plate (1), and filling the via holes (2) with a conductive material, and then forming a plurality of anodes (3) on the upper surface of the driving back plate (1), with each anode (3) covering at least one via hole (2); S2, sequentially growing an N-type highly doped region (41), an N-type epitaxial layer (42) and an oxide layer (48) on the driving back plate (1) and the anode (3) to form a semiconductor layer; S3, patterning the semiconductor layer, filling the removed portion with an interlayer dielectric layer (7), and smoothing the interlayer dielectric layer (7) using a chemical mechanical smoothing process, so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of the oxide layer (48); S4, etching the trench structure and growing a gate oxide layer (48), and depositing a polysilicon gate (43) in the trench; S5, using a chemical mechanical polishing process to polish the polysilicon layer so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of the N-type epitaxial layer (42), and then partially etching the polysilicon gate (43) to form a gate; S6, growing an oxide layer (48) on the polysilicon gate, depositing polysilicon again to form another gate section, and then coating an oxide film to form a split-gate structure; S7, ion implantation is performed on the N-type epitaxial layer (42) avoiding the split gate structure to form a P- region (44) and an N+ region (45) in sequence; S8, depositing an oxide layer (48) on the upper surface of the N+ region (45), etching a through hole, forming a P+ region (46) on the upper part of the P- region (44) by ion implantation through the through hole, depositing a metal layer (47) on the oxide layer (48), and the metal layer (47) passes through the through hole to contact the P+ region (46); S9, coating an ITO thin film layer (5) and an Al layer (6) on the metal layer (47), producing an interlayer dielectric layer (7) again, and grinding the interlayer dielectric layer (7) using a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of the Al layer (6); S10, using mass transfer and vacuum bonding technology to connect the RGB LED chips in the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, and the blue light-emitting sub-pixel B to the driving backplane (1); S11, depositing a Si layer (15) on the Al layer (6) of the pressure sensing sub-pixel S and patterning it to form a hollow structure, sequentially growing a thin SiO2 layer (16) and a P-type silicon (17) on the top of the Si layer (15) of the hollow structure, then performing deep silicon etching to drill holes, depositing tungsten (19) in the holes using a CVD process, and then bonding a P-type single crystal silicon sensing film (18) with a piezoresistive electrode using a bonding process; S12. Finally, grow a common cathode (8) and a thin film encapsulation layer (9).

8. A method for manufacturing a split-gate type light-emitting display equipped with a piezoresistive sensing function according to any one of claims 1 to 6, characterized in that: The steps include: Sa, forming a plurality of regularly arranged via holes (2) on the driving back plate (1), and filling the via holes (2) with a conductive material, and then forming a plurality of anodes (3) on the upper surface of the driving back plate (1), with each anode (3) covering at least one via hole (2); Sb, sequentially growing an N-type high-doping region (41), an N-type epitaxial layer (42) and an oxide layer (48) on the driving back plate (1) and the anode to form a semiconductor layer; Sc, a patterned semiconductor layer, the removed portion is filled with an interlayer dielectric layer (7), and the interlayer dielectric layer (7) is smoothed by a chemical mechanical smoothing process, so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of the oxide layer (48); Sd, etching the trench structure and growing a gate oxide layer (48), and depositing a polysilicon gate (43) in the trench; Se, using a chemical mechanical polishing process to polish the polysilicon layer so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of the N-type epitaxial layer (42), and then partially etching the polysilicon gate (43) to form a gate; Sf, growing an oxide layer (48) on the surface of the polysilicon gate (43) and the N-type epitaxial layer (42) above it, depositing polysilicon again to form another gate section, and then coating a layer of oxide film to form a split gate structure; Sg, ion implantation on the N-type epitaxial layer (42) avoiding the split gate structure to sequentially form a P- region (44) and an N+ region (45); Sh, depositing an oxide layer (48) on the upper surface of the N+ region (45) and then etching a through hole, forming a P+ region (46) on the upper part of the P- region (44) by ion implantation through the through hole, depositing a metal layer (47) on the oxide layer (48), and the metal layer (47) passes through the through hole and contacts the P+ region (46); Si, plating an ITO thin film layer (5) and an Al layer (6) on the metal layer (47), producing an interlayer dielectric layer (7) again, and grinding the interlayer dielectric layer (7) using a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer (7) is flush with the upper surface of the Al layer (6); Sj, using mass transfer and vacuum bonding technology to connect the RGB LED chips in the red light-emitting sub-pixel R, the green light-emitting sub-pixel G, and the blue light-emitting sub-pixel B to the driving backplane (1); Sk, depositing a Si layer (15) on the Al layer (6) of the pressure sensing sub-pixel S and patterning it to form a hollow structure, sequentially growing a thin SiO2 layer (16) and a P-type silicon (17) on the top of the Si layer (15) of the hollow structure, then performing deep silicon etching to drill holes and depositing tungsten (19) in the holes by a CVD process, and then bonding a P-type single crystal silicon sensing film (18) with a piezoresistive electrode by a bonding process; S1. Finally, grow the common cathode (8) and thin film encapsulation layer (9).

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