Non-volatile memory with layer-by-layer ramp down after program verification

Abstract

Memory cells are disclosed that are arranged as NAND strings to form blocks divided into sub-blocks, and each NAND string includes dummy memory cells connected to dummy word lines. The memory cells are programmed by applying program pulses to the selected word lines in the selected sub-blocks, wherein a program verify is performed between the pulses. Programming of an unselected NAND string in the selected sub-block is inhibited by boosting a channel of the unselected NAND string from a positive pre-charge voltage to a boosted voltage. The channel of the unselected NAND string is pre-charged while reducing a voltage at the end of a program verify by applying an overdrive voltage to a data word line in a sub-block closer to a source line than the selected sub-block, and before reducing the data word line in the sub-block closer to the source line to a static voltage, the NAND string is pre-charged by applying the overdrive voltage to the data word line in the sub-block closer to the source line. A dummy word line between the sub-blocks is lowered to the static voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of, and is hereby incorporated by reference in its entirety, for all purposes, U.S. non-provisional application Ser. No. 17 / 898,850, filed Aug. 30, 2022, and entitled “NON-VOLATILE MEMORY WITH TIER-WISE RAMP DOWN AFTER PROGRAM-VERIFY”. Background Art

[0003] The present disclosure relates to non-volatile storage devices.

[0004] Semiconductor memories are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories may include non-volatile memories or volatile memories. Non-volatile memories allow information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Examples of non-volatile memories include flash memory (e.g., NAND-type and NOR-type flash memory).

[0005] Users of nonvolatile memory can program (i.e., write) data to nonvolatile memory and subsequently read the data back. For example, a digital camera can take a picture and store the picture in nonvolatile memory. Later, the user of the digital camera can view the picture by having the digital camera read the picture from the nonvolatile memory. Because users often rely on the data they store, it is important for users of nonvolatile memory to be able to reliably store data so that the data can be successfully read back. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Like numbered elements refer to common parts in different figures.

[0007] Figure 1 is a block diagram depicting one embodiment of a storage system.

[0008] Figure 2A is a block diagram of one embodiment of a memory die.

[0009] Figure 2B is a block diagram of one embodiment of an integrated memory component.

[0010] Figure 3A and Figure 3B Various embodiments of integrated memory components are depicted.

[0011] Figure 4 is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

[0012] Figure 4A is a block diagram of one embodiment of a memory structure having two planes.

[0013] Figure 4B Depicted is a top view of a portion of one embodiment of a block of memory cells.

[0014] Figure 4C A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0015] Figure 4D A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0016] Figure 4E A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0017] Figure 4F is a cross-sectional view of one embodiment of a vertical column of memory cells.

[0018] Figure 4G A cross section of a memory hole implementing a vertical NAND string is depicted.

[0019] Figure 4H A cross section of a memory hole implementing a vertical NAND string is depicted.

[0020] Fig. 4I A cross section of a memory hole implementing a vertical NAND string is depicted.

[0021] Figure 4J is a schematic diagram of multiple NAND strings.

[0022] Figure 5A The threshold voltage distribution is depicted.

[0023] Figure 5B The threshold voltage distribution is depicted.

[0024] Figure 5C The threshold voltage distribution is depicted.

[0025] Figure 5D The threshold voltage distribution is depicted.

[0026] Figure 5E The threshold voltage distribution is depicted.

[0027] Fig. 5F The threshold voltage distribution is depicted.

[0028] Figure 6is a flow chart describing one embodiment of a process for programming non-volatile memory.

[0029] Figure 7 is a flow chart describing one embodiment of a process for performing program verification.

[0030] Figure 8 Depicted are NAND strings being precharged as part of the process of inhibiting the NAND strings from programming during the programming process.

[0031] Fig. 9 is a signal diagram that describes the behavior of various signals during program verify and precharge.

[0032] Fig.10 Depicted are NAND strings being precharged as part of the process of inhibiting the NAND strings from programming during the programming process.

[0033] Fig.11 Depicted are NAND strings being precharged as part of the process of inhibiting the NAND strings from programming during the programming process.

[0034] Fig.12 is a flow chart describing one embodiment of a process that includes precharging the channels of unselected memory cells while reducing the voltage at the end of program verification.

[0035] Fig.13 is a flow chart describing one embodiment of a process for programming that includes precharging the channels of unselected memory cells while reducing the voltage at the end of program verification.

[0036] Fig.14 is a signal diagram describing one embodiment of programming memory cells in a sub-block closest to a source line.

[0037] Fig.15 A NAND string is depicted.

[0038] Fig.16 is a signal diagram describing one embodiment of programming memory cells in a middle sub-block.

[0039] Fig.17 A NAND string is depicted.

[0040] Fig.18 is a signal diagram describing one embodiment of programming memory cells in a sub-block away from a source line.

[0041] Fig.19 A NAND string is depicted. DETAILED DESCRIPTION

[0042] Some systems program memory cells by applying a programming dose to a selected word line that is connected to a memory cell selected for programming (a selected memory cell). Between programming doses, a programming verification is performed to determine whether the programming is successful. Because the selected word line can be connected to selected memory cells and unselected memory cells (i.e., memory cells that should not be programmed), the system takes measures to avoid interference (e.g., undesired programming) of unselected memory cells, including precharging and boosting the voltage of the channel of the unselected memory cell to prevent interference. Precharging is typically performed after programming verification and before the next programming dose. Boosting is performed after precharging. In some memories, under certain conditions, some parts of the memory cannot access the precharged source. Without proper precharging, the boosting of the channel of the unselected memory cell may not be successful in preventing interference.

[0043] In order to overcome the above problems, it is proposed to complete the precharge of the channels of the unselected memory cells while reducing the voltage at the end of the programming verification. The proposed precharge scheme can be used with a memory system that performs sub-block operations. For example, the memory cells of a block are divided into sub-blocks. The selected memory cells of the selected sub-block connected to the selected data word line are programmed by applying the above-mentioned programming dose to the selected data word line, wherein the programming verification is performed between the doses. By boosting the channels of those unselected memory cells connected to the selected data word line from the positive precharge voltage to the boost voltage, the unselected memory cells of the selected sub-block connected to the selected data word line are prohibited from being programmed. The channels of unselected memory cells connected to the selected data word line are precharged to a precharge voltage, while the voltage at the end of program verification is reduced by applying an overdrive voltage to the data word line between the selected word line and one or more control lines (e.g., one or more source lines) while applying the precharge voltage to the one or more control lines to provide the channels of the unselected memory cells with access to the precharge voltage of the one or more control lines while reducing the voltage of the data word line farther from the one or more control lines than the selected word line. After precharging and before reducing the data word line between the selected word line and the one or more control lines from the overdrive voltage to one or more voltages lower than the threshold voltage of the memory cells connected to the data word line between the selected word line and the one or more control lines, the channels of the unselected memory cells are cut off from the one or more control lines.

[0044] Figure 11 is a block diagram of an embodiment of a non-volatile storage system 100 that implements the technology of the present invention described herein. In one embodiment, the non-volatile storage system 100 is a solid state drive ("SSD"). The non-volatile storage system 100 can also be a memory card, a USB drive, or other types of storage systems. The technology of the present invention is not limited to any one type of storage system. The storage system 100 is connected to a host 102, which can be a computer, a server, an electronic device (e.g., a smart phone, a tablet computer, or other mobile device), an appliance, or another device that uses a memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100, but is connected to the storage system. In other embodiments, the storage system 100 is embedded in the host 102.

[0045] Figure 1 The components of the memory system 100 depicted in FIG. 1 are electronic circuits. The memory system 100 includes a memory controller 120 connected to a non-volatile memory 130 and a local high-speed volatile memory 140 (e.g., DRAM). The memory controller 120 uses the local high-speed volatile memory 140 to perform certain functions. For example, the local high-speed volatile memory 140 stores logic in a physical address translation table ("L2P table").

[0046] The memory controller 120 includes a host interface 152 connected to and communicating with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) through PCI Express (PCIe). Other interfaces such as SCSI, SATA, etc. may also be used. The host interface 152 is also connected to a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit. NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of the system on chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Since all links in the NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of the integrated subsystem continues to increase, compared with previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges), NOC provides enhanced performance (such as throughput) and scalability. In other embodiments, NOC 154 may be replaced by a bus. Processor 156, ECC engine 158, memory interface 160, and DRAM controller 164 are connected to and communicate with NOC 154. DRAM controller 164 is used to operate and communicate with local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, local high-speed volatile memory 140 may be SRAM or another type of volatile memory.

[0047] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, the ECC engine 158 is an electronic circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a customized dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0048] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a customized dedicated hardware circuit without any software. Processor 156 also implements a conversion module, either as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using a physical address associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the storage system is idle to store data between the locations of one or more memory dies as desired. In order to implement such a system, memory controller 120 (e.g., conversion module) performs address conversion between the logical address used by the host and the physical address used by the memory die. An exemplary implementation is to maintain a table (i.e., the above-mentioned L2P table) that identifies the current conversion between the logical address and the physical address. The entries in the L2P table may include identification of the logical address and the corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table", they need not be tables in the literal sense. Rather, logical address to physical address tables (or L2P tables) may be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In this case, the entire set of L2P tables is stored in the memory die 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed volatile memory 140.

[0049] The memory interface 160 communicates with the non-volatile memory 130. In one embodiment, the memory interface provides a switch mode interface. Other interfaces may also be used. In some exemplary implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffer for transmitting data to one or more memory dies and receiving data from one or more memory dies.

[0050] In one embodiment, non-volatile memory 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of a memory die 200 including non-volatile memory 130. Each of the one or more memory dies of non-volatile memory 130 may be implemented as Figure 2A A memory die 200 is provided. Figure 2AThe components depicted in are circuits. The memory die 200 includes a memory array 202, which may include non-volatile memory cells, as described in more detail below. The array terminal lines of the memory array 202 include individual word line layers organized into rows, and individual bit line layers organized into columns. However, other orientations may also be implemented. The memory die 200 includes a row control circuit 220, the output end 208 of which is connected to the corresponding word line of the memory array 202. The row control circuit 220 receives a set of M row address signals and one or more various control signals from the system control logic circuit 206, and may generally include circuits such as a row decoder 222, an array terminal driver 224, and a block selection circuit 226 for both read operations and write (programming) operations. The row control circuit 220 may also include a read / write circuit. The memory die 200 also includes a column control circuit 210, which includes a sense amplifier 230, the input end / output end 206 of which is connected to the corresponding bit line of the memory array 202. Although only a single block is shown for array 202, the memory die may include multiple arrays that may be accessed individually. Column control circuitry 210 receives a set of N column address signals and one or more various control signals from system control logic 260, and may generally include circuits such as column decoders 212, array terminal receivers or driver circuits 214, and read / write circuits and I / O multiplexers.

[0051] The system control logic 260 receives data and commands from the memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 can be programmed by software. In other embodiments, the state machine 262 does not use software and is completely implemented in hardware (e.g., electronic circuits). In another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor that is on or outside the memory chip. The system control logic 262 may also include a power control module 264 that controls the power and voltage supplied to the rows and columns of the memory structure 202 during memory operation, and may include a charge pump and regulator circuit for generating a regulated voltage. The system control logic 262 includes a storage device 366 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating the memory array 202.

[0052] Commands and data are transmitted between the memory controller 120 and the memory die 200 via a memory controller interface 268 (also referred to as a "communication interface"). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a switch mode interface and an open NAND flash interface (ONFI). Other I / O interfaces may also be used.

[0053] In some embodiments, all elements of memory die 200, including system control logic 260, may be formed as part of a single die. In other embodiments, some or all of system control logic 260 may be formed on different dies.

[0054] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory integrally formed in one or more physical levels of memory cells having active regions disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0055] In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (eg, NOR-type flash memory) may also be used.

[0056] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required to implement the claimed new embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0057] An example of a ReRAM crosspoint memory includes a reversible resistance switching element arranged in a crosspoint array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0058] Another example is a magnetoresistive random access memory (MRAM) that stores data via magnetic storage elements. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the storage memory by the external magnetic field. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cells, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0059] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms using only laser pulses (or light pulses from another source). Therefore, the programming dose is a laser pulse. The memory cell can be disabled by preventing the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage light or other waves. These memory elements within each selectable memory cell or bit can include additional series elements as selectors, such as a bidirectional threshold switch or a metal insulator substrate.

[0060] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those of ordinary skill in the art.

[0061] Figure 2A The components of the invention can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuits, which include Figure 2A 202; however, this reduces the area of ​​the memory die available for peripheral circuitry. This can place quite severe constraints on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuitry within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic component 260, the reduction in available area can limit the available functionality that can be implemented on the chip. Therefore, in the design of the memory die of the memory system 100, a fundamental trade-off needs to be made between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuitry.

[0062] Another area where the memory structure 202 and the peripheral circuits often conflict is in the processing involved in forming these areas, as these areas often involve different processing technologies and the trade-offs when implementing different technologies on a single die. For example, when the memory structure 202 is a NAND flash memory, this is an NMOS structure, while the peripheral circuits are often CMOS based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic component 260 often employ CMOS devices. The processing operations used to manufacture a CMOS die will differ in many ways from processing operations optimized for NMOS flash memory, NAND memory, or other memory cell technologies.

[0063] To improve these limitations, the embodiments described below can Figure 2AThe components of the memory structure 202 are separated into separately formed dies, and then the dies are bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die), and some or all of the peripheral circuit elements (including one or more control circuits) can be formed on a separate die (referred to as the control die). For example, the memory die can be formed only by memory elements, such as a memory cell array of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types. Some or all of the peripheral circuits (even including elements such as decoders and sense amplifiers) can then be moved to a separate control die. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements that have now been moved to a control die that can be optimized for CMOS processing. This provides more room for peripheral elements, and if the peripheral elements are confined to the edge of the same die that houses the memory cell array, additional capabilities that may not be easily combined can now be combined. The two dies can then be bonded together in a bonded multi-die memory circuit where the array on one die is connected to the peripheral components on the other die. For example, although the following will focus on a bonded memory circuit with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0064] Figure 2B Shows Figure 2A An alternative arrangement to the arrangement of may be achieved using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of an integrated memory component 207 is depicted. One or more integrated memory components 207 may be used to implement the non-volatile memory 130 of the memory system 100. The integrated memory component 207 includes two types of semiconductor dies (or more succinctly, "dies"). The memory die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to connect to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

[0065] Figure 2B An example of peripheral circuitry is shown, including control circuits formed in a peripheral circuit or control die 211 that are coupled to a memory structure 202 formed in a memory die 201. Common components are shown in a similar manner to Figure 2ASystem control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of column control circuitry 210 and all or a portion of row control circuitry 220 are located on memory die 201. In some embodiments, some circuits in system control logic 260 are located on memory die 201.

[0066] The system control logic 260, row control circuit 220, and column control circuit 210 may be formed by conventional processes (e.g., CMOS processes), so that adding elements and functions more commonly found on the memory controller 120, such as ECC, may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 120 may also be used to manufacture the system control logic 260, row control circuit 220, and column control circuit 210). Therefore, while removing such circuits from a die (such as the memory 2 die 201) may reduce the number of steps required to manufacture such a die, adding such circuits to a die (such as the control die 211) may not require many additional process steps. Since some or all of the control circuits 260, 210, 220 are implemented using CMOS technology, the control die 211 may also be referred to as a CMOS die.

[0067] Figure 2B Column control circuitry 210 including sense amplifier 230 on control die 211 is shown coupled to memory structure 202 on memory die 201 via electrical path 206. For example, electrical path 206 may provide electrical connections between column decoder 212 and driver circuit 214 and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of memory die 201 that are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical path 306 connected to column control circuitry 210, including a pair of bond pads. Similarly, row control circuitry 220 (including row decoder 222, array driver 224, and block selector 226) is coupled to memory structure 202 via electrical path 208. Each of the electrical paths 208 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 211 and the memory die 201 .

[0068] For the purposes of this document, the phrase "control circuitry" or "one or more control circuits" may include any one or any combination of memory controller 120, state machine 262, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, a microcontroller, a microprocessor, and / or other similar functional circuitry. The control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, FGA, ASIC, integrated circuit, or other type of circuitry.

[0069] In some embodiments, there is more than one control die 211 and more than one memory die 201 in the integrated memory component 207. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory dies 201. Figure 3A Depicted is a side view of one embodiment of an integrated memory component 207 (e.g., including a stack of control dies 211 and memory dies 201) stacked on a substrate 271. The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control dies 211.

[0070] Each control die 211 is attached (e.g., bonded) to at least one of the memory dies 201. Some of the bonding pads 282 / 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which can be formed of epoxy or other resins or polymers. The solid layer 280 protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials can be used as the solid layer 280, but in an embodiment, the material can be Hysol epoxy resin from Henkel Corporation (which has offices in California, USA).

[0071] The integrated memory components 207 may be stacked, for example, in a stepped offset manner so that the bonding pads at each level are uncovered and accessible from above. Wire bonds 270 connected to the bonding pads connect the control die 211 to the substrate 271. Multiple such wire bonds may be formed across the width of each control die 211 (i.e., formed to Figure 3A ).

[0072] Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory die 201. Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211. TSVs 276, 278 may be formed before, during, or after the formation of the integrated circuits in the semiconductor die 201, 211. The TSVs may be formed by etching holes through the wafer. The holes may then be lined with a barrier to prevent metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor, such as copper, although other suitable materials may be used, such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof.

[0073] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory component 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory component 207 is to be used as an LGA package. Solder balls 272 may form part of the interface between integrated memory component 207 and memory controller 120.

[0074] Figure 3B A side view of another embodiment of an integrated memory component 207 stacked on a substrate 271 is depicted. Figure 3B The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are far more than three memory dies 201 and far more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, a control die 211 can be bonded to two or more memory dies 201.

[0075] Some of the bonding pads 282, 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of epoxy or other resins or polymers. Figure 3A Compared to the example in Figure 3B The integrated memory component 207 in FIG. 2 has no step offset. Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory die 201 . Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211 .

[0076] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory assembly 207 is to be used as an LGA package.

[0077] As briefly discussed above, the control die 211 and the memory die 201 can be bonded together. The bonding pads on each die 201, 211 can be used to bond the two dies together. In some embodiments, in the so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additional materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment, which is substantially free of environmental particles, otherwise the environmental particles may be deposited on the bonding pads and prevent close bonding. Under such properly controlled conditions, the bonding pads are aligned and pressed against each other to form mutual bonding based on surface tension. This bonding can be formed at room temperature, although heat can also be applied. In the embodiment using Cu-Cu bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 5 μm to 5 μm. Although the process is referred to as Cu-Cu bonding in this article, the term can also be applied to the case where the bonding pads are formed by materials other than copper.

[0078] When the area of ​​the bonding pad is small, it may be difficult to bond the semiconductor die together. By providing a film layer on the surface of the semiconductor die including the bonding pad, the size and spacing of the bonding pad can be further reduced. The film layer is arranged around the bonding pad. When the die are put together, the bonding pads can be bonded to each other, and the film layers on the individual dies can be bonded to each other. This bonding technology can be referred to as hybrid bonding. In an embodiment using hybrid bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 1 μm to 5 μm. Bonding technology can be used to provide bonding pads with smaller size and spacing.

[0079] Some embodiments may include a film on the surface of the tube core 201, 211. If such a film is not initially provided, the space between the tube cores can be filled with epoxy or other resins or polymers at the bottom. The bottom fill material can be applied as a liquid and then hardened into a solid layer. This bottom filling step protects the electrical connection between the tube core 201, 211 and further fixes the tube core together. Various materials can be used as the bottom fill material, but in an embodiment, the bottom fill material can be a Hysol epoxy resin from Henkel Corporation, which has offices in California, USA.

[0080] Figure 4 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array / structure that may include a memory structure 202 that includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4A portion 400 of a memory block is shown. The depicted structure includes a set of bit lines BL located above a stack 401 of alternating dielectric and conductive layers. For example, one of the dielectric layers is labeled D, and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. As will be explained below, in one embodiment, the alternating dielectric and conductive layers are divided into six (or a different number of) regions by isolation regions IR. These regions are sometimes referred to as fingers or strings. Figure 4 An isolation region IR is shown separating the two regions. A source line layer SL is located below the alternating dielectric layer and word line layer. A memory hole is formed in the stack of alternating dielectric layers and conductive layers. For example, the memory hole is marked as MH. Note that Figure 4 202, the dielectric layers are depicted as perspective views so that the reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping material to form vertical columns of memory cells. Each memory cell can store one or more data bits. More details of a three-dimensional monolithic memory array including memory structure 202 are provided below.

[0081] Figure 4A 4 and 5. 4. The memory cells of FIG. 20 are grouped into blocks. FIG. 20 is a block diagram illustrating an exemplary organization of a memory structure 202 that is divided into two planes 402 and 404. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, a different number of blocks and planes may also be used. In one embodiment, a block of memory cells is the unit of erase. That is, all memory cells of a block are erased together. Memory cells may also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells because the memory cells of a block share a common set of word lines. For example, the word lines of a block are all connected to all vertical NAND strings of the block. Although Figure 4A Two planes 402 / 404 are shown, but more or less than two planes may be implemented.In some embodiments, the memory structure 202 includes four planes, eight planes, or more than eight planes.

[0082] FIG. 4B to FIG. 4J An exemplary three-dimensional ("3D") NAND structure is depicted, corresponding to Figure 4 structure and can be used to implement Figure 2A and Figure 2B Memory structure 202. Figure 4B is a block diagram depicting a top view of a portion 406 of block 2 of plane 402. Figure 4B It can be seen that Figure 4BThe blocks depicted in FIG. extend in the direction of 432. In one embodiment, the memory array has many layers; however, Figure 4B Only the top layer is shown.

[0083] Figure 4B A plurality of circles representing vertical columns corresponding to memory holes are depicted. Each of the vertical columns includes a plurality of select transistors (also referred to as select gates / selection gates) and a plurality of memory cells. In one embodiment, each vertical column implements a NAND string. For example, Figure 4B A subset of vertical columns / NAND strings 426, 432, 436, 446, 456, 462, 466, 472, 474, and 476 are labeled.

[0084] Figure 4B Also depicted is a set of bit lines 415 , including bit lines 411 , 412 , 413 , 414 , . . . , 419 . Figure 4B Twenty-four bit lines are shown because only a portion of the block is shown. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line. For example, bit line 411 is connected to vertical columns 426, 436, 446, 456, 466, and 476.

[0085] Figure 4B The block depicted in FIG. 1 includes a set of isolation regions 480, 482, 484, 486, and 488, which are made of SiO 2 However, other dielectric materials may also be used. Isolation regions 480, 482, 484, 486, and 488 are used to divide the top layer of the block into six regions; for example, Figure 4B The top layer depicted in FIG is divided into regions 420, 430, 440, 450, 460, and 470. In one embodiment, the isolation regions divide only the layer used to implement the select gates (e.g., SGD) so that the NAND strings in different regions can be independently selected. In one exemplary implementation, the bit lines are connected to only one vertical column / NAND string in each of the regions 420, 430, 440, 450, 460, and 470. In this implementation, each block has twenty-four rows of active columns, and each bit line is connected to six rows in each block. In one embodiment, all six vertical columns / NAND strings connected to a common bit line are connected to the same word line (or word line group); therefore, the system uses the drain-side select line (SGD) to select one (or another subset) of the six to be subjected to a memory operation (program, verify, read, and / or erase).

[0086] although Figure 4BEach region 420, 430, 440, 450, 460, and 470 is shown as having four vertical columns in one block, and six regions have twenty-four vertical columns, but these exact numbers are exemplary implementations. Other embodiments may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block. Figure 4B It is also shown that the vertical columns are staggered. In other embodiments, different staggered patterns can be used. In some embodiments, the vertical columns are not staggered.

[0087] Figure 4C A side view of a portion 406 of block 2 of plane 402 is depicted, which is also shown in FIG. Figure 4B Depicted in. Figure 4C The side view of FIG. 1 shows that the memory array is implemented as a three-layer architecture, where each layer is separated by a bonding area. In one embodiment, the block is divided into sub-blocks so that each layer is a separate sub-block. For example, in Figure 4C In a three-layer architecture of FIG. 1 , the block is divided into three sub-blocks. The first sub-block, sub-block 0 (SB0), is the bottom sub-block. The second sub-block, sub-block 1 (SB1), is the middle sub-block. The third sub-block, sub-block 2 (SB2), is the top sub-block. In an exemplary embodiment including 270 word lines, SB0 includes word lines WL0-WL89, SB1 includes word lines WL90-WL179, and SB2 includes word lines WL180-WL269. In other embodiments, the block has more than three layers and / or the block is divided into more than three sub-blocks.

[0088] Figure 4D A portion of one embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B The cross-sectional view cuts through the vertical columns (NAND strings) 472 and 474 of region 470 (see Figure 4B ). Figure 4D The structure includes: three drain side selection layers SGD0, SGD1 and SGD2 (which form selection lines); three source side selection layers SGS0, SGS1 and SGS2 (which form selection lines); dummy word line layers D0L, D0U, D1L, D1I, D2L and D2U for connecting to dummy memory cells (not storing data from the host); 270 data word line layers WL0-WL269 for connecting to data memory cells (storing data), and a dielectric layer DL. Other embodiments may implement more or less than the above embodiments for Figure 4D In one embodiment, SGD0, SGD1 and SGD2 are connected together; and SGDS0, SGS1 and SGS2 are connected together.

[0089] Vertical columns 472 and 474 are depicted as protruding through the drain side select layer, source side select layer, dummy word line layer, and word line layer. In one embodiment, each vertical column includes a vertical NAND string. Below the vertical columns and the layers listed below is a substrate 453, an insulating film 454 on the substrate, and a source line SL. The NAND string of vertical column 472 has a source terminal at the bottom of the stack and a drain terminal at the top of the stack. Figure 4B Consistent, Figure 4D Vertical columns 442 connected to bit lines 414 via connectors 417 are shown.

[0090] For ease of reference, the drain side selection layer, the source side selection layer, the dummy word line layer, and the data word line layer are collectively referred to as the conductive layer. In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layer, such as doped polysilicon, metals (such as tungsten or metal silicide). In some embodiments, different conductive layers may be formed of different materials. Between the conductive layers is a dielectric layer DL. In one embodiment, the dielectric layer is made of SiO 2 In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0091] The non-volatile memory cells are formed along vertical columns that extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings to form a block having three sub-blocks SB0, SB1, and SB2. Word line layers WL0 to W269 are connected to the memory cells (also referred to as data memory cells). Each NAND string of the block includes memory cells in each word block in the three sub-blocks; for example, memory cells connected to word lines WL0 to WL89 are in SB0, memory cells connected to word lines WL90 to WL179 are in SB1, and memory cells connected to word lines WL180 to WL269 are in SB2. The dummy word line layer is connected to the dummy memory cells. The dummy memory cells do not store host data and are not eligible to store host data (data provided from an entity external to the host or storage system 100), while the data memory cells are eligible to store host data. The host data can be contrasted with system data generated by the memory system 100 (e.g., L2P table). In some embodiments, the data memory cells and the dummy memory cells may have the same structure. The drain side selection layers SGD0, SGD1, and SGD2 are used to electrically connect and disconnect the NAND string to the bit line. The source side selection layers SGS0, SGS1, and SGS2 are used to electrically connect and disconnect the NAND string to the source line SL.

[0092] Figure 4DTwo bonding regions are also shown. In one embodiment, etching so many word line layers intermixed with dielectric layers is expensive and / or challenging. To alleviate this burden, one embodiment includes laying down a first stack of word line layers (e.g., for SB0) alternating with dielectric layers, laying down a lower bonding region, laying down a second stack of word line layers (e.g., for SB1) alternating with dielectric layers, laying down an upper bonding region, and laying down a third stack of word line layers (e.g., for SB2) alternating with dielectric layers. The bonding region is located between the first stack and the second stack, and between the second stack and the third stack. In one embodiment, the bonding region is made of the same material as the word line layers.

[0093] In one set of embodiments, the data word lines are divided into three groups of data word lines: a first plurality of data word lines (e.g., WL0 to WL89) are connected to the non-volatile memory cells of the first sub-block SB0, but not to the non-volatile memory cells of the other sub-blocks SB1 and SB2; a second plurality of data word lines (e.g., WL90 to WL179) are connected to the non-volatile memory cells of the second sub-block SB1, but not to the non-volatile memory cells of the other sub-blocks SB0 and SB2, and a third plurality of data word lines (e.g., WL180 to WL269) are connected to the non-volatile memory cells of the second sub-block SB2, but not to the non-volatile memory cells of the other sub-blocks SB0 and SB1. In these embodiments, the dummy word lines D0U and D1L are closer to the source line SL than the second plurality of data word lines (e.g., WL90 to WL179) and the third plurality of data word lines (e.g., WL180 to WL269). The dummy word line D0U (and the dummy memory cells connected to D0U) are located on a first side of the bonding area, and the dummy word line D1L (and the dummy memory cells connected to D1L) are located on a second side of the bonding area. The dummy word lines D0U and D1L are located between a first plurality of data word lines (e.g., WL0 to WL89) and a second plurality of data word lines (e.g., WL90 to WL179). The dummy memory cells connected to the dummy word lines D0U and D1L are located between the first sub-block SB0 and the second sub-block SB1.

[0094] Figure 4E A portion of one embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B The cross-sectional view cuts through the vertical columns (NAND strings) 432 and 434 of region 430 (see Figure 4B ). Figure 4E Shown with Figure 4D Same alternating conductive and dielectric layers. Figure 4EAlso shown is an isolation region 482. Isolation regions 480, 482, 484, 486, and 488 occupy space that was already used for a portion of the memory holes / vertical columns / NAND strings. For example, isolation region 482 occupies space that was already used for a portion of vertical column 434. More specifically, a portion of vertical column 434 (e.g., half of the diameter) has been removed in layers SDG0, SGD1, SGD2, and DD0 to accommodate isolation region 482. Thus, while most of vertical column 434 is cylindrical (having a circular cross-section), portions of vertical column 434 in SGD0, SGD1, and SGD2 have a semicircular cross-section. In one embodiment, after forming a stack of alternating conductive and dielectric layers, the stack is etched to create space for the isolation region, and the space is subsequently filled with SiO 2 .

[0095] Figure 4F A portion of a vertical column 472 is depicted. Figure 4C In one embodiment, the vertical columns 472 are circular; however, in other embodiments, other shapes may be used. In one embodiment, the vertical columns 472 include a material such as SiO 2 An inner core layer 490 is made of a dielectric of. Other materials may also be used. Surrounding the inner core 490 is a polysilicon channel 491. Materials other than polysilicon may also be used. Note that channel 491 is connected to the bit line and the source line. Surrounding channel 491 is a tunneling dielectric 492. In one embodiment, tunneling dielectric 492 has an ONO structure. Surrounding tunneling dielectric 492 is a charge trapping layer 493, such as (for example) silicon nitride. Other memory materials and structures may also be used. The technology described herein is not limited to any particular material or structure.

[0096] Figure 4FA dielectric layer DL is depicted, as well as word line layers WL264, WL265, WL266, WL267, and WL268. Each of the word line layers includes a word line region 496 surrounded by an aluminum oxide layer 497, which is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer may be a vertical layer parallel to and adjacent to the charge trapping layer 493. The physical interaction of the word line layer with the vertical columns forms a memory cell. Thus, in one embodiment, a memory cell includes a channel 491, a tunneling dielectric 492, a charge trapping layer 493, a blocking oxide layer 498, an aluminum oxide layer 497, and a word line region 496. For example, word line layer WL268 and a portion of vertical column 472 constitute memory cell MC1. Word line layer WL267 and a portion of vertical column 472 constitute memory cell MC2. Word line layer WL266 and a portion of vertical column 472 constitute memory cell MC3. Word line layer WL265 and a portion of vertical column 472 constitute memory cell MC4. Word line layer WL264 and a portion of vertical column 472 constitute memory cell MC5. In other architectures, the memory cells may have different structures; however, the memory cells will still still be storage cells.

[0097] When programming a memory cell, electrons are stored in a portion of the charge trapping layer 493 that is associated with the memory cell (e.g., in the memory cell). In response to an appropriate voltage on the word line region 496, these electrons are attracted from the channel 491 into the charge trapping layer 493 through the tunneling dielectric 492. The threshold voltage (Vth) of the memory cell increases in proportion to the amount of charge stored. In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

[0098] Figure 4G Shows Figure 4F A cross section of a vertical column 472, wherein MC5 is cut through. Thus, Figure 4G Word line layer WL264, inner core 490, channel 491, tunnel dielectric 492, charge trapping layer 493, aluminum oxide layer 497, and blocking oxide layer 498 are depicted.

[0099] Figure 4H A cross section of a vertical column 472 is shown, with a cut through SGD1 (the select gate layer implementing the select gates). Figure 4HA drain side select line layer SGD1 , an inner core 490 , a channel 491 , a tunneling dielectric 492 , a charge trapping layer 493 , an aluminum oxide layer 497 , and a blocking oxide layer 498 are depicted.

[0100] Fig. 4I A cross section of a vertical column 434 is shown, with SGD1 cut through. Thus, Fig. 4I A drain side select line layer SGD1 , an inner core 490 , a channel 491 , a tunneling dielectric 492 , a charge trapping layer 493 , an aluminum oxide layer 497 , and a blocking oxide layer 498 are depicted. Fig. 4I A portion of isolation region 482 is also shown. Fig. 4I As can be seen in FIG. 4 , because the vertical columns (NAND strings) 434 intersect the isolation regions 482 , the select gates (select gate layers) of the vertical columns 434 are semicircular (or partially circular in shape).

[0101] Figure 4J yes Figures 4 to 4I Schematic diagram of a portion of memory array 202 is depicted in FIG. Figure 4J Physical data word lines WL0-WL269 are shown extending across the entire block. Figure 4J The structure corresponds to Figure 4A The portion 406 in block 2 includes bit lines 411. Within this block, in one embodiment, each bit line is connected to six NAND strings. Thus, Figure 4J Bit line 411 is shown connected to NAND string NS0 (which corresponds to vertical column 426), NAND string NS1 (which corresponds to vertical column 436), NAND string NS2 (which corresponds to vertical column 446), NAND string NS3 (which corresponds to vertical column 456), NAND string NS4 (which corresponds to vertical column 466), and NAND string NS5 (which corresponds to vertical column 476). As described above, in one embodiment, for each region separated by isolation regions (480, 482, 484, 486, and 487), SGD0, SGD1, and SGD2 are connected together to operate as a single logic select gate to form SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4, and SGD-s5. SGD0, SGD1, and SGD2 are also connected together to operate as a single logic select gate in the embodiment. Figure 4J Although the select gates SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4, and SGD-s5 are isolated from each other by the isolation regions, the data word lines WL0-WL269 of each region are connected together. Figure 4JAs can be seen, each word line (including the word line selected for memory operation) is connected to memory cells in a block, memory cells in multiple regions of the block (e.g., 420, 430, 44, 450, 460 and 470), and connected to memory cells in a sub-block (e.g., SB0, SB1 or Sb2) of the block. Figure 4J Only the NAND string connected to bit line 411 is shown. However, a complete schematic diagram of the block would show each bit line and the six vertical NAND strings connected to each bit line.

[0102] Although Figures 4 to 4J An exemplary memory of is a three-dimensional memory structure including vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein.

[0103] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process, the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. Figure 5A is a graph of threshold voltage versus number of memory cells and illustrates an exemplary threshold voltage distribution for a memory array when each memory cell stores one bit of data per memory cell. A memory cell storing one bit of data per memory cell is referred to as a single-level cell ("SLC"). Data stored in an SLC memory cell is referred to as SLC data; therefore, SLC data includes one bit per memory cell. Data stored as one bit per memory cell is SLC data. Figure 5A Two threshold voltage distributions are shown: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Thus, memory cells having threshold voltages in threshold voltage distribution E are in an erased data state (e.g., they are erased). Thus, memory cells having threshold voltages in threshold voltage distribution P are in a programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data "1" and programmed memory cells store data "0". Figure 5A Depicted is a read compare voltage Vr. By testing (eg, performing one or more sensing operations) whether the threshold voltage of a given memory cell is above or below Vr, the system can determine whether the memory cell is erased (state E) or programmed (state P). Figure 5A Also depicted is a verify reference voltage Vv. In some implementations, when programming memory cells to data state P, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv.

[0104] FIG. 5B to FIG. 5FAn exemplary threshold voltage distribution for a memory array when each memory cell stores multiple bits of data per memory cell is shown. Memory cells that store multiple bits of data per memory cell are referred to as multi-level cells ("MLC"). Data stored in an MLC memory cell is referred to as MLC data; therefore, MLC data includes multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. Figure 5B In an exemplary embodiment, each memory cell stores two bits of data. Other embodiments may use other data capacities per memory cell (e.g., such as three bits of data, four bits of data, five bits of data, or six bits of data per memory cell).

[0105] Figure 5B A first threshold voltage distribution E for erasing memory cells is shown. Also depicted are three threshold voltage distributions A, B, and C for programming memory cells. In one embodiment, the threshold voltages in distribution E are negative, and the threshold voltages in distributions A, B, and C are positive. Figure 5B Each different threshold voltage distribution corresponds to a predetermined value for a set of data bits. In one embodiment, each bit of the two bits of data stored in the memory cell is in a different logical page, referred to as a lower page (LP) and an upper page (UP). In other embodiments, all data bits stored in the memory cell are in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. Table 1 provides an exemplary encoding scheme.

[0106] Table 1

[0107] E A B C LP 1 0 0 1 UP 1 1 0 0

[0108] In one implementation, referred to as full sequence programming, the Figure 6 The process of programming memory cells directly from erased data state E to any of programmed data states A, B, or C (discussed below) is used. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state E. Then, a programming process is used to program the memory cells directly to data states A, B, and / or C. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and / or from data state E to data state C. Figure 5B The arrows represent full sequence programming. In some embodiments, data states AC may overlap, where the memory controller 120 (or control die 211) relies on error correction to identify the correct data being stored.

[0109] Figure 5C Depicted are exemplary threshold voltage distributions for memory cells, each of which stores three bits of data per memory cell (which is another example of MLC data). Figure 5C Eight threshold voltage distributions corresponding to eight data states are shown. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) AG represent programmed memory cells, and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value of a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. In one embodiment, the data value is assigned to the threshold voltage range using Gray code distribution, so that if the threshold voltage of the memory is incorrectly shifted to its adjacent physical state, only one bit will be affected. Table 2 provides an example of a coding scheme for an embodiment in which each bit of the three bits of data stored in the memory cell is in different logical pages, and the logical page is called a lower page (LP), a middle page (MP), and an upper page (UP).

[0110] Table 2

[0111] Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

[0112] Figure 5C Seven read compare voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG are shown for reading data from a memory cell. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is above or below the seven read compare voltages, the system can determine the data state (i.e., A, B, C, D, ...) that the memory cell is in.

[0113] Figure 5CAlso shown are seven verification comparison voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when the memory cells are programmed to data state A, the system will test whether the memory cells have a threshold voltage greater than or equal to VvA. When the memory cells are programmed to data state B, the system will test whether the memory cells have a threshold voltage greater than or equal to VvB. When the memory cells are programmed to data state C, the system will determine whether the memory cells have a threshold voltage greater than or equal to VvC. When the memory cells are programmed to data state D, the system will test whether the memory cells have a threshold voltage greater than or equal to VvD. When the memory cells are programmed to data state E, the system will test whether the memory cells have a threshold voltage greater than or equal to VvE. When the memory cells are programmed to data state F, the system will test whether the memory cells have a threshold voltage greater than or equal to VvF. When the memory cells are programmed to data state G, the system will test whether the memory cells have a threshold voltage greater than or equal to VvG. Figure 5C Also shown is Vev, which is the voltage level used to test whether the memory cell has been properly erased.

[0114] In an implementation utilizing full sequence programming, the Figure 6 The process of programming memory cells from erased data state Er directly to any of programmed data states AG (discussed below) can be used. For example, a group of memory cells to be programmed can be first erased so that all memory cells in the group are in erased data state Er. Then, the programming process is used to program the memory cells directly to data states A, B, C, D, E, F, and / or G. For example, while some memory cells are being programmed from data state ER to data state A, other memory cells are being programmed from data state ER to data state B and / or from data state ER to data state C, and so on. Figure 5C The arrows represent full sequence programming. In some embodiments, data states AG may overlap, where the control die 211 and / or memory controller 120 rely on error correction to identify the correct data being stored. Note that in some embodiments, the system may use a multi-pass programming process known in the art instead of using full sequence programming.

[0115] Generally speaking, during a verify operation and a read operation, a selected word line is connected to a voltage (an example of a reference signal) whose level is determined for each read operation (eg, see Figure 5C of read comparison voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG) or a verification operation (see, for example, Figure 5CThe verification target voltages (VvA, VvB, VvC, VvD, VvE, VvF, and VvG) of the memory cell are specified in order to determine whether the threshold voltage of the associated memory cell has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducting current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verification process, unselected memory cells are provided with one or more read pass voltages (also called bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are programmed or erased).

[0116] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured at the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string including the memory cell to discharge the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has been discharged. It should be noted that the techniques described herein can be used with different methods known in the art for verification / reading. Other reading and verification techniques known in the art can also be used.

[0117] Figure 5D Depicted is a threshold voltage distribution when each memory cell stores four bits of data, which is another example of MLC data. Figure 5D It is shown that there can be some overlap between the threshold voltage distributions (data states) S0 to S15. This overlap can occur due to factors such as memory cells losing charge (and therefore the threshold voltage dropping). Program disturbances can unintentionally increase the threshold voltage of a memory cell. Similarly, read disturbances can unintentionally increase the threshold voltage of a memory cell. Over time, the position of the threshold voltage distributions can change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read compare voltage can help mitigate such effects. Using ECC during the read process can repair errors and ambiguities. Note that in some embodiments, the threshold voltage distributions of a population of memory cells storing four bits of data per memory cell do not overlap and are separated from each other; for example, as Figure 5E Depicted. Figure 5D The threshold voltage distribution will include a read compare voltage and a verify compare voltage, as discussed above.

[0118] When four bits are used per memory cell, the memory can be programmed using the full sequence programming discussed above or a multi-pass programming process known in the art. Figure 5D Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted for the cell. Table 3 provides an example of an encoding scheme for an embodiment in which each bit of the four bits of data stored in the memory cell is in a different logical page, which is referred to as the lower page (LP), the middle page (MP), the upper page (UP), and the top page (TP).

[0119] Table 3

[0120] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 TP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 UP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1

[0121] Fig. 5F Depicted is a threshold voltage distribution when each memory cell stores five bits of data (which is another example of MLC data). In one exemplary implementation, when the memory cell stores five bits of data, the data is stored in any one of thirty-two data states (eg, S0 to S31).

[0122] Figure 6 2 is a flow chart describing one embodiment of a process for programming memory cells. For the purposes of this document, the term programming is synonymous with writing. In one exemplary embodiment, memory array 202 is programmed using one or more of the control circuits discussed above (e.g., system control logic 260, column control circuit 210, row control circuit 220). Figure 6 In one exemplary embodiment, Figure 6 The process is performed by the integrated memory component 207 using one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) of the control die 211 to program the memory cells on the memory die 201. The process includes multiple cycles (referred to as programming cycles), each cycle including a programming phase and a verification phase. Figure 6 to achieve full sequence programming and other programming schemes including multi-pass programming, which includes a programming process that uses multiple passes to complete programming. When implementing multi-pass programming, Figure 6 The process is used to implement any / each pass of the multi-pass programming process.

[0123] Typically, the programming voltage applied to the control gate (via a selected data word line) during a programming operation is applied as a series of programming pulses (e.g., voltage pulses). Between the programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the programming pulses increases by a predetermined step size with each successive pulse. Figure 6 In step 602, the programming voltage signal (Vpgm) is initialized to a starting value (e.g., about 12V to 16V or another suitable level), and the programming counter PC maintained by the state machine 262 is initialized to 1. In one embodiment, a group of memory cells selected for programming (referred to herein as selected memory cells) are programmed simultaneously and are all connected to the same word line (the selected word line). There may be other memory cells (unselected memory cells) that are not selected for programming that are also connected to the selected word line. That is, the selected word line will also be connected to the memory cells that should be prohibited from programming. In addition, when the memory cells reach their expected target data state, they will be prohibited from further programming. These NAND strings (e.g., unselected NAND strings) have their channels boosted to prohibit programming, and these strings include memory cells that are connected to the selected word line to be prohibited from programming. When the channel has an elevated voltage, the voltage difference between the channel and the word line is not enough to cause programming. To help boost, in step 604, the control die will precharge the channel of the NAND string including the memory cells connected to the selected word line that will be prohibited from programming. In some embodiments, precharging the channel of the unselected NAND string clears the channel of electrons and raises the channel to a low positive voltage (e.g., about 1v to 1.3v). In step 606, the NAND string including the memory cell connected to the selected word line to be prohibited from programming has its channel boosted to prohibit programming. Such NAND strings are referred to as "unselected NAND strings" herein. In one embodiment, the unselected word line receives one or more boost voltages (e.g., about 7 volts to 11 volts) (also referred to as pass voltage) to perform the boost scheme. The program inhibit voltage is applied to the bit line of the coupled unselected NAND string. For example, in one embodiment, the channel is precharged to about 2 volts and then floated in step 604. In step 606, the channel is boosted from 2 volts to a boost voltage of about 8 volts to 10 volts.

[0124] In step 608, a programming voltage pulse of a programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). In some embodiments, the magnitude and / or pulse width of the programming voltage pulse may be modified by one or more offsets from the standard magnitude and / or pulse width, as described below. If the memory cell on the NAND string should be programmed, the corresponding bit line is biased at a programming enable voltage. In step 608, a programming pulse is applied simultaneously to all memory cells connected to the selected word line so that all memory cells connected to the selected word line are programmed simultaneously (unless they are prohibited from programming). That is, they are programmed at the same time or during overlapping time (both are considered to be simultaneous). In this way, all memory cells connected to the selected word line will have their threshold voltage changes at the same time unless they are prohibited from programming.

[0125] In step 610, program verification is performed and memory cells that have reached their target state are locked out from further programming by the control die. Step 610 includes performing verification of programming by sensing at one or more verify compare levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached the appropriate verify compare voltage. Figure 5C In one embodiment, executing Figure 6 6. The process for memory cells being programmed to data states A, B, C, D, E, F, and G. In one embodiment, step 610 may include testing each of the data states A, B, C, D, E, F, and G (e.g., testing to see if the threshold voltage of the memory cell is greater than VvA, VvB, VvC, VvD, VvE, VvF, and VvG). In another embodiment, the system tests only a subset of data states A, B, C, D, E, F, and G based on the current threshold voltage of the memory cell during each cycle of steps 604 to 626 in a process referred to as smart verification. In step 610, after the memory cell has been verified (by testing of Vt) that the memory cell has reached its target state, the memory cell may be locked out.

[0126] If, in step 612, it is determined that all memory cells have reached their target threshold voltage (PASS), then the programming process is complete and successful because all selected memory cells have been programmed and verified to their target states. In step 614, a "PASS" status is reported. Otherwise, if, in step 612, it is determined that not all memory cells have reached their target threshold voltage (FAIL), then the programming process will continue to step 616.

[0127] In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distribution is counted. That is, the number of memory cells that have so far been unable to reach their target state is counted. This counting may be done by the state machine 262, the memory controller 120, or another circuit. In one embodiment, there is a total count that reflects the total number of memory cells currently being programmed that have failed the last verification step. In another embodiment, a separate count is maintained for each data state.

[0128] In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the read process of a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and report a "pass" status in step 614. In this case, enough memory cells are correctly programmed so that the remaining few memory cells that have not been fully programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 618 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read process to allow for future / additional errors. When programming less than all memory cells of a page, or comparing counts of only one data state (or less than all states), the predetermined limit can be a portion (proportional or non-proportional) of the number of bits that can be corrected by ECC during the read process of a page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0129] If the number of failed memory cells is not less than the predetermined limit, the programming process continues at step 620 and checks the programming counter PC against the programming limit value (PL). Examples of programming limit values ​​include 6, 12, 16, 19, 20, and 30; however, other values ​​may be used. If the programming counter PC is not less than the programming limit value PL, the programming process is deemed to have failed and a "failed" status is reported in step 624. If the programming counter PC is less than the programming limit value PL, the process continues at step 626, during which the programming counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped to the next magnitude. For example, the next pulse will have a magnitude that is a step size ΔVpgm (e.g., a step size of 0.1 volts to 1.0 volts) greater than the previous pulse. After step 626, the process loops back to step 604 and another programming pulse is applied (to the control die) to the selected word line so that execution Figure 6 Another cycle of the programming process (steps 604 to 626). Figure 6 The cycle of the programming process (steps 604 to 626) is called a programming cycle.

[0130] In some embodiments, the memory cells are programmed in order from the source side to the drain side. For example, first perform Figure 6 to program the memory cells connected to WL0, and then use Figure 6 The process of programming the memory cells connected to WL1 is then followed by Figure 6 The process of programming the memory cells connected to WL2 is then used Figure 6 to program the memory cells connected to WL3, ... and then use Figure 6 The process is used to program the memory cells connected to WL269.

[0131] In another embodiment, the memory cells are programmed in order from the drain side to the source side. For example, first perform Figure 6 The process of programming the memory cells connected to the WL269 is then used Figure 6 The process of programming the memory cells connected to the WL268 is then used Figure 6 The process of programming the memory cells connected to WL267 is then used Figure 6 The process of programming the memory cells connected to WL266 is then used Figure 6 The process of programming the memory cells connected to WL1 is then used Figure 6 The memory cells connected to WL0 are programmed by the process of

[0132] In one embodiment, the memory cells are erased prior to programming, and erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. Figure 5A The state P changes to the state E, from Figure 5B The state A / B / C changes to state E, from Figure 5C A changes to state G or changes from state E to state G Figure 5D States S1 to S15 are changed to state S0.

[0133] One technique for erasing memory cells in some memory devices is to bias the p-well (or other type) substrate to a high voltage to charge the NAND channel. When the NAND channel is at a high voltage, an erase enable voltage (e.g., a low voltage) is applied to the control gate of the memory cell to erase the non-volatile storage element (memory cell). This is referred to herein as p-well erase.

[0134] Another method of erasing a memory cell is to generate a gate induced drain leakage (GIDL) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while maintaining the NAND string channel potential to erase the memory cell. This is referred to herein as GIDL erase. Both p-well erase and GIDL erase can be used to lower the threshold voltage (Vt) of a memory cell.

[0135] In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a select transistor (e.g., SGD and / or SGS). The transistor drain-to-gate voltage that generates the GIDL current is referred to herein as the GIDL voltage. The GIDL current may be generated when the select transistor drain voltage is significantly higher than the select transistor control gate voltage. The GIDL current is the result of carrier generation, i.e., electron-hole pair generation and / or trap-assisted generation due to band-to-band tunneling. In one embodiment, the GIDL current may cause one type of carrier (e.g., hole) to move primarily into the NAND channel, thereby raising the potential of the channel. Another type of carrier (e.g., electron) is extracted from the channel by an electric field in the direction of the bit line or in the direction of the source line. During erase, holes may tunnel from the channel to the charge storage region of the memory cell and recombine with the electrons therein to lower the threshold voltage of the memory cell.

[0136] A GIDL current may be generated at either end of a NAND string. A first GIDL voltage may be generated between two terminals of a select transistor (e.g., a drain-side select transistor) connected to or near a bit line to generate a first GIDL current. A second GIDL voltage may be generated between two terminals of a select transistor (e.g., a source-side select transistor) connected to or near a source line to generate a second GIDL current. Erasing based on GIDL current at only one end of a NAND string is referred to as single-sided GIDL erasing. Erasing based on GIDL current at both ends of a NAND string is referred to as double-sided GIDL erasing.

[0137] In one embodiment, the memory structure can be operated in sub-block mode, which allows any sub-block to be programmed or read individually. That is, SB1 can be programmed before or after SB0 and / or SB2; SB0 can be programmed before or after SB1 and / or SB2; and SB2 can be programmed before or after SB0 and / or SB1. Any order in which the sub-blocks are programmed can be used. Each sub-block can be read without reading the other sub-blocks. When programming a sub-block, the memory cells may be programmed in an order from the source side to the drain side or from the drain side to the source side, for example, with respect to SB1, source side to drain side programming includes programming the memory cells connected to WL90, then programming the memory cells connected to WL91, then programming the memory cells connected to WL92, ... programming the memory cells connected to WL179, and drain side to source side programming includes programming the memory cells connected to WL179, then programming the memory cells connected to WL178, then programming the memory cells connected to WL177, ... programming the memory cells connected to WL90. In some examples, the sub-blocks may be erased independently, while in other examples, the entire block is erased at once.

[0138] Figure 7 is a flow chart describing one embodiment of a process for performing program verification. That is, Figure 7 The process is Figure 6 An exemplary implementation of a portion of step 610 is provided. Figure 7 In step 702, appropriate signals are applied to the word lines, bit lines, source lines, and select lines to provide a voltage between one or more of the verify compare voltages (e.g., Figure 5C Sensing is performed at VvA, VvB, VvC, VvD, VvE, VvF, and VvG of the memory cells of FIG. 704. Sensing is performed to determine whether the selected memory cell being programmed has a threshold voltage greater than the verification compare voltage being tested. In step 706, the system transitions from program verification to the next programming cycle (including the next programming pulse). For example, the system lowers all word line voltages to ground (or one or more other quiescent voltages) in preparation for the next programming cycle (e.g., steps 640 to 626).

[0139] In some cases, when transitioning from program verify to the next program cycle, the channels of unselected NAND strings may be undesirably pulled down to a negative voltage, which may disrupt subsequent boosting and cause disturb. This concept is discussed in Figures 8 to 11 A more detailed explanation is given in .

[0140] Figure 8A NAND string is depicted that is precharged as part of a process to inhibit the NAND string from being programmed during the programming process. In this example, the block in which the depicted NAND string resides is divided into two sub-blocks (sub-block 1 and sub-block 2), and the order of programming is from the drain side to the source side (as depicted by arrow 802). In addition, in this example, precharging is performed from the source side (see arrow 804) because the source line 806 is connected to VDDSA (precharge voltage of ~2.0v to 2.5v) and the bit line 808 is connected to the sense amplifier (S / A). All memory cells receive VCHPCH (~1.3v) (via word lines). SGD represents the drain side select gate. SGS represents the source side select gate. DU is a dummy memory cell in sub-block 1, and DL is a dummy memory cell in sub-block 0, such that the boundary between sub-block 0 and sub-block 1 is between (or near) DU and DL. The target memory cell for programming is indicated by box 810 and resides in sub-block 1.

[0141] Fig. 9 is described during programming verification and precharge Figure 8 Signal diagrams of the behavior of various signals of the structure. Fig. 9 The following signals are shown: selected SGD, UCG, CG, BL, and selected SGS. The selected signal SGD is the drain side select signal (SGD) for the selected region (e.g., regions 420, 430, 440, 450, 460, and 470). UCG is a signal applied to all unselected word lines. CG is a signal applied to the selected word line (the word line connected to the memory cell selected for programming). BL is a signal applied to the bit lines of the block. The selected SGS is a signal applied to the source side selected lines (SGS0, SGS1, SGS2). At time ta, the selected SGD is raised to VSG (which is a voltage high enough to turn on the transistor of the select gate ~3.5v to 6v), UCG is raised to Vread (e.g., 7 volts to 10 volts), a voltage spike is applied to CG, and the selected SGS is raised to VSG. Vread is an example of an overdrive voltage used to turn on a memory cell so that the memory cell fully conducts current regardless of which data state the memory cell is in. Shortly after the voltage spike, CG goes high in VCG_RV, which can be any verify compare voltage (e.g., Figure 5C The voltage Vsrc is not Fig. 9 The voltage of the source line depicted in , which may be at a low voltage at or near ground. When CG is at VCG_RV, the memory cell is sensed to see if it has successfully reached its target threshold voltage. The time period ta-tb represents Figure 7 Steps 702 and 704. Between tb and tc, Fig. 9 All signals depicted in the figure are dropped to ground. The time period tb-tc represents Figure 7 Step 706. Starting from time tc, a precharge process (e.g., Figure 6 Step 604). The selected signal SGD is raised to VSGDPCH, UCG and CG are raised to VCHPCH, the bit line BL is raised to VHSA (~3.5v), and the selected SGS is raised to VSGDPCH.

[0142] The problem with the channel of the unselected NAND string being pulled down to a negative voltage occurs between tb and tc. As the voltage on the word lines (CG and UCG) ramps down, when the voltage on the word line reaches the threshold voltage of the memory cell, the channel will be cut off and will float. The floating channel is coupled to the word line, but as the word line continues to ramp down, the channel potential will become negative. Therefore, the precharge will start from a negative voltage. In some cases, the precharge will clear the electrons in the channel and raise the potential of the channel to a positive voltage (e.g., 1v to 1.3v). However, if the memory is in sub-block mode, such that sub-block 0 has already been programmed, then when an attempt is made to program a memory cell in sub-block 1 that is in a high data state (e.g., data state G - see Figure 5C ) may not turn on in response to VCPCH; thus, keeping the channel cut off and holding the channel at a negative voltage during the precharge attempt. If the boost of step 606 begins with the channel at a negative potential, the boost may not bring the potential of the channel high enough to avoid disturbing the memory cells of the unselected NAND strings connected to the selected word line (CG). For example, the disturbed memory cell may have its threshold voltage increased, resulting in errors in the data being stored.

[0143] Fig.10 Depicted is a NAND string being precharged as part of the process of inhibiting the NAND string from programming during the programming process. Fig.10 In the example of , the order of programming sub-block 0 is from the drain side to the source side (according to arrow 1002), and when programming the memory cells of sub-block 0, the precharged source comes from the source line (according to arrow 1004). The order of programming sub-block 1 is from the source side to the drain side (according to arrow 1006), and when programming the memory cells of sub-block 1, the precharged source comes from the bit line (according to arrow 1008). Fig.10 The structure of the program verification is changed to the precharge of the next programming cycle by reducing the word line voltage (see Figure 6 ), the channels of the unselected NAND strings may be coupled downward to a negative voltage (as described above with respect to Figures 8 to 9However, since sub-block 1 is precharged from the bit line, sub-block 1 can be precharged regardless of whether sub-block 0 is programmed, and the potential of the channel can be raised to ~1v to 13.v before boosting. Similarly, because sub-block 0 is precharged from the source line, sub-block 0 can be precharged regardless of whether sub-block 1 is programmed, and the potential of the channel can be raised to 1v to 13.v before boosting. This scheme of precharge paths and programming order solves the problem of the channel of an unselected NAND string coupling to a negative voltage and disrupting subsequent boosting (which can cause interference). However, Fig.10 The structure is for a two-tier architecture. Figure 4C and Figure 4D The three-tier architecture is shown. Fig.10 The solution to the problem of the channels of the unselected NAND strings being coupled down to a negative voltage as depicted in FIG. 1 may not be applicable to a three-tier architecture, as described below with respect to FIG. Fig.11 As described.

[0144] Fig.11 Depicted is a NAND string being precharged as part of the process of inhibiting the NAND string from programming during the programming process. As previously described by Figure 4C and Figure 4D As described, Fig.11 The NAND string is part of a three-layer architecture. It is possible that when programming sub-block 0, the order of programming is from the drain side to the source side, and the precharge is started from the source line, as described above about Fig.10 As described, programming sub-block 0 will not have the problem of the channels of the unselected NAND strings being coupled down to a negative voltage prior to boosting as described above.

[0145] It is also possible that when programming sub-block 2, the order of programming is from the source side to the drain side, and precharging is started from the bit line, as described above for Fig.10 As described for sub-block 1, programming sub-block 2 will not have the problem of the channels of the unselected NAND strings being coupled down to a negative voltage prior to boosting as described above. However, when Fig.11 When programming sub-block 1 (the middle sub-block) of a memory cell, if sub-block 0 has already been programmed, the channel of sub-block 1 will not be able to precharge from the source line, and if sub-block 2 has already been programmed, the channel of sub-block 1 will not be able to precharge from the bit line; therefore, sub-block 1 may not have access to a precharged source. Without proper precharging, boosting of the channels of unselected memory cells may not be successful in preventing disturbances, for the reasons discussed above regarding the NAND channel being at a negative voltage after a previous program verify.

[0146] To overcome the problem of the NAND channel being at a negative voltage after a previous programming verification, it is proposed to precharge the channels of the unselected memory cells while lowering the voltage at the end of programming verification by applying an overdrive voltage to the data word lines in the sub-blocks closer to the source line than the selected sub-block, and lowering the dummy word lines between the selected sub-block and the sub-block closer to the source line to a quiescent voltage (e.g., 0 volts, ground or Vss) before lowering the data word lines in the sub-blocks closer to the source line to a quiescent voltage. Figures 12 to 19 Provides more details.

[0147] Fig.12 is a flow chart describing one embodiment of a process that includes precharging channels of unselected memory cells while lowering the voltage at the end of program verification by applying an overdrive voltage to data word lines in a sub-block closer to a source line than a selected sub-block, and lowering a dummy word line between a selected sub-block and a word block closer to the source line to a quiescent voltage before lowering the data word lines in the sub-block closer to the source line to a quiescent voltage. Fig.12 The process is Figure 7 An exemplary implementation of step 706 is shown. Fig.12 The process may be performed by any of the one or more control circuits discussed above. Fig.12 The process can be completely controlled by the control circuit on the memory tube core 200 (see Figure 2A ) or entirely by the control circuit on the integrated memory component 207 (see Figure 2B ) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of the system control logic component 260, the column control circuit 210, and the row control circuit 220. Fig.12 In another embodiment, Fig.12 The process is performed by or under the direction of the memory controller 120. In one embodiment, the block of non-volatile memory cells is executed Fig.12 In another embodiment, different groups of memory cells may be erased. In another embodiment, different groups of non-volatile memory cells may be erased. Fig.12 process.

[0148] In step 1202, the control circuit applies an overdrive voltage to a data word line between a selected word line and one or more control lines (e.g., a source line or other control line) while applying a precharge voltage to the one or more control lines to provide access to the precharge voltage of the one or more control lines to the channels of unselected memory cells while reducing the voltage of the data word lines that are farther away from the one or more control lines than the selected word line. For purposes of this document, an overdrive voltage is a voltage of sufficiently large magnitude that can turn on a memory cell so that it fully conducts current regardless of which data state the memory cell is in. For example, the control circuit applies Vread (an example of an overdrive voltage) to the data word line of SB0 during a programming process that programs the memory cells connected to WLn of SB1 while applying a precharge voltage to the source line SL so that the channels of the NAND strings under WLn in SB1 can access the source line and can be precharged from the source line while reducing the voltage on the data word line of SB2 to ground at the end of programming verification.

[0149] In step 1204, the control circuitry cuts off channels of unselected memory cells from the one or more control lines after precharging and before lowering the data word lines between the selected word line and the one or more control lines from the overdrive voltage to one or more voltages below the threshold voltages of the memory cells connected to the data word lines between the selected word line and the one or more control lines. For example, after the channels of the NAND strings under WLn in SB1 have reached a sufficient precharge level, the dummy word lines (e.g., D0U, D1L, or both) between SB0 and SB1 may be lowered to ground (or another quiescent voltage) to cut off the channels of the NAND strings under WLn in SB1 from the source line SL. After cutting off the channels of the NAND strings under WLn in SB1 from the source line SL, the data word line of SB0 is lowered to ground (or another quiescent voltage). For purposes of this document, a quiescent voltage is a voltage that is low in magnitude (eg, 0 volts or close to 0 volts) to which a signal line is lowered between operations (eg, between precharge and boost, between program verify and precharge, etc.).

[0150] Fig.13 is a flow chart describing one embodiment of a programming process that includes precharging channels of unselected memory cells while lowering the voltage at the end of programming verification by applying an overdrive voltage to data word lines in a sub-block closer to a source line than a selected sub-block, and lowering a dummy word line between a selected sub-block and a word block closer to the source line to a quiescent voltage before lowering the data word lines in the sub-block closer to the source line to a quiescent voltage. Fig.13 The process is Figure 6 In addition, Fig.13 The process includes Fig.12 An exemplary implementation of the process of. Fig.13 The process may be performed by any of the one or more control circuits discussed above. Fig.13 The process can be completely controlled by the control circuit on the memory tube core 200 (see Figure 2A ) or entirely by the control circuit on the integrated memory component 207 (see Figure 2B ) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of the system control logic component 260, the column control circuit 210, and the row control circuit 220. Fig.13 In another embodiment, Fig.13 The process is performed by the memory controller 120 or under its command. It should be noted that Fig.13 The steps may be performed in an order different from that depicted in the figures.

[0151] In one embodiment, a block of nonvolatile memory cells is executed Fig.13 In another embodiment, different groups of memory cells may be erased. In another embodiment, different groups of non-volatile memory cells may be erased. Fig.13 In one embodiment, the process of performing a memory including a plurality of data word lines connected to a plurality of NAND strings is performed. Fig.13 The process of storing a NAND string in a memory cell storage device is described in detail, wherein the NAND strings form a block having at least three sub-blocks, each NAND string includes memory cells in each of the three sub-blocks, the selected word line WLn is in the selected sub-block, and each NAND string includes one or more dummy memory cells. In addition, in some embodiments, each NAND string includes a source-side select gate between the memory cell and the source line, and the source-side select line is connected to the source-side select gate.

[0152] exist Fig.13 In step 1302, the control circuit applies a programming dose to the selected data word line. For example, a series of programming voltage pulses (e.g., see Figure 6 In step 1304, the control circuit inhibits programming of the unselected NAND strings in the selected sub-block by boosting the channels of the unselected NAND strings from the positive precharge voltage to the boost voltage (see, for example, Figure 6 In step 1306, the control circuit performs a program verification between pairs of consecutive programming doses (eg, see Figure 6In step 1308, the control circuit precharges the channels of the unselected NAND strings in the selected sub-block to a positive precharge voltage while lowering the voltage at the end of program verification.

[0153] In one embodiment of step 1308, the control circuit precharges the channels of the unselected NAND strings in the selected sub-block to a positive precharge voltage while lowering the voltage at the end of program verification by performing steps 1320 through 1332 simultaneously.

[0154] In step 1320, the control circuit applies a precharge voltage to the source line SL connected to the NAND string. In step 1322, the control circuit applies an overdrive voltage (e.g., Vread) to a data word line in a sub-block (e.g., SB0) that is closer to the source line than the selected sub-block (e.g., SB1). In step 1324, the control circuit applies an overdrive voltage to a dummy word line (e.g., D0U, D1L or both) between the selected sub-block and the sub-block that is closer to the source line than the selected sub-block (dummy word line is connected to a dummy memory cell). In step 1326, after starting to apply the overdrive voltage, the control circuit reduces the source side selection line (e.g., SGS) from the verification enable voltage to an intermediate voltage. In one embodiment, the magnitude of the intermediate voltage is higher than the threshold voltage of the source side selection gate. In step 1328, the control circuit reduces the voltage of the data word line (e.g., WLn+1-WL269) on the side of the selected word line that is farther away from the source line than the selected data word line. In step 1330, at the end of program verification, the control circuit lowers the selected word line (WLn) from the verification comparison voltage (e.g., VvA, VvB, VvC, VvD, VvE, VvF, and VvG) to the quiescent voltage of the selected word line while lowering the voltage of the data word line on the side of the selected word line farther from the source line than the selected data word line. In step 1332, the control circuit lowers the voltage of the data word lines (WL90 to WLn-1) on the side of the selected word line closer to the source line than the selected data word line in the selected sub-block while lowering the voltage of the data word line on the side of the selected word line farther from the source line than the selected data word line.

[0155] After precharging (in step 1308) the channels of the unselected NAND strings in the selected sub-block to a positive precharge voltage while lowering the voltage at the end of program verification, the control circuitry lowers (in step 1310) the dummy word lines between the selected sub-block and the sub-block closer to the source line to a quiescent voltage. After lowering the dummy word lines to a quiescent voltage in step 1310, and before the next programming dose (e.g., the next programming pulse), the control circuitry lowers (in step 1312) the data word lines in the sub-block closer to the source line to one or more quiescent voltages. After lowering the dummy word lines to a quiescent voltage in step 1310, and before the next programming dose (e.g., the next programming pulse), the control circuitry lowers (in step 1314) the source line from the precharge voltage to the quiescent voltage of the source line.

[0156] In one embodiment, when programming a sub-block other than the sub-block closest to the precharged source, executing Fig.12 and Fig.13 The process is not used when programming the sub-block closest to the precharged source. For example, when programming SB1 and SB2, perform Fig.12 and Fig.13 process, but not executed when programming SB0.

[0157] Fig.14 , Fig.16 and Fig.18 is a signal diagram that describes the behavior of various signals during program verify / precharge / boost / program for a system that precharges the channels of unselected memory cells while reducing the voltage at the end of program verify. Fig.14 is a signal diagram describing one implementation of programming memory cells in the sub-block closest to the source line (eg, SB0). Fig.14 The process described in this paper uses Fig.12 and Fig.13 process. Fig.16 is a signal diagram describing one implementation of programming memory cells in a middle sub-block (eg, SB1). Fig.16 The process described in Fig.12 and Fig.13 An exemplary implementation of the process of. Fig.18 is a signal diagram describing one implementation of programming memory cells in a sub-block that is away from a source line (eg, SB2). Fig.18 The process described in Fig.12 and Fig.13 Another exemplary implementation of the process.

[0158] Fig.14The following signals are depicted: BL(sel), BL(unsel), SGD(sel), SGD(unsel), WL(SB2), WL_D12, WLSB1, WL_D01, WLn, WLunsel(SB0), SGS, and SL. BL(sel) is the voltage applied to the bit lines connected to the NAND string that has the memory cells selected for programming. BL(unsel) is the voltage applied to the bit lines connected to the NAND string that does not have any memory cells selected for programming. SGD(sel) is the voltage applied to the drain side select (SGD) lines (e.g., SGD0, SGD1, and SGD2 connected together for one region) of the regions selected for programming (e.g., regions 420, 430, 440, 450, 460, and 470). SGD(unsel) is the voltage applied to the drain side select (SGD) lines (e.g., SGD0, SGD1, and SGD2 connected together for one region) of regions not selected for programming (e.g., regions 420, 430, 440, 450, 460, and 470). SGS is the voltage applied to the source side select (SGS) lines (e.g., SGS0, SGS1, and SGS2 connected together). SL is the voltage applied to the source line. WLn is the voltage on the data word line selected for programming, meaning that WLn is connected to the memory cell selected for programming. WL(SB2) is the data word line of sub-block SB2 (e.g., WL180 to WL269). WL_D12 is one or more dummy word lines (e.g., D1U and D2L) between sub-block SB1 and sub-block SB2. WL_D01 is one or more dummy word lines (e.g., D0U and D1L) between sub-block SB0 and sub-block SB1. WL(SB1) is a data word line (e.g., WL90 to WL179) of sub-block SB1. WLunsel(SB0) is a data word line of sub-block SB0 that is not selected for programming (e.g., all WL0 to WL89 except WLn).

[0159] Fig.14 One implementation of programming memory cells in SB0 is described. Fig.15 is based on Fig.141 is an exemplary NAND string of a block being operated on by the process of . Thus, WLn is in SB0, and the memory cells connected to WLn are being programmed (according to the P of the immediately adjacent memory cells). The memory cells of SB0 of the depicted NAND string located on the drain side of WLn have been programmed. The memory cells of SB0 of the depicted NAND string located on the source side of WLn have not yet been programmed, and are therefore in an erased state. In this example, the memory cells of SB1 and SB2 have already been programmed. Immediately adjacent to those memory cells that have received programming is R to indicate that they are storing data (R is used to indicate that the data can be any random data state). Immediately adjacent to those memory cells that have not yet received programming is Er to indicate that they are in an erased state.

[0160] Fig.14 The time period t1-t8 corresponds to the program verification during loop N of the program loop of steps 604 to 626 (see Figure 6 The time period t4-t8 corresponds to the transition to the next programming pulse ( Figure 7 The time period t4-t8 also corresponds to the channel precharge during cycle N+1 of the programming loop of steps 604 to 626 (see Figure 6 The time period t8-t10 corresponds to boosting the channels of the unselected NAND strings during cycle N+1 of the programming loop of steps 604 to 626 (see Figure 6 Step 606) and applying a programming voltage pulse to the selected data word line and the selected memory cell (see Figure 6 Step 608).

[0161] At time t0, Fig.14All signals depicted in are at Vss (ground or 0 volts). At time t1, BL(sel) is raised to Vbl (e.g., 0.5v to 1.5v), SGD(sel) is raised to Vsg (e.g., 4v to 6v), WL(SB2) is raised to Vread (e.g., 7 volts to 10 volts), WL_D12 is raised to Vread, WL(SB1) is raised to Vread, and WL_D01 is raised to Vread. In addition, at t1, a voltage spike is applied to WLn, and after the voltage on WLn stabilizes, WLn is then raised to Vcgv (which can be any verify compare voltage, such as VvA, VvB, VvC, VvD, VvE, VvF, and VvG). At time t2, SGS is raised to Vsg, which provides a path for the bit line voltage to dissipate. Between t2 and t3, the sense amplifier will sense (see step 704) whether the selected memory cell is turned on in response to Vcgv applied to WLn. If Vcgv is greater than the threshold voltage of the selected memory cell, the selected memory cell will conduct current and the bit line voltage will be dissipated via the source line, as depicted by curve 1404. If Vcgv is greater than the threshold voltage of the selected memory cell, the selected memory cell will not conduct current and the bit line voltage will not be dissipated via the source line, as depicted by curve 1402. During the time period t0-t8, BL(unsel) is at Vss. During the time period t0-t4, SL is at Vss. SGD(unsel) is at Vss. Fig.14 Vss is present during the entire period depicted in FIG.

[0162] During the time period of t4-t8, the system precharges the channels of the unselected memory cells while reducing the voltage at the end of programming verification. At t4, SGD (sel), WL (SB2), WL_D12, WLSB1, WLn, WLunsel (SB0), and WL_D01 are reduced to one or more static voltages (e.g., Vss, ground, 0 volts). Also at t4, SGS is slowly reduced from Vsg to an intermediate voltage (reaching the intermediate voltage at t6). The intermediate voltage is greater than the threshold voltage of the select gate connected to SGS. The source line SL is raised to VDDSA (precharge voltage of ~2v to 2.5v or a different voltage in other embodiments). Maintaining SGS above the intermediate voltage during t4-t5 provides access to a precharge voltage VDDSA on the source line (or another type of control line) to the channels of the unselected NAND strings (i.e., the channels connected to the selected word line and the unselected memory cells in the selected sub-block), so that those channels are precharged to the precharge voltage VDDSA (or a voltage magnitude slightly less than VDDSA); for example, when VDDSA=2v, the channels are precharged to ~1.3 volts. In one embodiment, the precharge occurs between t4 and t5. Therefore, at t6, SGS is lowered to one or more quiescent voltages (e.g., Vss, ground, 0 volts). At t7, the source line SL is lowered to Vcsrc (e.g., ~1.5v to 2.23v or other voltage). Note that some embodiments may decompose the source line into multiple source lines, and thus the NAND strings and memory cells will be connected to one or more source lines (one or more other types of control lines). It is also noted that although example voltage magnitudes are provided herein, the techniques described herein are not limited to these voltage magnitudes and other voltage magnitudes as appropriate for a particular implementation may also be used.

[0163] At time t8, the system begins the operation of applying the programming voltage pulse. The selected bit line BL(sel) remains at Vss, while the unselected bit line BL(unsel) is raised to the inhibit voltage Vinhibit (e.g., ~2.5 volts) at t8, and SGD(sel) is raised to Vsg. Also at t8, WL(SB2), WL_D12, WLSB1, WL_D01, WLn, and WLunsel(SB0) are all raised to Vpass (e.g., 7 volts to 10 volts). At time t9, WLn is raised from Vpass to Vpgm. The signal applied to WLn from t9 to t10 is Figure 6 The voltage programming pulse of step 608 is applied to WL(SB2), WL_D12, WLSB1, WL_D01 and WLunsel(SB0) including Figure 66. Thus, a first subset of NAND strings connected to BL(sel) will be programmed in response to application of a programming dose (e.g., a programming voltage pulse), while a second subset of NAND strings connected to BL(unsel) will be inhibited from programming due to the boosting of the channel. At time t10, all signals not already at Vss are lowered to Vss.

[0164] Fig.16 Describes the use Fig.12 and Fig.13 An embodiment of a process for programming memory cells in SB1. Fig.17 is based on Fig.16 1 is an exemplary NAND string of a block being operated on by the process of FIG. Thus, WLn is in SB1, and the memory cells connected to WLn are being programmed (according to the P of the immediately adjacent memory cells). The memory cells of SB1 of the depicted NAND string located on the drain side of WLn have been programmed. The memory cells of SB1 of the depicted NAND string located on the source side of WLn have not been programmed yet and are therefore in an erased state. In this example, the memory cells of SB0 and SB2 have been programmed.

[0165] Fig.16 The following signals are depicted: BL(sel), BL(unsel), SGD(sel), SGD(unsel), WL_Dr, WL_D12, WL_Src, WL_D01, WLn, WL(SB0), SGS, and SL. WL_Dr represents all unselected data word lines on the drain side (e.g., bit line side) of WLn. For example, WL_Dr may include all data word lines of SB2 and WLn+1–WL179 of SB1. WL_Src are all unselected data word lines of SB1 on the source side of WLn. For example, WL_Src may include WL90-WLn-1. WL(SB0) are all data word lines of SB0.

[0166] Fig.16 The time period t1-t8 corresponds to the program verification during loop N of the program loop of steps 604 to 626 (see Figure 6 The time period t4-t8 corresponds to the transition to the next programming pulse ( Figure 7 The time period t4-t8 also corresponds to the channel precharge during cycle N+1 of the programming loop of steps 604 to 626 (see Figure 6 The time period t8-t10 corresponds to boosting the channels of the unselected NAND strings during cycle N+1 of the programming loop of steps 604 to 626 (see Figure 6Step 606) and applying a programming voltage pulse to the selected data word line and the selected memory cell (see Figure 6 Step 608).

[0167] At time t0, Fig.16 All signals depicted in are at Vss (ground or 0 volts). At time t1, BL(sel) is raised to Vbl (e.g., 0.5v to 1.5v), SGD(sel) is raised to Vsg (e.g., 4v to 6v), WL_Dr is raised to Vread, WL_D12 is raised to Vread, WL_Src is raised to Vread, WL_D01 is raised to Vread, and WL(SB0) is raised to Vread. In addition, at t1, a voltage spike is applied to WLn, and after the voltage on WLn stabilizes, WLn is then raised to Vcgv (which can be any verify compare voltage, such as VvA, VvB, VvC, VvD, VvE, VvF, and VvG). At time t2, SGS is raised to Vsg, which provides a path for the bit line voltage to dissipate. Between t2 and t3, the sense amplifier will sense (see step 704) whether the selected memory cell is turned on in response to Vcgv applied to WLn. If Vcgv is greater than the threshold voltage of the selected memory cell, the selected memory cell will conduct current and the bit line voltage will be dissipated via the source line, as depicted by curve 1604. If Vcgv is greater than the threshold voltage of the selected memory cell, the selected memory cell will not conduct current and the bit line voltage will not be dissipated via the source line, as depicted by curve 1602. During the time period t0-t8, BL(unsel) is at Vss. During the time period t0-t4, SL is at Vss. SGD(unsel) is at Vss. Fig.16 Vss is present during the entire period depicted in FIG.

[0168] During the time period t4-t8, the system precharges the channels of the unselected memory cells while reducing the voltage at the end of the program verification. Therefore, the time period t4-t8 provides Fig.12 Steps 1202 to 1204 and Fig.1313. An exemplary implementation of steps 1320 to 1332 of . At t4, SGD(sel), WL_Dr, WL_D12, WL_Src, and WLn are lowered to one or more quiescent voltages (e.g., Vss, ground, 0 volts). Also at t4, SGS is slowly lowered from Vsg to an intermediate voltage (reaching the intermediate voltage at t7). At t4, the source line SL is raised to VDDSA. At Vread and SGS, which maintain WL_D01 above the intermediate voltage during t4-t5, the channels of the unselected NAND strings (i.e., the channels connected to the selected word line and the unselected memory cells in the selected sub-block) are provided with access to a precharge voltage VDDSA on the source line (or another type of control line), so that those channels are precharged to the precharge voltage VDDSA (or a voltage magnitude slightly less than VDDSA); for example, when VDDSA=2v, the channels are precharged to ~1.3 volts. In one embodiment, precharge occurs between t4 and t5. At t5, WL_D01 is lowered to one or more quiescent voltages (e.g., Vss, ground, 0 volts). When WL_D01 is lowered, once the voltage magnitude of WL_D01 is lower than the threshold voltage of the dummy memory cell connected to WL_D01, after precharge and before lowering WL(SB0), the channels of the unselected NAND strings (i.e., the channels of the unselected memory cells connected to the selected word line WLn and the selected sub-block) are cut off from the source line SL (or other one or more control lines). After the channels of the unselected NAND strings are cut off from the source line, at t6, WL(SB0) is lowered from Vread to one or more quiescent voltages (e.g., Vss, ground, 0 volts). At t7, SGS is lowered from the intermediate voltage to Vss. At t8, the source line SL is lowered to Vcsrc (e.g., ~1.5v to 2.23v or other voltage).

[0169] At time t8, the system begins the operation of applying the programming voltage pulse. The selected bit line BL(sel) remains at Vss, while the unselected bit line BL(unsel) is raised to the inhibit voltage Vinhibit (e.g., ~2.5 volts) at t8, and SGD(sel) is raised to Vsg. Also at t8, WL_Dr, WL_D12, WL_Src, WL_D01, WLn, and WL(SB0) are all raised to Vpass. At time t9, WLn is raised from Vpass to Vpgm. The signal applied to WLn from t9 to t10 is Figure 6 The voltage programming pulse of step 608 is applied to WL_Dr, WL_D12, WL_Src, WL_D01, WLn and WL(SB0) including Figure 66. Thus, a first subset of NAND strings connected to BL(sel) will be programmed in response to application of a programming dose (e.g., a programming voltage pulse), while a second subset of NAND strings connected to BL(unsel) will be inhibited from programming due to the boosting of the channel. At time t10, all signals not already at Vss are lowered to Vss.

[0170] Fig.18 The following signals are depicted: BL(sel), BL(unsel), SGD(sel), SGD(unsel), WL_DD, WL_SS, WL_D12, WL_D01, WLn, WL(SB0 & SB1), SGS, and SL. WL_DS are all unselected data word lines of SB2 on the drain side (e.g., bit line side) of WLn. For example, WL_DS may include WLn+1–WL269 of SB2. WL_SS are all unselected data word lines of SB2 on the source side of WLn. For example, WL_SS may include WL180-WLn-1. WL(SB0 & SB1) are all data word lines of SB0 and SB1.

[0171] Fig.18 Describes the use Fig.12 and Fig.13 An embodiment of a process for programming memory cells in SB2. Fig.19 is based on Fig.18 1 is an example NAND string of a block being operated on by the process of . Thus, WLn is in SB2, and the memory cells connected to WLn are being programmed (according to the P of the immediately adjacent memory cells). The memory cells of SB2 of the depicted NAND string located on the drain side of WLn have already been programmed. The memory cells of SB2 of the depicted NAND string located on the source side of WLn have not yet been programmed, and are therefore in an erased state. In this example, the memory cells of SB0 and SB1 have already been programmed. Note that in Figures 14 to 19 In the process, all word blocks are programmed in order from the drain side to the source side.

[0172] Fig.18 The time period t1-t8 corresponds to the program verification during loop N of the program loop of steps 604 to 626 (see Figure 6 The time period t4-t8 corresponds to the transition to the next programming pulse ( Figure 7 The time period t4-t8 also corresponds to the channel precharge during cycle N+1 of the programming loop of steps 604 to 626 (see Figure 6The time period t8-t10 corresponds to boosting the channels of the unselected NAND strings during cycle N+1 of the programming loop of steps 604 to 626 (see Figure 6 Step 606) and applying a programming voltage pulse to the selected data word line and the selected memory cell (see Figure 6 Step 608).

[0173] At time t0, Fig.18 All signals depicted in are at Vss (ground or 0 volts). At time t1, BL(sel) is raised to Vbl (e.g., 0.5v to 1.5v), SGD(sel) is raised to Vsg (e.g., 4v to 6v), WL_DS is raised to Vread, WL_SS is raised to Vread, WL_D12 is raised to Vread, WL_D01 is raised to Vread, and WL(SB0 & SB1) is raised to Vread. In addition, at t1, a voltage spike is applied to WLn, and after the voltage on WLn stabilizes, WLn is then raised to Vcgv (which can be any verify compare voltage, such as VvA, VvB, VvC, VvD, VvE, VvF, and VvG). At time t2, SGS is raised to Vsg, which provides a path for the bit line voltage to dissipate. Between t2 and t3, the sense amplifier will sense (see step 704) whether the selected memory cell is turned on in response to Vcgv applied to WLn. If Vcgv is greater than the threshold voltage of the selected memory cell, the selected memory cell will conduct current and the bit line voltage will be dissipated via the source line, as depicted by curve 1804. If Vcgv is greater than the threshold voltage of the selected memory cell, the selected memory cell will not conduct current and the bit line voltage will not be dissipated via the source line, as depicted by curve 1802. During the time period t0-t8, BL(unsel) is at Vss. During the time period t0-t4, SL is at Vss. SGD(unsel) is at Vss. Fig.18 Vss is present during the entire period depicted in FIG.

[0174] During the time period t4-t8, the system precharges the channels of the unselected memory cells while reducing the voltage at the end of the program verification. Therefore, the time period t4-t8 provides Fig.12 Steps 1202 to 1204 and Fig.1313. An exemplary implementation of steps 1320 to 1332 of . At t4, SGD(sel), WL_DS, WL_SS, and WLn are lowered to one or more quiescent voltages (e.g., Vss, ground, 0 volts). Also at t4, SGS is slowly lowered from Vsg to an intermediate voltage (reaching the intermediate voltage at t7). At t4, the source line SL is raised to VDDSA. While WL_D12, WL_D01, and WL(SB0 & SB1) are maintained at Vread and SGS above the intermediate voltage during t4-t5, access to a precharge voltage VDDSA on the source line (or another type of control line) is provided to the channels of the unselected NAND strings (i.e., the channels connected to the selected word line and the unselected memory cells in the selected sub-block), so that those channels are precharged to the precharge voltage VDDSA (or a voltage magnitude slightly less than VDDSA); for example, when VDDSA=2v, the channels are precharged to ~1.3 volts. In one embodiment, precharge occurs between t4 and t5. Therefore, at t5, WL_D12 is lowered to one or more quiescent voltages (e.g., Vss, ground, 0 volts). When WL_D12 is lowered, once the voltage magnitude of WL_D12 is lower than the threshold voltage of the dummy memory cell connected to WL_D12, after precharge and before lowering WL(SB0&SB1), the channels of the unselected NAND strings (i.e., the channels of the unselected memory cells connected to the selected word line WLn and the selected sub-block) are cut off from the source line SL (or other one or more control lines). After the channels of the unselected NAND strings are cut off from the source line, at t6, WL(SB0&SB1) and WL_D01 are lowered from Vread to one or more quiescent voltages (e.g., Vss, ground, 0 volts). At t7, SGS is lowered from the intermediate voltage to Vss. At t8, source line SL is lowered to Vcsrc (eg, ~1.5v to 2.23v or other voltage).

[0175] At time t8, the system starts the operation of applying the programming voltage pulse. The selected bit line BL(sel) remains at Vss, while the unselected bit line BL(unsel) is raised to the inhibit voltage Vinhibit at t8, and SGD(sel) is raised to Vsg. Also at t8, WL_DD, WL_SS, WL_D12, WL_D01, WLn, and WL(SB0&SB1) are all raised to Vpass. At time t9, WLn is raised from Vpass to Vpgm. The signal applied to WLn from t9 to t10 is Figure 6 The voltage programming pulse of step 608 is applied to WL_DD, WL_SS, WL_D12, WL_D01, WLn and WL(SB0 & SB1) including Figure 66. Thus, a first subset of NAND strings connected to BL(sel) will be programmed in response to application of a programming dose (e.g., a programming voltage pulse), while a second subset of NAND strings connected to BL(unsel) will be inhibited from programming due to the boosting of the channel. At time t10, all signals not already at Vss are lowered to Vss.

[0176] A memory system has been disclosed that provides the flexibility of programming sub-blocks independently and saves time during programming by precharging the channels of unselected memory cells while reducing the voltage at the end of program verification.

[0177] One embodiment includes a nonvolatile memory device, the nonvolatile memory device including: a data word line; one or more control lines; a plurality of nonvolatile memory cells connected to the data word line and the one or more control lines; a control circuit connected to the data word line and the one or more control lines and the memory cells. The control circuit is configured to precharge the channel of the unselected memory cell by applying an overdrive voltage to the data word line between the selected word line and the one or more control lines while applying a precharge voltage to the one or more control lines to reduce the voltage at the end of programming verification, while reducing the voltage at the end of programming verification to provide the channel of the unselected memory cell with access to the precharge voltage of the one or more control lines, while reducing the voltage of the data word line farther from the one or more control lines than the selected word line. The control circuit is configured to cut off the channels of the unselected memory cells from the one or more control lines after the precharge and before reducing the data word line between the selected word line and the one or more control lines from the overdrive voltage to one or more voltages below the threshold voltages of the memory cells connected to the data word line between the selected word line and the one or more control lines.

[0178] One embodiment includes a method of operating a nonvolatile memory device, the method comprising: applying a programming dose to a selected data word line among a plurality of data word lines connected to a plurality of NAND strings, the plurality of NAND strings forming a block having at least three sub-blocks, each NAND string including memory cells in each of the three sub-blocks, the selected word line being in the selected sub-block, each NAND string including dummy memory cells; inhibiting programming of unselected NAND strings in the selected sub-block by boosting channels of the unselected NAND strings from a positive precharge voltage to a boost voltage; performing program verification between pairs of consecutive programming doses; precharging channels of the unselected NAND strings in the selected sub-block to the positive precharge voltage, while reducing the voltage at the end of program verification by simultaneously: boosting the precharge voltage to a boost voltage; The invention relates to a method for programming a NAND string comprising: applying a voltage to a source line connected to the NAND string, applying an overdrive voltage to a data word line in a sub-block closer to the source line than the selected sub-block, reducing the voltage of the data word line on a side of the selected word line farther from the source line than the selected data word line, and applying an overdrive voltage to a dummy word line between the selected sub-block and the sub-block closer to the source line than the selected sub-block, the dummy word line being connected to the dummy memory cell of the NAND string; after the precharging, reducing the dummy word line between the selected sub-block and the sub-block closer to the source line to a quiescent voltage; and reducing the data word line in the sub-block closer to the source line than the selected sub-block to one or more quiescent voltages after reducing the dummy word line to the quiescent voltage and before a next programming dose.

[0179] One embodiment includes a nonvolatile memory device, the nonvolatile memory device including: a plurality of nonvolatile memory cells arranged as NAND strings to form a block having at least three sub-blocks, each NAND string including memory cells in each of the three sub-blocks, each NAND string including dummy memory cells; a plurality of data word lines connected to the NAND strings; dummy word lines connected to the dummy memory cells of the NAND strings; a plurality of bit lines connected to the NAND strings; a source line connected to the NAND strings; and a control circuit connected to the data word lines, the dummy word lines, the bit lines, and the source lines. The control circuit is configured to program the memory cells connected to the selected data word line by applying a series of programming voltage pulses to the boosted channels of the selected data word line and the unselected NAND strings. The control circuit is configured to perform programming verification between programming voltage pulses. The control circuit includes a device for precharging the channels of unselected NAND strings in a selected sub-block before the next programming voltage pulse from the source line, while reducing the voltage at the end of programming verification by applying an overdrive voltage to the data word lines in the sub-block closer to the source line than the selected sub-block, and reducing the dummy word line between the selected sub-block and the sub-block closer to the source line to the quiescent voltage before reducing the data word lines in the sub-block closer to the source line to the quiescent voltage.

[0180] An example of a means for precharging the channels of the unselected NAND strings in the selected sub-block includes performing Fig.12 , Fig.13 , Fig.16 or Fig.18 any one or any combination of the memory controller 120, the state machine 262, all or a portion of the system control logic unit 260, all or a portion of the row control circuit 220, all or a portion of the column control circuit 210, a microcontroller, a microprocessor and / or other similar functional circuits (including hardware only or a combination of hardware and software / firmware) of the process.

[0181] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0182] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0183] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0184] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0185] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0186] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A non-volatile storage device, comprising: Data word line; one or more control lines; a plurality of nonvolatile memory cells connected to the data word lines and the one or more control lines; and a control circuit connected to the data word line and the one or more control lines and the memory cell, the control circuit being configured to precharge the channel of the unselected memory cell by applying an overdrive voltage to the data word line between the selected word line and the one or more control lines while applying a precharge voltage to the one or more control lines, while reducing the voltage at the end of programming verification to provide the channel of the unselected memory cell with access to the precharge voltage of the one or more control lines, while reducing the voltage of the data word line farther away from the one or more control lines than the selected word line, the control circuit being configured to cut off the channel of the unselected memory cell from the one or more control lines after the precharge and before reducing the data word line between the selected word line and the one or more control lines from the overdrive voltage to one or more voltages lower than the threshold voltage of the memory cell connected to the data word line between the selected word line and the one or more control lines.

2. The nonvolatile memory device according to claim 1, wherein: The one or more control lines are one or more source lines; and The control circuit is configured to, after cutting off the channels of the unselected memory cells from the one or more source lines, reduce the one or more source lines from the precharge voltage to a quiescent voltage of the one or more source lines.

3. The nonvolatile storage device according to claim 1, further comprising: Dummy memory cell; and a dummy word line connected to the dummy memory cell, the dummy word line being located between the selected word line and the one or more control lines, the control circuit being configured to apply a first voltage to the dummy word line when precharging a channel of an unselected memory cell at the end of program verification, the first voltage being greater than a threshold voltage of the dummy memory cell, the control circuit being configured to cut off the channel of the unselected memory cell from the one or more control lines by reducing the dummy word line from the first voltage to a voltage lower than the threshold voltage of the dummy memory cell.

4. The nonvolatile memory device according to claim 1, wherein: The control circuit is configured to program memory cells connected to the selected data word line by applying a programming dose to the selected data word line and boosted channels of unselected memory cells after the precharging, the control circuit being configured to perform program verification between programming voltage pulses.

5. The nonvolatile memory device according to claim 1, wherein: The non-volatile memory cells form a block having at least three sub-blocks; The selected word line is in a selected sub-block; and The data word line between the selected word line and the one or more control lines is located in an unselected sub-block between the selected word line and the one or more control lines.

6. The nonvolatile storage device according to claim 5, further comprising: Dummy memory cell; and a dummy word line connected to the dummy memory cell, the dummy word line being located between the selected sub-block and the unselected sub-block between the selected word line and the one or more control lines, the control circuit being configured to apply a first voltage to the dummy word line when precharging a channel of the unselected memory cell at the end of program verification, the first voltage being greater than a threshold voltage of the dummy memory cell, the control circuit being configured to cut off the channel of the unselected memory cell from the one or more control lines by reducing the dummy word line from the first voltage to a voltage lower than the threshold voltage of the dummy memory cell.

7. The nonvolatile memory device according to claim 5, wherein: The control circuit is configured to reduce the selected word line from a verification comparison voltage to a quiescent voltage of the selected word line at the end of program verification while reducing a voltage of a data word line farther away from the one or more control lines than the selected word line.

8. The nonvolatile memory device according to claim 5, wherein: The control circuit is configured to lower a voltage of a data word line on a side of the selected word line closer to the one or more control lines in the selected subblock while lowering a voltage of a data word line farther away from the one or more control lines than the selected word line.

9. The nonvolatile memory device according to claim 1, wherein: The memory cells are arranged into NAND strings to form a block having at least three sub-blocks, each NAND string comprising memory cells in each of the three sub-blocks; The selected word line is in a selected sub-block; and The data word line between the selected word line and the one or more control lines is located in an unselected sub-block between the selected word line and the one or more control lines.

10. The nonvolatile storage device according to claim 9, further comprising: Dummy memory cells, each NAND string including at least one dummy memory cell; and a dummy word line connected to the dummy memory cell, the dummy word line being located between the selected sub-block and the unselected sub-block, the control circuit being configured to apply a first voltage to the dummy word line when precharging a channel of the unselected memory cell at the end of program verification, the first voltage being greater than a threshold voltage of the dummy memory cell, the control circuit being configured to cut off the channel of the unselected memory cell from the one or more control lines by reducing the dummy word line from the first voltage to a voltage lower than the threshold voltage of the dummy memory cell.

11. The nonvolatile memory device according to claim 10, wherein: The control circuit is configured to reduce the selected word line from a verification comparison voltage to a quiescent voltage of the selected word line at the end of program verification while reducing a voltage of a data word line farther away from the one or more control lines than the selected word line; as well as The control circuit is configured to lower a voltage of a data word line on a side of the selected word line closer to the one or more control lines in the selected subblock while lowering a voltage of a data word line farther away from the one or more control lines than the selected word line.

12. The nonvolatile memory device according to claim 10, wherein: The control circuit is configured to program memory cells connected to the selected data word line by applying a program dose to the selected data word line and boosted channels of unselected NANDs after the precharge, and the control circuit is configured to perform program verification between program voltage pulses.

13. A method of operating a non-volatile memory device, the method comprising: applying a programming dose to a selected data word line among a plurality of data word lines connected to a plurality of NAND strings, the plurality of NAND strings forming a block having at least three sub-blocks, each NAND string including memory cells in each of the three sub-blocks, the selected word line being in the selected sub-block, each NAND string including a dummy memory cell; inhibiting the unselected NAND strings in the selected sub-block from programming by boosting their channels from a positive precharge voltage to a boost voltage; performing program verification between pairs of consecutive programming doses; Precharging the channels of the unselected NAND strings in the selected sub-block to the positive precharge voltage while lowering the voltage at the end of program verification by simultaneously: applying a precharge voltage to a source line connected to the NAND string, applying an overdrive voltage to a data word line in a sub-block closer to the source line than the selected sub-block, lowering a voltage of a data word line on a side of the selected word line further away from the source line than the selected data word line, and applying an overdrive voltage to a dummy word line between the selected sub-block and the sub-block closer to the source line than the selected sub-block, the dummy word line being connected to the dummy memory cell of the NAND string; After the precharging, lowering the dummy word line between the selected sub-block and the sub-block closer to the source line to a quiescent voltage; as well as After lowering the dummy word line to the quiescent voltage and before the next programming dose, the data word line in the sub-block closer to the source line than the selected sub-block is lowered to one or more quiescent voltages.

14. The method according to claim 13, further comprising: At the end of program verification, the selected word line is lowered from a verification comparison voltage to a quiescent voltage of the selected word line while lowering a voltage of a data word line on the side of the selected word line farther from the source line than the selected data word line.

15. The method according to claim 13, further comprising: After the drive voltage is initially applied, a source side select line is lowered from a verify enable voltage to an intermediate voltage, each NAND string including a source side select gate between a memory cell and the source line, the source side select line being connected to the source side select gate, the intermediate voltage being higher in magnitude than a threshold voltage of the source side select gate.

16. The method according to claim 13, further comprising: At the end of program verification, while lowering the voltage of the data word line on the side of the selected word line farther away from the source line than the selected data word line, the voltage of the data word line on the side of the selected word line that is closer to the source line than the selected data word line in the selected sub-block is lowered.

17. The method according to claim 13, further comprising: After lowering the dummy word line to the quiescent voltage and before the next programming dose, the source line is lowered from the precharge voltage to a lower voltage.

18. The method of claim 13, wherein: The lowering of the dummy word line to the quiescent voltage includes lowering the dummy word line from a voltage greater than a threshold voltage of the dummy memory cell to a voltage less than the threshold voltage of the dummy memory cell.

19. The method of claim 13, wherein: The lowering of the voltage of the data word line on the side of the selected word line further away from the source line than the selected data word line includes lowering the data word line on the side of the selected word line further away from the source line than the selected data word line from one or more overdrive voltages to one or more quiescent voltages.

20. A non-volatile storage device, comprising: a plurality of nonvolatile memory cells arranged as NAND strings to form a block having at least three sub-blocks, each NAND string comprising memory cells in each of the three sub-blocks, each NAND string comprising a dummy memory cell; a plurality of data word lines connected to the NAND strings; a dummy word line connected to the dummy memory cell of the NAND string; a plurality of bit lines connected to the NAND strings; a source line connected to the NAND string; and a control circuit connected to the data word line, the dummy word line, the bit line, and the source line; The control circuit is configured to program memory cells connected to a selected data word line by applying a series of programming voltage pulses to the selected data word line and boosted channels of unselected NAND strings, the control circuit is configured to perform programming verification between the programming voltage pulses, the control circuit includes means for precharging channels of unselected NAND strings in a selected sub-block before a next programming voltage pulse from a source line, while reducing the voltage at the end of programming verification by applying an overdrive voltage to data word lines in a sub-block closer to the source line than the selected sub-block, and reducing a dummy word line between the selected sub-block and the sub-block closer to the source line to the quiescent voltage before reducing the data word line in the sub-block closer to the source line to the quiescent voltage.

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