Method for manufacturing patterned FD-SOI wafer

Abstract

A method for preparing a donor silicon wafer by applying a SiGe layer on a silicon substrate wafer, depositing a silicon layer on the SiGe layer, etching the silicon layer to form an opening in the silicon layer, wet etching the SiGe layer through the opening in the silicon layer to partially remove SiGe material from the SiGe layer and retain the silicon layer, and removing the donor silicon wafer from the silicon substrate wafer. Depositing a buried oxide layer on the silicon layer, etching the buried oxide layer to form a body bias region, and depositing silicon in the body bias region; bonding an acceptor process wafer to the etched buried oxide layer of the donor silicon wafer to define a BOX; and wet etching the SiGe layer to release the donor silicon wafer from the acceptor treated wafer.

Description

[0001] Related patent applications

[0002] This application claims priority to commonly owned U.S. Application No. 63 / 426,657, filed on November 18, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates to fully depleted silicon-on-insulator (FD-SOI) wafer production, and in particular to the production of patterned FD-SOI wafers from a standard silicon starting substrate wafer. Background Art

[0004] Fully Depleted Silicon-On-Insulator (FD-SOI) wafers are also called Ultra-Thin or Extremely Thin Silicon-On-Insulator (ET-SOI) wafers. Generally speaking, FD-SOI wafers are obtained from substrate manufacturers, and then the buried oxide layer (BOX) is patterned and epitaxially grown. This is very expensive. Patterned FD-SOI wafers are expensive because of the total process cost, including the cost of the FD-SOI substrate and the additional cost associated with etching the patterned buried oxide layer (BOX) area and regrowing the body bias area through epitaxial (EPI) growth.

[0005] Conventional methods for forming FD-SOI wafers result in a continuous buried oxide layer (BOX) and device silicon layer, which must be patterned to allow the top side to contact the body. For example, FD-SOI wafers have a silicon top layer, so the buried oxide layer (BOX) is not exposed. The buried oxide layer (BOX) should be opened or exposed for body bias. In order to open or expose the ultra-thin buried oxide (BOX) area for substrate contact, the wafer undergoes further processing, such as etching. The cost associated with further processing to expose the ultra-thin buried oxide (BOX) area makes FD-SOI expensive.

[0006] There is a need for a cost-reduced and simplified patterning FD-SOI wafer process that produces FD-SOI wafers with an exposed buried oxide (BOX) for substrate contacts. Summary of the invention

[0007] Various aspects provide a method for producing a patterned FD-SOI wafer from a standard silicon starting substrate wafer, wherein the method utilizes a selective Si / SiGe wet etch chemistry and a dual purpose STI / release hole pattern to form a pre-patterned FD-SOI wafer.

[0008] One aspect provides a method, which includes: preparing a donor silicon wafer, including: applying a sacrificial SiGe layer on a silicon substrate wafer; depositing a donor silicon layer on the SiGe layer; etching the donor silicon layer to form at least one opening in the silicon layer; wet etching the sacrificial SiGe layer through the at least one opening in the silicon layer to partially remove SiGe material from the sacrificial SiGe layer and retain the donor silicon layer; depositing a SiO2 layer on the donor silicon layer; etching the SiO2 layer to form at least one body bias region; and depositing silicon or polysilicon in the at least one body bias region; bonding an acceptor process wafer to the etched SiO2 layer of the donor silicon wafer; and wet etching the sacrificial SiGe layer to release the donor silicon wafer from the acceptor process wafer, whereby the SiO2 layer and the donor silicon layer remain bonded to the acceptor process wafer to form a fully depleted silicon-on-insulator (FD-SOI) wafer, wherein the SiO2 layer is a buried oxide layer.

[0009] One aspect provides a method according to the preceding paragraph, wherein applying a sacrificial SiGe layer on the silicon substrate wafer comprises epitaxially growing the SiGe layer.

[0010] One aspect provides a method according to any of the preceding paragraphs, wherein applying the sacrificial SiGe layer on the silicon substrate wafer results in a sacrificial SiGe layer having a thickness that is about ten times the thickness of the silicon substrate wafer.

[0011] One aspect provides a method according to any of the preceding paragraphs, wherein at least one opening in the silicon layer comprises a dummy fill opening.

[0012] One aspect provides a method according to any of the preceding paragraphs, wherein etching the donor silicon layer to form at least one opening in the silicon layer comprises etching the silicon layer to form a plurality of openings in the silicon layer in a first predetermined pattern.

[0013] One aspect provides a method according to any of the preceding paragraphs, wherein etching the SiO2 layer to form at least one body bias region comprises etching a buried oxide layer to form a plurality of body bias regions in a second predetermined pattern.

[0014] One aspect provides a method according to any of the preceding paragraphs, wherein depositing a SiO 2 layer on the donor silicon layer comprises filling at least one opening with SiO 2 .

[0015] One aspect provides a method according to any of the preceding paragraphs, wherein depositing a SiO2 layer on the donor silicon layer comprises filling at least one opening with SiO2 material without bridging oxide material between the silicon substrate wafer and the donor silicon layer.

[0016] One aspect provides a method according to any of the preceding paragraphs, comprising patterning a sacrificial SiGe layer with a shallow trench isolation mask.

[0017] One aspect provides a method according to any of the preceding paragraphs, the method comprising patterning a SiO 2 layer to define at least one body bias region in the SiO 2 layer.

[0018] One aspect provides a method according to any of the preceding paragraphs, the method comprising polishing the SiO 2 layer and at least one body bias region to planarize the SiO 2 layer.

[0019] One aspect provides a method according to any of the preceding paragraphs, comprising polishing the SiO2 layer and at least one body bias region.

[0020] One aspect provides a method according to any of the preceding paragraphs, the method comprising doping an implant in a receptor process wafer.

[0021] On the other hand, a device made by a method is provided, the device comprising: a fully depleted silicon-on-insulator (FD-SOI) wafer, the fully depleted silicon-on-insulator (FD-SOI) wafer comprising: a silicon substrate, the silicon substrate comprising doping implants; a silicon layer, the silicon layer having a plurality of openings arranged in a first predetermined pattern; and a SiO2 layer between the silicon substrate and the silicon layer, wherein the SiO2 layer has a plurality of body bias regions arranged in a second predetermined pattern, thereby exposing the SiO2 layer through the plurality of openings, wherein the device is made by the method described in any of the preceding paragraphs.

[0022] According to another aspect, a device is provided, comprising: a fully depleted silicon-on-insulator (FD-SOI) wafer, the fully depleted silicon-on-insulator (FD-SOI) wafer comprising: a silicon substrate; a SiO2 layer on the silicon substrate, wherein the SiO2 layer has at least one buried oxide (BOX); a silicon layer on the SiO2 layer, wherein the silicon layer has at least one opening, through which the at least one BOX is exposed via an exposure plug in the at least one opening, wherein the exposure plug has a box dimension larger than an exposure dimension, wherein the box dimension is close to a proximal end of the exposure plug where the exposure plug is joined to the BOX, and the exposure dimension is close to a distal end of the exposure plug.

[0023] One aspect provides a device according to the preceding paragraph, wherein the FD-SOI wafer comprises doping implants in the silicon substrate.

[0024] One aspect provides a device according to any one of the two preceding paragraphs, wherein the silicon layer of the FD-SOI wafer includes a plurality of openings arranged in a first predetermined pattern, through which a plurality of BOXs arranged in a second predetermined pattern in the SiO2 layer are exposed via a plurality of exposure plugs in the plurality of openings.

[0025] One aspect provides a device according to any one of the three preceding paragraphs, wherein the exposed plug has a trapezoidal cross-section. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings illustrate aspects of an FD-SOI wafer device having an exposed buried oxide layer (BOX) for substrate contact and a method for producing a patterned FD-SOI wafer from a standard silicon starting substrate wafer, wherein the method utilizes a selective Si / SiGe wet etch chemistry and a dual-purpose STI / release hole pattern to form a pre-patterned FD-SOI wafer.

[0027] Figure 1A A cross-sectional side view of a silicon substrate having a sacrificial SiGe layer and a donor silicon layer is shown.

[0028] Figure 1B Shows Figure 1A An expanded cross-sectional side view of a first example of an opening in a donor silicon layer is shown.

[0029] Figure 1C Shows Figure 1A An expanded cross-sectional side view of a second example of an opening in a donor silicon layer is shown.

[0030] Figure 1D Shows Figure 1A A cross-sectional side view of a wafer is shown where the wafer has undergone a partial selective wet etch of the SiGe layer while retaining the donor silicon layer.

[0031] Figure 1E Shows Figure 1D Shown is a cross-sectional side view of a wafer to which a SiO2 layer has been added by non-conformal oxide deposition.

[0032] Figure 1F Shows Figure 1E A cross-sectional side view of a wafer is shown in which a body bias region has been formed.

[0033] Figure 1G Shows Figure 1F A cross-sectional side view of a donor silicon wafer is shown with an acceptor handle wafer positioned for bonding to the donor silicon wafer.

[0034] Figure 1H Shows Figure 1GA cross-sectional side view of a wafer is shown with a receptor handle wafer bonded to a donor silicon wafer.

[0035] Fig. 1I Shows Figure 1H A cross-sectional side view of a bonded wafer is shown where the SiGe layer has been wet etched to release the donor silicon wafer from the acceptor handle wafer.

[0036] Figure 1J Shows Fig. 1I A cross-sectional side view of a completed receptor handle wafer is shown, where the receptor handle wafer is inverted so that the buried oxide layer (BOX) and body bias region are at the top surface.

[0037] Figure 2 A flow chart showing a method for manufacturing a FD-SOI wafer is shown.

[0038] Figure 3 yes Figure 1J An enlarged cross-sectional side view of a portion of receptor handle wafer 120 is shown.

[0039] Reference numerals for any illustrated element that appear in multiple different figures have the same meaning in the multiple figures, and reference or discussion herein to any illustrated element in the context of any particular figure also applies to every other figure (if any) in which the same illustrated element is shown. DETAILED DESCRIPTION

[0040] Methods for producing patterned FD-SOI wafers from standard silicon starting substrate wafers are described herein, which utilize selective Si / SiGe wet etch chemistry and dual-purpose (shallow trench isolation) STI / release hole patterns to form patterned FD-SOI wafers. The method can utilize commonly available silicon processing tools to form patterned FD-SOI wafers with dual-purpose release etch / STI regions and substrate contact regions from standard silicon starting substrates. No specialized implanter is required in the process. No wafer splitting tool is required in the process. The method can use only a new original silicon wafer for each cycle, making the process cheaper than patterning and etching the FD-SOI wafer to expose a buried oxide (BOX) layer. The method can produce a fully depleted silicon-on-insulator (FD-SOI) wafer, which includes: a silicon substrate; a buried oxide layer on the silicon substrate, wherein the buried oxide layer has at least one body bias region; and a silicon layer on the buried oxide layer, wherein the silicon layer has at least one opening, through which the buried oxide layer is exposed.

[0041] The FD-SOI process may not require a doped channel. The behavior of the transistor may be controlled by the gate and may also be controlled by the body bias. The FD-SOI process may use a standard starting silicon substrate and commonly available semiconductor processing tools to form the body bias region during the formation of the buried oxide layer (BOX) and device layers.

[0042] Figure 1A A cross-sectional side view of an original standard starting wafer in the form of a silicon substrate 102 is shown. A sacrificial silicon germanium (SiGe) layer 104 has been epitaxially grown or deposited on the silicon substrate 102. A donor silicon layer 106 has been epitaxially grown or deposited on the sacrificial SiGe layer 104 to form a donor silicon wafer 108. The donor silicon layer 106 has been patterned with a shallow trench isolation (STI) mask and photoetched to form an opening 110 in the donor silicon layer 106. The STI mask is a special masking layer that can be used for isolation between devices. The STI mask can have a dual purpose, in that it defines the area that will eventually have the isolation oxide (the area called the STI area), and also provides the opening 110 for the initial or first release etch. The etching of the donor silicon layer 106 can form a plurality of openings 110 in the donor silicon layer 106 in a first predetermined pattern. STI (also known as box isolation technology) is an integrated circuit feature that prevents current leakage between adjacent semiconductor device components. STI is typically used on CMOS process technology nodes of 250 nanometers and smaller. As used herein, the STI region reaches down to the SiO2 layer (see Figure 1J ). For higher voltage silicon CMOS (e.g. for bipolar CMOS-DMOS (BCD)), additional masks can provide deeper trenches that are not on the buried oxide, so that flash or precision analog of patterned FD-SOI can provide some bulk CMOS area. The bulk CMOS area can be provided much deeper using different masks (>> In one aspect, there may be shallow trenches and deeper trenches. In some aspects, a final FD-SOI integrated circuit wafer may have many CMOS regions, but may not have as many buried oxides (BOX) in the final FD-SOI integrated circuit wafer. The deeper trenches may be made in the bulk CMOS region without the BOX. Etching only through the silicon in the bulk CMOS region may be simpler than etching through the device silicon, the SiO2 layer, and then into the handle wafer.

[0043] Figure 1B Shows Figure 1AA first example of an enlarged cross-sectional side view of an opening 110 in the donor silicon layer 106 is shown. The thickness of the sacrificial SiGe layer 104 relative to the size of the opening 110 in the donor silicon layer 106 can affect the amount of SiGe that is dissolved away in the later wet etch described below. The large openings 110 (STI regions) can then be at least partially filled so that subsequent oxide deposition used to fill these openings 110 (areas opened using the STI mask) may not form a continuous bridge to the bottom of the wet etched area. The size of the opening 110 can affect the initial wet etch. If the opening 110 is too large, the initial wet etch of SiGe may completely remove the SiGe layer 104, and then the subsequent oxide deposition will be continuous from the donor silicon layer 106 to the silicon substrate 102. If the SiO2 layer 112 bridges (see Figure 1E ), the second SiGe wet etch may not release the donor silicon layer 106 from the silicon substrate 102. Fig. 1I The large opening area may not pinch off subsequent non-conformal oxide deposition, the entire area of ​​SiGe under the large opening area may be removed, and subsequent oxide deposition may be filled to the bottom of the wet etched hole. This may prevent the wafer from separating during the second SiGe wet etch. In one aspect, the diameter of the opening 110 is 50% of the thickness of the SiGe layer 104, which may inhibit bridging.

[0044] Figure 1C Shows Figure 1A A second example of an enlarged cross-sectional side view of an opening 110 in the donor silicon layer 106 is shown. If a relatively large isolation region is desired, the isolation region can be formed by adding dummy fill to make many small openings adjacent to each other, such as Figure 1C As shown. As shown in the figure, the opening 110 includes an array of smaller openings. Figure 1B Multiple dummy fill openings 110 may be used to slow down the wet etching process so that less of the SiGe layer 104 is dissolved away, compared to the one relatively large opening 110 shown. If an isolation region greater than 50% of the thickness of the SiGe layer 112 is desired, a dummy fill may be added (see Figure 1C) to inhibit the initial wet etching through the entire thickness of the SiGe layer 104, and may also pinch off oxide deposition to inhibit bridging to the silicon substrate 102. The dummy fill is a pattern that is not electrically active and is placed to make the pattern denser because non-uniformities may occur in large areas without patterns (e.g., areas that may be etched when the dummy fill is applied in the area). Dummy fill may be added in large opening areas to effectively make the large opening areas an array of smaller opening areas that will be processed more uniformly. Adding dummy fill may inhibit the first SiGe wet etch from etching through the entire film thickness, and may also allow subsequent non-conformal oxide deposited to discontinuously fill the opening areas, thereby connecting the device silicon to the processing wafer. The large opening areas patterned into the device silicon layer may form wet etch holes that are etched all the way down through the SiGe layer 104 during the first wet etch. When the SiO2 material is deposited, it can then be conformal and join the silicon substrate 102 to the donor silicon layer 106, which can prevent separation during the second wet etch of the SiGe layer 104, because it is not the SiGe material that connects the two layers, but the SiO2 material that forms the bridge. In order to reduce the possibility of SiO2 bridges, large areas can be added with dummy fillers. Dummy fillers can be automatically added to the mask based on a given set of rules. This is usually done for metal layers. The routine of adding dummy fillers at the STI layer can add patterns to the large opening area and make it an array of small opening areas instead of one large opening area.

[0045] Figure 1D Shows Figure 1A 1 is a cross-sectional side view of a donor silicon wafer 108, wherein the wafer has undergone a partially selective wet etch of the sacrificial SiGe layer 104, while the donor silicon layer 106 has been retained. In the case where the pattern of the openings 110 allows more penetration of the wet etchant into the SiGe layer 104, as described with respect to Figure 1B and Figure 1C As described above, more of the sacrificial SiGe layer 104 can be removed. A portion of the sacrificial SiGe layer 104 remains to support the donor silicon layer 106, but enough of the sacrificial SiGe layer is removed to allow the donor silicon layer 106 to be later separated from the starting silicon substrate 102. Release can be achieved via a single etch from the periphery without an initial etch through the opening 110 in the donor silicon layer 106. However, a single perimeter etch will take a longer time period than is practical because the etchant will only be able to enter from the edge at the periphery of the wafer, and it will take an extremely long time to etch all the way to the center of the wafer, especially on a 300 mm wafer. In some aspects, about half of the SiGe layer 104 can be removed by a first etch through the opening in the donor silicon layer 106 (see Figure 1D), and then a second etch may be performed to remove enough of the remaining SiGe layer 104 from the periphery of the wafer to release the donor silicon layer 106. Fig. 1I If the openings 110 are relatively large or the plurality of openings 110 are closely spaced, the time period of the first wet etch may be shortened to reduce the amount of SiGe layer 104 etched away so that a sufficient amount of SiGe layer 104 remains to support the donor silicon layer 106. If the openings 110 are relatively small or the plurality of openings 110 are spaced far apart, the time period of the first wet etch may be extended to increase the amount of SiGe layer 104 etched away so that enough of the SiGe layer 104 is etched away so that a second wet etch from the periphery of the wafer can remove the remaining SiGe layer 104 to achieve separation within a reasonable time period. In the case where the dummy fills may form an array of smaller opening areas, the wet etch time of the first wet etch of the SiGe layer 104 may be longer without significantly increasing the risk of etching all the way through the SiGe layer 104.

[0046] Figure 1E Shows Figure 1D A cross-sectional side view of a donor silicon wafer 108 is shown in which a SiO2 layer 112 has been added by non-conformal oxide deposition. When the SiO2 layer 112 is deposited, the SiO2 may pass through the openings 110 in the donor silicon layer 106. If too much SiO2 passes through the openings 110 in the donor silicon layer 106, it may form a bridge from the starting silicon substrate wafer 102 to the donor silicon layer 106. The bridge between the starting silicon substrate 102 and the donor silicon layer 106 may make it more difficult to release the donor silicon layer 106 from the starting silicon substrate wafer in a later singulation process. Therefore, one aspect of the process is to deposit the SiO2 layer 112 so that the SiO2 is deposited at and through the openings 110 in the donor silicon layer 106 to form the exposed plugs 130, but without bridging the SiO2 with the starting silicon substrate 102. Non-conformal SiO2 deposition processes have a characteristic known as "bread loafing", which increases the deposition rate at the corners of the features deposited thereon. After a certain amount of oxide is deposited, the "bread loaf" may cause the openings 110 to close, so that each opening 110 in the donor silicon layer 106 (see Figure 1D ) to form SiO2 exposed plug 130 (see Figure 1E ). In some aspects, it may be desirable to keep the opening 110 small enough so that it closes during the SiO2 deposition to inhibit areas of oxide bridging from the donor silicon layer 106 and the silicon substrate 102. After the SiO2 layer 112 is added by non-conformal oxide deposition, the SiO2 layer 112 may then undergo a polishing process or a chemical mechanical polishing (CMP) process to planarize the SiO2 layer 112 to a desired buried oxide (BOX) layer thickness 114.

[0047] Figure 1F Shows Figure 1E 1 is a cross-sectional side view of a donor silicon wafer 108 in which a body bias region 116 has been formed. The body bias region 116 may be formed by selective epitaxial (EPI) growth, or deposition, or doping of polysilicon. In particular, in one example, the body bias region 116 may be patterned and the SiO2 layer 112 (see Figure 1E ) may be etched to remove SiO2 material from the body bias region 116. Silicon may then be formed in the etched body bias region 116 by EPI growth, thereby causing the SiO2 layer 112 to have BOX 132 separated by the body bias region 116. Etching the SiO2 layer 112 to form the body bias region 116 may include etching the SiO2 layer 112 to form a plurality of body bias regions 116 in a second predetermined pattern. Alternatively, doped polysilicon may be formed in the etched body bias region 116 by deposition. The BOX 132 with the body bias region 116 formed therebetween may then be planarized by polishing or chemical mechanical polishing (CMP), wherein a desired buried oxide (BOX) layer thickness 114 may be obtained by CMP.

[0048] Figure 1G Shows Figure 1F A cross-sectional side view of a donor silicon wafer 108 is shown, wherein an acceptor handle wafer 120 is positioned for bonding to the side of the donor silicon wafer 108 having BOXes 132, wherein a body bias region 116 is formed between the BOXes, i.e., bonded to a top side 124. The acceptor handle wafer 120 can be prepared to include highly doped implants 122. In particular, well regions on the acceptor handle wafer can be patterned and highly doped to form the highly doped implants 122. In some aspects, the acceptor handle wafer 120 can be highly doped as deposited, or it can be highly doped subsequently by ion implantation so that electrical contact can be made to the acceptor handle wafer 120. The amount of doping that is considered highly doped can vary based on the tolerable resistance, for example, about 20 mOhm-cm. A body bias region 116 (see Figure 1F ) to the highly doped implant 122 (see Figure 1G ) current path, which allows the voltage under BOX 132 to be controlled from the top side 138 of the acceptor handle wafer 120. Figure 1J This current path may be used for a FDSOI transistor that may be built in the device silicon above BOX 132 .

[0049] The acceptor handle wafer 120 may be planarized in preparation for bonding with the donor silicon wafer 108 .

[0050] Figure 1H Shows Figure 1GA cross-sectional side view of a donor silicon wafer 108 and an acceptor handle wafer 120 is shown, wherein the acceptor handle wafer 120 has been bonded to the donor silicon wafer 108. In particular, the silicon acceptor handle wafer 120 is bonded to the combined body bias region 116 and SiO2 layer 112 of the donor silicon wafer 108.

[0051] Fig. 1I Shows Figure 1H The donor silicon wafer 108 and the acceptor handle wafer 120 are shown in cross-sectional side view, wherein the sacrificial SiGe layer 104 is wet etched again. Figure 1D . This second wet etch allows the etchant to flow from the periphery of the wafer toward the center of the wafer to remove enough of the SiGe layer 104 to release the starting silicon substrate 102 from the donor silicon layer 106, which is now part of the acceptor handle wafer 120. The wet etch may be injected from the side of the periphery between the wafers 108 and 120 and may propagate through the entire sacrificial SiGe layer 104 because the sacrificial SiGe layer 104 has been removed by the reference Figure 1D The aforementioned previous etching removes most of the SiGe material. This selective wet etching of the sacrificial SiGe layer 104 retains the SiO2 material including the BOX 132 of the exposed plugs 130 filling the openings 110 of the donor silicon layer 108 and allows the acceptor handle wafer 120 to be released from the silicon substrate 102 of the donor silicon wafer 106.

[0052] The donor silicon wafer 108 may thereafter be polished or chemically mechanically polished (CMP) to remove any remaining portions of the sacrificial SiGe layer 104 so that it can be used as an acceptor process wafer 120 in the next production cycle.

[0053] Figure 1J Shows Fig. 1I A cross-sectional side view of a receptor handle wafer 120 is shown, wherein the receptor handle wafer 120 is inverted so that BOX 132 and body bias region 116 are located at top side 138 as shown. The receptor handle wafer 120 may be polished or chemically mechanically polished (CMP) to planarize the final patterned FD-SOI wafer.

[0054] Figure 2 A method for manufacturing an FD-SOI wafer is shown. According to the method, a SiGe layer 104 may be applied 202 to a silicon substrate 102 by epitaxial growth, having a thickness of about ten times (10x) the thickness of the silicon substrate 102. The SiGe layer 104 may be a sacrificial layer. A donor silicon layer 108 may be deposited 2204 on the SiGe layer 104. The donor silicon layer 108 may be masked or patterned and etched 206 to form an opening 110. See Figure 1AWith respect to the epitaxial growth of the SiGe layer 104 on the silicon substrate 102, the donor silicon layer 106 may be patterned with a dual purpose release etch / STI pattern, wherein the first purpose is to provide an opening 110 through the donor silicon layer 106 for a first etch of the SiGe layer 104 (see Figure 1D ), and the second purpose is to fill the opening 110 with SiO2 to form an exposed plug 130 used as an STI region to isolate between devices. Figure 1E . The pattern for shallow trench isolation (STI) that is subsequently filled with oxide is dual purpose in that the pattern is initially used to facilitate a first partial release etch of the SiGe layer 104. The large pattern openings 110 (STI regions) may be at least partially filled with a dummy fill material so that subsequent oxide deposition used to fill these openings may not form a continuous bridge to the bottom of the wet etched region. The SiGe layer is wet etched 408 through the openings in the donor silicon layer 106 to partially remove the SiGe material from the SiGe layer 106 and retain the donor silicon layer 104. The wet etch 408 may etch more than 50% of the SiGe, and the wet etch 408 is selective to silicon because it etches SiGe at a much higher rate than Si. See Figure 1D A silicon oxide (SiO2) layer 112 may be deposited 210 on the donor silicon layer to fill the opening 110 and achieve a preselected buried oxide (BOX) layer thickness 114, but the oxide may not be conformal or bridge to the bottom of the wet etched area. By controlling the size of the opening 110 and the duration of the wet etch, a desired amount of the SiGe layer 104 may be removed. The deposition 210 of the SiO2 layer may have a preselected layer thickness corresponding to the preselected buried oxide (BOX) layer thickness 114. See Figure 1E The silicon oxide (SiO2) layer 112 may be patterned and etched 212 to form a body bias region 116. The body bias region 116 may be filled 214 with selective silicon EPI or highly doped polysilicon, followed by polishing or chemical mechanical polishing (CMP) of the donor silicon wafer 108. Figure 1F . Selective silicon EPI can also be doped (see Figure 1G The highly doped implant 122 in the gate is provided to provide an electrical path from the top side 138 of the acceptor handle wafer 120 to the silicon under the BOX 132 so there is a good electrical connection from the body bias region 116 through the highly doped implant 122 under the gate. The acceptor handle wafer 120 may be patterned and implanted 216 to form a highly doped well region or highly doped implant 122. See Figure 1G The donor silicon wafer 108 may be bonded 218 to the acceptor handle wafer 120. Figure 1H The SiGe layer may be wet etched 220 from the side to complete the release of the two wafers. Fig. 1IThe receptor handle wafer 120 (now a patterned FD-SOI wafer) may undergo a polishing process or a chemical mechanical polishing (CMP) process to planarize the portion of the SiO2 layer 112 forming the exposure plugs 130 extending through the openings 110 of the STI regions so that the exposure plugs 130 are flush with the device silicon. Fig. 1I and 1J The method produces a fully depleted silicon-on-insulator (FD-SOI) wafer having a BOX 132 of a desired thickness 114. Figure 1J . Donor silicon wafer 108 (see Fig. 1I ) can become a receptor wafer 120 in the next process cycle (see Figure 1G ).

[0055] Figure 3 yes Figure 1J An enlarged cross-sectional side view of a portion of an acceptor handle wafer 120 is shown. The acceptor handle wafer 120 has a silicon substrate 102, a SiO2 layer 112, and a donor silicon layer 106. The SiO2 layer 112 has a number of BOXes 132 separated by body bias regions 116. The donor silicon layer 106 has an opening 110 filled with exposed plugs 130. When the STI region is etched to form the opening 110 in the silicon donor layer 106, there is a slight taper of the silicon sidewalls. The top of the opening is slightly wider than the bottom. Because the opening 110 is formed early in the process and the acceptor handle wafer 120 is flipped over, the wider portion of the opening 110 is on the bottom, as shown in FIG. Figure 3 As shown. Therefore, the exposed plug 130 has a box dimension 136 that is larger than the exposed dimension 134. The box dimension 136 of the exposed plug 130 is near the proximal end of the exposed plug 130 engaged with the BOX 132, and the exposed dimension 134 is near the distal end of the exposed plug 132, as shown. Figure 3 As shown. The exposed plug 130 is Figure 3 The view plane shown has a trapezoidal cross section.

[0056] Although examples have been described above, other modifications and examples may be made in accordance with this disclosure without departing from the spirit and scope of these disclosed examples.

Claims

1. A method, comprising: Preparing a donor silicon wafer, comprising: applying a sacrificial SiGe layer on a silicon substrate wafer; depositing a donor silicon layer on the SiGe layer; etching the donor silicon layer to form at least one opening in the silicon layer; wet etching the sacrificial SiGe layer through the at least one opening in the silicon layer to partially remove SiGe material from the sacrificial SiGe layer and retain the donor silicon layer; depositing a SiO2 layer on the donor silicon layer; etching the SiO2 layer to form at least one body bias region; and depositing silicon or polysilicon in the at least one body bias region; bonding an acceptor handle wafer to the etched SiO2 layer of the donor silicon wafer, whereby a buried oxide (BOX) is defined by the donor silicon layer, the at least one body bias region, and the acceptor handle wafer; and wet etching the sacrificial SiGe layer to release the donor silicon layer from the silicon substrate wafer, The SiO2 layer and the donor silicon layer thereby remain bonded to the acceptor handle wafer to form a fully depleted silicon-on-insulator (FD-SOI) wafer. 2 . The method of claim 1 , wherein applying the sacrificial SiGe layer on the silicon substrate wafer comprises epitaxially growing the SiGe layer.

3. The method of claim 1 or claim 2, wherein applying the sacrificial SiGe layer on the silicon substrate wafer results in the sacrificial SiGe layer having a thickness that is approximately ten times the thickness of the silicon substrate wafer. 4 . The method of claim 1 , wherein the at least one opening in the silicon layer comprises a dummy fill opening. 5 . The method of claim 1 , wherein etching the donor silicon layer to form the at least one opening in the silicon layer comprises etching the silicon layer to form a plurality of openings in the silicon layer in a first predetermined pattern. 6 . The method of claim 1 , wherein etching the SiO 2 layer to form the at least one body bias region comprises etching a buried oxide layer to form a plurality of body bias regions in a second predetermined pattern.

7. The method according to any one of claims 1 to 6, wherein depositing the SiO2 layer on the donor silicon layer comprises filling the at least one opening with SiO2.

8. The method of any one of claims 1 to 7, wherein depositing the SiO2 layer on the donor silicon layer comprises filling the at least one opening with SiO2 material without bridging oxide material between the silicon substrate wafer and the donor silicon layer.

9. The method according to any one of claims 1 to 8, comprising patterning the sacrificial SiGe layer with a shallow trench isolation mask.

10. A method according to any one of claims 1 to 9, comprising patterning the SiO2 layer to define the at least one body bias region in the SiO2 layer.

11. The method of any one of claims 1 to 10, comprising polishing the SiO2 layer and the at least one body bias region to planarize the SiO2 layer.

12. The method according to any one of claims 1 to 11, comprising polishing the SiO2 layer and the at least one body bias region.

13. A method according to any one of claims 1 to 12, comprising doping an implant in the receptor handle wafer.

14. A device, comprising: A fully depleted silicon-on-insulator (FD-SOI) wafer, the fully depleted silicon-on-insulator (FD-SOI) wafer comprising: Silicon substrate; a SiO2 layer on the silicon substrate, wherein the SiO2 layer has at least one buried oxide (BOX); a silicon layer on the SiO2 layer, wherein the silicon layer has at least one opening, through which the at least one BOX is exposed via an exposure plug in the at least one opening, wherein the exposure plug has a box-shaped dimension larger than an exposure dimension, wherein the box-shaped dimension is close to a proximal end of the exposure plug where it is joined to the BOX, and the exposure dimension is close to a distal end of the exposure plug.

15. The device of claim 14, wherein the FD-SOI wafer comprises doping implants in the silicon substrate.

16. The device according to any one of claims 14 to 15, wherein the silicon layer of the FD-SOI wafer includes a plurality of openings arranged in a first predetermined pattern, through which a plurality of BOXs arranged in a second predetermined pattern in the SiO2 layer are exposed via a plurality of exposure plugs in the plurality of openings. 17 . The device according to claim 14 , wherein the exposed plug has a trapezoidal cross section.

18. A device made by the method, the device comprising: A fully depleted silicon-on-insulator (FD-SOI) wafer, the fully depleted silicon-on-insulator (FD-SOI) wafer comprising: a silicon substrate comprising dopant implants; a silicon layer having a plurality of openings arranged in a first predetermined pattern; and A SiO2 layer between the silicon substrate and the silicon layer, wherein the SiO2 layer has a plurality of body bias regions arranged in a second predetermined pattern to define a plurality of buried oxides (BOXs), whereby the plurality of BOXs are respectively exposed through the plurality of openings, wherein the device is manufactured by the method of any one of claims 1 to 13.

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