Particle detector with reduced inter-symbol interference

Abstract

Systems and methods for fabricating a substrate for a charged particle detector in a charged particle beam apparatus are disclosed. The substrate may include a charge sensing element formed on a first surface of the substrate and configured to detect charged particles derived from a sample; and a plurality of transistors formed in a first region of a second surface of the substrate, the second surface being opposite the first surface, where a top surface of each transistor of the plurality of transistors is coplanar with a top surface of the first region and the second surface of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to EP application 22189243.3, filed on August 8, 2022, and the entire contents of which are incorporated herein by reference. Technical Field

[0003] The description herein relates to particle detectors that may be used in the field of charged particle beam systems, and more particularly to charged particle detectors with reduced inter-symbol interference. Background Art

[0004] Detectors can be used to sense physically observable phenomena. For example, charged particle beam tools such as electron microscopes can include detectors that receive charged particles projected from a sample and output detection signals. Detection signals can be used to reconstruct images of inspected sample structures, and can be used, for example, for metrology processes or to reveal defects in samples. Metering is related to the precise measurement of sample structures and other miniaturized features. For example, in semiconductor wafers, metrology can include measurements such as critical dimensions (width of minimum device features), critical dimension uniformity, line width, overlay, line edge roughness, line end shortening, bottom surface tilt, sidewall angles, and other dimensional parameters. Metering can also include material analysis based on reconstructed images from detection signals. When manufacturing semiconductor devices that may include a large number of densely packaged miniaturized integrated circuit (IC) components, it is also increasingly important to detect defects in samples. For these and other purposes, an inspection system can be provided.

[0005] Existing multi-beam detection devices typically use pixelated detectors to detect charged particles. The pixelated detector may include a diode array arranged on one layer for picking up charged particles and generating signals, and a corresponding transistor array arranged on another layer for picking up signals. In order to electrically isolate the diodes, a shallow trench isolation ("STI") topology is typically used. A shallow trench can be formed between two diodes by depositing a silicon dioxide layer that is typically hundreds of nanometers thick. However, when a detector with an STI topology is exposed to ion implantation, the silicon dioxide layer may make it difficult for charge carriers to penetrate for subsequent implantation. Both may result in a reduction in the implant dose under the area covered by the shallow trench, and may also result in charge accumulation near the transistor channel of the detector (referred to herein as "fixed charge"). This fixed charge may affect the performance and functionality of the detector. Summary of the invention

[0006] Embodiments of the present disclosure provide systems and methods for manufacturing a substrate for a charged particle detector in a charged particle beam device. The substrate may include: a charge sensing element formed on a first surface of the substrate and configured to detect charged particles originating from a sample; and a plurality of transistors formed in a first region of a second surface of the substrate, the second surface being opposite to the first surface, wherein a top surface of each of the plurality of transistors is coplanar with a top surface of the first region and the second surface of the substrate.

[0007] Another aspect of the present disclosure relates to a charged particle detector. The charged particle detector may include: a substrate layer including a first surface and a second surface opposite to the first surface; a charge sensing element formed on the first surface and configured to detect charged particles originating from a sample; and a plurality of transistors formed in a first region of the second surface of the substrate, wherein a top surface of each of the plurality of transistors is coplanar with a top surface of the first region and the second surface of the substrate.

[0008] Another aspect of the present disclosure relates to a charged particle beam device. The device may include: a charged particle source configured to emit primary charged particles to be incident on a sample; and a charged particle detector configured to detect secondary charged particles generated from the sample when interacting with the primary charged particles. The charged particle detector may include: a substrate layer including a first surface and a second surface opposite to the first surface; a charge sensing element formed on the first surface and configured to detect charged particles originating from the sample; and a plurality of transistors formed in a first region of a second surface of the substrate, wherein a top surface of each of the plurality of transistors is coplanar with a top surface of the first region and a second surface of the substrate.

[0009] Another aspect of the present disclosure relates to a method for manufacturing a substrate for a charged particle detector. The method may include the following steps: forming a charge sensing element on a first surface of the substrate, the charge sensing element being configured to detect charged particles originating from a sample; forming a plurality of transistors in a first region of a second surface of the substrate, the second surface being opposite to the first surface, wherein a top surface of each of the plurality of transistors is coplanar with a top surface of the first region and the second surface.

[0010] Other advantages of the embodiments of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings, in which certain embodiments of the present invention are set forth by way of illustration and example. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1is a diagrammatic representation of an example electron beam inspection (EBI) system according to some embodiments of the present disclosure.

[0012] FIG. 2A to FIG. 2C is a diagram illustrating an example charged particle beam apparatus that may be an electron beam tool according to some embodiments of the present disclosure.

[0013] Figure 2D Illustrated is an electron arrival distribution on an example detector in a charged particle beam apparatus according to some embodiments of the present disclosure.

[0014] Figure 3A and Figure 3B is a diagrammatic representation of an example structure of a detector in a charged particle beam apparatus according to some embodiments of the present disclosure.

[0015] Figure 4 is a schematic diagram illustrating an example charged particle detector with readout electronics according to some embodiments of the present disclosure.

[0016] Figure 5 is a schematic diagram illustrating an example simulation of a transistor with shallow trench isolation in a charged particle detector according to some embodiments of the present disclosure.

[0017] Figure 6 is a schematic diagram illustrating an exemplary charged particle detector having a substantially topology-free substrate according to some embodiments of the present disclosure.

[0018] Figure 7 is a flow chart illustrating an example method for fabricating a substrate for a charged particle detector according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] Now, reference is made in detail to example embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which, unless otherwise indicated, the same reference numerals in different figures represent the same or similar elements. The implementations set forth in the following description of the example embodiments do not represent all implementations consistent with the present disclosure. Instead, they are merely examples of devices and methods according to aspects related to the subject matter described in the appended claims. Without limiting the scope of the present disclosure, some embodiments may be described in the context of providing a detection system and a detection method in a system utilizing an electron beam ("e-beam"). However, the present disclosure is not limited thereto. Other types of charged particle beams (e.g., including protons, ions, muons, or any other particles carrying an electric charge) may also be applied. In addition, the systems and methods for detection may be used in other imaging systems, such as optical imaging, photon detection, x-ray detection, ion detection, or any imaging system that may cause a charging effect (which will be described in the present disclosure), etc.

[0020] Electronic devices consist of circuits formed on a piece of semiconductor material called a substrate. The semiconductor material may include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium. Many circuits may be formed together on the same silicon wafer and are referred to as integrated circuits or ICs. The size of these circuits has been significantly reduced so that more circuits can be mounted on a substrate. For example, an IC chip in a smartphone may be as small as a thumbnail and may also include more than 2 billion transistors, each of which is less than 1 / 1000 the size of a human hair.

[0021] Manufacturing these ICs with extremely small structures or components is a complex, time-consuming and expensive process, often involving hundreds of individual steps. An error in even one step can result in a defect in the finished IC, thereby rendering it useless. Therefore, one goal of the manufacturing process is to avoid such defects in order to maximize the number of functional ICs manufactured in the process, that is, to increase the overall yield of the process.

[0022] One component of improving yield is to monitor the chip manufacturing process to ensure that it produces a sufficient number of functional integrated circuits. One way to monitor the process is to inspect the chip circuit structure at various stages of its formation. Inspection can be performed using a scanning charged particle microscope (SCPM). For example, the SCPM can be a scanning electron microscope (SEM). The SCPM can be used to image these extremely small structures, in effect, taking a "photo" of the structure of the wafer. The image can be used to determine whether the structure is formed in the correct location. If the structure is defective, the process can be adjusted so that the defect is less likely to occur again.

[0023] An image of a wafer can be formed by scanning one or more primary beams (e.g., "probe" beams) of a scanning charged particle microscope across the wafer and collecting particles (e.g., secondary electrons) generated from the wafer surface at a detector. The secondary electrons can form one or more secondary beams directed toward the detector. For each secondary beam, the secondary electrons landing on the detector may cause an electrical signal (e.g., current, charge, voltage, etc.) to be generated in the detector. These signals can be output from the detector and can be processed by an image processor to form an image of the sample.

[0024] Typically, the detection process includes measuring the amplitude of an electrical signal generated when an electron lands on a detector. In another approach, electron counting can be used, in which the detector can count individual electron arrival events as they occur. In either approach, the intensity of the secondary beam can be determined based on an electrical signal generated in the detector, which changes proportionally to changes in the intensity of the secondary beam. However, using electron counting, the discrete number of electrons that arrive at the detector from the secondary electron beam can be determined, and the detection results can be output in digital form. The intensity of the beam can be determined by analyzing the frequency of electron arrival events.

[0025] Distortions are present in the detection signal of the detector. One of the distortions is inter-symbol interference, which is a distorted form of a symbol in a specified time interval interfering with another symbol in another specified time interval. For a detector of a charged particle beam inspection device, inter-symbol interference occurs when some charged particles are delayed in arriving at the sensing element (e.g., a diode) of the detector within a specified time interval, which may contribute to the generation of a signal in a subsequent time interval. Similar to crosstalk, which is a form of signal interference in the spatial domain, inter-symbol interference is a form of signal interference in the time domain.

[0026] Existing multi-beam detection devices typically use pixelated detectors to detect charged particles. The pixelated detector may include a diode array arranged on one layer as a sensing element, and a corresponding transistor array arranged on another layer for picking up and processing signals. In order to prevent current leakage between adjacent diodes, an isolation technology called shallow trench isolation ("STI") is used. A shallow trench can be formed between two diodes by etching. The shallow trench can form a trench pattern. A layer of dielectric material (e.g., silicon dioxide) can be deposited to fill the trench, which is typically hundreds of nanometers thick. As used herein, a dielectric material refers to a material or medium that is an electrical insulator that can be polarized by applying an electric field thereto. The detector surface to which STI is applied has a non-uniform topology (referred to herein as "STI topology").

[0027] However, when a detector having an STI topology is exposed to ion implantation, the dielectric material layer may be difficult for the implanted ions to penetrate for subsequent implantation. Both may result in reduced implantation dose under the area covered by the shallow trench, and also result in the formation of fixed charges near the transistor channel of the detector when exposed to x-ray radiation. Such fixed charges may cause inter-symbol interference to the detector and may produce low-quality inspection images.

[0028] Embodiments of the present disclosure may provide a detector with reduced inter-symbol interference. The substrate of the charged particle detector may include a charge sensing element, such as a diode, a photodiode, or other suitable charge sensing element, on one surface. A plurality of transistors may be formed on a surface of the substrate opposite to the surface including the charge sensing element. One or more of the plurality of transistors may be formed in a well region so that the top surface of each of the plurality of transistors in the well region is coplanar with the top surface of the well region and the surface on which the plurality of transistors are formed. Such a substrate may be used for a charged particle detector, which in turn may be used for a charged particle beam image inspection system.

[0029] Compared with existing charged particle detectors that use STI or field oxide for isolation, the technical solutions disclosed herein provide various technical benefits. For example, because the top surface of the transistor on the first side is coplanar with the surface between the multiple transistors on the first side, the surface of the substrate layer can have a large flatness, and dopants can be injected into the substrate layer with a uniform penetration depth. Such a planar surface can help reduce or eliminate the possibility of the formation of charge pockets. In the context of the present disclosure, a "charge pocket" refers to an area or region where the charge concentration is higher or lower than the charge concentration of the adjacent coplanar area. In addition, due to the increased planarity of the surface of the substrate layer, the potential below the substrate layer can have a flat profile due to the uniform penetration depth of the dopant and the uniform dopant concentration, which can greatly reduce inter-symbol interference, thereby improving image quality. In addition, by not using STI or field oxide for isolation, when the detector is in operation, due to the uniform depth penetration of the injected ions, x-rays are less likely to generate fixed charges, which can provide better control of the transistors in the detector and make the transistors less sensitive to radiation damage caused by x-rays.

[0030] For the sake of clarity, the relative sizes of components in the drawings may be exaggerated. In the following description of the drawings, identical or similar reference numerals refer to identical or similar components or entities, and only the differences with respect to individual embodiments are described.

[0031] As used herein, unless otherwise specifically stated, the term "or" encompasses all possible combinations, except where not feasible. For example, if a component is described that may include A or B, then unless otherwise specifically stated or not feasible, the component may include A, or B, or A and B. As a second example, if a component is described that may include A, B, or C, then unless otherwise specifically stated or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0032] Now, refer to Figure 1 , Figure 1 An example electron beam inspection (EBI) system 10 that may be used for wafer inspection according to some embodiments of the present disclosure is illustrated. Figure 1 As shown, the EBI system 10 includes a main chamber 11, a load / lock chamber 20, an electron beam tool 100 (e.g., a scanning electron microscope (SEM)), and an equipment front end module (EFEM) 30. The electron beam tool 100 is located in the main chamber 11 and can be used for imaging. The EFEM 30 includes a first load port 30a and a second load port 30b. The EFEM 30 may include additional load ports. The first load port 30a and the second load port 30b receive a wafer front opening transport box (FOUP), which contains wafers (e.g., semiconductor wafers or wafers made of other materials) or samples to be inspected (wafers and samples may be collectively referred to as "wafers" herein).

[0033] One or more robotic arms (not shown) in the EFEM 30 can transport the wafer to the load / lock chamber 20. The load / lock chamber 20 is connected to a load / lock vacuum pump system (not shown), which removes gas molecules in the load / lock chamber 20 to reach a first pressure lower than atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) can transport the wafer from the load / lock chamber 20 to the main chamber 11. The main chamber 11 is connected to a main chamber vacuum pump system (not shown), which removes gas molecules in the main chamber 11 to reach a second pressure lower than the first pressure. After reaching the second pressure, the wafer is inspected by the electron beam tool 100. The electron beam tool 100 can be a single beam system or a multi-beam system. The controller 109 is electrically connected to the electron beam tool 100 and can also be electrically connected to other components. The controller 109 can be a computer configured to perform various controls on the EBI system 10. Although the controller 109 is not limited to a single beam system or a multi-beam system, the controller 109 can be electrically connected to the electron beam tool 100. Figure 1 1 is shown as being external to the structure including the main chamber 11, the load / lock chamber 20, and the EFEM 30, but it should be appreciated that the controller 109 may be part of the structure.

[0034] Charged particle beam microscope (such as charged particle beam microscope formed by EBI system 10 or charged particle beam microscope that can be included in EBI system 10) can have resolution as low as nanometer level, for example, and can be used as the actual tool for checking IC components on wafer.Through e-beam system, the electrons of primary electron beam can be focused on the detection spot on the inspected wafer.The interaction of primary electron and wafer may cause the formation of secondary particle beam.Secondary particle beam can include backscattered electrons, secondary electrons or Auger electrons etc. produced by the interaction of primary electron and wafer.The characteristic (for example, intensity) of secondary particle beam can change based on the internal structure or external structure of wafer or the property of material, and therefore can indicate whether wafer includes defect.

[0035] Detector can be used to determine the intensity of secondary particle beam. Secondary particle beam can form beam spot on the surface of detector. Detector can generate electrical signal (for example, electric current, charge, voltage etc.) representing the intensity of detected secondary particle beam. Measurement circuit system can be utilized to measure electrical signal, and this measurement circuit system can include other components (for example, analog-to-digital converter) to obtain the distribution of detected electron. The electron distribution data collected during the detection time window can be used to reconstruct the image of inspected wafer structure or material in conjunction with the corresponding scanning path data of the primary electron beam incident on the wafer surface. Reconstructed image can be used to reveal the internal structure of wafer or the various features of external structure or material, and can be used to reveal the defect that may be present in wafer.

[0036] Figure 2A An example of a charged particle beam device according to an embodiment of the present disclosure, which may be an electron beam tool 100, is illustrated. The charged particle beam device 200A may be a multi-beam tool that uses multiple beamlets formed from a primary electron beam to simultaneously scan multiple locations on a wafer.

[0037] like Figure 2A As shown, the electron beam tool 100A may include an electron source 202, a gun aperture 204, a focusing lens 206, a primary electron beam 210 emitted from the electron source 202, a source conversion unit 212, a plurality of sub-beams 214, 216 and 218 of the primary electron beam 210, a primary projection optical system 220, a wafer stage ( Figure 2A ), a plurality of secondary electron beams 236, 238 and 240, a secondary optical system 242 and an electron detection device 244. The electron source 202 can generate primary particles, such as electrons of the primary electron beam 210. A controller, an image processing system, etc. can be coupled to the electron detection device 244. The primary projection optical system 220 can include a beam splitter 222, a deflection scanning unit 226 and an objective lens 228. The electron detection device 244 can include detection sub-areas 246, 248 and 250.

[0038] Electron source 202, gun aperture 204, focusing lens 206, source conversion unit 212, beam splitter 222, deflection scanning unit 226, and objective lens 228 may be aligned with primary optical axis 260 of apparatus 200A. Secondary optical system 242 and electron detection device 244 may be aligned with secondary optical axis 252 of apparatus 200A.

[0039] The electron source 202 may include a cathode, an extractor, or an anode, wherein primary electrons may be emitted from the cathode and extracted or accelerated to form a primary electron beam 210 having an intersection point (virtual or real) 208. The primary electron beam 210 may be visualized as being emitted from the intersection point 208. The gun aperture 204 may block peripheral electrons of the primary electron beam 210 to reduce the size of the detection spots 270, 272, and 274.

[0040] The source conversion unit 212 may include an imaging element array ( Figure 2A ) and the beam-limiting aperture array ( Figure 2A 216 and 218). An example of the source conversion unit 212 can be found in U.S. Patent No. 9,691,586, U.S. Publication No. 2017 / 0025243, and International Publication No. WO / 2018122176, the entire contents of which are incorporated herein by reference. The imaging element array may include a microdeflector or a microlens array. The imaging element array may form multiple parallel images (virtual images or real images) of the intersection 208 together with the multiple sub-beams 214, 216, and 218 of the primary electron beam 210. The beam limiting aperture array may limit the multiple sub-beams 214, 216, and 218.

[0041] The converging lens 206 can focus the primary electron beam 210. By adjusting the focal length of the converging lens 206 or by changing the radial size of the corresponding beam-limiting apertures in the beam-limiting aperture array, the current of the sub-beams 214, 216 and 218 downstream of the source conversion unit 212 may change. The converging lens 206 can be an adjustable converging lens, which can be configured so that the position of its first principal plane is movable. The adjustable converging lens can be configured to have magnetism, which may cause the off-axis sub-beams 216 and 218 to land on the sub-beam limiting aperture at a rotation angle. The rotation angle changes with the focal length and position of the first principal plane of the adjustable converging lens. In some embodiments, the adjustable converging lens can be an adjustable anti-rotation converging lens, which includes an anti-rotation lens having a movable first principal plane. Examples of adjustable converging lenses are further described in U.S. Publication No. 2017 / 0025241, the entire contents of which are incorporated herein by reference.

[0042] Objective lens 228 can focus beamlets 214, 216, and 218 onto wafer 230 for inspection, and can form a plurality of detection spots 270, 272, and 274 on the surface of wafer 230. Secondary electron beamlets 236, 238, and 240 can be formed, which are emitted from wafer 230 and travel back toward beam splitter 222.

[0043] The beam splitter 222 can be a Wien filter type beam splitter that generates an electrostatic dipole field and a magnetic dipole field. In some embodiments, if the electrostatic dipole field and the magnetic dipole field are applied, the force applied by the electrostatic dipole field on the electrons of the sub-beams 214, 216, and 218 can be equal in magnitude and opposite in direction to the force applied by the magnetic dipole field on the electrons. Therefore, the sub-beams 214, 216, and 218 can pass straight through the beam splitter 222 at a zero deflection angle. However, the total dispersion of the sub-beams 214, 216, and 218 generated by the beam splitter 222 can also be non-zero. The beam splitter 222 can separate the secondary electron beams 236, 238, and 240 from the sub-beams 214, 216, and 218, and guide the secondary electron beams 236, 238, and 240 toward the secondary optical system 242.

[0044] The deflection scanning unit 226 can deflect the sub-beams 214, 216 and 218 so that the detection spots 270, 272 and 274 are scanned across the area on the surface of the wafer 230. In response to the sub-beams 214, 216 and 218 being incident at the detection spots 270, 272 and 274, secondary electron beams 236, 238 and 240 can be emitted from the wafer 230. The secondary electron beams 236, 238 and 240 can include electrons with energy distributions, including secondary electrons and backscattered electrons. The secondary optical system 242 can focus the secondary electron beams 236, 238 and 240 onto the detection sub-areas 246, 248 and 250 of the electron detection device 244. The detection sub-areas 246, 248 and 250 can be configured to detect the corresponding secondary electron beams 236, 238 and 240 and generate corresponding signals used to reconstruct an image of the surface of the wafer 230. Detection sub-regions 246, 248, and 250 may include separate detector packages, separate sensing elements, or separate regions of an array detector. In some embodiments, each detection sub-region may include a single sensing element.

[0045] Figure 2B 200B (also referred to herein as device 200B) may be an example of the electron beam tool 100. The electron beam tool 200B may be used with Figure 2AThe electron beam tool 200A is shown to be similar. However, unlike the apparatus 200A, the apparatus 200B may be a single beam tool that uses one primary electron beam to scan one location on the wafer at a time.

[0046] like Figure 2B As shown, the apparatus 200B includes a wafer holder 136 supported by a motorized stage 134 to hold a wafer 150 to be inspected. The electron beam tool 200B includes an electron emitter, which may include a cathode 103, an anode 121, and a gun aperture 122. The electron beam tool 200B also includes a beam limiting aperture 125, a converging lens 126, a cylindrical aperture 135, an objective lens assembly 132, and a detector 144. In some embodiments, the objective lens assembly 132 may be a modified SORIL lens, which includes a pole piece 132a, a control electrode 132b, a deflector 132c, and an excitation coil 132d. During detection or imaging, the electron beam 161 emitted from the tip of the cathode 103 may be accelerated by the voltage of the anode 121, pass through the gun aperture 122, the beam limiting aperture 125, the focusing lens 126, and be focused by the improved SORIL lens into a detection spot 170, and illuminate the surface of the wafer 150. The detection spot 170 may be scanned across the surface of the wafer 150 by a deflector (such as the deflector 132c or other deflectors in the SORIL lens). Secondary particles or scattered particles emitted from the wafer surface, such as secondary electrons or scattered primary electrons, may be collected by the detector 144 to determine the intensity of the beam so that an image of the region of interest on the wafer 150 may be reconstructed.

[0047] It should be appreciated that the electron beam tools 200A and 200B may include an image processing system 199, which includes an image acquisition device 120, a storage device 130, and a controller 109. The image acquisition device 120 may include one or more processors. For example, the image acquisition device 120 may include a computer, a server, a mainframe, a terminal, a personal computer, any type of mobile computing device, etc., or a combination thereof. The image acquisition device 120 may be connected to the detector 144 of the electron beam tool 200B through a medium such as an electrical conductor, an optical cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, radio, or a combination thereof. The image acquisition device 120 may receive a signal from the detector 144 and may construct an image. Thus, the image acquisition device 120 may acquire an image of the wafer 150. The image acquisition device 120 may also perform various post-processing functions, such as image averaging, generating contours, superimposing indicators on the acquired image, etc. The image acquisition device 120 may be configured to perform adjustments to the brightness and contrast of the acquired image, etc. The storage device 130 may be a storage medium such as a hard disk, a random access memory (RAM), a cloud storage device, other types of computer-readable memory, etc. The storage device 130 may be coupled to the image acquirer 120 and may be used to save the scanned raw image data as a raw image, as well as a post-processed image. The image acquirer 120 and the storage device 130 may be connected to the controller 109. In some embodiments, the image acquirer 120, the storage device 130, and the controller 109 may be integrated together as an electronic control unit.

[0048] In some embodiments, the image acquirer 120 may acquire one or more images of the sample based on the imaging signal received from the detector 144. The imaging signal may correspond to a scanning operation for performing charged particle imaging. The acquired image may be a single image including a plurality of imaging regions, which may include various features of the wafer 150. The single image may be stored in the storage device 130. Imaging may be performed on an imaging frame basis.

[0049] The convergence and illumination optics of an electron beam tool may include or be supplemented by an electromagnetic quadrupole electron lens. Figure 2B As described, the electron beam tool 200B may include a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses may be used to control the electron beam. For example, the first quadrupole lens 148 may be controlled to adjust the beam current, and the second quadrupole lens 158 may be controlled to adjust the beam spot size and beam shape.

[0050] In some embodiments of the present disclosure, a PIN detector may be used as an in-lens detector in a deceleration objective SEM column of an EBI system 10. The PIN detector may be placed between a cathode for generating an electron beam and the objective. The potential of the electron beam emitted from the cathode may be -BE keV (typically about -10 kV). The electrons of the electron beam may be instantly accelerated and travel through the column. The column may be at ground potential. Therefore, the electrons may travel with a kinetic energy of BE keV while passing through the opening 145 of the detector 144. Since the wafer surface potential may be set to (BE - LE) keV, the pole piece (such as Figure 2B Electrons in the pole piece 132a of the objective lens assembly 132 can be rapidly decelerated to a landing energy of LE keV.

[0051] Figure 2C An example of a charged particle beam device 200C according to some embodiments of the present disclosure is illustrated. The charged particle beam device 200C may be, for example Figure 2A Charged particle beam device 200A or Figure 2B Charged particle beam device 200B. The emitted electrons 171, including, for example, secondary electrons or backscattered electrons, are emitted from the wafer surface by the incidence of electrons of the primary electron beam 105. The deceleration electric field that can slow down the primary electrons as they approach the detection spot 170 can act as an accelerating electric field to accelerate the emitted electrons backward toward the surface of the PIN detector 144. For example, Figure 2C As shown, due to the interaction with the wafer 150 at the probe spot 170, emitted electrons 171 traveling backward toward the detector 144 can be generated. Electrons 171 emitted from the wafer surface traveling along the optical axis 105 can reach the surface of the detector 144 with a position distribution. The landing positions of the emitted electrons can be within a roughly circular area with a radius of, for example, several millimeters. The geometric spread of the landing positions of the emitted electrons may be caused by the electrons having different trajectories, which may depend on, for example, the initial kinetic energy and the emission angle of the electrons. Other factors may affect the geometric distribution or other characteristics of the landing positions. These factors are discussed below with respect to embodiments of the present disclosure.

[0052] Figure 2DAn example of a distribution of landing points of emitted electrons on the detector surface is illustrated. Electrons 171a can land at different points on the surface of detector 144, and typically, when there is no deflection field, most of the electrons can be gathered around the central portion of detector 144. As discussed above, the emitted electrons can include, for example, secondary electrons or backscattered electrons. In some embodiments, for example, the distribution can include between 60% and 85% secondary electrons and between 40% and 15% backscattered electrons. The landing point distribution can be offset depending on the emission position and the SEM deflection field (e.g., scanning field). Therefore, in some applications, if a specific field of view (FOV) of the SEM image is required, the required size of the in-lens PIN detector may be quite large. Typically, the diameter of the detector can be, for example, 10 mm or larger. In some embodiments, the diameter of the detector can be, for example, approximately 4 mm to 10 mm.

[0053] The detector 144 may be placed along the optical axis 105. The primary electron beam may be configured to travel along the optical axis 105. Thus, the detector 144 may include a hole 145 at its center so that the primary electron beam may pass through to reach the wafer 150. Figure 2B and Figure 2C An example of a detector 144 having an opening at its center is shown. However, some embodiments may use a detector that is placed off-axis relative to the optical axis along which the primary electron beam travels. For example, as in Figure 2A As in the example shown, a beam splitter 222 may be provided to direct the emitted electron beam toward an off-axis detector. The beam splitter 222 may be configured to steer the emitted electron beam toward the electron detection device 244 at an angle α, such as Figure 2A Therefore, in some embodiments of the present disclosure, a detector without a central opening may be provided.

[0054] Figure 2A Detector 244 or FIG. 2B to FIG. 2D The detector 144 may include a sensing element such as a diode or an element similar to a diode, which can convert incident energy into a measurable signal. For example, the sensing element in the detector may include a single photon avalanche diode (SPAD), an avalanche photodiode (APD), or a PIN diode. Throughout this disclosure, although the sensing element or other components may deviate from the ideal circuit behavior of electrical elements such as diodes, resistors, capacitors, etc., the sensing element may be represented as a diode. In an embodiment of the present disclosure, the detector in the charged particle beam system may include a pixelated array of multiple sensing elements. The sensing element may be configured for charged particle counting. The sensing element of the detector that can be used for charged particle counting is discussed in U.S. Publication No. 2019 / 0378682, the entire contents of which are incorporated herein by reference.

[0055] Figure 3A and Figure 3B An example structure of a pixelated electron counting detector (PECD) according to some embodiments of the present disclosure is shown. Figure 3A Detector 344a or Figure 3B A detector such as detector 344b is used as Figure 2A The detector 244 shown or FIG. 2B to FIG. 2D The detector 144 is shown. Figure 3A , detector 344a includes a sensor layer 301 and a signal processing layer 302. Sensor layer 301 may include a sensor die consisting of a plurality of sensing elements including sensing elements 311, 312, 313, and 314. In some embodiments, the plurality of sensing elements may be provided in an array of sensing elements, each of which may have a uniform size, shape, and arrangement.

[0056] Signal processing layer 302 may include a plurality of signal processing circuits including circuits 321, 322, 323, and 324. The circuits may include interconnects (e.g., wiring paths) configured to communicatively couple sensing elements. Each sensing element of sensor layer 301 may have a corresponding signal processing circuit in signal processing layer 302. The sensing elements and their corresponding circuits may be configured to operate independently. Figure 3A As shown, circuits 321 , 322 , 323 , and 324 may be configured to be communicatively coupled to outputs of sensing elements 311 , 312 , 313 , and 314 , respectively, as indicated by four dashed lines between sensor layer 301 and signal processing layer 302 .

[0057] In some embodiments, the signal processing layer 302 can be configured as a single tube core on which multiple circuits are provided. The sensor layer 301 and the signal processing layer 302 can be in direct contact. In some embodiments, the components and functions of different layers can be combined or omitted. For example, the signal processing layer 302 can be combined with the sensor layer 301 into a single layer. In addition, the circuit for counting charged particles can be integrated at various points in the detector, for example, in a separate readout layer of the detector or on a separate chip. Other details of the electronic counting circuit system and alternative structures for the sensor layer 301 and the signal processing layer 302 can be found in the international publication WO2022 / 008518, the entire contents of which are incorporated herein by reference.

[0058] like Figure 3B As shown, a detector 344b having an array of sensing elements 311 may be provided. The detector 344b may be, for example, a photoelectrochemical detector (PECD). Figure 3AAs shown, the detector 344b may include a sensor layer 301 and a signal processing layer 302. The detector circuit system may include an electron counting circuit provided separately for each sensing element. The detector 344b may include a board 351, wherein a plurality of sensing elements 311 are formed on the board 351. The board 351 may include an opening 345 for allowing the primary electron beam to pass through the board 351.

[0059] When the individual sensing elements 311 of the detector become smaller than the geometric diffusion of the emitted electrons incident on the detector, individual electron counting can be achieved. For example, each sensing element can have its own counting unit, which includes a circuit system configured to measure the output signal from the sensing element. When the sensing element is made smaller, the rate at which electrons reach each sensing element is reduced, so the electronic counting at each sensing element can be enabled. In addition, the capacitance of the detector can be proportional to the area of ​​the detector surface. Some noise sources such as noise sources caused by components coupled to the detector (e.g., amplifier) ​​may be related to capacitance. The small area of ​​each individual element in the photoelectrochemical detector allows a much lower capacitance than, for example, a large continuous sensing surface. For example, the individual sensing element can be a square or other shape with a side length of, for example, 5 μm, 10 μm, 25 μm, 50 μm, 100 μm, 200 μm or 300 μm. The sensing element can be larger, for example, millimeter level. A typical detector may include, for example, 100, 500, 1000, 5000, 10000, 50000, or 100000 or more sensing elements.

[0060] By way of example, Figure 4 is a schematic diagram illustrating an example charged particle detector 400 with readout electronics 402 according to some embodiments of the present disclosure. In some embodiments, the detector 400 may be used to Figure 3A Detector 344a or Figure 3B In some embodiments, the detector 400 may be used as Figure 2A The electron detection device 244 in the electron beam tool 200A. In some embodiments, the detector 400 can be used as Figure 2B In some embodiments, the readout electronics 402 may include a combination of Figure 3A The signal processing layer 302 is shown and described.

[0061] like Figure 4 As shown, the detector 400 may have a surface 406 that may receive a secondary charged particle beam (formed by Figure 4A plurality of sensing elements (indicated by the thick solid lines on the top of surface 406) may be formed on surface 406 for receiving and facilitating detection of the secondary charged particle beam. Below the sensing elements, detector 400 may also include a switch matrix ( Figure 4 In some embodiments, the switches in the switch matrix may be implemented using transistors (eg, NMOS, PMOS). The readout electronics 402 may be implemented via a plurality of junctions 408 (formed by Figure 4 400. In some embodiments, the junction portion 408 may include interconnects (eg, wiring paths) between the sensing element and the signal processing circuitry, such as a junction portion 408. Figure 3A The interconnection described.

[0062] The output signal of the readout electronics 402 can also be output to a computer or processor ( Figure 4 (not shown) for further signal processing. Figure 4 As shown, the readout electronics 402 can be located on a base 404. For example, the base 404 can be a base 404 such as a base 404. Figure 3B Plate 351 as shown and described.

[0063] By way of example, Figure 5 is a schematic diagram illustrating an example simulation of a transistor with shallow trench isolation in a charged particle detector according to some embodiments of the present disclosure. For example, the detector 500 may be Figure 4 Implementation of detector 400. Detector 500 may include a plurality of complementary metal oxide semiconductor (CMOS) transistors, the plurality of CMOS transistors including NMOS transistor 502 (e.g., N-type metal oxide semiconductor) and PMOS transistor 504 (e.g., P-type metal oxide semiconductor). In order to electrically isolate N-type transistor 502 and P-type transistor 504, a plurality of trenches are generated between NMOS transistor 502 and PMOS transistor 504 using shallow trench isolation (STI) technology, the plurality of trenches including STI trenches 506, 508, and 510. STI trenches 506, 508, and 510 may be formed using dielectric materials such as, but not limited to, silicon dioxide, silicon nitride, silicon oxynitride, and other suitable dielectric materials. For example, STI trenches 506, 508, and 510 may be formed by depositing or forming a silicon dioxide layer (SiO2) layer having a thickness of 10 nm or more, or a thickness of 50 nm or more, or a thickness of 100 nm or more, or a thickness of 500 nm or more, or other suitable thicknesses.

[0064] like Figure 5As shown, NMOS transistor 502 is formed in a P-type well (“P-well”) 512, and PMOS transistor 504 is formed in an N-type well (“N-well”) 514. NMOS transistor 502, PMOS transistor 504, STI trenches 506, 508, and 510, P-well 512, and N-well 514 may all be formed inside an implant layer 516 (e.g., an N-type implant layer). Implant layer 516 may be in direct contact with substrate layer 518 (e.g., a silicon layer). In some embodiments, substrate layer 518 may be a layer having, for example, 10 13 Atom / cm 3 or lower low doping concentration high resistivity substrate, and can utilize 10 13 Atom / cm 3 The implantation layer 516 may be doped with a doping concentration of 100 Å or higher. Both the implantation layer 516 and the substrate layer 518 may be inside the detector 500, wherein the substrate layer 518 may extend to the surface of the detector 500 (eg, Figure 4 Surface 406 is shown).

[0065] like Figure 5 As shown, the detector 500 may receive a secondary charged particle beam (by Figure 5 The sensing element of the detector 500 ( Figure 5 The secondary charged particle beam (not shown) can facilitate detection of the secondary charged particle beam, and the secondary charged particles of the secondary charged particle beam can enter the substrate layer 518 (e.g., in an upward direction) and generate charge carrier pairs (e.g., electron-hole pairs). The charge carrier pairs can be biased by an external electric field, and carriers with the same charge type (e.g., negative charge type) can move toward the injection layer 516. The circuit formed by multiple NMOS and PMOS transistors can also collect the charge carriers, amplify the charge carrier pairs, convert the charge carriers into detection signals, and also output the detection signals to the corresponding binding parts (e.g., Figure 4 The binding portion may also route the detection signal to a readout electronic device (e.g., Figure 4 During this process, an internal electric field may be formed inside the detector. Figure 5 As illustrated, potential balance lines 520 represent equipotential lines of the internal electric field within detector 500 .

[0066] By turning on or off (eg, by switching the transistor gate) at least one of the NMOS transistor 502 or the PMOS transistor 504, the transistor 504 may be turned on or off. Figure 5If the transistor is turned off, then by design, the transistor will not output any detection signal to its corresponding binding portion. By doing so, the sensing element corresponding to the transistor can be disabled (e.g., Figure 3A Any of the illustrated sensing elements 311, 312, 313, or 314), and areas of detector 500 corresponding to the sensing elements (eg, referred to as "pixels") may be deselected for charged particle detection.

[0067] However, it has been determined that STI isolation in detector 500 (eg, STI trenches 506, 508, and 510) may cause several technical challenges, some of which are Figure 5 For example, the dielectric constants of NMOS transistor 502, PMOS transistor 504, and STI trenches 506, 508, and 510 may be different. Figure 5 When an incoming secondary charged particle beam (e.g., accelerated electrons) in the substrate passes through the substrate, the charge carriers may be decelerated and induce bremsstrahlung (e.g., x-rays). This bremsstrahlung radiation can illuminate the STI trenches 506, 508, and 510 and generate fixed positive charges in the STI trenches. For example, if the charge carriers are electrons, the bremsstrahlung radiation can generate positive charges near the regions of the STI trenches 506, 508, and 510. This positive charge can form Figure 5 The charge accumulations illustrated as 540, 542 and 544 in FIG. 5 are referred to as "fixed charges".

[0068] Fixed charges 540, 542, and 544 may interfere with the function of detector 500 in several ways. For example, fixed charges 540 and 542 may increase the conductivity of the area of ​​NMOS transistor 502 near one or more STI trenches (e.g., STI trenches 506 or 508). If NMOS transistor 502 is turned off by turning off its gate, the charge may still remain moving in NMOS transistor 502. In fact, NMOS transistor 502 may not be completely turned off due to fixed charges 540 and 542. In this case, the pixel corresponding to NMOS transistor 502 cannot be deselected, and the pixel can continue to generate a detection signal even when no secondary charged particle beam lands on it. This interference may eventually cause the resulting inspection image to appear undesirable blur.

[0069] As another example, even when NMOS transistor 502 is turned on, fixed charges 540 and 542 may interfere with the function of detector 500. If detector 500 is running for a long time, NMOS transistor 502 may be switched many times between the "on" state and the "off" state. When the pixel corresponding to NMOS transistor 502 is selected, the first secondary charged particle beam may land on the pixel and add the charge to the fixed charges 540 and 542. Thereafter, when the second secondary charged particle beam lands on the pixel, fixed charges 540 and 542 may not have been exhausted. This fixed charge can be superimposed with the charge carriers caused by the second secondary charged particle beam and distort its detection signal (e.g., by increasing or decreasing its amplitude or charge particle count). This distortion is a form of inter-symbol interference, which in turn may cause the resulting inspection image to appear undesirable blur.

[0070] In another example, it has been recognized that fixed charge 544 may reduce the conductivity of a region of PMOS transistor 504 near one or more STI trenches (eg, STI trenches 508 or 510 ). This reduction in conductivity may increase the isolation of PMOS transistor 504 .

[0071] In another example, it has been recognized that the STI isolation in the detector 500 may affect the implantation of the implant layer 516 during the manufacturing process of the detector 500. Typically, the STI isolation is implemented after forming the CMOS transistor and before doping the implant layer 516. However, due to the non-uniform morphology (e.g., Figure 5 As shown, in which NMOS transistor 502, PMOS transistor 504, and STI trenches 506, 508, and 510 are not coplanar), mechanical stress may be formed near the STI trenches. Such mechanical stress may affect the mobility of charge carriers (e.g., dopants). In addition, because the STI trenches can be formed of a dielectric material, it may be more difficult for charge carriers to penetrate the STI trenches. The mechanical stress and dielectric properties of the STI trenches may cause a shielding effect, which may reduce the implantation dose in the area near the STI trenches. The reduced implantation dose may then result in non-uniform doping of the implantation layer 516. As an example, such non-uniformity of the doping profile may be caused by Figure 5 The non-uniform doping of the implant layer 516 may also affect the function and performance of the detector 500.

[0072] To alleviate one or more of the identified challenges, a substrate for a charged particle detector is disclosed herein. Figure 6 , Figure 6A schematic diagram of an exemplary charged particle detector 600 according to some embodiments of the present disclosure is illustrated, the exemplary charged particle detector 600 having a substrate including a substantially topologically free surface. In the context of the present disclosure, a "substantially topologically free" surface of a substrate refers to a surface that is substantially planar or substantially free of protrusions or depressions caused by depositing on the substrate, creating grooves in the substrate, or oxidizing the substrate, or any other manufacturing step that may produce penetration differences for implantation during the manufacture of the detector. After the implantation process, processing steps such as, but not limited to, depositing silicon or other materials, oxidizing the substrate, or etching to create grooves may be performed. In some embodiments, the substantially topologically free surface may include protrusions having a maximum height of 5 nm or less, 4 nm or less, 3 nm or less, 2 nm or less, 1 nm or less, or 0.5 nm or less, and depressions having a maximum depth of 5 nm or less, 4 nm or less, 3 nm or less, 2 nm or less, 1 nm or less, or 0.5 nm or less.

[0073] The detector 600 may include a substrate layer 618 having a first surface 614 and a second surface 616. In the context of the present disclosure, the "first surface" or "front surface" refers to the surface of the substrate upon which the incoming secondary charged particles are incident, and the "second surface" or "rear surface" refers to the surface of the substrate opposite the first surface. In some embodiments, the substrate layer 618 may be positioned such that the rear surface 616 may be located downstream of the front surface 614. As used in the context of the present disclosure, "downstream" refers to a portion of the substrate that is downstream of the front surface 614 along the secondary charged particle beam 640 (e.g., Figure 2A The substrate layer 618 may include a silicon substrate layer. The silicon substrate layer may be an intrinsic or lightly doped (e.g., doping concentration <10 13 Atom / cm 3 In some embodiments, the substrate layer 618 may include a semiconductor material including, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or other suitable substrate materials.

[0074] In some embodiments, the detector 600 may include charge sensing elements 611 and 613 formed on the first surface 614 of the substrate layer 618. In some embodiments, the charge sensing element may include a diode (e.g., a SPAD, an APD, or a PIN diode). By way of example, the charge sensing element 611 or 613 may be a combination of Figure 3A and Figure 3BThe sensing element 311 shown and described. In some embodiments, the disclosed substrate may include a plurality of charge sensing elements formed on the first surface 614. The plurality of charge sensing elements may form a sensor die, and the sensor die may also form a sensor layer (e.g., in combination with Figure 3A Sensor layer 301 as shown and described).

[0075] In some embodiments, the detector 600 may include a plurality of transistors 602, 608 formed on the second surface 616 of the substrate layer 618. The plurality of transistors may include at least one of an NMOS transistor or a PMOS transistor. In some embodiments, the plurality of transistors may include a CMOS (e.g., a combination of Figure 5 CMOS as shown and described above). Figure 6 As illustrated, one or more transistors 602 may be formed within the substrate layer 618 such that a top surface of the transistor 602 is coplanar with the second surface 616. In some embodiments, the substrate layer 618 may include a plurality of doped regions 624. One or more transistors 602 may be formed within the doped regions 624 such that a top surface of the transistor 602 may be coplanar with a top surface of the doped regions 624 and the second surface 616 of the substrate layer 618.

[0076] In some embodiments, transistor 602 may be an NMOS transistor, and doped region 624 may be a p-well region doped with p-type dopants such as, but not limited to, boron, gallium, and other dopants. In some embodiments, transistor 608 may be a CMOS transistor formed inside doped region 624, including a combination of an NMOS transistor and a PMOS transistor.

[0077] According to some embodiments of the present disclosure, the doped region 624 may provide a conductive isolation well formed on the second surface 616 inside the substrate layer 618. For example, the conductive isolation well implemented by the p-well may be configured to electrically isolate transistors (e.g., NMOS transistors) among the plurality of transistors. In some embodiments, the conductive isolation well (e.g., the doped region 624) may form one or more PN junctions with the NMOS transistor.

[0078] By way of example, a conductive isolation well can be formed using junction isolation technology without any STI isolation. As used herein, a conductive isolation well refers to an isolation well formed by a conductive material such as a doped semiconductor or a non-intrinsic semiconductor. In some embodiments, for a transistor formed on the second surface 616 of the substrate layer 618, an impurity or dopant can be injected into the surrounding area of ​​the transistor to form a PN junction. The formed PN junction can provide a conductor. When the formed PN junction is reverse biased (e.g., by a bias voltage), an isolation well can be formed around the transistor, and the transistor can be electrically isolated by the formed isolation well. Different from the isolation well formed by the STI trench formed by a dielectric material (e.g., oxide or nitride), the isolation well formed by the biased PN junction can be made of a conductive material.

[0079] In some embodiments, one or more transistors 602 may be configured to activate charge sensing elements 611 and 613, deactivate charge sensing elements 611 and 613, control charge sensing elements 611 and 613, or communicate with charge sensing elements 611 and 613. In some embodiments, a single transistor may be configured to activate a corresponding charge sensing element, deactivate a corresponding charge sensing element, control a corresponding charge sensing element, or communicate with a corresponding charge sensing element. Alternatively or additionally, multiple transistors may activate a single charge sensing element, deactivate a single charge sensing element, or communicate with a single charge sensing element. In the context of the present disclosure, activating a charge sensing element refers to enabling a charge sensing element to detect charged particles by a switching function provided by a transistor. Deactivating a charge sensing element refers to disabling a charge sensing element from detecting charged particles incident on the charge sensing element by turning off a transistor.

[0080] It has been recognized that in the field of manufacturing semiconductor devices with shrinking geometries, junction isolation technology may not be the preferred isolation technology because of its large size and large footprint compared to STI technology. The formation of large doped regions or isolation wells in which one or more transistors are formed may be counterproductive to efforts to achieve high device density on IC chips with sub-100 nm technology nodes. However, it has been recognized that for charged particle detectors with dimensions of hundreds of microns (e.g., 100 microns, 200 microns, 300 microns, etc.) and low circuit system complexity, junction isolation technology may not incur area penalties and may be desirable.

[0081] Compared with existing STI isolation technology, the disclosed substrate can have several advantages. As described in the exemplary embodiments of the present disclosure, because the top surface of multiple transistors is coplanar with the surface between the transistors, unlike the detector in which STI isolation is applied, the disclosed substrate can have a flat topology on its surface, and thus can cause less mechanical stress in the area near the multiple transistors. In this case, the mobility of the charge carriers is less likely to be affected by such mechanical stress, and the potential within the substrate layer can have a flat profile. Ultimately, the possibility of fixed charge formation can be greatly reduced or eliminated. By reducing or eliminating fixed charges, inter-symbol interference in the detector can be greatly suppressed, and the clarity of the resulting inspection image can be greatly improved.

[0082] In some embodiments, forming a conductive isolation well using junction isolation technology may reduce the occurrence of bremsstrahlung when charged particles pass through it, which may reduce the formation of fixed charges (e.g., Figure 5 In addition, due to the conductive material of the isolation well, charge carriers may easily penetrate the conductive isolation well of the disclosed substrate compared to the dielectric material in STI isolation, and thus reduce or eliminate the shielding effect. Reducing or eliminating the shielding effect may help to form the injection layer of the detector (e.g., Figure 5 A uniform doping profile of the implanted layer 516) can be achieved, which can further improve the functionality and performance of the detector.

[0083] According to some embodiments of the present disclosure, the disclosed substrate may be used in a charged particle detector (e.g., Figure 2A The electron detection device 244 in the electron beam tool 200A or Figure 2B According to some embodiments of the present disclosure, the disclosed substrate may be used for a charged particle detector, which may further be used for an image inspection device (e.g., Figure 2A Electron beam tool 200A or Figure 2B Electron beam tool 200B).

[0084] According to some embodiments of the present disclosure, a method for manufacturing a substrate for a charged particle detector is disclosed. As an example, Figure 7 is a flow chart illustrating an exemplary method 700 for fabricating a substrate for a charged particle beam detector in a charged particle beam apparatus.

[0085] At step 702, a first surface (eg, Figure 6 A sensing element (eg, a combination of Figure 3AThe sensing element 311 or Figure 6 In some embodiments, the sensing element may include a diode (eg, a SPAD, an APD, or a PIN diode). The substrate layer may include a first surface and a second surface (eg, Figure 6 The first surface may be configured to receive secondary charged particles originating from the sample. The second surface may be opposite to the first surface. In some embodiments, the substrate layer may include a silicon layer (e.g., a silicon layer in combination with Figure 5 The substrate layer 518 is shown and described.

[0086] At step 704, a plurality of transistors may be formed on the second surface of the substrate layer. The plurality of transistors may include at least one of an NMOS transistor or a PMOS transistor. In some embodiments, the plurality of transistors may include a CMOS (e.g., a combination of Figure 5 One or more transistors (e.g., Figure 6 The transistor 602 is formed such that the top surface of the transistor is coplanar with the second surface. In some embodiments, the substrate layer may include a plurality of doped regions (e.g., Figure 6 One or more transistors may be formed inside the doped region such that a top surface of the transistor may be coplanar with a top surface of the doped region and the second surface of the substrate layer.

[0087] In some embodiments, the plurality of transistors may include a plurality of N-type transistors. In some embodiments, the plurality of N-type transistors may include a plurality of N metal oxide semiconductor (NMOS) transistors. In some embodiments, when the plurality of transistors include a plurality of N-type transistors, the method 700 may further include the following steps: forming a p-type doped region (e.g., in combination with a second surface of the substrate layer) on the second surface of the substrate layer; Figure 5 The p-well 512 or Figure 6 doped region 624).

[0088] The embodiments may also be described using the following terms.

[0089] 1. A substrate for a charged particle detector, the substrate comprising:

[0090] a charge sensing element formed on the first surface of the substrate and configured to detect charged particles originating from the sample; and

[0091] A plurality of transistors are formed in a first region of a second surface of the substrate, the second surface being opposite to the first surface,

[0092] A top surface of each of the plurality of transistors is coplanar with a top surface of the first region and the second surface of the substrate.

[0093] 2. The substrate of clause 1, wherein the charge sensing element comprises a diode, a photodiode, a single photon avalanche diode, or an avalanche photodiode.

[0094] 3. The substrate according to any one of clauses 1 and 2, wherein the plurality of transistors comprises a plurality of n-type metal oxide semiconductor (NMOS) transistors or a plurality of p-type metal oxide semiconductor (PMOS) transistors.

[0095] 4. The substrate according to any one of clauses 1 and 3, wherein the first region comprises a p-type well formed inside the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate.

[0096] 5. The substrate of any one of clauses 1 and 4, wherein the first region comprises a conductive isolation well formed inside the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate.

[0097] 6. The substrate of clause 5, wherein the conductive isolation well forms a pn junction with a transistor of the plurality of transistors.

[0098] 7. A substrate according to any of clauses 1 to 6, wherein the second surface is located downstream of the first surface relative to the path of the charged particles.

[0099] 8. A substrate according to any of clauses 1 to 7, wherein the second surface comprises a substantially topologically free surface.

[0100] 9. The substrate of any of clauses 1 to 8, wherein transistors of the plurality of transistors are isolated from each other by junction isolation.

[0101] 10. The substrate of clause 9, wherein transistors of the plurality of transistors are isolated from each other without dielectric or shallow trench isolation (STI).

[0102] 11. A charged particle detector comprising:

[0103] A substrate layer comprising a first surface and a second surface, wherein the second surface is opposite to the first surface;

[0104] a charge sensing element formed on the first surface and configured to detect charged particles originating from the sample; and

[0105] A plurality of transistors are formed in a first region of the second surface of the substrate layer,

[0106] A top surface of each of the plurality of transistors is coplanar with a top surface of the first region and the second surface of the substrate layer.

[0107] 12. A charged particle detector according to clause 11, wherein the charge sensing element comprises a diode, a photodiode, a single photon avalanche diode or an avalanche photodiode.

[0108] 13. A charged particle detector according to any one of clauses 11 and 12, wherein the plurality of transistors comprises a plurality of n-type metal oxide semiconductor (NMOS) transistors or a plurality of p-type metal oxide semiconductor (PMOS) transistors.

[0109] 14. A charged particle detector according to any one of clauses 11 to 13, wherein the first region comprises a p-type well formed inside the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate layer.

[0110] 15. A charged particle detector according to any one of clauses 11 to 14, wherein the first region comprises a conductive isolation well formed inside the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate layer.

[0111] 16. The charged particle detector of clause 15, wherein the conductive isolation well forms a pn junction with a transistor of the plurality of transistors.

[0112] 17. A charged particle detector according to any of clauses 11 to 16, wherein the second surface is located downstream of the first surface relative to the path of the charged particles.

[0113] 18. A charged particle detector according to any of clauses 11 to 17, wherein the second surface comprises a substantially topologically free surface.

[0114] 19. A charged particle detector according to any of clauses 11 to 18, wherein transistors of the plurality of transistors are isolated from each other by junction isolation.

[0115] 20. The charged particle detector of clause 19, wherein transistors of the plurality of transistors are isolated from each other without dielectric or shallow trench isolation (STI).

[0116] 21. A charged particle beam device comprising:

[0117] a charged particle source configured to emit primary charged particles for incidence on the sample; and

[0118] a charged particle detector configured to detect secondary charged particles generated from the sample upon interaction with the primary charged particles, the charged particle detector comprising:

[0119] A substrate layer comprising a first surface and a second surface, wherein the second surface is opposite to the first surface;

[0120] a charge sensing element formed on the first surface and configured to detect charged particles originating from the sample; and

[0121] A plurality of transistors are formed in a first region of the second surface of the substrate layer,

[0122] A top surface of each of the plurality of transistors is coplanar with a top surface of the first region and the second surface of the substrate layer.

[0123] 22. A charged particle beam apparatus according to clause 21, wherein the charge sensing element comprises a diode, a photodiode, a single photon avalanche diode or an avalanche photodiode.

[0124] 23. A charged particle beam apparatus according to any of clauses 21 and 22, wherein the plurality of transistors comprises a plurality of n-type metal oxide semiconductor (NMOS) transistors or a plurality of p-type metal oxide semiconductor (PMOS) transistors.

[0125] 24. A charged particle beam apparatus according to any of clauses 21 and 23, wherein the first region comprises a p-type well formed inside the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate layer.

[0126] 25. A charged particle beam apparatus according to any of clauses 21 and 24, wherein the first region comprises a conductive isolation well formed inside the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate layer.

[0127] 26. The charged-particle beam apparatus of clause 21, wherein the conductive isolation well forms a pn junction with a transistor of the plurality of transistors.

[0128] 27. A charged particle beam device according to any of clauses 21 to 26, wherein the second surface is located downstream of the first surface with respect to the path of the charged particles.

[0129] 28. A charged particle beam apparatus according to any of clauses 21 to 27, wherein the second surface comprises a substantially topologically free surface.

[0130] 29. A charged particle beam device according to any of clauses 21 to 28, wherein transistors of the plurality of transistors are isolated from each other by junction isolation.

[0131] 30. The charged-particle beam apparatus of clause 29, wherein transistors of the plurality of transistors are isolated from each other without dielectric or shallow trench isolation (STI).

[0132] 31. A method for manufacturing a substrate for a charged particle detector, the method comprising:

[0133] forming a charge sensing element on a first surface of the substrate, the charge sensing element being configured to detect charged particles originating from a sample;

[0134] forming a plurality of transistors in a first region of a second surface of the substrate, the second surface being opposite to the first surface,

[0135] A top surface of each of the plurality of transistors is coplanar with a top surface of the first region and the second surface of the substrate.

[0136] 32. The method of clause 31, wherein the substrate comprises a silicon layer.

[0137] 33. The method of any of clauses 31 and 32, wherein forming the charge sensing element comprises forming a diode, a photodiode, a single photon avalanche diode, or an avalanche photodiode.

[0138] 34. The method of any of clauses 31 to 33, wherein forming the plurality of transistors comprises forming a plurality of n-type metal oxide semiconductor (NMOS) transistors or a plurality of p-type metal oxide semiconductor (PMOS) transistors.

[0139] 35. The method of any one of clauses 31 to 34, further comprising: forming the first region inside the substrate such that a top surface of the first region is coplanar with the second surface of the substrate.

[0140] 36. The method of clause 35, wherein forming the first region comprises doping the first region with a p-type dopant to form a p-type well.

[0141] 37. The method of clause 36, wherein forming the first region comprises forming a conductive isolation well within the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate.

[0142] 38. The method of clause 37, wherein the conductive isolation well forms a pn junction with a transistor of the plurality of transistors.

[0143] 39. The method of any of clauses 31 to 38, further comprising: forming the second surface to be substantially free of topological structures.

[0144] 40. The method of any of clauses 31 to 39, further comprising forming junction isolation to isolate transistors in the plurality of transistors from each other by the junction isolation.

[0145] 41. The method of clause 40, further comprising isolating transistors of the plurality of transistors by forming the isolation without a dielectric or shallow trench isolation (STI).

[0146] The block diagram in the figure illustrates the architecture, function and operation of the possible implementation of the system, method and computer hardware or software product according to various example embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, section or part of the code, and the module, section or part includes one or more executable instructions for implementing a specified logical function. It should be understood that in some alternative implementations, the functions indicated in the box may not occur in the order shown in the figure. For example, depending on the function involved, two boxes shown in succession can be executed or implemented substantially simultaneously, or sometimes two boxes can be executed in reverse order. Some boxes can also be omitted. It should also be understood that each box of the block diagram and the combination of boxes can be implemented by a system based on special-purpose hardware that performs a specified function or action or by a combination of special-purpose hardware and computer instructions.

[0147] It should be appreciated that the embodiments of the present disclosure are not limited to the exact constructions that have been described above and illustrated in the drawings, and that various modifications and changes may be made without departing from the scope of the present disclosure.

Claims

1. A substrate for a charged particle detector, the substrate comprising: a charge sensing element formed on the first surface of the substrate and configured to detect charged particles originating from the sample; as well as A plurality of transistors are formed in a first region of a second surface of the substrate, the second surface being opposite to the first surface, A top surface of each of the plurality of transistors is coplanar with a top surface of the first region and the second surface of the substrate. 2 . The substrate of claim 1 , wherein the charge sensing element comprises a diode, a photodiode, a single photon avalanche diode, or an avalanche photodiode. 3 . The substrate according to claim 1 , wherein the plurality of transistors comprises a plurality of n-type metal oxide semiconductor (NMOS) transistors or a plurality of p-type metal oxide semiconductor (PMOS) transistors. 4 . The substrate of claim 1 , wherein the first region comprises a p-type well formed inside the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate layer. 5 . The substrate of claim 1 , wherein the first region comprises a conductive isolation well formed inside the substrate such that a top surface of the p-type well is coplanar with the second surface of the substrate. 6 . The substrate of claim 5 , wherein the conductive isolation well forms a pn junction with a transistor of the plurality of transistors.

7. The substrate of claim 1, wherein the second surface is located downstream of the first surface relative to a path of the charged particles.

8. The substrate of claim 1, wherein the second surface comprises a substantially topology-free surface. 9 . The substrate of claim 1 , wherein transistors in the plurality of transistors are isolated from each other by junction isolation. 10 . The substrate of claim 9 , wherein transistors of the plurality of transistors are isolated from each other without dielectric material or shallow trench isolation (STI).

11. A charged particle beam device, comprising: a charged particle source configured to emit primary charged particles for incidence on the sample; as well as a charged particle detector configured to detect secondary charged particles generated from the sample upon interaction with the primary charged particles, the charged particle detector comprising: A substrate layer comprising a first surface and a second surface, wherein the second surface is opposite to the first surface; a charge sensing element formed on the first surface and configured to detect charged particles originating from the sample; and A plurality of transistors are formed in a first region of the second surface of the substrate layer, wherein a top surface of each of the plurality of transistors is coplanar with a top surface of the first region and the second surface of the substrate layer. 12 . The apparatus of claim 11 , wherein the first region comprises a conductive isolation well formed inside the substrate layer such that a top surface of the p-type well is coplanar with the second surface of the substrate layer.

13. The apparatus of claim 11 , wherein transistors of the plurality of transistors are isolated by junction isolation, and wherein the isolation by the junction isolation comprises: Isolation of transistors without dielectric material or shallow trench isolation (STI).

14. The device of claim 11, wherein the second surface comprises a substantially topologically free surface.

15. A method for manufacturing a substrate for a charged particle detector, the method comprising: forming a charge sensing element on a first surface of the substrate, the charge sensing element being configured to detect charged particles originating from a sample; forming a plurality of transistors in a first region of a second surface of the substrate, the second surface being opposite to the first surface, A top surface of each of the plurality of transistors is coplanar with a top surface of the first region and the second surface of the substrate.

Images