Analog IP associated digital circuit testing method, electronic device and medium

Abstract

The present invention relates to the field of chip testing technology, and in particular to a method, electronic device and medium for testing analog IP-related digital circuits. The method comprises: step S1, obtaining interfaces {A1, A2, .., A1, A2, .., A2, A1, A2 ... m ,...,A M}; Step S2: Check each A based on the preset check item list m , if A m Any item in the preset inspection item list, A m From {A1,A2,..,A m ,...,A M}, and generate a set of simulated IP interfaces to be processed {B1, B2, ..., B n ,..,B N}; Step S3, for each B n Insert the corresponding bypass circuit; Step S4, test the analog IP-related digital circuit in the test mode based on the chip design after the bypass circuit is inserted. The present invention improves the coverage and accuracy of the analog IP-related digital circuit test.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a method for testing an analog IP-associated digital circuit, an electronic device and a medium. Background Art

[0002] Chip design includes digital IP (Intellectual Property) and analog IP. The digital circuits set around and connected to the analog IP are called analog IP-associated digital circuits. During chip testing, the analog IP-associated digital circuits need to be tested. In existing testing methods, the analog IP-associated digital circuits are bypassed by simply setting a bypass circuit, resulting in low test coverage of the analog IP-associated digital circuits. In addition, the existing testing methods do not fully consider the behavior of the analog IP during the test, resulting in poor test accuracy. Therefore, how to improve the coverage and accuracy of the analog IP-associated digital circuit test has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present invention aims to provide a method, electronic device and medium for testing analog IP-related digital circuits, thereby improving the coverage and accuracy of testing analog IP-related digital circuits.

[0004] According to a first aspect of the present invention, a method for testing an analog IP-associated digital circuit is provided, wherein the analog IP-associated digital circuit is a digital circuit arranged around an analog IP and connected to the analog IP, and the method comprises:

[0005] Step S1, obtain the interfaces {A1, A2, .., A m ,...,A M}, A m is the mth simulated IP interface, where the value of m ranges from 1 to M, and M is the total number of simulated IP interfaces in the chip design under test;

[0006] Step S2: Check each A based on the preset check item list. m , if A m Any item in the preset inspection item list, A m From {A1,A2,..,A m ,...,A M}, and generate a set of simulated IP interfaces to be processed {B1, B2, ..., B n ,..,B N},B n is the nth simulated IP interface to be processed, where n ranges from 1 to N, and N is the total number of simulated IP interfaces to be processed.n ,..,B N} is {A1,A2,..,A m ,...,A M}, the preset inspection item list includes a plurality of inspection items that do not require the insertion of a bypass circuit;

[0007] Step S3: for each B n Insert the corresponding bypass circuit so that in the test mode, the D2A signal is bypassed or the D2A signal corresponding to the B n Access preset value, B corresponding to each A2D signal n At least one test path is connected. The D2A signal is output from the digital IP to a B in the chip under test design. n The A2D signal is a signal from a B n Output signal to digital IP;

[0008] Step S4: testing the analog IP-related digital circuit in a test mode based on the chip design to be tested after the bypass circuit is inserted.

[0009] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the present invention provides an analog IP-related digital circuit testing method, electronic equipment and medium that can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0012] The present invention sets a preset check item list to check and exclude all interfaces of analog IP that do not need to be inserted with bypass circuits, and then inserts bypass circuits as needed for each interface of analog IP that needs to be inserted with bypass circuits, so that in the test mode, the D2A signal is bypassed or the B corresponding to the D2A signal is n Access preset value, B corresponding to each A2D signal n At least one test path is connected to improve the coverage and accuracy of the analog IP-related digital circuit test. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a method for testing an analog IP-associated digital circuit provided by an embodiment of the present invention.

[0015] Figure 2 A schematic diagram of bypass circuit configuration provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0017] In chip testing, the chip to be tested is designed to include analog IP, digital IP, and a circuit connecting the analog IP and the digital IP. An embodiment of the present invention provides a method for testing an analog IP-associated digital circuit. The analog IP-associated digital circuit is a digital circuit arranged around the analog IP and connected to the analog IP. The analog IP-associated digital circuit mainly includes a D2A circuit and an A2D circuit. The D2A circuit is a circuit for transmitting a D2A signal. The D2A signal is a signal transmitted from the digital IP to the analog IP, and is usually a signal for controlling the behavior of the analog IP. The A2D signal is a signal transmitted from the analog IP to the digital IP, and is usually a signal fed back from the analog IP to the digital IP.

[0018] like Figure 1 As shown, the method includes:

[0019] Step S1, obtain the interfaces {A1, A2, .., A m ,...,A M}, A m is the mth simulated IP interface, the value range of m is 1 to M, and M is the total number of simulated IP interfaces in the chip design to be tested.

[0020] Among them, the interface of the analog IP may be an interface for transmitting D2A signals, an interface for transmitting A2D signals, an interface for communication between analog IPs, or an interface for connecting power signals, etc. In the process of testing the analog IP-associated digital circuit, in order not to damage the analog IP and avoid malfunction of the analog IP, it is necessary to bypass the D2A signal or configure the behavior of the analog IP to assist in the test. For example, in the test mode, the interface of the analog IP corresponding to the D2A signal is connected to the preset value, and during the test, the output value of the A2D signal does not need to be paid attention to, but the connection on the transmission path of the A2D signal needs to be tested, and the transmission path of the D2A signal also needs to be tested.

[0021] Step S2: Check each A based on the preset check item list. m , if A m Any item in the preset inspection item list, A m From {A1,A2,..,A m ,...,A M}, and generate a set of simulated IP interfaces to be processed {B1, B2, ..., B n ,..,B N},B n is the nth simulated IP interface to be processed, where n ranges from 1 to N, and N is the total number of simulated IP interfaces to be processed. n ,..,B N} is {A1,A2,..,A m ,...,A M}, the preset inspection item list includes multiple inspection items that do not require the insertion of a bypass circuit.

[0022] It should be noted that before testing the analog IP-related digital circuit, it is necessary to accurately m Insert the corresponding bypass circuit, so it is necessary to change {A1, A2, .., A m ,...,A M} to accurately select the interface that needs to be inserted into the corresponding bypass circuit. Any omission or multiple selection may cause the test to fail. This application pre-sets a preset check item list, lists all the interface conditions of the analog IP that do not need to be inserted into the bypass circuit, and then checks the interfaces of the analog IP one by one based on the preset check item list, and removes the interfaces of the analog IP that do not need to be inserted into the bypass circuit from {A1, A2, .., A m ,...,A M}, and finally generate a set of interfaces of all analog IPs that need to be inserted into the bypass circuit. It can be understood that the analog IP interface to be processed is the interface of the analog IP that needs to be inserted into the bypass circuit.

[0023] Step S3: for each B n Insert the corresponding bypass circuit so that in the test mode, the D2A signal is bypassed or the D2A signal corresponding to the B n Access preset value, B corresponding to each A2D signal n At least one test path is connected. The D2A signal is output from the digital IP to a B in the chip under test design. n The A2D signal is a signal from a B n Output signal to digital IP.

[0024] It should be noted that, during the test of analog IP-related digital circuits, some D2A signals need to be bypassed, and some digital IP interfaces corresponding to D2A signals need to be connected to preset values. According to specific bypass requirements, corresponding bypass circuits are inserted. In addition, in order to improve the coverage rate during the test of analog IP-related digital circuits, the present invention will n Connect to at least one test path.

[0025] Step S4: testing the analog IP-related digital circuit in a test mode based on the chip design to be tested after the bypass circuit is inserted.

[0026] It should be noted that for each B n After inserting the corresponding bypass circuit, the test mode is turned on, and the analog IP-related digital circuit is tested in the test mode.

[0027] As an embodiment, according to the principle of not mixing analog and digital, a preset inspection item list is set, and the preset inspection item list includes the following inspection items:

[0028] Interface corresponding to the power signal of the analog IP.

[0029] Simulate the inout interface of IP. The inout interface is a bidirectional input and output interface.

[0030] IO interface assigned to the simulation IP.

[0031] The digital IO interface corresponds to the interface of multiple drivers connected to the analog pins.

[0032] The interface of the bypass circuit in the test mode is set inside the analog IP or digital IP.

[0033] It should be noted that the preset check item list includes all the interface types of analog IPs that do not require the insertion of bypass circuits. If a bypass circuit is inserted into the interface of the above-mentioned types of analog IPs, it may cause the failure of the analog IP-associated digital circuit test and may also cause waste of chip area and resources. By obtaining the analog IP interfaces that actually need to insert bypass circuits through the preset check item list, the accuracy of the analog IP-associated digital circuit test is improved and the waste of chip area and resources is avoided.

[0034] As an embodiment, the interface of the bypass circuit in the test mode set inside the analog IP or digital IP includes: using the test mode signal inside the analog IP or digital IP to set the bypass circuit in the test mode for the D2A signal, and the test mode signal includes a scan mode signal, an analog IP test mode signal, etc. Specifically, the scan mode enable signal and the D2A signal can be set to a value that meets the bypass circuit requirement in the test mode through an AND gate or the like. The interface of the bypass circuit in the test mode set inside the analog IP or digital IP also includes: setting the bypass circuit in the test mode for the reset signal inside the analog IP, and the reset signal includes a power-on reset and a global reset signal, etc. For the interface of the bypass circuit in the test mode set inside the analog IP or digital IP, if the bypass circuit is set repeatedly, it will lead to a waste of chip area and resources. The interface of the bypass circuit in the test mode set inside the analog IP or digital IP is also set as an inspection item in the preset inspection item list, which can avoid repeated setting of the bypass circuit and avoid waste of chip area and resources.

[0035] As an embodiment, step S3 includes:

[0036] Step S31: If B n The corresponding signal is D2A signal, and needs to be bypassed in test mode, then it is B n Insert the corresponding bypass circuit so that in test mode, B n The corresponding D2A signal is bypassed. In functional mode, B n The corresponding D2A signal is not bypassed.

[0037] As an embodiment, step S3 includes:

[0038] Step S32: If B n The corresponding signal is D2A signal, and it needs to be fixed to the preset value in test mode, then it is B n Insert the corresponding bypass circuit so that in test mode, B n The corresponding input value is always the preset value. In function mode, B n The corresponding D2A signal is not bypassed.

[0039] Specifically, B n is the enable signal of the analog IP, and the analog IP needs to work in the test mode. Therefore, the enable signal of the analog IP needs to be set to 1 in the test mode. The enable signal of the power analog IP is bypassed through an OR gate. One pin of the OR gate is connected to the bypass enable signal, and the other pin is connected to the corresponding output port on the digital IP. In the test mode, the bypass enable signal is set to 1, so that the enable signal of the analog IP needs to be always set to 1 in the test mode. In the functional mode, the bypass enable signal is set to 0. At this time, B n The corresponding signal is that the D2A signal is connected normally.

[0040] As an embodiment, step S3 includes:

[0041] Step S33: If B n The corresponding signal is a D2A signal, and different preset values ​​{C1, C2, ..., C i ,...,C I}, C i In the test mode, the i-th cycle needs to be set at B n The preset value of i ranges from 1 to I, where I is B n The total number of corresponding preset values ​​is B n Set I test registers, the i-th test register D i Storage C i During the test, I test registers form a scan chain. In the test mode, D i C i Input to B n middle.

[0042] Through step S33, it is possible to make B n According to C1,C2,...,C i ,...,C I The sequence settings correspond to the preset values.

[0043] As an embodiment, step S3 includes:

[0044] Step S34: construct a tree structure composed of XOR gates, wherein the tree structure includes X input pins and Y output pins, X=P+Q, P is the B of the corresponding signal D2A signal. n Quantity, Q is the corresponding signal for the A2D signal B n Quantity, the output pin is connected to the corresponding interface of A2D of the digital IP, Y≤Q.

[0045] It should be noted that the tree structure includes a plurality of XOR gates, and the plurality of XOR gates are hierarchically arranged. The specific number of XOR gates and the hierarchical arrangement method are determined according to the B of the D2A signal. n Number, A2D signal B n To determine the quantity.

[0046] Step S35: If B n The corresponding signal is A2D signal, then B n Insert the corresponding bypass circuit and switch B n The corresponding A2D signal is connected to the tree structure and can be connected to B n The corresponding signal is an input pin of the digital IP corresponding interface, so that in test mode, B n The corresponding A2D signal is connected to the XOR gate and then transmitted to the digital IP. In the functional mode, B n The corresponding signal is that the A2D signal is turned on.

[0047] It should be noted that, through the setting of step S35, each slave B n The corresponding A2D signal is connected to an input pin of the tree structure, so that in the test mode, it is transmitted to the digital IP after XOR logic, so that in the test mode, each B n The path where the corresponding A2D signal is located can be tested, thereby improving the test coverage.

[0048] Step S36: If B n The corresponding signal is D2A signal, then B n The corresponding signal is that the D2A signal is connected to an input pin of the tree structure, so that in the test mode, B n The corresponding D2A signal is XORed with the A2D signal or other D2A signal and then transmitted to the corresponding digital IP.

[0049] It should be noted that, through the setting of step S36, the path corresponding to each D2A signal is connected to an input pin of the tree structure, so that in the test mode, B n The corresponding D2A signal is XORed with the A2D signal or other D2A signal and then transmitted to the corresponding digital IP, so that in the test mode, each B n The path where the corresponding D2A signal is located can be tested, thereby improving the test coverage.

[0050] Figure 2 A bypass circuit setting is briefly shown. Figure 2The digital IP shown in the figure includes a first digital IP interface and a second digital IP interface, and the analog IP includes a first analog IP interface and a second analog IP interface. The first analog IP interface and the second analog IP interface are {B1, B2, ..., B n ,..,B N}interface. A path for transmitting a D2A signal is formed between the first digital IP interface and the first analog IP interface. The present application sets an OR gate between the first digital IP interface and the first analog IP interface. One input pin of the OR gate is connected to the first digital IP interface, and the other input pin is connected to the bypass enable signal. A path for an A2D signal is formed between the second analog IP interface and the second digital IP interface. The second analog IP interface is connected to the first input pin of the XOR gate. The D2A signal between the first digital IP interface and the first analog IP interface is XORed with the A2D signal, or other D2A signals, and then connected to the second input pin of the XOR gate. After being XORed with the A2D signal, the D2A signal is output to the first input pin of the selector. The second analog interface is connected to the second input pin of the selector. The selector is connected to the bypass enable signal. The output of the selector is connected to the second digital IP interface. When the bypass enable signal is set to 0, the second input pin of the selector is turned on. When the bypass enable signal is set to 1, the first input pin of the selector is turned on.

[0051] exist Figure 2 In the structure shown, in the functional mode, the bypass enable signal is set to 0, at which time the second input pin of the selector is connected, and the output of the OR gate is also completely controlled by the D2A signal. Therefore, in the functional mode, the D2A signal path between the first digital IP interface and the first analog IP interface and the A2D signal path between the second analog IP interface and the second digital IP interface are both normally connected.

[0052] exist Figure 2 In the structure shown, in the test mode, the bypass enable signal is set to 1, at which time the first input pin of the selector is connected, and the output result of the XOR gate is transmitted to the second analog IP interface, so that the connection of the second analog IP interface, the first digital IP interface, and the second digital IP interface are all covered in the test mode. In the test mode, the output of the OR gate is always 1, bypassing the D2A signal. It should be noted that Figure 2 This is just a simple example. There may be multiple paths for transmitting A2D signals and multiple paths for transmitting D2A signals in the first digital IP interface and the second digital IP interface. The corresponding bypass circuits can be specifically set according to the steps S31 to S36.

[0053] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0054] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0055] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0056] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A method for testing an analog IP-related digital circuit, characterized in that: The analog IP associated digital circuit is a digital circuit arranged around the analog IP and connected to the analog IP, and the method includes: Step S1, obtain the interfaces {A1, A2, .., A m ,...,A M }, A m is the mth simulated IP interface, where the value of m ranges from 1 to M, and M is the total number of simulated IP interfaces in the chip design under test; Step S2: Check each A based on the preset check item list. m , if A m Any item in the preset inspection item list, A m From {A1,A2,..,A m ,...,A M }, and generate a set of simulated IP interfaces to be processed {B1, B2, ..., B n ,..,B N },B n is the nth simulated IP interface to be processed, where n ranges from 1 to N, and N is the total number of simulated IP interfaces to be processed. n ,..,B N } is {A1,A2,..,A m ,...,A M }, the preset inspection item list includes a plurality of inspection items that do not require the insertion of a bypass circuit; Step S3: for each B n Insert the corresponding bypass circuit so that in the test mode, the D2A signal is bypassed or the D2A signal corresponding to the B n Access preset value, B corresponding to each A2D signal n At least one test path is connected. The D2A signal is output from the digital IP to a B in the chip under test design. n The A2D signal is a signal from a B n Output signal to digital IP; Step S4: testing the analog IP-related digital circuit in a test mode based on the chip design to be tested after the bypass circuit is inserted.

2. The method according to claim 1, characterized in that The preset inspection item list includes the following inspection items: The interface corresponding to the power signal of the analog IP; Simulate the IP inout interface; IO interface assigned to the simulation IP; The digital IO interface corresponds to the interface of multiple drivers connected to the analog pins; The interface of the bypass circuit in the test mode is set inside the analog IP or digital IP.

3. The method according to claim 2, characterized in that: The interfaces of the analog IP or digital IP that have been set up with bypass circuits in test mode include: Use the test mode signal inside the analog IP or digital IP to set the bypass circuit in the test mode for the D2A signal; A bypass circuit is set for the reset signal in the analog IP in the test mode.

4. The method according to claim 1, characterized in that: The step S3 comprises: Step S31: If B n The corresponding signal is D2A signal, and needs to be bypassed in test mode, then it is B n Insert the corresponding bypass circuit so that in test mode, B n The corresponding D2A signal is bypassed. In functional mode, B n The corresponding D2A signal is not bypassed.

5. The method according to claim 1, characterized in that: The step S3 comprises: Step S32: If B n The corresponding signal is a D2A signal, and in the test mode it needs to be fixed to the preset value, then it is B n Insert the corresponding bypass circuit so that in test mode, B n The corresponding input value is always the preset value. In function mode, B n The corresponding D2A signal is not bypassed.

6. The method according to claim 1, characterized in that: The step S3 comprises: Step S33: If B n The corresponding signal is a D2A signal, and different preset values ​​{C1, C2, ..., C i ,...,C I }, C i In the test mode, the i-th cycle needs to be set at B n The preset value of i ranges from 1 to I, where I is B n The corresponding total number of preset values ​​is B n Set I test registers, the i-th test register D i Storage C i During the test, I test registers form a scan chain. In the test mode, D i C i Input to B n middle.

7. The method according to claim 1, characterized in that: The step S3 comprises: Step S34: construct a tree structure composed of XOR gates, wherein the tree structure includes X input pins and Y output pins, X=P+Q, P is the B of the corresponding signal D2A signal. n Quantity, Q is the corresponding signal for the A2D signal B n Quantity, the output pin is connected to the interface corresponding to A2D of the digital IP, Y≤Q; Step S35: If B n The corresponding signal is A2D signal, then B n Insert the corresponding bypass circuit and switch B n The corresponding A2D signal is connected to the tree structure and can be connected to B n The corresponding signal is an input pin of the digital IP corresponding interface, so that in test mode, B n The corresponding A2D signal is connected to the XOR gate and then transmitted to the digital IP. In the functional mode, B n The corresponding signal is that the A2D signal is turned on; Step S36: B n The corresponding signal is that the D2A signal is connected to an input pin of the tree structure, so that in the test mode, B n The corresponding D2A signal is XORed with the A2D signal or other D2A signal and then transmitted to the corresponding digital IP.

8. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-7.

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