Asynchronous data transmission method and device, electronic equipment, storage medium and program product

Abstract

The invention discloses an asynchronous data transmission method and device, electronic equipment, a storage medium and a program product, and belongs to the technical field of electronics. The method comprises the steps that under the condition that a Slave end receives a write instruction, a first pointer is shifted, the first pointer is a pointer for writing data into an asynchronous FIFO at the Slave end and comprises N bits, the bit for performing (i + 1) th shift change on the first pointer is a bit adjacent to the left side of the bit for performing ith shift change on the first pointer, and the bit is a bit adjacent to the left side of the bit for performing ith shift change on the first pointer; n is an integer greater than 1, 1 < = i < = N; on the basis of the first pointer and a second pointer, whether the asynchronous FIFO is in a non-full state or not is determined, the second pointer is a pointer for reading data from the asynchronous FIFO by the Master end, and the first pointer and the second pointer are pointers synchronized across clock domains.

Description

Technical Field

[0001] The present application belongs to the field of electronic technology, and specifically relates to an asynchronous data transmission method, device, electronic equipment, storage medium and program product. Background Art

[0002] In order to improve the performance of electronic devices and reduce power consumption, subsystems within a multimedia system on a chip (SOC) are often in different clock domains to meet the specific performance and power consumption requirements of the subsystem.

[0003] When an electronic device performs image processing, the Image Signal Processor (ISP) subsystem usually needs to receive image data from the Mobile Industry Processor Interface (MIPI) subsystem or the Double Data Rate (DDR) subsystem on the camera module side. Since different subsystems are in different clock domains, data transmission between them needs to be implemented through an asynchronous bridge (such as a Vbus asynchronous bridge) to ensure correct data transmission. Asynchronous bridges are usually implemented using asynchronous First In First Out (FIFO). Asynchronous FIFO is a data buffering mechanism used for data transmission between different clock domains. It uses a pointer encoding method of Gray code or one-hot code to reduce data transmission errors at clock domain boundaries.

[0004] However, the encoding method of Gray code is to perform an XOR operation on each bit and the bit adjacent to its left side from the right side of the last encoding to the left side to obtain the value of each bit in the new Gray code. Since Gray code encoding requires operation on each bit, more decoding circuits are consumed. The characteristic of one-hot code is that only one bit is 1 and the rest are 0. Its encoding method is to shift the 1 in the last encoding to the left by one bit, that is, change the bit where 1 is located to 0 and change the bit adjacent to the left side of the bit where 1 is located to 1, and keep the rest as 0, so as to obtain a new one-hot code. Since only one bit is 1 in one-hot code, its encoding density is low and it needs to occupy more register bit width. Therefore, how to use less decoding circuits while occupying less bit width is a problem to be solved urgently. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide an asynchronous data transmission method, device, electronic device, storage medium and program product, which can use less decoding circuits to determine whether the asynchronous FIFO is in a non-full state or a non-empty state while the pointer occupies less bit width when data is transmitted through an asynchronous bridge, thereby improving the utilization of the bit width while saving the use of decoding circuits.

[0006] In a first aspect, an embodiment of the present application provides an asynchronous data transmission method, the method comprising: when a Slave end receives a write instruction, shifting a first pointer, the first pointer being a pointer for the Slave end to write data into an asynchronous FIFO, the first pointer comprising N bits, the bit that is shifted and changed for the i+1th time on the first pointer is the bit adjacent to the left of the bit that is shifted and changed for the i-th time on the first pointer, N is an integer greater than 1, 1≤i≤N; based on the first pointer and the second pointer, determining whether the asynchronous FIFO is in a non-full state, the second pointer being a pointer for the Master end to read data from the asynchronous FIFO, the above-mentioned first pointer and second pointer are pointers synchronized across clock domains.

[0007] In the second aspect, an embodiment of the present application provides an asynchronous data transmission device, which includes: an execution module and a determination module. The execution module is used to shift a first pointer when a write instruction is received on the Slave side. The first pointer is a pointer for the Slave side to write data into an asynchronous FIFO. The first pointer includes N bits. The bit that is shifted and changed for the i+1th time on the first pointer is the bit adjacent to the left of the bit that is shifted and changed for the i-th time on the first pointer. N is an integer greater than 1, and 1≤i≤N. The determination module is used to determine whether the asynchronous FIFO is in a non-full state based on the first pointer and the second pointer obtained by the execution module. The second pointer is a pointer for the Master side to read data from the asynchronous FIFO. The above-mentioned first pointer and second pointer are pointers synchronized across clock domains.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0009] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0010] In a fifth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the first aspect.

[0011] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method described in the first aspect.

[0012] In an embodiment of the present application, when the slave end receives a write instruction, the first pointer can be shifted, and then based on the first pointer and the second pointer, it can be determined whether the asynchronous FIFO is in a non-full state, the first pointer is a pointer for the slave end to write data into the asynchronous FIFO, and the second pointer is a pointer for the Master end to read data from the asynchronous FIFO. The first pointer includes N bits, wherein the bit that is shifted i+1 times to the first pointer is the bit adjacent to the left of the bit that is shifted i-th time to the first pointer. In this scheme, since the shift encoding method used when shifting the first pointer is that the bit changed each time is compared with the bit changed in the previous shift, the bit changed this time is the bit adjacent to the left of the bit changed in the previous shift, and the other bits remain unchanged, that is, the present application is by changing 1 bit, and relative to the previous shift, each shift only needs to change the bit adjacent to the left of the bit changed in the previous shift. Therefore, compared with the Gray code encoding method, the Gray code has a high encoding density, and the shift encoding method used in this application reduces the pointer encoding density, and compared with the one-hot code encoding method, the one-hot code occupies more bit width, and the shift encoding method used in this application reduces the pointer occupied bit width. In this way, the pointer encoding density of the present application is low, and the pointer occupies less bit width. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram of a traditional asynchronous bridge provided by the related art;

[0014] Figure 2 This is one of the flowcharts of the asynchronous data transmission method provided in the embodiment of the present application;

[0015] Figure 3 is a schematic diagram of the structure of an asynchronous bridge provided in an embodiment of the present application;

[0016] Figure 4 It is a schematic diagram of Gray code and one-hot code provided by the related art;

[0017] Figure 5 is a schematic diagram of shift coding provided in an embodiment of the present application;

[0018] Figure 6is a schematic diagram of the jump logic of the pointer provided in the embodiment of the present application;

[0019] Figure 7 This is the second flowchart of the asynchronous data transmission method provided in the embodiment of the present application;

[0020] Figure 8 It is a structural diagram of the Slave end provided in an embodiment of the present application;

[0021] Fig. 9 This is the third flowchart of the asynchronous data transmission method provided in the embodiment of the present application;

[0022] Fig.10 This is the fourth flowchart of the asynchronous data transmission method provided in the embodiment of the present application;

[0023] Fig.11 This is the fifth flowchart of the asynchronous data transmission method provided in the embodiment of the present application;

[0024] Fig.12 It is a schematic diagram of the structure of the Master end provided in the embodiment of the present application;

[0025] Fig.13 This is the sixth flowchart of the asynchronous data transmission method provided in the embodiment of the present application;

[0026] Fig.14 is a timing diagram of the asynchronous data transmission method provided in an embodiment of the present application;

[0027] Fig.15 It is one of the schematic diagrams of the asynchronous data transmission device provided in the embodiment of the present application;

[0028] Fig.16 This is the second schematic diagram of the asynchronous data transmission device provided in the embodiment of the present application;

[0029] Fig.17 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0030] Fig.18 It is a schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0032] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0033] The terms "at least one (item)", "at least one of" and the like in this application refer to any one, any two or a combination of more than two of the objects included therein. For example, at least one (item) of a, b, and c can be represented by: "a", "b", "c", "a and b", "a and c", "b and c" and "a, b and c", where a, b, and c can be single or multiple. Similarly, "at least two (items)" refers to two or more, and its meaning is similar to that of "at least one (item)".

[0034] The following, in conjunction with the accompanying drawings, describes in detail the asynchronous data transmission method, device, electronic device, storage medium and program product provided by the embodiments of the present application through specific embodiments and their application scenarios.

[0035] The embodiments of the present application can be applied to the scenario where image data is transmitted between subsystems in different clock domains in the SOC when the electronic device processes the image. Specifically, the SOC includes multiple subsystems, and in order to meet the performance and power consumption requirements of different subsystems, each subsystem is usually in a different clock domain. When the electronic device processes the image, it needs to be processed by the ISP subsystem, and the ISP subsystem usually needs to receive image data from the MIPI subsystem or DDR subsystem on the camera module side for processing. Since different subsystems are in different clock domains, the data transmission between different subsystems needs to be implemented through an asynchronous bridge to ensure the correct transmission of data. For example, image data can be transmitted through the vbus asynchronous bridge.

[0036] The structure of the traditional vbus asynchronous bridge is as follows Figure 1 As shown, where:

[0037] 1) s_vbus_rstn: The reset signal from the USB power line (vbus) on the slave side is used to indicate the state change of the vbus voltage, such as connection or disconnection, and to control the reset logic of the system according to these state changes.

[0038] 2)m_vbus_rstn: reset signal of vbus in Master end.

[0039] 3)s_vbus_clk: The clock signal of vubs in the Slave end, used to synchronize the operations in the Slave end.

[0040] 4) m_vbus_clk: The clock signal of vubs in the Master side, used to synchronize the operations in the Master side.

[0041] 5)s_vbus_data[DW-1:0], s_vbus_data_vld, s_vbus_fsof, s_vbus_lsof, s_vbus_feos, s_vbus_leof, s_vbus_fsync: image data received by the Slave end from the ISP data input source, where s_vbus_data_vld is used to characterize the validity of the other 6 data.

[0042] 6)m_vbus_data[DW-1:0], m_vbus_data_vld, m_vbus_fsof, m_vbus_lsof, m_vbus_feos, m_vbus_leof, m_vbus_fsync: image data input by the Master through the data input source, among which m_vbus_data_vld is used to characterize the validity of the other 6 data.

[0043] 7) s_vbus_drdy: The data ready signal sent by the slave end to the input source of the ISP subsystem is used to notify the input source of the ISP system that the slave end is ready to receive data.

[0044] 8) m_vbus_drdy: The data ready signal sent by the Master to the ISP subsystem is used to notify the ISP subsystem that the Master is ready to send data.

[0045] 9)vubs_async_bridge: is the vbus asynchronous bridge.

[0046] 10)async_fifo: asynchronous FIFO.

[0047] Asynchronous bridges are usually implemented using the asynchronous FIFO mentioned above. Asynchronous FIFO is a data buffer mechanism used for data transmission between different clock domains. It uses a pointer encoding method of Gray code or one-hot code to reduce data transmission errors at the clock domain boundary.

[0048] Gray code has only 1 bit change between adjacent states, and the coding density is high. When representing the same number of states (e.g., 8 states), Gray code can use fewer digits (3 digits) to represent it, and occupies less bit width (3 bits) in the register, while one-hot code needs to use more digits to represent 8 states (8 digits), and occupies more bit width (8 bits) in the register, so using Gray code can reduce the bit width of the register compared to using one-hot code. When comparing states, one-hot code has only 1 bit as 1, and the rest are all 0 (e.g., 01000000 and 00100000), and the coding density is low. When comparing states, only one bit can be used to determine the size, so that the state is determined according to the size relationship, while Gray code has a higher coding density (e.g., 101 and 111), and all bits need to be used to determine the size, and the state is determined according to the size relationship, so using one-hot code can simplify the decoding logic and reduce the area of ​​the decoding circuit compared to using Gray code.

[0049] However, Gray code has a high encoding density. When comparing states, it is necessary to determine the size through all bits and determine the state based on the size relationship, so a large number of decoding circuits are needed when decoding. The one-hot code has a low encoding density. When representing the same number of states, more bits are needed, thus occupying more register bit widths. Therefore, how to use less decoding circuits while occupying less bit width is an urgent problem to be solved.

[0050] The embodiment of the present application provides an asynchronous data transmission method, device, electronic device, storage medium and program product. Since the shift encoding method adopted by the electronic device when shifting the first pointer is that the bit changed by each shift is compared with the bit changed by the last shift, the bit changed this time is the bit adjacent to the left of the bit changed by the last shift, and the other bits remain unchanged, that is, the present application is by changing 1 bit, and relative to the last shift, each shift only needs to change the bit adjacent to the left of the bit changed by the last shift, so compared with the encoding method of Gray code, Gray code has a high encoding density, and the shift encoding method adopted by the present application reduces the encoding density of the pointer, and compared with the encoding method of one-hot code, one-hot code occupies more bit width, and the shift encoding method adopted by the present application reduces the bit width occupied by the pointer. In this way, the pointer encoding density of the present application is low, and the bit width occupied by the pointer is small.

[0051] The execution subject of the asynchronous data transmission method provided in the embodiment of the present application may be an asynchronous data transmission device, which may be an electronic device, or a functional module or functional entity in the electronic device. The technical solution provided in the embodiment of the present application is described below using an electronic device as an example.

[0052] Figure 2A flowchart of an asynchronous data transmission method provided by an embodiment of the present application is shown. Figure 2 As shown, the asynchronous data transmission method provided in the embodiment of the present application may include the following steps 201 and 202.

[0053] Step 201: When a Slave terminal receives a write instruction, the electronic device shifts a first pointer.

[0054] In the embodiment of the present application, the first pointer is a pointer for the slave end (also referred to as a slave end or a write end) to write data into the asynchronous FIFO.

[0055] In an embodiment of the present application, the above-mentioned first pointer includes N bits, and the bit that undergoes the i+1th shift change on the first pointer is the bit adjacent to the left of the bit that undergoes the i-th shift change on the first pointer, N is an integer greater than 1, 1≤i≤N.

[0056] It should be noted that the above-mentioned asynchronous FIFO is a buffer for storing data in an asynchronous bridge. The read pointer (i.e., the above-mentioned first pointer) and write pointer (i.e., the second pointer described below) of the asynchronous FIFO can be controlled by different clock domains respectively, and a special synchronization mechanism is used to ensure the correct reading and writing of data, and it can work normally even when the clock frequencies are different or the phases are mismatched. The asynchronous bridge is a circuit or design technology used in digital system design to realize data transmission between different clock domains. It can convert and synchronize data from one clock domain to another clock domain to ensure the correctness and reliability of the data during the transmission process. In the embodiment of the present application, the Slave end and the Master end (also referred to as the master end or the read end) are at both ends of the asynchronous bridge and are in different clock domains. The electronic device can write data to the asynchronous FIFO through the write pointer of the Slave end, and read data from the asynchronous FIFO through the read pointer of the Master end described below, so as to realize the transmission of data between different clock domains.

[0057] In an embodiment of the present application, the electronic device includes a SOC, on which an asynchronous bridge circuit is integrated, which is used to realize data transmission of the asynchronous bridge, and the Slave end and the Master end are the two ends of the asynchronous bridge. The SOC includes multiple subsystems, such as an ISP subsystem, a MIPI subsystem, and a DDR subsystem. The above-mentioned asynchronous bridge is used to receive data (such as multimedia data) from the MIPI subsystem or the DDR subsystem through the Slave end, and send the data to the ISP subsystem through the Master end.

[0058] For example, Figure 3As shown in the figure, an asynchronous bridge is divided into two ends: Slave (vbus_slv in the figure) and Master (vbus_mst in the figure). The Slave end is connected to the input source of ISP data (such as MIPI subsystem or DDR subsystem), and the Master end is connected to the ISP subsystem. The figure includes:

[0059] 1)payld_async[(DW+6)*8-1:0]: connects the data signal line between the Slave end and the Master end, used to transmit data from the Slave end to the Master end.

[0060] 2) wr_ptr_async[DEPTH-1:0]: connects the write pointer line of the Slave end and the Master end, and is used to transmit the Slave end pointer from the Slave end to the Master end.

[0061] In the embodiment of the present application, in each clock cycle, the slave end can transmit the pointer of the slave end to the master end through the above-mentioned write pointer line. Similarly, in each clock cycle, the master end can also transmit the pointer of the master end to the slave end through the following read pointer line.

[0062] 3)rd_ptr_async[DEPTJ-1:0]: connects the read pointer line of the Slave end and the Master end, and is used to transfer the Master end pointer from the Master end to the Slave end.

[0063] In the embodiment of the present application, fewer signal connections (3) are used between the Slave end and the Master end of the above-mentioned asynchronous bridge, which is conducive to partitioning (partitioning, that is, dividing the system into multiple independent clock domains) between the Slave end and the Master end. This is because in the design of a multi-clock domain system, fewer signal connections can reduce the complexity and potential synchronization problems when signals are transmitted between different clock domains. When the Slave end and the Master end are partitioned, it means that the communication between them may be interrupted due to clock deviation, signal delay or other factors. In this case, fewer signal connections help ensure that even when partitioned, the key parts of the system can still maintain communication and operation, thereby improving the robustness and reliability of the system.

[0064] It should be noted that the above bits are bits in the pointer, and the number of bits in the pointer can be called the bit length, that is, the bit width. The above pointer can be encoded in a variety of encoding methods, including Gray code, one-hot code, etc.

[0065] For example, Figure 4The coding form when Gray code and one-hot code represent 8 state numbers (i.e., the decimal number in the figure) is shown, wherein the bit width occupied by Gray code to represent 8 state numbers is 3 bits (for example, 3'b000 represents 3 bits and the code is 000), and the bit width occupied by one-hot code is 8 bits. Gray code has only 1 bit change between adjacent ones, and the coding density is high. When representing the same state number (for example, 8 states), Gray code can use fewer digits to represent (3 digits), occupying less bit width (3 bits) in the register, while one-hot code needs to use more digits to represent 8 states (8 digits), occupying more bit width (8 bits) in the register, so using Gray code can reduce the occupation of register bit width compared to using one-hot code. When comparing states, the one-hot code has only 1 bit as 1, and the rest are 0 (for example, 01000000 and 00100000), and the coding density is low. When comparing states, only one bit can be used to determine the size, and the state is determined according to the size relationship. The Gray code has a higher coding density (for example, 101 and 111), and all bits are required to determine the size, and the state is determined according to the size relationship. Therefore, the use of one-hot code can simplify the decoding logic and reduce the area of ​​the decoding circuit compared to the use of Gray code.

[0066] Optionally, in an embodiment of the present application, the bit widths of the first pointer and the second pointer are the same, and both the first pointer and the second pointer adopt a pointer encoding method of shift encoding.

[0067] In the embodiment of the present application, the above shift encoding is a new pointer encoding method. Figure 4 ,like Figure 5 As shown, taking the bit width of 4 bits as an example, the initial state of the pointer of the shift code can be 0000, and after each shift, it will become 0001, 0011, 0111, 1111, 1110, 1100, 1000, for a total of 8 cases. When the pointer of the shift code is 1000, if the shift continues, the electronic device can change the 1 in the pointer 1000 of the shift code to 0, so that the pointer becomes 0000, that is, the initial state of the pointer of the shift code. When the bit width is 4 bits, there are 8 cases for the pointer of the shift code, that is, when representing 8 state numbers, the bit width occupied by the shift code is 4 bits. The bit width occupied by the one-hot code when representing 8 state numbers is 8 bits, so when representing the same 8 state numbers, the use of shift coding can reduce the occupation of the 4-bit register bit width compared to the use of the one-hot code, thereby improving the utilization rate of the register bit width.

[0068] For example, Figure 6The jump logic of the pointer encoded in the pointer encoding mode of shift encoding in the embodiment of the present application is shown. Taking the pointer bit width of 8 bits as an example, the jump of the pointer (i.e., fifo_pointer in the figure) starts from 0000_0000, that is, the state number 0 in the figure (the state number is hexadecimal). In the first clock cycle, the electronic device receives the first image data (i.e., {s_vbus_data[DW-1:0], s_vbus_data_vld, s_vbus_fsof, s_vbus_lsof, s_vbus_feos, s_vbus_leof, s_vbus_fsync} in the figure), and splices it into the first data bit of the asynchronous FIFO, and then the pointer jumps from 0000_0000 to 0000_0001. In the second clock cycle, the electronic device receives the second image data and splices it into the second data bit of the asynchronous FIFO, and then the pointer jumps from 0000_0001 to 0000_0011, and the status number is 1. And so on, until the data bits in the asynchronous FIFO are full. In the 15th clock cycle, the electronic device receives the 15th image data and splices it into the 15th data bit of the asynchronous FIFO, and then the pointer jumps from 1100_0000 to 1000_0000, and the status number is 80. In the 16th clock cycle, the electronic device receives the 16th image data and splices it into the 16th data bit of the asynchronous FIFO, and then the pointer jumps from 1000_0000 to 0000_0000, and the status number is 0. At this time, the data bits in the asynchronous FIFO are full, so there are no empty data bits in the asynchronous FIFO. The (DW+6)xDEPTH in the figure is the spliced ​​data, which is transmitted to the Master end through payld_async[(DW+6)*8-1:0] in the figure (that is, the data signal line connecting the Slave end and the Master end).

[0069] In the embodiment of the present application, the above-mentioned shift is: when the bit changed by the shift is 0, the electronic device can change the bit from 0 to 1; when the bit changed by the shift is 1, the electronic device can change the bit from 1 to 0.

[0070] Optionally, in the embodiment of the present application, the above N bits are arranged in order from right to left. Figure 2 ,like Figure 7 As shown, the "shifting the first pointer" in the above step 201 can be implemented by the following step 201a.

[0071] Step 201a: The electronic device shifts the first pointer for the i-th time by changing the value of the i-th bit among the N bits and keeping the values ​​of the bits except the i-th bit among the N bits.

[0072] For example, taking the bit width as 4 bits, Figure 4 As shown, in the case where the first pointer is 0000, the first pointer changes from 1000 to 0000 during the last shift change, that is, the bit changed last time is the 4th bit, and the left adjacent bit of the 4th bit can be wrapped back from the 4th bit to the 1st bit, that is, the left adjacent bit of the 4th bit is the 1st bit, so the bit changed by this shift change is the 1st bit, that is, 0000 is changed to 0001;

[0073] In the case where the first pointer is 0001, the first pointer changes from 0000 to 0001 during the last shift change, that is, the bit changed last time is the first bit, and the bit adjacent to the left of the first bit is the second bit, so the bit changed this time is the second bit, that is, 0001 is changed to 0011;

[0074] In the case where the first pointer is 0011, the first pointer changes from 0001 to 0011 during the last shift change, i.e. the bit changed last time is the second bit, and the bit adjacent to the left of the second bit is the third bit, so the bit changed this time is the third bit, i.e. 0011 is changed to 0111;

[0075] In the case where the first pointer is 0111, the first pointer changes from 0011 to 0111 during the last shift change, i.e., the bit changed last time is the 3rd bit, and the bit adjacent to the left of the 3rd bit is the 4th bit, so the bit changed this time is the 4th bit, i.e., 0111 is changed to 1111;

[0076] In the case where the first pointer is 1111, the first pointer changes from 0111 to 1111 during the last shift change, i.e., the bit changed last time is the 4th bit, and the bit adjacent to the left of the 4th bit can be wrapped back from the 4th bit to the 1st bit, i.e., the bit adjacent to the left of the 4th bit is the 1st bit, so the bit changed by this shift change is the 1st bit, i.e., 1111 is changed to 1110;

[0077] In the case where the first pointer is 1110, the first pointer changes from 1111 to 1110 during the last shift change, i.e. the bit changed last time is the first bit, and the bit adjacent to the left of the first bit is the second bit, so the bit changed this time is the second bit, i.e. 1110 is changed to 1100;

[0078] In the case where the first pointer is 1100, the first pointer changes from 1110 to 1100 during the last shift change, i.e., the bit changed last time is the second bit, and the bit adjacent to the left of the second bit is the third bit, so the bit changed this time is the third bit, i.e., 1100 is changed to 1000;

[0079] When the first pointer is 1000, the first pointer changes from 1100 to 1000 during the last shift change, that is, the bit that changed last time is the 3rd bit, and the bit adjacent to the left of the 3rd bit is the 4th bit, so the bit that changes this time is the 4th bit, that is, 1000 is changed to 0000. So far, when the bit width is 4, the shift codes of all 8 cases in the first pointer are shifted, and the shift can be restarted from 0000.

[0080] In this way, the electronic device can change the bit changed by this shift while keeping the other N bits, so that only one bit needs to be changed between two adjacent shift codes to complete the shift, reducing the difficulty of comparing the first pointer with the second pointer.

[0081] Step 202: The electronic device determines whether the asynchronous FIFO is in a non-full state based on the first pointer and the second pointer.

[0082] In the embodiment of the present application, the second pointer is a pointer for the Master end to read data from the asynchronous FIFO, and the first pointer and the second pointer are pointers synchronized across clock domains.

[0083] In the embodiment of the present application, the Slave end can receive image data from other subsystems in the SOC, and when it is determined that the asynchronous FIFO is not full, the electronic device can splice the image data and write it into the asynchronous FIFO.

[0084] For example, in combination Figure 3 , Figure 8The structure of the Slave end is shown. After the SOC startup initialization is completed, the clock (Clock) / power (Power) of the Slave end of the Vbus asynchronous bridge is enabled, and then the Slave end packages the received image data (including fsync, fsof, feof, lsof, leof, vbus_data[DW-1:0], vbus_vld, that is, s_vbus_data[DW-1:0], s_vbus_data_vld, s_vbus_fsof, s_vbus_lsof, s_vbus_feos, s_vbus_leof, s_vbus_fsync in the figure) and sends it to the upstrm_payld module (that is, upstrm_payld in the figure). Then, the electronic device can jump the read pointer (i.e., fifo_wptr_inc in the figure), that is, shift the pointer pointing to the asynchronous FIFO (i.e., the read pointer) to the next empty data bit, and judge the first pointer and the second pointer through the Slave end, and when the first pointer and the second pointer indicate that the asynchronous FIFO is not full, through the upstrm_payld module, according to the actual required asynchronous FIFO depth (i.e., DEPTH in the figure, that is, the number of data bits in the asynchronous FIFO) size, the image data is spliced ​​(i.e., splice in the figure) to obtain spliced ​​data (x DEPTH and DFF in the figure are used to temporarily store spliced ​​data).

[0085] Optionally, in the embodiment of the present application, after the Slave end packages the received image data and sends it to the upstrm_payld module, the electronic device can confirm the valid data in the image data (i.e. Figure 8 The validity of s_vbus_data_vld in the image data is checked, and when the valid data indicates that other image data are valid, each data in the image data is spliced ​​to obtain spliced ​​data, and the pointer pointing to the asynchronous FIFO is shifted to the next empty data bit.

[0086] In this way, the electronic device can determine the validity of the image data before splicing the image data, and splice the individual data in the image data if the image data is valid, thereby avoiding splicing invalid image data.

[0087] Optionally, in the embodiment of the present application, combined with Figure 2 ,like Fig. 9 As shown, the above step 202 can be implemented by the following step 202a or step 202b.

[0088] Step 202a: If the first bit in the first pointer and the second bit in the second pointer have the same value, the electronic device determines that the asynchronous FIFO is in a non-full state.

[0089] In the embodiment of the present application, the first bit is the bit that performs the i-th shift change on the first pointer, and the second bit is the bit in the second pointer that has the same position as the first bit.

[0090] Exemplarily, taking the bit width as 4 bits as an example, when the first pointer is 0000, the bit changed by this shift is the first bit, so it is necessary to compare the first bit of the first pointer with the first bit of the second pointer. If the first bit in the first pointer has the same value as the first bit in the second pointer, the electronic device determines that the asynchronous FIFO is in a non-full state.

[0091] When the first pointer is 0001, the bit changed by this shift is the second bit, so the second bits of the first pointer and the second pointer need to be compared. If the second bit in the first pointer is the same as the second bit in the second pointer, the electronic device determines that the asynchronous FIFO is not full.

[0092] When the first pointer is 0011, the bit changed by this shift is the third bit, so the third bits of the first pointer and the second pointer need to be compared. If the third bit in the first pointer is the same as the third bit in the second pointer, the electronic device determines that the asynchronous FIFO is not full.

[0093] When the first pointer is 0111, the bit changed by this shift is the 4th bit, so the 4th bit of the first pointer needs to be compared with the 4th bit of the second pointer. If the value of the 4th bit in the first pointer is the same as the value of the 4th bit in the second pointer, the electronic device determines that the asynchronous FIFO is not full.

[0094] When the first pointer is 1111, the bit changed by this shift is the first bit, so the first bit of the first pointer needs to be compared with the first bit of the second pointer. If the first bit in the first pointer has the same value as the first bit in the second pointer, the electronic device determines that the asynchronous FIFO is not full.

[0095] When the first pointer is 1110, the bit changed by this shift is the second bit, so the second bits of the first pointer and the second pointer need to be compared. If the second bit in the first pointer has the same value as the second bit in the second pointer, the electronic device determines that the asynchronous FIFO is not full.

[0096] When the first pointer is 1100, the bit changed by this shift is the third bit, so the third bits of the first pointer and the second pointer need to be compared. If the third bit in the first pointer has the same value as the third bit in the second pointer, the electronic device determines that the asynchronous FIFO is not full.

[0097] When the first pointer is 1000, the bit changed by this shift is the 4th bit, so it is necessary to compare the 4th bit of the first pointer with the 4th bit of the second pointer. If the value of the 4th bit in the first pointer is the same as the value of the 4th bit in the second pointer, the electronic device determines that the asynchronous FIFO is not full.

[0098] Step 202b: If the values ​​of the first bit in the first pointer and the second bit in the second pointer are different, the electronic device determines that the asynchronous FIFO is in a full state.

[0099] Exemplarily, taking the bit width of 4 bits as an example, when the first pointer is 0000, the bit changed in this shift is the 1st bit, so it is necessary to compare the 1st bit of the first pointer and the 1st bit of the second pointer. If the value of the 1st bit in the first pointer is different from the value of the 1st bit in the second pointer, the electronic device determines that the asynchronous FIFO is full.

[0100] Optionally, in the embodiment of the present application, the slave end can use the write pointer to compare with the read pointer synchronized from the master end to determine the full state. If the asynchronous FIFO is not full, Figure 8 s_vbus_drdy (i.e., the first status bit described below) is 1, indicating that upstream data can continue to be received. Because the full state logic is used to output s_vbus_drdy, the shift encoding provided in the embodiment of the present application simplifies the comparison process. It is only necessary to determine that the asynchronous FIFO is not full when one bit is the same, which simplifies the full state logic judgment, thereby optimizing the s_vbus_drdy output logic.

[0101] In this way, the electronic device can determine whether the asynchronous FIFO is full by judging a bit in the first pointer and the second pointer, thereby simplifying the judgment logic, improving the judgment efficiency, and saving the decoding circuit.

[0102] The embodiment of the present application provides an asynchronous data transmission method, because the shift encoding method adopted by the electronic device when shifting the first pointer is that the bit changed by each shift is compared with the bit changed by the last shift, and the bit changed this time is the bit adjacent to the left of the bit changed by the last shift, while the other bits remain unchanged, that is, the present application is by changing 1 bit, and relative to the last shift, each shift only needs to change the bit adjacent to the left of the bit changed by the last shift, so compared with the encoding method of Gray code, the encoding density of Gray code is high, and the shift encoding method adopted by the present application reduces the encoding density of the pointer, and compared with the encoding method of one-hot code, the one-hot code occupies more bit width, and the shift encoding method adopted by the present application reduces the bit width occupied by the pointer. In this way, the pointer encoding density of the present application is low, and the bit width occupied by the pointer is small.

[0103] Optionally, in an embodiment of the present application, the asynchronous data transmission method provided in the embodiment of the present application further includes the following step 301.

[0104] Step 301: When the asynchronous FIFO is full, the electronic device sets a first status bit of a first pointer.

[0105] In the embodiment of the present application, the first status bit after being set is used to indicate that the asynchronous FIFO is in a full state.

[0106] Optionally, in the embodiment of the present application, both the upstream and downstream of the Slave end and the Master end support valid / ready handshake, which can ensure the stability and accuracy of the ISP system data flow.

[0107] It should be noted that the valid signal is generated by the data sender to indicate whether the data is ready to be sent, while the ready signal is generated by the data receiver to indicate whether the receiver is ready to receive data. Data will only be transmitted when both the valid and ready signals are high.

[0108] Optionally, in an embodiment of the present application, the electronic device can send a first status bit (i.e., a ready signal, i.e., the above-mentioned s_vbus_drdy) to an upstream subsystem (i.e., a subsystem that sends image data to the Slvae end) through the Slave end, so that the upstream subsystem can stop sending image data when the first status bit indicates that the asynchronous FIFO is full.

[0109] In this way, the electronic device can stop sending image data to the Slave end when the asynchronous FIFO is full, thereby avoiding data congestion.

[0110] Fig.10 A flowchart of an asynchronous data transmission method provided by an embodiment of the present application is shown. Fig.10 As shown, the asynchronous data transmission method provided in the embodiment of the present application may include the following steps 401 and 402.

[0111] Step 401: When the Master receives a read instruction, the electronic device shifts the second pointer.

[0112] In the embodiment of the present application, the second pointer is a pointer used by the Master end to read data from the asynchronous FIFO.

[0113] In an embodiment of the present application, the second pointer includes N bits, and the bit of the second pointer that is shifted for the i+1th time is the bit adjacent to the left of the bit of the second pointer that is shifted for the i-th time, N is an integer greater than 1, 1≤i≤N.

[0114] In the embodiment of the present application, the jump logic of the second pointer is the same as the jump logic of the first pointer, that is, the jump logic of the pointer encoded in a shift-encoded pointer encoding method, which will not be repeated here.

[0115] Optionally, in the embodiment of the present application, the above N bits are arranged in order from right to left. Fig.10 ,like Fig.11 As shown, the "shifting the second pointer" in the above step 401 can be implemented by the following step 401a.

[0116] Step 401a: The electronic device shifts the second pointer for the i-th time by changing the value of the i-th bit among the N bits and keeping the values ​​of the bits except the i-th bit among the N bits.

[0117] In the embodiment of the present application, the bit shifting method of the second pointer is the same as the bit shifting method and beneficial effect of the first pointer, and will not be repeated here.

[0118] Step 402: The electronic device determines whether the asynchronous FIFO is in a non-empty state based on the first pointer and the second pointer.

[0119] In the embodiment of the present application, the first pointer is a pointer for the Slave end to write data into the asynchronous FIFO, and the first pointer and the second pointer are pointers synchronized across clock domains.

[0120] For example, Fig.12The structure of the Master end is shown. The Master end sends the received spliced ​​data to the dnstrm_payld module. When the Master end receives the ready data of the upstream subsystem of the SOC (i.e., m_vbus_drdy in the figure), the electronic device can shift the second pointer, judge the first pointer and the second pointer through the Master end, and when the Master end judges that the asynchronous FIFO is not empty according to the first pointer and the second pointer, the electronic device can split the spliced ​​data through the dnstrm_payld module (i.e., split in the figure), and each piece of data is disassembled into the form required by the ISP system (including fsync, fsof, feof, lsof, leof, vbus_data[DW-1:0], vbus_vld, i.e., m_vbus_data[DW-1:0], m_vbus_data_vld, m_vbus_fsof, m_vbus_lsof, m_vbus_feos, m_vbus_leof, m_vbus_fsync in the figure), and then send the disassembled data to the downstream ISP subsystem.

[0121] Optionally, in the embodiment of the present application, combined with Fig.10 ,like Fig.13 As shown, the above step 402 can be implemented by the following step 402a or step 402b.

[0122] Step 402a: If the first bit in the first pointer and the second bit in the second pointer have the same value, the electronic device determines that the asynchronous FIFO is in a non-empty state.

[0123] In the embodiment of the present application, the second bit is the bit that performs the i-th shift change on the second pointer, and the first bit is the bit in the first pointer that has the same position as the second bit.

[0124] Exemplarily, taking the bit width of 4 bits as an example, when the first pointer is 0000, the bit changed in this shift is the 1st bit, so it is necessary to compare the 1st bit of the first pointer and the 1st bit of the second pointer. If the value of the 1st bit in the first pointer is the same as the value of the 1st bit in the second pointer, the electronic device determines that the asynchronous FIFO is in a non-empty state.

[0125] Step 402b: If the values ​​of the first bit in the first pointer and the second bit in the second pointer are different, the electronic device determines that the asynchronous FIFO is in an empty state.

[0126] Exemplarily, taking the bit width of 4 bits as an example, when the first pointer is 0000, the bit changed in this shift is the 1st bit, so it is necessary to compare the 1st bit of the first pointer and the 1st bit of the second pointer. If the value of the 1st bit in the first pointer is different from the value of the 1st bit in the second pointer, the electronic device determines that the asynchronous FIFO is in an empty state.

[0127] Optionally, in the embodiment of the present application, the Master end uses the read pointer to compare with the write pointer synchronized from the Slave end to make an empty state judgment. If the Master end is not empty, dst_valid (i.e., the second state bit described below) is 1, indicating that there is data to be transmitted to the downstream ISP. Because the empty state logic is used to output m_vbus_data_vld, the shift encoding provided in the embodiment of the present application simplifies the comparison process. It is only necessary to judge that the asynchronous FIFO is not empty when judging that 1 bit is different, thereby optimizing the output logic of m_vbus_data_vld.

[0128] The embodiment of the present application provides an asynchronous data transmission method. Since the shift encoding method adopted by the electronic device when shifting the second pointer is that the bit changed by each shift is compared with the bit changed by the last shift, the bit changed this time is the bit adjacent to the left of the bit changed by the last shift, and the other bits remain unchanged, that is, the present application is by changing 1 bit, and relative to the last shift, each shift only needs to change the bit adjacent to the left of the bit changed by the last shift, so compared with the encoding method of Gray code, the encoding density of Gray code is high, and the shift encoding method adopted by the present application reduces the encoding density of the pointer, and compared with the encoding method of one-hot code, the one-hot code occupies more bit width, and the shift encoding method adopted by the present application reduces the bit width occupied by the pointer. In this way, the pointer encoding density of the present application is low, and the bit width occupied by the pointer is small.

[0129] Optionally, in the embodiment of the present application, the asynchronous data transmission method provided in the embodiment of the present application further includes the following step 501.

[0130] Step 501: When the asynchronous FIFO is full, the electronic device sets the second status bit of the second pointer.

[0131] In the embodiment of the present application, the second status bit after being set is used to indicate that the asynchronous FIFO is in a full state.

[0132] Optionally, in the embodiment of the present application, the electronic device can determine whether the first status bit is in a full state through the Master end, and when the first status bit indicates that the asynchronous FIFO is in a full state, if a ready signal (i.e. Fig.12If the m_vbus_drdy in the ISP subsystem indicates that the ISP subsystem can receive data, the electronic device can decompose the data and send the data to the ISP subsystem.

[0133] In this way, the electronic device can start sending data to the ISP subsystem when the ISP subsystem can receive the data, so that the ISP subsystem can process the data in time.

[0134] Fig.14 This is a timing diagram of the asynchronous data transmission method provided in this embodiment. Fig.14 As shown in the figure, s_vbus_clk represents the clock cycle, and each clock cycle is represented by an arrow, that is, each adjacent two vertical dotted lines in the figure represent the same clock cycle. The timing diagram of the slave end is above the horizontal dotted line in the figure, and the timing diagram of the master end is below the horizontal dotted line. The fifo_wptr_inc[7:0] in the figure is the write pointer, and the s_vbus_data, s_vbus_data_vld, s_vbus_fsof, s_vbus_lsof, s_vbus_feos, s_vbus_leof, and s_vbus_fsync in the figure are the image data. As shown in the figure, the s_vbus_fsync in the image data is spliced ​​and sent at the third clock cycle, and the write pointer is sent to the master end, and the write pointer points to 0 at the third clock cycle. The fifo_rptr_inc[7:0] in the figure is the read pointer of the master end. In the 5th clock cycle, the Master receives the write pointer, which is wptr_inc_ss[7:0] in the figure. In the 6th clock cycle, the Master's read pointer points to 0 and sends a read pointer to the Slave. In the 7th clock cycle, the Master splits and splices the data, which is m_vbus_fsync in the figure, and jumps the pointer to 1. In the 8th clock cycle, the Slave receives the read pointer sent by the Master, which is rptr_inc_ss[7:0] in the figure. And so on, until the 29th clock cycle, the Master receives all the image data, and until the 31st clock cycle, the Slave receives the last read pointer sent by the Master.

[0135] Optionally, in the embodiment of the present application, the transmitted image data may be in vbus format. If the image data to be transmitted is not in vbus format, the transmitted data format may be repackaged in a certain format so that the data conforms to the format specification of vbus, and data transmission may be performed by the method provided in the embodiment of the present application.

[0136] Optionally, in an embodiment of the present application, considering the scenario of low-power application, a clock and power management module may be added to the asynchronous bridge to facilitate the power management unit (Power Management Unit, PMU) to perform low-power management.

[0137] Each of the above-mentioned method embodiments, or various possible implementation methods in each method embodiment can be executed separately, or any two or more of them can be executed in combination with each other. The specific implementation method can be determined according to actual usage requirements, and the embodiments of the present application do not limit this.

[0138] The asynchronous data transmission method provided in the embodiment of the present application can be executed by an asynchronous data transmission device. In the embodiment of the present application, an asynchronous data transmission device executing the asynchronous data transmission method is taken as an example to illustrate the asynchronous data transmission device provided in the embodiment of the present application.

[0139] Fig.15 A possible structural diagram of an asynchronous data transmission device involved in some embodiments of the present application is shown. Fig.15 As shown, the asynchronous data transmission device 70 may include: an execution module 71 and a determination module 72 .

[0140] Among them, the execution module 71 is used to shift the first pointer when the Slave end receives a write instruction. The first pointer is the pointer for the Slave end to write data into the asynchronous FIFO. The first pointer includes N bits. The bit that is shifted and changed for the i+1th time on the first pointer is the bit adjacent to the left of the bit that is shifted and changed for the i-th time on the first pointer. N is an integer greater than 1, and 1≤i≤N.

[0141] The determination module 72 is used to determine whether the asynchronous FIFO is in a non-full state based on the first pointer and the second pointer obtained by the execution module 71. The second pointer is a pointer for the Master end to read data from the asynchronous FIFO. The first pointer and the second pointer are pointers synchronized across clock domains.

[0142] In a possible implementation, the N bits are arranged from right to left. The execution module 71 is specifically configured to perform an i-th shift on the first pointer by changing the value of the i-th bit in the N bits and keeping the values ​​of the bits in the N bits except the i-th bit.

[0143] In a possible implementation, the determination module 72 is specifically used to: if the first bit in the first pointer and the second bit in the second pointer have the same value, then determine that the asynchronous FIFO is in a non-full state; if the first bit in the first pointer and the second bit in the second pointer have different values, then determine that the asynchronous FIFO is in a full state; wherein the first bit is the bit that performs the i-th shift change on the first pointer, and the second bit is the bit in the second pointer that has the same position as the first bit.

[0144] In a possible implementation, the execution module 71 is further configured to set a first status bit of the first pointer when the asynchronous FIFO is full, and the set first status bit is used to indicate that the asynchronous FIFO is full.

[0145] In an embodiment of the present application, an asynchronous data transmission device is provided. Since the shift encoding method adopted by the data transmission device when shifting the first pointer is that the bit changed by each shift is compared with the bit changed by the last shift, the bit changed this time is the bit adjacent to the left of the bit changed by the last shift, and the other bits remain unchanged, that is, the present application is by changing 1 bit, and relative to the last shift, each shift only needs to change the bit adjacent to the left of the bit changed by the last shift, so compared with the encoding method of Gray code, the encoding density of Gray code is high, and the shift encoding method adopted by the present application reduces the encoding density of the pointer, and compared with the encoding method of one-hot code, the one-hot code occupies more bit width, and the shift encoding method adopted by the present application reduces the bit width occupied by the pointer. In this way, the pointer encoding density of the present application is low, and the pointer occupies less bit width.

[0146] Fig.16 A possible structural diagram of an asynchronous data transmission device involved in some embodiments of the present application is shown. Fig.16 As shown, the asynchronous data transmission device 73 may include: an execution module 74 and a determination module 75 .

[0147] Among them, the execution module 74 is used to shift the second pointer when the Master side receives a read instruction. The second pointer is a pointer for the Master side to read data from the asynchronous FIFO. The second pointer includes N bits. The bit that is shifted for the i+1th time on the second pointer is the bit adjacent to the left of the bit that is shifted for the i-th time on the second pointer. N is an integer greater than 1, and 1≤i≤N.

[0148] The determination module 75 is used to determine whether the asynchronous FIFO is in a non-empty state based on a first pointer and a second pointer, wherein the first pointer is a pointer for the Slave end to write data into the asynchronous FIFO, and the first pointer and the second pointer are pointers synchronized across clock domains.

[0149] In a possible implementation, the N bits are arranged in order from right to left. The execution module 74 is specifically configured to perform an i-th shift on the second pointer by changing the value of the i-th bit in the N bits and maintaining the values ​​of the bits in the N bits except the i-th bit.

[0150] In a possible implementation, it is characterized in that the determination module 75 is specifically used to: if the first bit in the first pointer and the second bit in the second pointer have the same value, then determine that the asynchronous FIFO is in a non-empty state; if the first bit in the first pointer and the second bit in the second pointer have different values, then determine that the asynchronous FIFO is in an empty state; wherein the second bit is the bit that performs the i-th shift change on the second pointer, and the first bit is the bit in the first pointer that has the same position as the second bit.

[0151] In a possible implementation, the execution module is further configured to set a second status bit of the second pointer when the asynchronous FIFO is in an empty state, and the set second status bit is used to indicate that the asynchronous FIFO is in an empty state.

[0152] In the embodiment of the present application, an asynchronous data transmission device is provided. Since the shift encoding method adopted by the data transmission device when shifting the second pointer is that the bit changed each time is compared with the bit changed in the previous shift, the bit changed this time is the bit adjacent to the left of the bit changed in the previous shift, and the other bits remain unchanged, that is, the present application is by changing 1 bit, and relative to the previous shift, each shift only needs to change the bit adjacent to the left of the bit changed in the previous shift. Therefore, compared with the encoding method of Gray code, the encoding density of Gray code is high, and the shift encoding method adopted by the present application reduces the encoding density of the pointer. Compared with the encoding method of one-hot code, the one-hot code occupies more bit width, and the shift encoding method adopted by the present application reduces the bit width occupied by the pointer. In this way, the pointer encoding density of the present application is low, and the pointer occupies less bit width. .

[0153] The asynchronous data transmission device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc. It can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0154] The asynchronous data transmission device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0155] The asynchronous data transmission device provided in the embodiment of the present application can implement each process implemented in the above method embodiment, and will not be described again here to avoid repetition.

[0156] Alternatively, if Fig.17 As shown, an embodiment of the present application also provides an electronic device 1000, including a processor 1001 and a memory 1002, wherein the memory 1002 stores programs or instructions that can be executed on the processor 1001, and when the program or instructions are executed by the processor 1001, the various steps of the above-mentioned asynchronous data transmission method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they are not repeated here.

[0157] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0158] Fig.18 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of the present application.

[0159] The electronic device 100 includes but is not limited to components such as a radio frequency unit 101, a network module 102, an audio output unit 103, an input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, and a processor 110.

[0160] Those skilled in the art will appreciate that the electronic device 100 may also include a power source (such as a battery) for supplying power to various components, and the power source may be logically connected to the processor 110 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.18 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0161] In one implementation, the processor 110 is used to shift a first pointer when a write instruction is received at the Slave end. The first pointer is a pointer for the Slave end to write data into the asynchronous FIFO. The first pointer includes N bits. The bit that is shifted for the i+1th time on the first pointer is the bit adjacent to the left of the bit that is shifted for the i-th time on the first pointer. N is an integer greater than 1, and 1≤i≤N.

[0162] The processor 110 is further configured to determine whether the asynchronous FIFO is not full based on a first pointer and a second pointer, wherein the second pointer is a pointer for the Master to read data from the asynchronous FIFO, and the first pointer and the second pointer are pointers synchronized across clock domains.

[0163] Optionally, the N bits are arranged from right to left. The processor 110 is specifically configured to perform an i-th shift on the first pointer by changing the value of the i-th bit in the N bits and keeping the values ​​of the bits in the N bits except the i-th bit.

[0164] Optionally, the above-mentioned processor 110 is specifically used to: if the first bit in the first pointer and the second bit in the second pointer have the same value, determine that the asynchronous FIFO is in a non-full state; if the first bit in the first pointer and the second bit in the second pointer have different values, determine that the asynchronous FIFO is in a full state; wherein the first bit is the bit that performs the i-th shift change on the first pointer, and the second bit is the bit in the second pointer that has the same position as the first bit.

[0165] Optionally, the processor 110 is further configured to set a first status bit of the first pointer when the asynchronous FIFO is in a full state, and the set first status bit is used to indicate that the asynchronous FIFO is in a full state.

[0166] The embodiment of the present application provides an electronic device, because the shift encoding method adopted by the electronic device when shifting the first pointer is that the bit changed each time by the shift is compared with the bit changed by the last shift, and the bit changed this time is the bit adjacent to the left of the bit changed by the last shift, while the other bits remain unchanged, that is, the present application is by changing 1 bit, and relative to the last shift, each shift only needs to change the bit adjacent to the left of the bit changed by the last shift, so compared with the encoding method of Gray code, the encoding density of Gray code is high, and the shift encoding method adopted by the present application reduces the encoding density of the pointer, and compared with the encoding method of one-hot code, the one-hot code occupies more bit width, and the shift encoding method adopted by the present application reduces the bit width occupied by the pointer. In this way, the pointer encoding density of the present application is low, and the bit width occupied by the pointer is small.

[0167] In another implementation scheme, the above-mentioned processor 110 is used to shift the second pointer when the Master side receives a read instruction. The second pointer is the pointer for the Master side to read data from the asynchronous FIFO. The second pointer includes N bits. The bit that is shifted and changed for the i+1th time on the second pointer is the bit adjacent to the left of the bit that is shifted and changed for the i-th time on the second pointer. N is an integer greater than 1, and 1≤i≤N.

[0168] The processor 110 is further configured to determine whether the asynchronous FIFO is in a non-empty state based on a first pointer and a second pointer, wherein the first pointer is a pointer for the slave end to write data into the asynchronous FIFO, and the first pointer and the second pointer are pointers synchronized across clock domains.

[0169] Optionally, the N bits are arranged in order from right to left. The processor 110 is specifically configured to perform an i-th shift on the second pointer by changing the value of the i-th bit in the N bits and maintaining the values ​​of the bits in the N bits except the i-th bit.

[0170] Optionally, the above-mentioned processor 110 is specifically used to: if the first bit in the first pointer and the second bit in the second pointer have the same value, determine that the asynchronous FIFO is in a non-empty state; if the first bit in the first pointer and the second bit in the second pointer have different values, determine that the asynchronous FIFO is in an empty state; wherein the second bit is the bit that performs the i-th shift change on the second pointer, and the first bit is the bit in the first pointer that has the same position as the second bit.

[0171] Optionally, the processor 110 is further configured to set a second status bit of the second pointer when the asynchronous FIFO is in an empty state, and the set second status bit is used to indicate that the asynchronous FIFO is in an empty state.

[0172] The embodiment of the present application provides an electronic device, because the shift encoding method adopted by the electronic device when shifting the second pointer is that the bit changed each time by the shift is compared with the bit changed by the last shift, and the bit changed this time is the bit adjacent to the left of the bit changed by the last shift, while the other bits remain unchanged, that is, the present application is by changing 1 bit, and relative to the last shift, each shift only needs to change the bit adjacent to the left of the bit changed by the last shift, so compared with the encoding method of Gray code, the encoding density of Gray code is high, and the shift encoding method adopted by the present application reduces the encoding density of the pointer, and compared with the encoding method of one-hot code, the one-hot code occupies more bit width, and the shift encoding method adopted by the present application reduces the bit width occupied by the pointer. In this way, the pointer encoding density of the present application is low, and the bit width occupied by the pointer is small.

[0173] The electronic device provided in the embodiment of the present application can implement each process implemented in the above method embodiment, and can achieve the same technical effect. To avoid repetition, it is not repeated here. The beneficial effects of various implementations in this embodiment can be specifically referred to the beneficial effects of the corresponding implementations in the above method embodiment. To avoid repetition, it is not repeated here.

[0174] It should be understood that in the embodiment of the present application, the input unit 104 may include a graphics processor (Graphics Processing Unit, GPU) 1041 and a microphone 1042, and the graphics processor 1041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 107 includes a touch panel 1071 and at least one of other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 may include two parts: a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0175] The memory 109 can be used to store software programs and various data. The memory 109 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 109 may include a volatile memory or a non-volatile memory, or the memory 109 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0176] The processor 110 may include one or more processing units; optionally, the processor 110 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 110.

[0177] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned asynchronous data transmission method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0178] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0179] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned asynchronous data transmission method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0180] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0181] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned asynchronous data transmission method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0182] It should be noted that, in this article, the term "comprises", "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0183] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0184] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. An asynchronous data transmission method, characterized in that: include: When the Slave end receives a write instruction, shift the first pointer, the first pointer being the pointer for the Slave end to write data into the asynchronous FIFO, the first pointer comprising N bits, the bit changed by the i+1th shift of the first pointer being the bit adjacent to the left of the bit changed by the ith shift of the first pointer, N being an integer greater than 1, 1≤i≤N; Determine whether the asynchronous FIFO is in a non-full state based on the first pointer and the second pointer, the second pointer being a pointer for the Master end to read data from the asynchronous FIFO, the first pointer and the second pointer being pointers synchronized across clock domains; Among them, the Slave end and the Master end are the two ends of the asynchronous bridge; the Slave end is used to receive data from the upstream system of the asynchronous bridge, and when the asynchronous FIFO is not full, the data is packaged and spliced ​​and written into the asynchronous FIFO; the Master end is used to receive the packaged and spliced ​​data from the Slave end, and the data is split and transmitted to the downstream system of the asynchronous bridge.

2. The method according to claim 1, characterized in that The N bits are arranged in order from right to left; The shifting of the first pointer comprises: The first pointer is shifted for an i-th time by changing the value of the i-th bit among the N bits and maintaining the values ​​of the bits among the N bits except the i-th bit.

3. The method according to claim 1, characterized in that The determining, based on the first pointer and the second pointer, whether the asynchronous FIFO is in a non-full state comprises: If the first bit in the first pointer and the second bit in the second pointer have the same value, determining that the asynchronous FIFO is in a non-full state; If the values ​​of the first bit in the first pointer and the second bit in the second pointer are different, determining that the asynchronous FIFO is in a full state; The first bit is the bit that is shifted and changed for the first pointer for the i-th time, and the second bit is the bit in the second pointer that has the same position as the first bit.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: When the asynchronous FIFO is in a full state, the first state bit of the first pointer is set, and the set first state bit is used to indicate that the asynchronous FIFO is in a full state.

5. An asynchronous data transmission method, characterized in that: include: When the Master receives a read instruction, the second pointer is shifted, the second pointer is a pointer for the Master to read data from the asynchronous FIFO, the second pointer includes N bits, the bit that is shifted (i+1) for the second pointer is the bit adjacent to the left of the bit that is shifted (i) for the second pointer, N is an integer greater than 1, 1≤i≤N; Determine whether the asynchronous FIFO is in a non-empty state based on a first pointer and a second pointer, wherein the first pointer is a pointer for the slave end to write data into the asynchronous FIFO, and the first pointer and the second pointer are pointers synchronized across clock domains; The Slave end and the Master end are the two ends of the asynchronous bridge; the Slave end is used to receive data from the upstream system of the asynchronous bridge, and to package and splice the data; the Master end is used to receive the packaged and spliced ​​data from the Slave end, and when the asynchronous FIFO is in a non-empty state, split the data and transmit it to the downstream system of the asynchronous bridge.

6. The method according to claim 5, characterized in that The N bits are arranged in order from right to left; The shifting of the second pointer comprises: The second pointer is shifted for the i-th time by changing the value of the i-th bit among the N bits and maintaining the values ​​of the bits among the N bits except the i-th bit.

7. The method according to claim 5, characterized in that The step of determining whether the asynchronous FIFO is in a non-empty state based on the first pointer and the second pointer includes: If the first bit in the first pointer and the second bit in the second pointer have the same value, determining that the asynchronous FIFO is in a non-empty state; If the values ​​of the first bit in the first pointer and the second bit in the second pointer are different, determining that the asynchronous FIFO is in an empty state; The second bit is the bit that is shifted for the i-th time on the second pointer, and the first bit is the bit in the first pointer that has the same position as the second bit.

8. The method according to any one of claims 5 to 7, characterized in that The method further comprises: When the asynchronous FIFO is in an empty state, the second state bit of the second pointer is set, and the set second state bit is used to indicate that the asynchronous FIFO is in an empty state.

9. An asynchronous data transmission device, characterized in that: include: An execution module and a determination module; The execution module is used for shifting a first pointer when a Slave end receives a write instruction, the first pointer being a pointer for the Slave end to write data into an asynchronous first-in-first-out FIFO, the first pointer comprising N bits, the bit changed by the i+1th shift of the first pointer being the bit adjacent to the left of the bit changed by the ith shift of the first pointer, N being an integer greater than 1, 1≤i≤N; The determination module is used to determine whether the asynchronous FIFO is in a non-full state based on the first pointer and the second pointer obtained by the execution module, the second pointer is a pointer for the Master end to read data from the asynchronous FIFO, and the first pointer and the second pointer are pointers synchronized across clock domains.

10. An asynchronous data transmission device, characterized in that: include: An execution module and a determination module; The execution module is used for shifting a second pointer when the master receives a read instruction, the second pointer being a pointer for the master to read data from the asynchronous first-in-first-out FIFO, the second pointer comprising N bits, the bit for which the second pointer is shifted for the i+1th time being the bit adjacent to the left of the bit for which the second pointer is shifted for the ith time, N being an integer greater than 1, 1≤i≤N; The determination module is used to determine whether the asynchronous FIFO is in a non-empty state based on a first pointer and a second pointer, wherein the first pointer is a pointer for the Slave end to write data into the asynchronous FIFO, and the first pointer and the second pointer are pointers synchronized across clock domains.

11. An electronic device, characterized in that: It includes a processor and a memory, the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, it implements the steps of the asynchronous data transmission method as described in any one of claims 1-4, or implements the steps of the asynchronous data transmission method as described in any one of claims 5-8.

12. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the asynchronous data transmission method as described in any one of claims 1-4 are implemented, or the steps of the asynchronous data transmission method as described in any one of claims 5-8 are implemented.

13. A computer program product, characterized in that The program product is stored in a storage medium, and the program product is executed by at least one processor to implement the asynchronous data transmission method according to any one of claims 1 to 4, or to implement the asynchronous data transmission method according to any one of claims 5 to 8.

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