Automatic identification methods, systems, devices and media for asynchronous serial communication protocols

Abstract

The present invention relates to the field of asynchronous serial communication technology, and specifically to an asynchronous serial communication protocol automatic identification method, system, device and medium, which can calculate the baud rate of the protocol by using the time difference of pulses of different widths; use the high-frequency logic circuit of programmable logic to quickly compare the data in the cache, and the identification speed is relatively fast, which is very beneficial for on-site equipment layout and application scenarios where the protocol is unknown. The present invention can calculate the baud rate by sampling 3-6 low pulse width counts, and calculate the minimum unit value by using the different length values ​​of the 3-6 pulses themselves and the difference between them; use the time difference of pulses of different widths to calculate the baud rate of the protocol, and then cache the online data into a programmable logic device according to the baud rate, and use the high-frequency logic circuit of programmable logic to quickly compare the data in the cache, thereby obtaining the data format and finally completing the protocol identification.

Description

Technical Field

[0001] This invention relates to the field of asynchronous serial communication technology, and specifically to an automatic identification method, system, device, and medium for asynchronous serial communication protocols. Background Technology

[0002] Asynchronous serial communication is widely used in electronic devices, typically for low-speed data transmission and device debugging. Currently, the common practice is to pre-determine the sending baud rate and have the receiving end receive at a fixed rate; or to pre-determine the required baud rate for the receiving end and have the user send at the specified baud rate. However, this approach is cumbersome, has poor scalability, and is prone to data anomalies due to oversight.

[0003] Currently, some serial communication protocol automatic identification technologies can automatically identify the baud rate and data format of a protocol after receiving a certain amount of communication data, thus eliminating the need for setup. These technologies can directly parse the standard baud rate, achieving frame synchronization and speed matching, and completely reproducing real-time data. However, this method still has significant limitations. Specifically, by setting a threshold for baud rate calculation, the parsing process is initiated only when the threshold is reached. This can easily lead to redundant calculations, or even erroneous calculations, wasting computation time and failing to guarantee the accuracy and precision of the identification. Summary of the Invention

[0004] In view of this, the present invention provides an automatic identification method, system, device and medium for asynchronous serial communication protocols, which can calculate the baud rate of the protocol using the time difference of pulses of different widths; it uses a high-frequency logic circuit of programmable logic to quickly compare the data in the cache, resulting in a fast identification speed, which is very beneficial for field equipment deployment and application scenarios where the protocol is unknown.

[0005] To achieve the above objectives, this invention provides an automatic identification method for asynchronous serial communication protocols, which first obtains the baud rate and then identifies the data format; wherein the baud rate is obtained in the following way:

[0006] By acquiring 3-6 low-pulse signals of different widths, the duration of a single-bit signal can be calculated. The reciprocal of the single-bit duration is the baud rate. Specifically, acquire the widths t1, t2, and t3 of the three low-pulse signals on the signal line. If the single-bit count can be calculated, output the result; otherwise, continue acquiring t4, t5, and t6 one by one. If the single-bit count can be calculated during the acquisition process, output the result and stop acquiring.

[0007] In the identification of data format, according to the protocol standard, the start bit is low, followed by data, and finally the stop bit, with the length of the data in between unknown. Then, different data lengths are compared with the existing data. If they conform to the standard, the length used in the current communication is confirmed and the word length is output. Otherwise, the bit length is incremented by 1 and written back to the FIFO. Then, it is processed according to the word length n. It is determined whether the start bit plus n bits after excluding the start and end bits is the stop bit. If so, the word length is confirmed and output. Otherwise, the bit length is incremented by 1 and the process is repeated until the word length is confirmed and output.

[0008] If there are several different word lengths, multiple comparisons are performed when comparing the existing data with different data lengths. Each time data is read out, it is written back to the FIFO for use next time.

[0009] In the identification of data word length in UART serial communication, the data on the line is continuously and temporarily stored in FIFO according to the baud rate. FIFO contains some redundant free bits.

[0010] Among them, programmable logic devices are used to obtain the low pulse signal width on the signal line.

[0011] The present invention also provides an automatic identification system for asynchronous serial communication protocols, including a baud rate acquisition module circuit and a data format identification unit;

[0012] The baud rate acquisition unit is used to acquire the baud rate. It mainly consists of registers and a divider IP to form the baud rate acquisition module circuit. Multiple registers store multiple values, and the divider is used to identify each integer multiple value. The data format recognition unit is used to identify the data format according to the protocol standard. The start bit is low level, followed by the data, and the stop bit is last. The length of the data in the middle is obtained by the word length recognition module. The baud rate acquisition module circuit is implemented by constructing the logic circuit using a programmable logic device FPGA.

[0013] The word length recognition module includes a FIFO module, a sampling module, a read / write control module, and a comparison module.

[0014] The FIFO module utilizes the internal storage resources of the FPGA and is implemented in IP form. The FIFO module stores the raw data sampled from the UART bus.

[0015] The sampling module samples the data from the UART bus based on the BPS and writes it into the FIFO. During sampling, a counter is used to cycle from 0 to the BPS count. Data is sampled when the BPS count is 50%. Another counter is also included to eliminate interference from redundant idle bits. After sampling 10 consecutive high-level bits, subsequent high-level bits are not written to the FIFO until a low-level bit is sampled.

[0016] The read / write control module reads data from the FIFO and then writes it back into the FIFO;

[0017] The comparison module's function is to compare the long string of data in the FIFO byte by byte according to the UART data format. If all match, the UART data format is obtained. During the comparison process, the data length is changed, and each length is compared with the entire FIFO data. If there is no match or the matching length is greater than one, the entire recognition process needs to be restarted.

[0018] The read / write control module and the comparison module include two counters: one for writing back to the FIFO and the other for comparing data in a single operation. When reading data, the corresponding length of data is read out one by one according to the set word length and output to the comparison module. If the model comparison fails halfway, the remaining data is read out and written back continuously.

[0019] The comparison module includes a parity check unit, which is calculated according to the formula parity=data[0]^data[1]^…^data[n], where n is the assumed data length. If the data length matches, the parity check result is counted, and all results are 0 or 1, corresponding to even or odd checks respectively. If this rule is not met, there is no check.

[0020] The present invention also provides an electronic device, the electronic device including a processor and a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the instructions to implement the asynchronous serial communication protocol automatic identification method of the present invention.

[0021] The present invention also provides a computer-readable storage medium storing a computer program for executing the asynchronous serial communication protocol automatic identification method described in this invention.

[0022] Beneficial effects:

[0023] 1. This invention's method only requires sampling 3-6 low-pulse width counts to calculate the baud rate. It uses the different lengths of these 3-6 pulses and their differences to calculate the minimum unit value; the time difference between pulses of different widths is used to calculate the protocol's baud rate; and based on this baud rate, the online data is buffered in a programmable logic device. The high-frequency logic circuitry of the programmable logic device quickly compares the buffered data to obtain the data format, ultimately completing protocol identification. This invention can potentially meet the requirements with only 2-3 bytes of asynchronous online signal transmission, offering fast identification speeds and being highly advantageous for field equipment deployment and applications where the protocol is unknown.

[0024] 2. In the method of this invention, programmable logic devices are used for rapid sampling to obtain a relatively accurate pulse time count; data format recognition only caches data once, and valid data is repeatedly used after caching until a matching data word length is found and parity bit and stop bit information are obtained; when the programmable logic device processes the cached data, it uses a high-frequency circuit, and only requires 1-2 bit time to complete the processing. If the cached data is small and no result can be obtained, the next round of recognition can be started quickly.

[0025] 3. In the method of the present invention, there is no need to wait for the UART bus to be idle, and it can be identified at any time. There is no need to find the start bit or wait for a single bit pulse signal.

[0026] 4. The system of this invention is used to implement the method of this invention. The baud rate can be calculated by sampling 3-6 low-pulse width counts. The minimum unit value is calculated using the different lengths of the 3-6 pulses and their differences. The baud rate of the protocol is calculated using the time difference of pulses with different widths. Based on this baud rate, the online data is cached in a programmable logic device. The high-frequency logic circuit of the programmable logic device is used to quickly compare the data in the cache, thereby obtaining the data format and finally completing the protocol identification. This invention can potentially meet the requirements with only 2-3 bytes of asynchronous online signal transmission, resulting in fast identification speed. This is highly beneficial for field equipment deployment and applications where the protocol is unknown.

[0027] 5. In the system of this invention, programmable logic devices are used for rapid sampling to obtain a relatively accurate pulse time count; data format recognition only caches data once, and valid data is repeatedly used after caching until a matching data word length is found and parity bit and stop bit information are obtained; when the programmable logic device processes the cached data, it uses a high-frequency circuit, and only requires 1-2 bit time to complete the processing. If the cached data is small and no result can be obtained, the next round of recognition can be started quickly.

[0028] 6. In the system of the present invention, there is no need to wait for the UART bus to be idle, and it can be identified at any time. There is no need to find the start bit or wait for a single bit pulse signal. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a typical data frame format for a UART serial port.

[0030] Figure 2 This is a schematic diagram of the baud rate processing flow in an embodiment of the method of the present invention.

[0031] Figure 3 This is a schematic diagram of three low pulses of the serial port signal in an embodiment of the method of the present invention.

[0032] Figure 4This is a schematic diagram of the internal logic of the character length recognition module of the present invention.

[0033] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0034] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0035] Asynchronous serial communication uses RS232, RS485, and RS422 electrical signals, which are converted to TTL signals after electrical conversion. This is generally called UART serial communication, and its typical data frame format is as follows: Figure 1 As shown. Figure 1 The format represents 8 bits of data, plus one start bit and one stop bit. The protocol standard supports 5-8 bits of data. 5 bits do not support parity checking, while 8 bits can have an additional parity bit. The start bit is represented by a low level, and the stop bit by a high level, supporting lengths of 1, 1.5, and 2 bits. When the communication bus is idle, it is represented by a high level, with no change in the stop bit.

[0036] This invention provides an automatic identification method for asynchronous serial communication protocols, which first obtains the baud rate and then identifies the data format.

[0037] The baud rate acquisition fully utilizes the characteristic in UART serial communication that the width of all low pulse signals is an integer multiple of the width of a single bit signal. By acquiring 3-6 low pulse signals of different widths, the duration of a single bit signal can be calculated, and the reciprocal of the single bit duration is the baud rate. Specifically, the baud rate processing flow is as follows: Figure 2 As shown, the process includes the following steps: Using a programmable logic device, acquire the widths t1, t2, and t3 of three low-pulse signals on the signal line. If a single-bit count can be calculated, output the result; otherwise, continue acquiring t4, t5, and t6 one by one. During the acquisition process, if a single-bit count can be calculated, output the result and stop acquiring. The key to obtaining the result is that, under certain conditions, the ratio of n counts with different widths is unique. A specific example is given below:

[0038] exist Figure 2In the serial port input, three low pulse signal width counts t1, t2, and t3 can be obtained. First, sort them by size, resulting in t3 > t1 > t2, and obtain two differences ta = t3 - t1 and tb = t1 - t2. Then sort them again, resulting in t3 > t1 > t2 > ta = tb. Assuming that the value of tmin (i.e., the minimum value, which is ta and tb) is 1 times the value of a single bit, the ratio of t3, t1, t2, ta, and tb is 4:3:2:1:1 or 8:6:4:2:2 (tmin is twice the value of a single bit), and cannot be 12:9:6:3:3, because the longest low level is 10 bits, which includes 1 start bit, 8 data bits, and 1 parity bit. Based on the above counts t1, t2, and t3, it is impossible to obtain a single-bit count. Therefore, another count t4 needs to be obtained. t4 is not equal to any of t1, t2, and t3. If it is equal to ta, then the ratio of multiple pulse widths still has two possibilities, and no result can be obtained. At this time, t5 is obtained. If its value is 5 times tmin, then the obtained ratio is 5:4:3:2:1:1:1, or it could be 10:8:6:4:2:2:2, which is the most extreme case. Then, t6 is obtained, which requires a width different from t1-t5. Therefore, the obtained pulse width must be between 6 and 10 times a single bit, and the obtained ratio is unique, thus obtaining the single-bit width duration count. In another scenario, if the ratio of t3, t1, and t2 is 8:5:3, then t4 is not needed to obtain the single-bit duration. Under this ratio, the minimum tmin = t1 - t2. If set to 1 times the single bit, the ratio becomes 4:2.5:1.5:1.5:1, which does not meet the requirement of being an integer multiple of the single bit. If tmin is set to 2 times the single bit, the ratio becomes 8:5:3:3:2, which perfectly satisfies the requirement. In the embodiment of the method of this invention, the three low pulses of the serial port signal are as follows... Figure 3 As shown.

[0039] In identifying the data format, according to the protocol standard, the start bit is low, followed by the data, and finally the stop bit, with the length of the data in between unknown. Then, different data lengths are compared with existing data. If the data conforms to the standard, the length used in the current communication is confirmed, and the word length is output. Otherwise, the bit length is incremented by 1 and written back to the FIFO. Then, the data is processed according to word length n, checking if the start bit plus n bits equals the stop bit. If so, the word length is confirmed and output; otherwise, the bit length is incremented by 1, and this process is repeated until the word length is confirmed and output. Because several different word lengths exist, multiple comparisons may be necessary, and each time data is read, it needs to be written back to the FIFO for future use. Specifically, in this embodiment, we first assume n is the data length. A data length n is read out at once, and the last bit is checked for high-order bits. If it is high-order, the next data length is read, and this process is repeated until the entire FIFO space is read. If all reads match, the data is confirmed. If any reads do not match, the next length is checked (i.e., the data length is n+1), and the last bit is checked for high-order bits, performing the same operation as the previous word length. After multiple rounds of reading and comparison, the data length is obtained. In UART serial communication, the data word length is identified by continuously storing the data on the line into a FIFO (First-In-First-Out memory in FPGA) according to the baud rate. This data will be used later. When reading the FIFO output data, it needs to be written back to the FIFO. This embodiment uses a front-end / back-end cyclic read / write mechanism. To avoid missing valid data, the FIFO will contain some redundant empty bits.

[0040] The present invention also provides an asynchronous serial communication protocol automatic identification system for identifying the method of the present invention, including a baud rate acquisition module circuit and a data format identification unit.

[0041] The baud rate acquisition unit is used to acquire the baud rate, and all functions are implemented through logic circuits built using a programmable logic device (FPGA). In baud rate acquisition, a high-frequency sampling clock is needed to obtain the width counts of different low-frequency pulses. If the frequency is too low, the sampled counts will be small, resulting in larger calculation errors and lower accuracy. This invention's system mainly uses registers and a divider IP to construct the baud rate acquisition module circuit. Multiple registers store multiple values, and the divider is used to identify various integer multiple ratios. According to the baud rate acquisition principle in the method, tmin is used as the divisor, and the other terms tn (referring to other pulse width counts) are used as dividends. The divider obtains several quotients, thus obtaining the ratio relationship. tmin can only be 1, 2, or 3 times the single-bit count, and the remainder produced by the division operation can only be 0, 1 / 2, 1 / 3, and 2 / 3. In actual operation, the integer ratio is obtained accordingly.

[0042] The data format recognition unit identifies the data format according to the protocol standard. The start bit is low, followed by the data, and finally the stop bit. The length of the data in between is obtained through the word length recognition module. The functional block diagram of the word length recognition module is shown below. Figure 4 As shown, it includes a FIFO module, a sampling module, a read / write control module, and a comparison module.

[0043] The FIFO module utilizes the internal storage resources of the FPGA and is implemented in IP form. The FIFO module mainly stores the raw data sampled by the UART bus. Its independent read / write ports and first-in-first-out method are particularly suitable for serial data processing.

[0044] The main function of the sampling module is to sample data from the UART bus based on the BPS and write it to the FIFO. Sampling is primarily achieved through a counter that cycles from 0 to the BPS count, sampling data when the BPS count reaches 50%. Additionally, a counter is needed to eliminate interference from redundant idle bits (due to potential long waiting times between asynchronously transmitted bytes). Therefore, after sampling 10 consecutive high-level bits, subsequent high-level bits are not written to the FIFO until a low-level bit is sampled, at which point writing resumes.

[0045] The main function of the read / write control module is to read data from the FIFO and write it back to the FIFO. The purpose of writing back is to ensure that the data is used multiple times and remains unchanged, without any shift at the beginning or end.

[0046] The comparison module's function is to compare the long string of data in the FIFO byte by byte according to the UART data format. If all match, the UART data format is determined. During the comparison process, the data length needs to be changed, and each length is compared with the entire FIFO stored data separately. If no match is found or the matching length is greater than one, the entire recognition process needs to be restarted.

[0047] The comparison module includes a parity check unit, which calculates parity according to the formula parity = data[0]^data[1]^…^data[n], where n is the assumed data length. If the data length matches, the parity check result is counted, and all results are 0 or 1, corresponding to even or odd checks respectively. If this rule is not met, there is no check.

[0048] The read / write control module and the comparison module require two counters: one for writing back to the FIFO and the other for comparing data in a single operation. When reading data, the corresponding length of data is read out one by one according to the set word length and output to the comparison module. If the model comparison fails halfway, then the remaining data only needs to be read out and written back continuously.

[0049] Furthermore, there may be extra high levels between the two compared word lengths. This is because the sampling module samples extra data to avoid losing actual data. However, during the comparison, the extra data needs to be discarded.

[0050] This application also provides an electronic device. Figure 5 The structure of an electronic device provided in an embodiment of the present invention is illustrated. For example, the electronic device 50 may include a processor 51, a memory 52, and a transmission device 53. The processor 51 is used to execute the asynchronous serial communication protocol automatic identification method mentioned in the above embodiments. The processor and the memory can be connected via a bus or other means, taking a bus connection as an example. The transmission device can be connected to the processor and the memory via wired or wireless means. The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the asynchronous serial communication protocol automatic identification method in the embodiments of this application. The processor executes various functional applications and data processing by running the non-transitory software programs, instructions, and modules stored in the memory, thereby realizing the asynchronous serial communication protocol automatic identification method in the above method embodiments. The memory may include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a function; the data storage area may store data created by the processor, etc. In addition, the memory may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, and this remote memory may be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The one or more modules stored in the memory, when executed by the processor, perform the asynchronous serial communication protocol automatic identification method described in the embodiments.

[0051] In another aspect, this application also provides a computer-readable storage medium, which may be the computer-readable storage medium included in the apparatus described in the above embodiments; or it may be a standalone computer-readable storage medium not assembled into the device. The computer-readable storage medium may be a tangible storage medium, such as random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, floppy disk, hard disk, removable storage disk, CD-ROM, or any other form of storage medium known in the art. The computer-readable storage medium stores one or more programs, which are used by one or more processors to execute the asynchronous serial communication protocol automatic identification method described in this application.

[0052] In summary, the above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An automatic identification method for asynchronous serial communication protocols, characterized in that, First, obtain the baud rate, then identify the data format; the method for obtaining the baud rate is as follows: By acquiring 3-6 low-pulse signals of different widths, the duration of a single-bit signal can be calculated. The reciprocal of the single-bit duration is the baud rate. Specifically, acquire the widths t1, t2, and t3 of three low-pulse signals on the signal line. If the single-bit count can be calculated, output the result; otherwise, continue acquiring t4, t5, and t6 one by one. If the single-bit count can be calculated during the acquisition process, output the result and stop acquiring. In identifying the data format, according to the protocol standard, the start bit is low, followed by the data, and finally the stop bit, with the length of the data in between unknown. Then, different data lengths are compared with the existing data. If the data conforms to the standard, it is the length currently used for communication, and the word length is confirmed and output. Otherwise, the bit length is incremented by 1 and written back to the FIFO. Then, it is processed according to the word length n, and it is determined whether the start bit plus n bits after excluding the start and end bits is the stop bit. If so, the word length is confirmed and output. Otherwise, the bit length is incremented by 1 and the process is repeated until the word length is confirmed and output.

2. The method as described in claim 1, characterized in that... If there are several different word lengths, multiple comparisons are performed when comparing the existing data with different data lengths. Each time data is read out, it is written back to the FIFO for use next time.

3. The method as described in claim 2, characterized in that, In UART serial communication, the data word length is identified by continuously storing the data on the line into a FIFO according to the baud rate. The FIFO contains some redundant free bits.

4. The method according to any one of claims 1-3, characterized in that, The low pulse signal width on the signal line is obtained using a programmable logic device.

5. An automatic identification system for asynchronous serial communication protocols, characterized in that, This includes a baud rate acquisition unit and a data format recognition unit; The baud rate acquisition unit is used to acquire the baud rate. This unit includes registers and a divider IP. Multiple registers store multiple values, and the divider identifies the integer multiples of each value. The data format recognition unit identifies the data format according to the protocol standard. The start bit is low, followed by the data, and finally the stop bit. The data length is obtained through a word length recognition module. The baud rate acquisition unit is implemented using a programmable logic device (FPGA) to construct the logic circuit. The baud rate is acquired in the following way: By acquiring 3-6 low-pulse signals of different widths, the duration of a single-bit signal can be calculated. The reciprocal of the single-bit duration is the baud rate. Specifically, acquire the widths t1, t2, and t3 of the three low-pulse signals on the signal line. If the single-bit count can be calculated, output the result; otherwise, continue acquiring t4, t5, and t6 one by one. If the single-bit count can be calculated during the acquisition process, output the result and stop acquiring.

6. The system as described in claim 5, characterized in that, The data format recognition unit includes a FIFO module, a sampling module, a read / write control module, and a comparison module; The FIFO module utilizes the internal storage resources of the FPGA and is implemented in IP form. The FIFO module stores the raw data sampled from the UART bus. The sampling module samples the data from the UART bus based on the BPS and writes it into the FIFO. During sampling, a counter is used to cycle from 0 to the BPS count. Data is sampled when the BPS count is 50%. Another counter is also included to eliminate interference from redundant idle bits. After sampling 10 consecutive high-level bits, subsequent high-level bits are not written to the FIFO until a low-level bit is sampled. The read / write control module reads data from the FIFO and then writes it back into the FIFO; The comparison module's function is to compare the long string of data in the FIFO byte by byte according to the UART data format. If all match, the UART data format is obtained. During the comparison process, the data length is changed, and each length is compared with the entire FIFO data. If there is no match or the matching length is greater than one, the entire recognition process needs to be restarted. The read / write control module and the comparison module include two counters: one for writing back to the FIFO and the other for comparing data in a single operation. When reading data, the corresponding length of data is read out one by one according to the set word length and output to the comparison module. If the model comparison fails halfway, the remaining data is read out and written back continuously.

7. The system as described in claim 5 or 6, characterized in that, The comparison module has a parity check unit, which is calculated according to the formula parity=data[0]^data[1]^…^data[N], where N is the assumed data length; if the data length matches, the parity check result is counted, and all are 0 or 1, corresponding to even or odd checks respectively. If this rule is not met, there is no check.

8. An electronic device, characterized in that, The electronic device includes a processor and a memory for storing executable instructions of the processor; the processor is configured to read the executable instructions from the memory and execute the instructions to implement the asynchronous serial communication protocol automatic identification method according to any one of claims 1-4.

9. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which is used to execute the asynchronous serial communication protocol automatic identification method according to any one of claims 1-4.

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