Array receiver multi-path DDC synchronous acquisition output system and implementation method

Abstract

The application discloses a kind of array receiver multi-path DDC synchronous acquisition output system and implementation method, its system includes main channel receiver, array processing board and auxiliary channel receiver, and reception channel is equipped by radio frequency and digital processing module on main channel receiver and auxiliary channel receiver;The application adopts synchronous interface design, utilizes asynchronous serial communication protocol with synchronous pulse, realizes multi-path DDC data synchronous control and state return, is realized with few control line, and wiring is simple and low in cost, and using array receiver address coding and the design of synchronous pulse time slot, the state return and instruction control of multiple reception channels and multiple DDC data are well solved, in addition, priority arbitration mechanism is used, the multi-path DDC multiple sampling rate data transmission flow control of array receiver is solved, avoids the problem of data loss caused by buffer overflow, has data buffer state monitoring function, and improves buffer utilization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data synchronization acquisition and output, and particularly relates to a multi-channel DDC synchronization acquisition and output system of an array receiver and an implementation method. BACKGROUND

[0002] A receiver is the most commonly used receiving equipment in the field of radio electromagnetic spectrum monitoring. It can express the electrical signal received by an antenna in the form of a frequency spectrum through amplification, filtering, frequency conversion, sampling, signal processing and other circuits, so as to monitor the activities of radio signals in the sky.

[0003] DDC is the abbreviation of digital down converter. The intermediate frequency signal of a digital receiver is converted into a digital signal through an analog-to-digital converter, and a baseband digital signal can be obtained through DDC processing, which can be used for digital demodulation and various signal parameter measurement. DDC processing includes processes such as quadrature digital mixing, digital filtering and sampling rate conversion.

[0004] An array receiver refers to an electronic device for receiving wireless signals composed of multiple receivers that are used for the same local oscillator or clock source and receive the same frequency signal. It has the characteristics of synchronous acquisition of multiple receivers and consistency of amplitude and phase, and can be used for radio direction finding and beam synthesis. The synchronization control uses a synchronization control interface, which generally includes a synchronization trigger pulse and a synchronization instruction, and is generally realized by a hardware interface through a synchronization control line for interconnection between devices.

[0005] In order to meet the current demand for more signals in radio monitoring, the array receiver is required to receive multiple radio signals at the same time, which is usually realized by using a multi-channel digital DDC method. With the increase in the number of DDC channels, the design of the synchronization control interface control becomes more complex and difficult, involving the synchronization of acquisition and data packaging of each DDC. Since the sampling rates of each DDC are different due to different bandwidths, and the data buffer space provided by the hardware FPGA is limited, it is necessary to carefully design the control instruction transceiver word length and instruction transmission speed, as well as the control packaging process, in order to ensure the complete and stable output of data without overflow or packet loss.

[0006] At present, an array receiver is composed of a master control device and a multi-channel receiver. The master control device is used for synchronization control instruction transceiving, and the multi-channel receiver is used for receiving multiple antenna signals. The master control device and the multi-channel receiver are connected through a synchronization control interface in a cascading manner. The master control device provides a clock to the multi-channel receiver, so that the clock of the multi-channel receiver is guaranteed to be the same source. The synchronization control interface includes synchronization trigger pulses, control instructions, state returns and other signals. These signals are usually transmitted in the form of differential pairs. The control instructions are transmitted in the form of synchronous serial instructions to ensure the reliability of instruction transmission. The synchronization control process of the master control device on the array receiver is as shown in Figure 1 .

[0007] The synchronous control mode controls the interface communication protocol simply, can only control one DDC synchronous output, cannot realize multi-channel DDC synchronous output, and has simple control flow, no handshake response mechanism, cannot realize accurate control, lacks data buffer state monitoring, has low buffer utilization rate, is easy to overflow, and lacks transmission priority processing mechanism, which is easy to cause data loss. SUMMARY

[0008] In view of the above problems, the present application aims to provide an array receiver multi-channel DDC synchronous acquisition output system and implementation method to solve the problems of the existing array receiver synchronous control mode, such as simple control interface communication protocol, which leads to the inability to realize multi-channel DDC synchronous output, the inability to realize accurate control, the lack of data buffer state monitoring, the low buffer utilization rate, the easy overflow, and the data loss.

[0009] In order to achieve the purpose of the present application, the present application realizes the following technical scheme: an array receiver multi-channel DDC synchronous acquisition output system, comprising a main channel receiver, an array processing board and an auxiliary channel receiver, wherein the main channel receiver and the auxiliary channel receiver are each provided with a receiving channel composed of a radio frequency and a digital processing module, the main channel receiver is connected with the array processing board through a first synchronous control interface and connected with the second synchronous control interface on the auxiliary channel receiver, the main channel receiver is provided with a first main RS485 transceiver circuit, a second main RS485 transceiver circuit, a time code conversion module, a synchronous control module and a main dial switch, the first synchronous control interface is composed of the second main RS485 transceiver circuit, the synchronous control module and the main dial switch on the main channel receiver, the second synchronous control interface connection on the array processing board and the auxiliary channel receiver is composed of a slave RS485 transceiver circuit, a slave dial switch and a synchronous logic processing module, and the main channel receiver and the auxiliary channel receiver transmit data to the array processing board through their respective high-speed AURORA optical ports, wherein the transmitted data includes 1 wideband phase data, 4 narrowband IQ data and 48 voice DDC IQ data.

[0010] Further improvement lies in that the first synchronous control interface is provided with 4 pairs of RS485 differential lines, which are respectively used for outputting time mark information, synchronous control commands and synchronous pulses of the main channel receiver and inputting state information returned by each auxiliary channel according to the allocated time slot.

[0011] Further improvement lies in that the sampling rate of the 1 wideband phase data is 256Mp / s when the maximum bandwidth is 200MHz, and the bit width of each sample point is 16bit, so that the maximum flow is 256X2=512MB / s=4096Mb / s.

[0012] A further improvement is that the four narrowband IQ data channels include nine bandwidths, with the IQ data sampling rate at the maximum bandwidth of 5MHz being 6.4Mp / s. The bit width of each sample point is 16 bits for both I and Q, so the maximum data throughput is 6.4 x 4 = 25.6 MB / s = 204.8 Mb / s.

[0013] A further improvement is that the IQ data of the 48-channel voice DDC includes 14 bandwidths, with the IQ data sampling rate at the maximum bandwidth of 25kHz being 32kp / s. The bit width of each sample point is 32bit for both I and Q, so the maximum data throughput is 32 x 8 = 256kB / s = 2048kb / s.

[0014] Further improvements are made in the following ways: The first synchronization control interface uses the SYNC_TXD_CODE differential pair to transmit the time code signal generated by the host through the second pulse, time code signal and millisecond counter, uses the SYNC_TXD differential pair to transmit the command information output by the host synchronization control interface, uses the SYNC_PULSE differential pair to transmit the synchronization pulse signal after the command information output by the main synchronization control interface, and uses the SYNC_RXD differential pair to transmit the status information reported by each auxiliary machine to the host.

[0015] A method for implementing synchronous acquisition and output of multiple DDC channels in an array receiver includes the following steps:

[0016] Step 1: After receiving the synchronization control signal, the synchronization control module in the main channel receiver generates synchronization control signals for each sub-module, packages the data and transmits it, and uses the synchronization control signals to perform synchronization control on each module respectively.

[0017] Step 2: When each module receives synchronization control, each channel receives a synchronization command. Each synchronization module performs synchronization processing according to the synchronization command, and ensures that data from each channel is collected and transmitted simultaneously through synchronization triggering.

[0018] Further improvements are made in the following steps: In step one, the synchronization control of each module includes resetting the AD data receiving module, resetting the register, adjusting the RF gain control, resetting the DDR3 cache, resetting the broadband DDC, resetting the channelized DDC, resetting the broadband spectrum calculation synchronously, resetting the 48-channel voice DDC synchronously, resetting the 4-channel digital DDC synchronously, and resetting the packet control module synchronously.

[0019] The beneficial effects of this invention are as follows: This invention adopts a synchronous interface design and utilizes an asynchronous serial communication protocol with synchronous pulses to achieve synchronous control and status return of multiple DDC data channels. It is implemented with very few control lines, resulting in simple wiring and low cost. Furthermore, the design of array receiver address encoding and synchronous pulse time slots effectively solves the status return and command control of multiple receiving channels and multiple DDC data channels. It has a handshake response control mechanism to achieve precise control. In addition, it adopts a priority arbitration mechanism to solve the data transmission flow control of multiple DDC data channels with multiple sampling rates in the array receiver, avoiding buffer overflow and data loss problems. It also has a data buffer status monitoring function, which improves buffer utilization. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the synchronous acquisition and output system structure in an embodiment of the present invention;

[0022] Figure 2 This is a timing diagram of the first synchronization control interface in an embodiment of the present invention;

[0023] Figure 3 This is a communication format diagram of the 8-bit UART communication protocol in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the synchronization control principle of the main channel receiver and the auxiliary channel receiver in an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of the data packaging and transmission process in an embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Example 1

[0028] See Figure 1 , Figure 2 , Figure 3This embodiment provides a multi-channel DDC synchronous acquisition and output system for an array receiver, including one main channel receiver, one array processing board, and four auxiliary channel receivers. Both the main channel receiver and the auxiliary channel receivers have receiving channels, including radio frequency and digital processing modules. The output data is transmitted to the array processing board via a high-speed data interface, corrected, packaged, and then output via 10 Gigabit Ethernet. The main channel receiver has a first synchronization control interface, and both the array processing board and the auxiliary channel receivers have second synchronization control interfaces. The connection between the main channel receiver, the array processing board, and the auxiliary channel receivers is achieved through the first and second synchronization control interfaces. The system includes a first master RS485 transceiver circuit, a second master RS485 transceiver circuit, a time code conversion module, a synchronization control module, and a master DIP switch. The second master RS485 transceiver circuit, the synchronization control module, and the master DIP switch together form the first synchronization control interface. The array processing board and the auxiliary channel receiver each have a slave RS485 transceiver circuit, a slave DIP switch, and a synchronization logic processing module, which together form the second synchronization control interface. The master channel receiver and the auxiliary channel receiver transmit data to the array processing board via their respective high-speed AURORA optical ports. The transmitted data includes one channel of broadband phase data, four channels of narrowband IQ data, and 48 channels of voice DDC IQ data.

[0029] The first synchronization control interface is equipped with four pairs of RS485 differential lines, which are used by the main channel receiver to output time stamp information, synchronization control commands and synchronization pulses, and to input the status information (including AD energy detection status) returned by each auxiliary channel according to the allocated time slot.

[0030] The sampling rate of one-channel broadband phase data at a maximum bandwidth of 200MHz is 256Mbps, and the bit width of each sample point is 16 bits. Therefore, the maximum throughput is 256 x 2 = 512MB / s = 4096Mb / s. Adding the packet header information increases the throughput by 3.03%, resulting in an actual transmission rate of 4096 * 1.0303 = 4224Mb / s. With a receiving bandwidth of 200MHz and a frequency resolution of 3.125kHz, the maximum number of samples per frame of phase data (16 bits = 2B) is 256 / 0.003125 = 81920, AURORA transmits data in sub-packets of 2112B each. Therefore, one frame of phase data (16 bits = 2B) has 256 / 0.003125 / 1024 = 80 sub-packets. Each sub-packet contains 1024 phase samples. At a resolution of 3.125k, the data sampling time is 1 / 3.125 = 320µs. The transmission time for each sub-packet is less than 4µs. This embodiment requires an AURORA transmission rate greater than 2112 * 8 / 4 = 4.224 Gbps.

[0031] The four narrowband IQ data streams include nine bandwidths. The maximum bandwidth is 5MHz, with an IQ data sampling rate of 6.4Mp / s. Each sample point has a bit width of 16 bits for both I and Q. Therefore, the maximum data throughput is 6.4 x 4 = 25.6 MB / s = 204.8 Mb / s. The transmission rate required for AURORA to transmit four data streams is 4 * 204.8 = 819.2 Mb / s. After adding the packet header information, the throughput increases by 3.03%. The actual required transmission rate is 819.2 * 1.0303 = 844.0218 Mb / s.

[0032] The IQ data of the 48-channel voice DDC includes 14 bandwidths. The IQ data sampling rate at the maximum bandwidth of 25kHz is 32kp / s. The bit width of each sample point is 32bit for both I and Q. Therefore, the maximum data throughput is 32 x 8 = 256kB / s = 2048kb / s. The transmission rate required for AURORA to transmit 48 channels of data is 48 * 2048 = 98.304Mb / s. After adding the packet header information, the throughput increases by 3.03%. The actual transmission rate requirement is 98.304 * 1.0303 = 101.2826Mb / s.

[0033] In this embodiment, the total data flow of the three types transmitted through AURORA by each receiving channel is 4224 + 844.0218 + 101.2826 = 5169.3044 Mb / s. The maximum transmission rate of AURORA is 10 Gb / s, which meets the transmission speed requirement.

[0034] like Figure 2 As shown, the first synchronization control interface uses the SYNC_TXD_CODE differential pair to transmit the time code signal generated by the host through the second pulse, time code signal and millisecond counter. The time code signal contains: year, month, day, hour, minute, second and millisecond, and uses UART serial communication.

[0035] The SYNC_TXD differential pair transmits command information output from the master synchronization control interface and broadcasts it to other slave receivers. The command information is transmitted at a rate of 5 Mbaud using an 8-bit UART communication protocol, with the communication format as follows: Figure 3 As shown;

[0036] The SYNC_PULSE differential pair is used to transmit the synchronization pulse signal after the command information output by the main synchronization control interface. Since the command transmission uses an asynchronous communication protocol, the synchronization pulse is used together to realize the synchronous command transmission and ensure that the command arrives at each device synchronously.

[0037] The SYNC_RXD differential pair is used to transmit the status information reported by each auxiliary receiver to the master. Since multiple auxiliary channel receivers share one differential pair signal line, a time slot needs to be allocated to each auxiliary channel receiver. During power-on initialization, the master channel receiver will allocate time slots to each auxiliary channel receiver according to the number of auxiliary channel receivers. The width of each time slot is one synchronization clock cycle (320us). The synchronization logic processing module of the auxiliary channel receiver determines whether to upload status information within the time slot allocated to its own receiver by monitoring the synchronization clock. The master channel receiver also determines which receiver the received information comes from by using the time slot position.

[0038] See Figure 4 In this embodiment, data packaging includes two levels: channel data packaging and array board data packaging. Data transmitted through each channel is stored in the buffer of each channel board. Each channel needs to transmit 53 data streams, and each type of data requires two 2112-byte buffers. The two buffers switch operations in a ping-pong fashion, allowing data to be stored simultaneously during data transmission to ensure data continuity and prevent loss. The channel board requires a total of 53 * 2112 * 2 bytes of buffer. Data transmission in the first buffer must be completed before the second buffer is full to prevent buffer overflow and data loss. The 53 data streams have different sampling rates; higher sampling rates require less time to fill the buffer, while lower rates take longer. To prevent high-rate data overflow, it should be transmitted first. The array board has superior... The priority arbitration mechanism, based on the readiness status of each channel's data returned by the synchronization control port, triggers the transmission of high-priority data first, ensuring timely transmission of all data. The AURORA receive buffer groups the IQ data from the five channels into packets for the same data path at the same time, processes them through the correction and beamforming modules, and then passes them to the transmit queue buffer module for output from the 10 Gigabit network. The receive buffer packet grouping module and the transmit buffer queue module notify the priority arbitration mechanism of their register status and data processing status. The priority arbitration mechanism, based on the data processing and 10 Gigabit network data transmission status, restricts whether the receive buffer packet grouping restricts the transmission of data through the receive channel, thus acting as a flow limiter to prevent data loss due to buffer overflow caused by the simultaneous arrival of 53 data paths and the inability of data processing and the 10 Gigabit network to transmit.

[0039] Example 2

[0040] See Figure 5 This embodiment provides a method for implementing synchronous acquisition and output of multiple DDC channels in an array receiver, including the following steps:

[0041] Step 1: After receiving the synchronization control signal, the synchronization control module in the main channel receiver generates synchronization control signals for each sub-module. The synchronization control signals are used to perform synchronization control on each module, including AD data receiving module reset, register reset, RF gain control adjustment, DDR3 buffer reset, wideband DDC reset, channelized DDC reset, wideband spectrum calculation synchronization reset, 48-channel voice DDC synchronization reset, 4-channel digital DDC synchronization reset, and packet assembly control module synchronization reset.

[0042] Step 2: When each module receives synchronization control, each channel receives a synchronization command. Each synchronization module performs synchronization processing according to the synchronization command. For example, if the RF gain needs to be synchronized, it is adjusted simultaneously. When the frequency or bandwidth of a certain digital DDC changes, the NCO, filter, decimation rate and other parameters of that DDC are synchronously reset. At the same time, the IQ data packing buffer is cleared. Synchronous triggering ensures that the data of each channel is collected and transmitted simultaneously.

[0043] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-channel DDC synchronous acquisition and output system for an array receiver, characterized in that: The system includes a main channel receiver, an array processing board, and an auxiliary channel receiver. Both the main and auxiliary channel receivers have receiving channels composed of radio frequency and digital processing modules. The main channel receiver is connected to the array processing board and the auxiliary channel receiver via a first synchronization control interface and a second synchronization control interface. The main channel receiver includes a first main RS485 transceiver circuit, a second main RS485 transceiver circuit, a time code conversion module, a synchronization control module, and a main DIP switch. The first synchronization control interface is composed of the second main RS485 transceiver circuit, the synchronization control module, and the main DIP switch on the main channel receiver. The connection between the array processing board and the auxiliary channel receiver's second synchronization control interface consists of a slave RS485 transceiver circuit, a slave DIP switch, and a synchronization logic processing module. The main and auxiliary channel receivers transmit data to the array processing board via their respective high-speed AURORA optical ports. The transmitted data includes one channel of broadband phase data, four channels of narrowband IQ data, and 48 channels of voice DDC IQ data. The control method for the array receiver multi-channel DDC synchronous acquisition and output system includes the following steps: Step 1: After receiving the synchronization control signal, the synchronization control module in the main channel receiver generates synchronization control signals for each sub-module, and packages and transmits the data. The synchronization control signals are used to perform synchronization control on each sub-module, including resetting the AD data receiving module, resetting the register, adjusting the RF gain control, resetting the DDR3 cache, resetting the wideband DDC, resetting the channelized DDC, resetting the wideband spectrum calculation synchronization, resetting the 48-channel voice DDC, resetting the 4-channel digital DDC, and resetting the packet control module. Step 2: When each submodule receives synchronization control, each channel receives a synchronization command. Each synchronization module performs synchronization processing according to the synchronization command, and ensures that data from each channel is collected and transmitted simultaneously through synchronization triggering.

2. The array receiver multi-channel DDC synchronous acquisition and output system according to claim 1, characterized in that: The first synchronization control interface is provided with 4 pairs of RS485 differential lines, which are respectively used by the main channel receiver to output time stamp information, synchronization control commands and synchronization pulses, and to input the status information returned by each auxiliary channel according to the allocated time slot.

3. The array receiver multi-channel DDC synchronous acquisition and output system according to claim 1, characterized in that: The sampling rate of the one-channel broadband phase data at a maximum bandwidth of 200MHz is 256Mp / s, and the bit width of each sample point is 16bit. Therefore, the maximum throughput is 256X2=512MB / s=4096Mb / s.

4. The array receiver multi-channel DDC synchronous acquisition and output system according to claim 1, characterized in that: The four narrowband IQ data streams include nine bandwidths. The maximum bandwidth is 5MHz, and the IQ data sampling rate is 6.4Mp / s. The bit width of each sample point is 16 bits for both I and Q. Therefore, the maximum data throughput is 6.4 x 4 = 25.6MB / s = 204.8Mb / s.

5. The array receiver multi-channel DDC synchronous acquisition and output system according to claim 1, characterized in that: The IQ data of the 48-channel voice DDC includes 14 bandwidths. The IQ data sampling rate is 32kp / s when the maximum bandwidth is 25kHz. The bit width of each sample point is 32bit for I and Q. Therefore, the maximum data throughput is 32 x 8 = 256kB / s = 2048kb / s.

6. The array receiver multi-channel DDC synchronous acquisition and output system according to claim 1, characterized in that: The first synchronization control interface uses the SYNC_TXD_CODE differential pair to transmit the time code signal generated by the host through the second pulse, time code signal and millisecond counter, uses the SYNC_TXD differential pair to transmit the command information output by the host synchronization control interface, uses the SYNC_PULSE differential pair to transmit the synchronization pulse signal after the command information output by the main synchronization control interface, and uses the SYNC_RXD differential pair to transmit the status information reported by each auxiliary machine to the host.

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