Model training method, chip design method, device and electronic device

Abstract

The present application discloses a model training method, a chip design method, an apparatus, and an electronic device. The method includes: obtaining a sample data set for chip design; obtaining a chip design tool and a chip test design use case set; based on the chip design tool, the chip test design use case set, and the sample data set, performing multiple training operations on an initial prediction model until a training end condition is met, to obtain a trained prediction model. For each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design use case conform to the sample optimization target information. The trained prediction model has the ability to predict the setting parameters of the chip design tool, and the predicted tool parameters enable the predicted chip design tool to generate chip design results that conform to the optimization target information.

Description

Technical Field

[0001] This application belongs to the field of artificial intelligence technology, and particularly relates to a model training method, a chip design method, a device, and an electronic device. Background Art

[0002] With the increasing complexity of integrated circuit design and the scale of transistors, the number of setup parameters involved in chip design tools exceeds hundreds. These setup parameters affect and depend on each other, and the combination and values of the setup parameters are extremely important for obtaining the optimal chip design result.

[0003] When automatically generating a chip design, it is usually necessary to optimize multiple objectives simultaneously, such as area, power consumption, performance, etc. Currently, by manually adjusting the setup parameters of the chip design tool, it is difficult for the chip design result to meet the optimization objectives of the chip design. Summary of the Invention

[0004] Embodiments of this application provide a model training method, a chip design method, a device, and an electronic device, which can at least to some extent make the chip design result more in line with the optimization objectives.

[0005] Other features and advantages of this application will become apparent through the following detailed description, or be learned in part through the practice of this application.

[0006] According to the first aspect of the embodiments of this application, a model training method is provided, including:

[0007] Obtain a sample data set for chip design, where the sample data set includes multiple groups of sample data, and each group of sample data includes sample process parameters for chip design and sample optimization target information, and the sample optimization target information includes at least one sample optimization strategy for chip design;

[0008] Obtain a chip design tool and a chip test design case set, where the chip test design case set includes multiple chip test design cases;

[0009] Based on the chip design tool, the chip test design case set, and the sample data set, perform multiple training operations on an initial prediction model until the training end condition is met, to obtain a trained prediction model and sample tool parameters corresponding to each sample data output by the trained prediction model. For each group of sample data, when the sample tool parameters output by the trained prediction model are used as the setup parameters of the chip design tool, the chip design result generated based on each chip test design case meets the sample optimization target information.

[0010] In some possible implementation manners, each training operation includes:

[0011] For each set of sample data, input the sample data into the initial prediction model to obtain sample tool parameters;

[0012] Use the sample tool parameters as the setting parameters corresponding to the current training operation of the chip design tool, and based on the chip design tool, run each chip test design case respectively to obtain each sample chip design result corresponding to the current training operation;

[0013] Based on the sample chip design results corresponding to the executed training operations respectively, adjust the parameters of the initial prediction model, and use the initial prediction model with adjusted parameters as the initial prediction model corresponding to the next training operation.

[0014] In some possible implementation manners, adjusting the parameters of the initial prediction model based on the sample chip design results corresponding to the executed training operations respectively includes:

[0015] For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations respectively, determine the change information of each sample chip design result corresponding to the chip test design case;

[0016] Based on the change information corresponding to each chip test design case of each set of sample data respectively, and the parameter iteration strategy corresponding to the previous training operation, determine the parameter iteration strategy corresponding to the current training operation;

[0017] Based on the parameter iteration strategy corresponding to the current training operation, adjust the parameters of the initial prediction model.

[0018] In some possible implementation manners, the change information includes single - time change information and global change information. For each chip test design case of each set of sample data, determining the change information of the sample chip design results based on the sample chip design results corresponding to the executed training operations respectively includes:

[0019] For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations respectively, determine the distribution information of each sample chip design result, and determine the global change information based on the distribution information of each sample chip design result;

[0020] For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the previous training operation and the sample chip design results corresponding to the current training operation, determine the single - time change information.

[0021] In some possible implementation manners, determining the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each group of sample data and the parameter iteration strategy corresponding to the previous training operation includes:

[0022] For each chip test design case of each group of sample data, if the change information corresponding to the chip test design case conforms to the optimization target information, then use the parameter iteration strategy corresponding to the previous training operation as the parameter iteration strategy corresponding to the current training operation;

[0023] If the change information corresponding to at least a preset number of chip test design cases does not conform to the optimization target information, then adjust the parameter iteration strategy corresponding to the previous training operation to obtain the parameter iteration strategy corresponding to the current training operation.

[0024] In some possible implementation manners, the training end condition includes at least one of the following:

[0025] For each chip test design case of each group of sample data, the sample chip design result corresponding to the current training operation conforms to the corresponding sample target optimization information or conforms to the corresponding reference chip design result;

[0026] The number of times of the training operation reaches a preset number of times.

[0027] In some possible implementation manners, the sample process parameters are obtained in the following manner:

[0028] Obtain initial sample process parameters, where the initial sample process parameters include the parameters of multiple processes of chip design;

[0029] Based on the influence factors of each initial sample process parameter, screen the initial sample process parameters to obtain the sample process parameters, where the influence factor is used to characterize the correlation degree between the initial sample process parameter and the corresponding sample chip design result.

[0030] According to the second aspect of the embodiments of the present application, there is provided a chip design method, including:

[0031] Obtain the target data of chip design, where the target data includes the process parameters of chip design and the optimization target information;

[0032] Input the target data into the trained prediction model to obtain the target tool parameters, where the prediction model is trained based on the above model training method;

[0033] Use the target tool parameters as the setting parameters of the chip design tool, and run the target chip design use case based on the chip design tool to obtain the target chip design result.

[0034] According to the third aspect of the embodiments of the present application, a model training device is provided, including:

[0035] A sample data acquisition module, configured to acquire a sample data set for chip design, where the sample data set includes multiple groups of sample data, and each group of sample data includes sample process parameters for chip design and sample optimization target information, and the sample optimization target information includes at least one sample optimization strategy for chip design;

[0036] A tool acquisition module, configured to acquire a chip design tool and a chip test design use case set, where the chip test design use case set includes multiple chip test design use cases;

[0037] A training module, configured to perform multiple training operations on the initial prediction model based on the chip design tool, the chip test design use case set, and the sample data set until the training end condition is met, to obtain the trained prediction model and the sample tool parameters corresponding to each sample data output by the trained prediction model. For each group of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design use case meet the sample optimization target information.

[0038] In some possible implementation manners, when performing each training operation, the training module is specifically configured to:

[0039] For each group of sample data, input the sample data into the initial prediction model to obtain sample tool parameters;

[0040] Use the sample tool parameters as the setting parameters corresponding to the current training operation of the chip design tool, and run each chip test design use case based on the chip design tool to obtain the respective sample chip design results corresponding to the current training operation;

[0041] Based on the sample chip design results corresponding to the executed training operations, adjust the parameters of the initial prediction model, and use the initial prediction model with adjusted parameters as the initial prediction model corresponding to the next training operation.

[0042] In some possible implementation manners, when the training module adjusts the parameters of the initial prediction model based on the sample chip design results corresponding to the executed training operations, it is specifically configured to:

[0043] For each chip test design case of each set of sample data, based on the sample chip design results respectively corresponding to the executed training operations, determine the change information of each sample chip design result corresponding to the chip test design case;

[0044] Based on the change information respectively corresponding to each chip test design case of each set of sample data, and the parameter iteration strategy corresponding to the previous training operation, determine the parameter iteration strategy corresponding to the current training operation;

[0045] Based on the parameter iteration strategy corresponding to the current training operation, adjust the parameters of the initial prediction model.

[0046] In some possible implementation manners, the change information includes single - time change information and global change information. When the training module determines the change information of the sample chip design results for each chip test design case of each set of sample data based on the sample chip design results respectively corresponding to the executed training operations, it is specifically used for:

[0047] For each chip test design case of each set of sample data, based on the sample chip design results respectively corresponding to the executed training operations, determine the distribution information of each sample chip design result, and determine the global change information based on the distribution information of each sample chip design result;

[0048] For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the previous training operation and the sample chip design results corresponding to the current training operation, determine the single - time change information.

[0049] In some possible implementation manners, when the training module determines the parameter iteration strategy corresponding to the current training operation based on the change information respectively corresponding to each chip test design case of each set of sample data, and the parameter iteration strategy corresponding to the previous training operation, it is specifically used for:

[0050] For each chip test design case of each set of sample data, if the change information corresponding to the chip test design case conforms to the optimization target information, use the parameter iteration strategy corresponding to the previous training operation as the parameter iteration strategy corresponding to the current training operation;

[0051] If the change information corresponding to at least a preset number of chip test design cases does not conform to the optimization target information, adjust the parameter iteration strategy corresponding to the previous training operation to obtain the parameter iteration strategy corresponding to the current training operation.

[0052] In some possible implementation manners, the training end condition includes at least one of the following:

[0053] For each chip test design case of each group of sample data, the sample chip design result corresponding to the current training operation conforms to the corresponding sample target optimization information or conforms to the corresponding reference chip design result;

[0054] The number of times of the training operation reaches a preset number of times.

[0055] In some possible implementation manners, the sample process parameters are obtained in the following manner:

[0056] Obtain initial sample process parameters, where the initial sample process parameters include parameters of multiple processes of chip design;

[0057] Based on the influence factors of each initial sample process parameter, screen the initial sample process parameters to obtain sample process parameters, where the influence factor is used to characterize the correlation degree between the initial sample process parameter and the corresponding sample chip design result.

[0058] According to the fourth aspect of the embodiments of the present application, there is provided a chip design device, including:

[0059] A target data acquisition module, configured to acquire target data of chip design, where the target data includes process parameters of chip design and optimization target information;

[0060] A parameter acquisition module, configured to input the target data into a trained prediction model to obtain target tool parameters, where the prediction model is trained by the above model training method;

[0061] A chip design module, configured to use the target tool parameters as setting parameters of a chip design tool, and run the target chip design case based on the chip design tool to obtain a target chip design result.

[0062] According to the fifth aspect of the embodiments of the present application, there is provided an electronic device, including a memory, a processor, and a computer program stored on the memory, and the processor executes the computer program to implement the steps of the method in the above embodiments.

[0063] According to the sixth aspect of the embodiments of the present application, there is provided a computer-readable storage medium, on which a computer program is stored, and characterized in that when the computer program is executed by a processor, the steps of the method in the above embodiments are implemented.

[0064] It should be understood that the above general description and subsequent detailed description are only exemplary and explanatory, and cannot limit the present application.

[0065] The beneficial effects brought by the technical solutions provided by the embodiments of the present application are:

[0066] Train an initial prediction model with sample process parameters and sample optimization target information of chip design, and verify whether the sample tool parameters output by the initial prediction model meet the training requirements through a chip design tool and a chip test design case set. After training the prediction model, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design case meet the sample optimization target information. That is to say, the prediction model has the ability to predict the setting parameters of the chip design tool, and the predicted setting parameters enable the chip design results generated by the predicted chip design tool to meet the optimization target information. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0068] Figure 1 is a flowchart showing a model training method provided by an embodiment of the present application;

[0069] Figure 2 is a schematic diagram showing a model training solution provided by an example of the present application;

[0070] Figure 3 is a flowchart showing a chip design method provided by an embodiment of the present application;

[0071] Figure 4 is a schematic diagram showing the structure of a model training device provided by an embodiment of the present application;

[0072] Figure 5 is a schematic diagram showing the structure of a chip design device provided by an embodiment of the present application;

[0073] Figure 6 is a schematic diagram showing the structure of an electronic device for model training or chip design provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0074] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0075] In addition, the described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0076] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0077] The flowcharts shown in the drawings are only illustrative and do not necessarily include all the contents and operations / steps, nor are they necessarily executed in the described order. For example, some operations / steps may be decomposed, while some operations / steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

[0078] It should also be noted that the terms "first", "second", etc. in the description, claims, and above-mentioned drawings of the present application are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such objects may be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described.

[0079] The technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application will be described below through the description of several exemplary embodiments. It should be noted that the following embodiments may refer to, draw on, or combine with each other. For the same terms, similar features, and similar implementation steps in different embodiments, they will not be described repeatedly.

[0080] The model training method of the present application can be executed by any electronic device, and the electronic device may include a server or a terminal.

[0081] Those skilled in the art can understand that the server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. It can also be a cloud server or server cluster that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), as well as big data and artificial intelligence platforms. The terminal can be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a laptop computer, a digital broadcast receiver, a MID (Mobile Internet Devices), a PDA (Personal Digital Assistant), a desktop computer, a smart home appliance, a vehicle terminal (such as a vehicle navigation terminal, a vehicle computer, etc.), a smart speaker, a smart watch, etc. The terminal and the server can be directly or indirectly connected through wired or wireless communication methods, but are not limited thereto. The embodiments of the present invention can be applied to various scenarios, including but not limited to cloud technology, artificial intelligence, intelligent transportation, assisted driving, etc. Specifically, it can also be determined based on the actual application scenario requirements and is not limited herein. The terminal (which can also be referred to as a user terminal or user device) can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart voice interaction device (such as a smart speaker), a wearable electronic device (such as a smart watch), a vehicle terminal, a smart home appliance (such as a smart TV), an AR / VR device, an aircraft, etc., but is not limited thereto.

[0082] As Figure 1 shown, in some possible implementation manners, the embodiment of the present application provides a model training method. Taking the server as the execution subject, the method may include the following steps:

[0083] Step S101, obtain a sample data set for chip design.

[0084] Among them, the sample data set includes multiple groups of sample data. Each group of sample data includes sample process parameters for chip design and sample optimization target information. The sample optimization target information includes at least one sample optimization strategy for chip design.

[0085] Among them, the sample process parameters include the relevant parameters of each process of chip design, such as the parameters corresponding to logic synthesis, DFT (Design for Testability), layout, static timing analysis, clock tree synthesis, routing, GDS (a file format for circuit layout) layout, or FPGA (Field-Programmable Gate Array) bitstream respectively.

[0086] Specifically, the sample process parameters can also be obtained in the following way:

[0087] Obtain the initial sample process parameters, where the initial sample process parameters include the parameters of multiple processes in chip design;

[0088] Based on the influencing factors of each initial sample process parameter, screen the initial sample process parameters to obtain the sample process parameters, where the influencing factor is used to characterize the correlation degree between the initial sample process parameter and the corresponding sample chip design result.

[0089] That is to say, the sample process parameters that have a greater impact on the chip design result can be screened out from multiple initial sample process parameters, reducing the influence of irrelevant initial sample process parameters and reducing the data processing volume.

[0090] Among them, the sample optimization strategy can include the constraint conditions and optimization strategies of chip design. The constraint conditions can include meeting the requirements of all timing constraints WNS (Worst Negative Slack) and TNS (Total Negative Slack), and meeting the manufacturability requirements, including clearing DRC (Design Rule Check) violations and clearing LVS (Linux Virtual Server) violations. The optimization strategies include but are not limited to: minimizing the chip area A, minimizing the power consumption Pow, maximizing the frequency Per, and minimizing the running time T. These are the most basic chip performance-related design goals in addition to the chip functional design goals. Usually, the exploration direction of a chip design includes minimizing the chip area when both the power consumption and frequency meet the requirements; minimizing the power consumption when the chip area cannot be reduced and the main frequency cannot be further optimized; and minimizing the overall running time of the EDA software when the above performance design goals are met.

[0091] Step S102, obtain the chip design tool and the chip test design case set.

[0092] Among them, the chip design tool can include EDA (Electronic Design Automation) tools, simulation tools, layout tools, and so on.

[0093] Among them, the chip test design case set includes multiple chip test design cases.

[0094] Specifically, the chip design tool is used to run each chip test design case in the chip test design case set after adjusting the setting parameters to obtain the corresponding chip design result.

[0095] Step S103: Based on the chip design tool, the chip test design case set, and the sample data set, perform multiple training operations on the initial prediction model until the training end condition is met, obtaining the trained prediction model and the sample tool parameters corresponding to each sample data output by the trained prediction model.

[0096] Among them, for each group of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design case conform to the sample optimization target information.

[0097] It can be understood that the trained prediction model actually constructs the correspondence between the sample data set and the corresponding sample tool parameters, that is, constructs the mapping relationship between the sample process parameters, sample optimization target information, and sample tool parameters of chip design, and the mapping relationship can be stored in the form of a weight matrix.

[0098] Specifically, during each training operation, the sample tool parameters output by the initial prediction model can be used as the setting parameters of the chip design tool, and then the chip design tool runs multiple chip test design cases in the chip test design case set respectively to obtain the corresponding sample chip design results, and then judge whether the sample chip design results conform to the sample optimization target information, so as to judge whether to continue the training operation. The specific training process of the initial prediction model will be further elaborated below.

[0099] In some possible implementation manners, the training end condition includes at least one of the following:

[0100] For each chip test design case of each group of sample data, the sample chip design result corresponding to the current training operation conforms to the corresponding sample target optimization information or conforms to the corresponding reference chip design result;

[0101] The number of training operations reaches a preset number.

[0102] Specifically, the iteration number of the training operation can be set, or the same sample tool parameters can be input into the reference design tool to obtain a benchmark result as the reference chip design result.

[0103] For example, when the chip design tool is an EDA tool, the reference design tool can be Golden EDA (benchmark EDA tool).

[0104] In this embodiment, the initial prediction model is trained with the sample process parameters and sample optimization target information of the chip design, and the chip design tool and the chip test design case set are used to verify whether the sample tool parameters output by the initial prediction model meet the training requirements. After the prediction model is trained, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design case meet the sample optimization target information. That is to say, the prediction model has the ability to predict the setting parameters of the chip design tool, and the predicted setting parameters enable the chip design results generated by the predicted chip design tool to meet the optimization target information.

[0105] The training process for the initial prediction model will be further elaborated below in conjunction with the embodiments.

[0106] In some possible implementation manners, each training operation includes:

[0107] (1) For each set of sample data, input the sample data into the initial prediction model to obtain sample tool parameters;

[0108] (2) Use the sample tool parameters as the setting parameters of the chip design tool corresponding to the current training operation, and run each chip test design case based on the chip design tool to obtain each sample chip design result corresponding to the current training operation;

[0109] (3) Based on the sample chip design results corresponding to the executed training operations respectively, adjust the parameters of the initial prediction model, and use the initial prediction model with adjusted parameters as the initial prediction model corresponding to the next training operation.

[0110] Specifically, that is to say, in the process of each training operation, first, the initial prediction model is used to predict the sample tool parameters corresponding to the sample data, then the sample tool parameters are used as the setting parameters of the chip design tool, and the corresponding chip test design case is run based on the chip design tool to obtain the corresponding sample chip design result, and then the parameters of the initial prediction model are adjusted according to the sample chip design result, and the next training operation is repeated.

[0111] Specifically, for each set of sample data, input the sample data into the initial prediction model, and the initial prediction model iteratively generates sample tool parameters according to optimization algorithms, including simulated annealing, linear programming, genetic algorithms, artificial intelligence algorithms, quantum annealing, etc.

[0112] Among them, the initial prediction model may include BP (back propagation, feedforward neural network), RBF (Radial Basis Function) neural network, Hopfield (feedback neural network) network, etc., which are not limited in this application.

[0113] In the specific implementation process, based on the sample chip design results corresponding to the executed training operations respectively, adjusting the parameters of the initial prediction model may include:

[0114] ① For each chip test design case of each group of sample data, based on the sample chip design results corresponding to the executed training operations respectively, determine the change information of each sample chip design result corresponding to the chip test design case.

[0115] Among them, the change information includes single - change information and global change information.

[0116] In the specific implementation process, for each chip test design case of each group of sample data, based on the sample chip design results corresponding to the executed training operations respectively, determining the change information of the sample chip design results may include:

[0117] For each chip test design case of each group of sample data, based on the sample chip design results corresponding to the executed training operations respectively, determine the distribution information of each sample chip design result, and determine the global change information based on the distribution information of each sample chip design result;

[0118] For each chip test design case of each group of sample data, based on the sample chip design result corresponding to the previous training operation and the sample chip design result corresponding to the current training operation, determine the single - change information.

[0119] For example, if the training operation has been executed 100 times, for a chip test design case of a group of sample data, the sample chip design results corresponding to 100 training operations have been obtained. Then, the single - change information can be determined according to the sample chip design result obtained from the 100th training operation and the sample chip design result obtained from the 99th training operation, and the global change information can also be determined according to the sample chip design results corresponding to these 100 training operations respectively.

[0120] In the specific implementation process, the global change information can be obtained through statistical analysis, including linear regression, confidence interval, probability distribution, etc.

[0121] ②Based on the change information corresponding to each chip test design case of each group of sample data, and the parameter iteration strategy corresponding to the previous training operation, determine the parameter iteration strategy corresponding to the current training operation.

[0122] In some possible implementation manners, based on the change information corresponding to each chip test design case of each group of sample data, and the parameter iteration strategy corresponding to the previous training operation, determining the parameter iteration strategy corresponding to the current training operation includes:

[0123] For each chip test design case of each group of sample data, if the change information corresponding to the chip test design case conforms to the optimization target information, then use the parameter iteration strategy corresponding to the previous training operation as the parameter iteration strategy corresponding to the current training operation;

[0124] If the change information corresponding to at least a preset number of chip test design cases does not conform to the optimization target information, then adjust the parameter iteration strategy corresponding to the previous training operation to obtain the parameter iteration strategy corresponding to the current training operation.

[0125] Specifically, the change information can be the change information for chip area, power consumption, frequency, running time, etc. For example, for single change information, if the sample optimization target information includes the minimum chip area and the minimum power, then it can be judged whether the area and power of the sample chip design result obtained from the current training operation show a decreasing trend compared with the area and power of the sample chip design result obtained from the previous training operation.

[0126] ③Based on the parameter iteration strategy corresponding to the current training operation, adjust the parameters of the initial prediction model.

[0127] Specifically, if the sample chip design result obtained from the current training operation does not reach the reference chip design result corresponding to the training end condition, then based on the parameter iteration strategy corresponding to the current training operation, adjust the parameters of the initial prediction model, and repeat the training operation until the training end condition is met.

[0128] To more clearly elaborate on the above model training method, the following will be further described in conjunction with examples.

[0129] As Figure 2 shown, in an example, taking the chip design tool as the EDA tool, the model training method of the present application may include the following steps:

[0130] Obtain a sample data set for chip design, including sample process parameters and sample optimization target information of the chip design. The sample process parameters may include parameters corresponding to logic synthesis, DFT, placement, static timing analysis, clock tree synthesis, routing, GDS layout, or FPGA bitstream respectively; the sample optimization target information may include minimizing chip area A, minimizing power consumption Pow, maximizing frequency Per, minimizing running time T, and so on;

[0131] Perform multiple training operations on the initial prediction model based on the sample data set. Among them, each training operation includes: inputting the sample data set into the initial prediction model, and the model iteratively generates sample tool parameters according to optimization algorithms, including simulated annealing, linear programming, genetic algorithm, AGI, quantum annealing, etc.; the EDA tool runs the chip test design case according to the sample tool parameters to obtain the sample chip design result, and stores the sample chip design result in the database;

[0132] Perform statistical analysis on each sample chip design result in the database, including linear regression, confidence interval, probability distribution, etc., and statistically obtain the change information of the sample chip design result, including global change information and single-iteration change information, and determine whether to stop training. If the sample optimization target information is not reached, then determine whether the change information Δ meets the expected strategy requirements. If it meets the strategy requirements, continue the next iteration. If it does not meet the strategy requirements, correct the iteration strategy, including adjusting the sampling interval of the sample process parameters, which can be adjusted according to the probability distribution, and then continue the next training operation until the training end condition is met;

[0133] After the training is completed, obtain the mapping relationship among the sample process parameters, sample optimization target information, and sample tool parameters, and store this mapping relationship in a multi-dimensional matrix data structure.

[0134] The above model training method trains the initial prediction model through the sample process parameters and sample optimization target information of the chip design, and verifies whether the sample tool parameters output by the initial prediction model meet the training requirements through the chip design tool and the chip test design case set. After the training, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design result generated based on each chip test design case meets the sample optimization target information. That is to say, the prediction model has the ability to predict the setting parameters of the chip design tool, and the predicted setting parameters enable the predicted chip design tool to generate chip design results that can meet the optimization target information.

[0135] In some possible implementation manners, as Figure 3 shown, a chip design method is provided, including:

[0136] Step S301, obtain the target data of chip design.

[0137] Among them, the target data includes the process parameters of chip design and the optimization target information.

[0138] Step S302, input the target data into the trained prediction model to obtain the target tool parameters.

[0139] Among them, the prediction model is trained based on the above model training method.

[0140] Specifically, the prediction model has constructed the mapping relationship between the sample process parameters, the sample optimization target information, and the corresponding sample tool parameters through training. Then, the corresponding target tool parameters can be obtained through the process parameters and the optimization target information.

[0141] Step S303, use the target tool parameters as the setting parameters of the chip design tool, and run the target chip design use case based on the chip design tool to obtain the target chip design result.

[0142] Specifically, during the training process of the initial prediction model, multiple chip test design use cases are combined for verification. That is to say, for the target tool parameters predicted by the trained prediction model, when the chip design tool adopts the target tool parameters, for various different chip test cases, the target chip design results that relatively best meet the optimization target information can be obtained.

[0143] In the above chip design method, through the trained prediction model, the target tool parameters are obtained based on the target data of chip design. The prediction model has constructed the mapping relationship between the sample process parameters, the sample optimization target information, and the corresponding sample tool parameters through training. And during the training process of the initial prediction model, multiple chip test design use cases are combined for verification. Then, when the chip design tool adopts the target tool parameters, the target chip design results that relatively best meet the optimization target information can be obtained, and the chip design efficiency can also be effectively improved.

[0144] In some possible implementation manners, as Figure 4 shown, a model training device 40 is provided, including:

[0145] A sample data acquisition module 401, configured to acquire a sample data set of chip design. Among them, the sample data set includes multiple groups of sample data, and each group of sample data includes the sample process parameters of chip design and the sample optimization target information. The sample optimization target information includes at least one sample optimization strategy for chip design;

[0146] A tool acquisition module 402, configured to acquire chip design tools and a chip test design case set, where the chip test design case set includes multiple chip test design cases;

[0147] A training module 403, configured to perform multiple training operations on an initial prediction model based on the chip design tools, the chip test design case set, and a sample data set until a training end condition is met, to obtain a trained prediction model and sample tool parameters corresponding to each sample data output by the trained prediction model. For each group of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design case meet the sample optimization target information.

[0148] In some possible implementation manners, when performing each training operation, the training module 403 is specifically configured to:

[0149] For each group of sample data, input the sample data into the initial prediction model to obtain sample tool parameters;

[0150] Use the sample tool parameters as the setting parameters corresponding to the current training operation of the chip design tool, and run each chip test design case based on the chip design tool to obtain each sample chip design result corresponding to the current training operation;

[0151] Based on the sample chip design results corresponding to the executed training operations respectively, adjust the parameters of the initial prediction model, and use the initial prediction model with adjusted parameters as the initial prediction model corresponding to the next training operation.

[0152] In some possible implementation manners, when the training module 403 adjusts the parameters of the initial prediction model based on the sample chip design results corresponding to the executed training operations respectively, it is specifically configured to:

[0153] For each chip test design case of each group of sample data, determine the change information of each sample chip design result corresponding to the chip test design case based on the sample chip design results corresponding to the executed training operations respectively;

[0154] Based on the change information corresponding to each chip test design case of each group of sample data respectively, and the parameter iteration strategy corresponding to the previous training operation, determine the parameter iteration strategy corresponding to the current training operation;

[0155] Based on the parameter iteration strategy corresponding to the current training operation, adjust the parameters of the initial prediction model.

[0156] In some possible embodiments, the change information includes single - change information and global - change information. When the training module 403 determines the change information of the sample chip design results for each chip test design case of each group of sample data based on the sample chip design results respectively corresponding to the executed training operations, it is specifically used for:

[0157] For each chip test design case of each group of sample data, based on the sample chip design results respectively corresponding to the executed training operations, determine the distribution information of each sample chip design result, and determine the global - change information based on the distribution information of each sample chip design result;

[0158] For each chip test design case of each group of sample data, based on the sample chip design result corresponding to the previous training operation and the sample chip design result corresponding to the current training operation, determine the single - change information.

[0159] In some possible embodiments, when the training module 403 determines the parameter iteration strategy corresponding to the current training operation based on the change information respectively corresponding to each chip test design case of each group of sample data and the parameter iteration strategy corresponding to the previous training operation, it is specifically used for:

[0160] For each chip test design case of each group of sample data, if the change information corresponding to the chip test design case conforms to the optimization target information, then use the parameter iteration strategy corresponding to the previous training operation as the parameter iteration strategy corresponding to the current training operation;

[0161] If the change information corresponding to at least a preset number of chip test design cases does not conform to the optimization target information, then adjust the parameter iteration strategy corresponding to the previous training operation to obtain the parameter iteration strategy corresponding to the current training operation.

[0162] In some possible embodiments, the training end conditions include at least one of the following:

[0163] For each chip test design case of each group of sample data, the sample chip design result corresponding to the current training operation conforms to the corresponding sample optimization target information or conforms to the corresponding reference chip design result;

[0164] The number of training operations reaches a preset number.

[0165] In some possible embodiments, the sample process parameters are obtained in the following manner:

[0166] Obtain initial sample process parameters, where the initial sample process parameters include the parameters of multiple processes of chip design;

[0167] Based on the influence factors of each initial sample process parameter, the initial sample process parameters are screened to obtain sample process parameters, where the influence factor is used to characterize the degree of association between the initial sample process parameter and the corresponding sample chip design result.

[0168] The above model training device trains the initial prediction model through the sample process parameters of chip design and the sample optimization target information, and verifies whether the sample tool parameters output by the initial prediction model meet the training requirements through the chip design tool and the chip test design case set. After the prediction model is trained, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design result generated based on each chip test design case meets the sample optimization target information. That is to say, the prediction model has the ability to predict the setting parameters of the chip design tool, and the predicted setting parameters enable the chip design result generated by the predicted chip design tool to meet the optimization target information.

[0169] In some possible implementation manners, such as Figure 5 shown, a chip design device 50 is provided, including:

[0170] A target data acquisition module 501, configured to acquire target data for chip design, where the target data includes process parameters and optimization target information for chip design;

[0171] A parameter acquisition module 502, configured to input the target data into the trained prediction model to obtain target tool parameters, where the prediction model is trained based on the above model training method;

[0172] A chip design module 503, configured to use the target tool parameters as the setting parameters of the chip design tool, and run the target chip design case based on the chip design tool to obtain a target chip design result.

[0173] The above chip design device obtains target tool parameters based on the target data of chip design through the trained prediction model. The prediction model has constructed a mapping relationship between the sample process parameters, the sample optimization target information, and the corresponding sample tool parameters through training. And during the training of the initial prediction model, multiple chip test design cases are combined for verification. Then, when the chip design device adopts the target tool parameters, it can obtain a target chip design result that relatively most conforms to the optimization target information, and can also effectively improve the chip design efficiency.

[0174] In an alternative embodiment, an electronic device is provided, such as Figure 6 shown, Figure 6The electronic device 4000 shown includes: a processor 4001 and a memory 4003. Among them, the processor 4001 and the memory 4003 are connected, such as through a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, and the transceiver 4004 can be used for data interaction between this electronic device and other electronic devices, such as data transmission and / or data reception, etc. It should be noted that in practical applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present application.

[0175] The processor 4001 can be a CPU (Central Processing Unit, central processor), a general-purpose processor, a DSP (Digital Signal Processor, data signal processor), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), an FPGA (Field Programmable Gate Array, field programmable gate array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in connection with the disclosure of the present application. The processor 4001 can also be a combination that implements computing functions, such as a combination including one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0176] The bus 4002 may include a path for transmitting information between the above components. The bus 4002 can be a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture, extended industry standard architecture) bus, etc. The bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, Figure 6 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0177] The memory 4003 can be a ROM (Read Only Memory), or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory), or other types of dynamic storage devices that can store information and instructions. It can also be an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and can be read by a computer, which is not limited herein.

[0178] The memory 4003 is used to store the computer program for implementing the embodiments of the present application and is controlled by the processor 4001 for execution. The processor 4001 is used to execute the computer program stored in the memory 4003 to implement the steps shown in the foregoing method embodiments.

[0179] The embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps and corresponding contents of the foregoing method embodiments can be implemented.

[0180] The embodiments of the present application further provide a computer program product, including a computer program. When the computer program is executed by a processor, the steps and corresponding contents of the foregoing method embodiments can be implemented.

[0181] It should be understood that although the flowchart of the embodiments of the present application indicates each operation step by an arrow, the execution order of these steps is not limited to the order indicated by the arrow. Unless otherwise clearly stated in this application, in some implementation scenarios of the embodiments of the present application, the implementation steps in each flowchart can be executed in other orders according to requirements. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage of these sub-steps or stages can also be executed at different times respectively. In the scenario where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and the embodiments of the present application do not limit this.

[0182] The above are only optional implementation manners of some implementation scenarios of this application. It should be noted that for those of ordinary skill in the art, without departing from the technical concept of the solution of this application, adopting other similar implementation means based on the technical idea of this application also belongs to the protection scope of the embodiments of this application.

Claims

1. A model training method, characterized in that: include: Acquire a sample data set for chip design, wherein the sample data set includes multiple groups of sample data, each group of sample data includes sample process parameters and sample optimization target information for chip design, and the sample optimization target information includes at least one sample optimization strategy for chip design; Acquire a chip design tool and a chip test design case set, wherein the chip test design case set includes a plurality of chip test design cases; Based on the chip design tool, the chip test design case set and the sample data set, the initial prediction model is trained multiple times until the training end condition is met, and the trained prediction model and the sample tool parameters corresponding to each sample data output by the trained prediction model are obtained, wherein, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design result generated based on each of the chip test design cases meets the sample optimization target information, and the trained prediction model is used to construct a mapping relationship between the process parameters, optimization target information and tool parameters of chip design; Wherein, each training operation includes: For each set of sample data, the sample data is input into an initial prediction model to obtain sample tool parameters; Using the sample tool parameters as setting parameters corresponding to the current training operation of the chip design tool, and running each of the chip test design cases based on the chip design tool to obtain each sample chip design result corresponding to the current training operation; Based on the sample chip design results corresponding to the executed training operations, the parameters of the initial prediction model are adjusted, and the initial prediction model after the adjustment of the parameters is used as the initial prediction model corresponding to the next training operation.

2. The method according to claim 1, characterized in that The adjusting the parameters of the initial prediction model based on the sample chip design results respectively corresponding to the executed training operations includes: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, determine the change information of each sample chip design result corresponding to the chip test design case; Determine the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation; Based on the parameter iteration strategy corresponding to the current training operation, the parameters of the initial prediction model are adjusted.

3. The method according to claim 2, characterized in that The change information includes single change information and global change information. For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, the change information of the sample chip design result is determined, including: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, the distribution information of each sample chip design result is determined, and the global change information is determined based on the distribution information of each sample chip design result; For each chip test design case of each set of sample data, the single change information is determined based on the sample chip design result corresponding to the last training operation and the sample chip design result corresponding to the current training operation.

4. The method according to claim 2, characterized in that: The step of determining the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation includes: For each chip test design case of each set of sample data, if the change information corresponding to the chip test design case meets the optimization target information, the parameter iteration strategy corresponding to the previous training operation is used as the parameter iteration strategy corresponding to the current training operation; If the change information corresponding to at least a preset number of chip test design cases does not conform to the optimization target information, the parameter iteration strategy corresponding to the previous training operation is adjusted to obtain the parameter iteration strategy corresponding to the current training operation.

5. The method according to claim 1, characterized in that The training end condition includes at least one of the following: For each chip test design case of each set of sample data, the sample chip design result corresponding to the current training operation conforms to the corresponding sample target optimization information or conforms to the corresponding reference chip design result; The number of training operations reaches a preset number.

6. The method according to claim 1, characterized in that The sample process parameters are obtained in the following manner: Acquire initial sample process parameters, wherein the initial sample process parameters include parameters of multiple processes of chip design; Based on the influencing factors of each initial sample process parameter, the initial sample process parameters are screened to obtain sample process parameters, wherein the influencing factors are used to characterize the degree of correlation between the initial sample process parameters and the corresponding sample chip design results.

7. A chip design method, characterized in that: include: Acquiring target data for chip design, wherein the target data includes process parameters and optimization target information for chip design; Inputting the target data into a trained prediction model to obtain target tool parameters, wherein the prediction model is trained based on the model training method according to any one of claims 1 to 6; The target tool parameters are used as setting parameters of a chip design tool, and a target chip design use case is run based on the chip design tool to obtain a target chip design result.

8. A model training device, characterized in that: include: A sample data acquisition module, used to acquire a sample data set for chip design, wherein the sample data set includes multiple groups of sample data, each group of sample data includes sample process parameters and sample optimization target information for chip design, and the sample optimization target information includes at least one sample optimization strategy for chip design; A tool acquisition module, used to acquire a chip design tool and a chip test design case set, wherein the chip test design case set includes a plurality of chip test design cases; A training module, used to perform multiple training operations on the initial prediction model based on the chip design tool, the chip test design case set and the sample data set until the training end condition is met, to obtain the trained prediction model and the sample tool parameters corresponding to each sample data output by the trained prediction model, wherein, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as setting parameters of the chip design tool, the chip design result generated based on each of the chip test design cases meets the sample optimization target information; Among them, the training module is specifically used to: For each set of sample data, the sample data is input into an initial prediction model to obtain sample tool parameters; Using the sample tool parameters as setting parameters corresponding to the current training operation of the chip design tool, and running each of the chip test design cases based on the chip design tool to obtain each sample chip design result corresponding to the current training operation; Based on the sample chip design results corresponding to the executed training operations, the parameters of the initial prediction model are adjusted, and the initial prediction model after the adjustment of the parameters is used as the initial prediction model corresponding to the next training operation.

9. A chip design device, characterized in that: include: A target data acquisition module, used to acquire target data of chip design, wherein the target data includes process parameters and optimization target information of chip design; A parameter acquisition module, used for inputting the target data into a trained prediction model to obtain target tool parameters, wherein the prediction model is trained based on the model training method according to any one of claims 1 to 6; The chip design module is used to use the target tool parameters as setting parameters of the chip design tool, run the target chip design use case based on the chip design tool, and obtain the target chip design result.

10. An electronic device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images