System and method for protocol customized scenario model based on FPGA

Abstract

The present invention provides a system and method for a protocol customized scene model based on FPGA, including: a hardware module, an FPGA function module and a scene model software module; the hardware module is integrated in the FPGA function module and is used to send IP instructions to the FPGA function module; the scene model software module is used to set the parameters generated by the scene model framework, and transmit them to the FPGA function module, and uniformly manage the scene model framework and data; the FPGA function module is used to form an IP core of the protocol customized scene model based on the hardware module and the scene model software module, and transmit the IP core data to a bus, and transmit the data to the hardware module and the scene model software module at the same time for circuit protection. The present invention omits the work of compiling, downloading, debugging, etc. and directly customizes the scene model.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a system and method for a protocol customized scenario model based on FPGA, and in particular, to a protocol customized CompactRIO scenario model system based on FPGA. Background Art

[0002] CompactRIO is a reconfigurable embedded measurement and control system. The CompactRIO system has a solid hardware architecture, including: AD / DA modules, I / O modules, a chassis with a reconfigurable field programmable gate array (FPGA), and a real-time controller. In addition, users can use graphical development tools to program CompactRIO and apply it to various embedded control and monitoring applications. The CompactRIO system provides high processing performance, sensor-specific I / O, and tightly integrated software tools, making it an ideal choice for industrial IoT, monitoring, and control applications.

[0003] At present, CompactRIO technology mainly relies on the RIO kit of National Instruments (NI), and needs to be developed in collaboration with its LabVIEW, FPGA Module, FPGA compiler and other software and drivers.

[0004] The present invention is mainly based on: self-developed high-speed PXIE-ADDA board and adjustable PXIE-resistance board, integrating RIO IP cores of various standard protocols and customized protocols inside the onboard FPGA chip, and the software level is responsible for the unified standard protocol and customized protocol model establishment, model parameter setting, data monitoring, data analysis and algorithm parsing.

[0005] The difference between the present invention and the NI system is that the NI system is uniformly managed by LabVIEW software, including FPGA code construction, compilation, downloading and other tasks; while the present invention IP-izes the existing standardized protocols and customized protocol bus types, and integrates them into the FPGA, eliminating the need for compilation, downloading and other tasks; at the software level, various different protocols and usage scenarios are modeled, and unified management and post-data processing are performed.

[0006] The Chinese patent document with application number CN202111620660.6 discloses a data transmission method for an underwater acoustic signal processing hardware platform based on CompactRIO. The invention discloses a data transmission method for an underwater acoustic signal processing hardware platform based on CompactRIO. First, after the platform is powered on, the app.out file pre-stored in the built-in U disk is read under the RT system and written to the DSP, thereby completing the startup of the DSP; secondly, the RT system, the host computer, and the DSP are interconnected in pairs through a switch, and the host computer shakes hands with the RT system and the DSP under the UDP protocol. Manual and self-check, at this point each extension enters the working state; again, the host computer issues a transmission command, after receiving the command, the RT system analyzes the signal form and retrieves the waveform file in the built-in U disk and sends it to the FPGA. Under the action of the system clock, the FPGA sends the digital information of the waveform to the transmitting transducer through the DA data transmission module for transmission; then, the AD data acquisition module collects the underwater acoustic signal in real time and uploads the original waveform data to the RT system. On the one hand, the data is stored in the platform's built-in U disk, and on the other hand, it is passed to the DSP for real-time data processing; finally, the DSP sends the calculated delay and distance information back to the host computer for display. Differences: The invention is a data transmission method for the subsequent underwater acoustic signal processing hardware platform using NI's CompactRIO technology, while the present invention uses self-developed hardware equipment and software to customize the CompactRIO model for the protocol, thereby replacing NI's CompactRIO technology, which is essentially different.

[0007] The Chinese patent document with application number CN201810055100.2 discloses "a robot control system based on CompactRIO". This invention belongs to the field of intelligent control, and particularly relates to a robot control system based on CompactRIO, including a host computer with a LabVIEW platform, a power supply, a CompactRIO integrated controller, NI's C series I / O interface module, NI's C series analog output module, a servo drive, a servo motor, an auxiliary power supply, and a two-degree-of-freedom robotic arm. The LabVIEW platform of the host computer is provided with a human-computer interaction interface, and the human-computer interaction interface includes a switch control servo motor start-stop module, a fractional-order PD control module, a robotic arm position output module, a robotic arm torque output module, and an analog voltage output module. The control system is easy to operate and has a simple program. Compared with traditional PID control, its control effect is more flexible and more robust. It can realize torque regulation and position control of a two-degree-of-freedom robotic arm, improve the control accuracy and robustness of the system, and will not reduce real-time performance due to the complex control system of the robotic arm. Differences: That invention uses NI's CompactRIO technology to control the signal outputs of the robot control system, while the present invention uses self-developed hardware and software to customize the CompactRIO model for the protocol, thereby replacing NI's CompactRIO technology. There is an essential difference.

[0008] The Chinese patent document with application number CN202110887214.5 discloses "LabVIEW-based assembly printed circuit board detection device and method thereof". The invention provides a LabVIEW-based assembly printed circuit board detection device and detection method thereof, wherein the detection device comprises a LabVIEW host computer with an MCU main control board, a MotoHawk controller module connected to the LabVIEW host computer, a relay module connected to the MotoHawk controller module, an assembly printed circuit board fixture module connected to the LabVIEW host computer and the relay module, a brake module connected to the LabVIEW host computer, and a motor, wherein the MotoHawk controller module controls the relay module to attract the relay; the assembly printed circuit board fixture module is used to fix the assembly printed circuit board, and the assembly printed circuit board outputs U-phase current, V-phase current and W-phase current to the motor. The present invention completes the automated test of the assembly printed circuit board function based on the LabVIEW host computer and the MotoHawk controller module, reduces the consumption of manpower and time, and saves costs. Differences: That invention is a method for subsequent assembly of printed circuit board detection equipment using NI's LabVIEW technology, while the present invention uses self-developed hardware equipment and software to customize the CompactRIO model for the protocol, thereby replacing NI's CompactRIO and LabVIEW technology, which is essentially different.

[0009] Therefore, a system and method for a protocol customized scenario model based on FPGA is needed for unified management and post-data processing. Summary of the invention

[0010] In view of the defects in the prior art, the object of the present invention is to provide a system and method for a protocol customized scenario model based on FPGA.

[0011] A system for protocol customized scene model based on FPGA provided by the present invention includes: a hardware module, an FPGA function module and a scene model software module;

[0012] The hardware module is integrated into the FPGA function module and is used to send IP instructions to the FPGA function module;

[0013] The scene model software module is used to set the parameter set generated by the scene model framework, transmit it to the FPGA function module, and uniformly manage the scene model framework and data;

[0014] The FPGA functional module is used to form an IP core of a protocol customized scenario model based on the hardware module and the scenario model software module, and transmit the IP core data to the bus, and at the same time transmit the data to the hardware module and the scenario model software module for circuit protection.

[0015] Preferably, the scene model software module includes:

[0016] The scene model library submodule is used to store the scene model framework and the customized and improved scene model framework;

[0017] The parameter setting submodule is used to set the signal mode parameters, automatic impedance parameters, signal physical layer parameters, signal electrical layer parameters, and signal protocol layer parameters corresponding to the scene model framework in the scene model library, and integrate all the settings into a parameter set and transmit it to the FPGA function module.

[0018] Preferably, the hardware module includes:

[0019] The high-speed board submodule is used to match the received parameter configuration, obtain the parameter configuration information corresponding to the FPGA, and send the parameter configuration information and IP instructions to make the FPGA function module form a model IP core;

[0020] The adjustable resistor card submodule is used to generate signal data based on the FPGA function module and transmit the data to the scene model software module;

[0021] The adjustable resistor clamp module also includes a circuit protection unit; the circuit protection unit is used to adjust the circuit breaking function of the input and output signals through a high-speed analog switch; to adjust the current limiting function through a resistor and a current detection chip; and to set the serial impedance and parallel impedance of the signal at the input end and adjust the differential signal impedance through a relay control array;

[0022] The signals of the high-speed card submodule and the adjustable resistor card submodule are connected in series and integrated inside the FPGA function module to control and protect the FPGA function module.

[0023] Preferably, the FPGA functional module includes:

[0024] A receiving unit, used to receive IP instructions and parameter configuration information of the hardware module, and also receive a parameter set of the scene model software module;

[0025] The IP core unit is used to convert the received parameter configuration information and parameter set into IP, obtain the IP core of the protocol customized scenario model, integrate the data of the IP core, and pass it to the scenario model software module and the adjustable resistance card submodule;

[0026] The interaction unit transfers the data of the IP core to the bus for data interaction with the bus.

[0027] Preferably, the IP core unit includes:

[0028] The set protocol model IP core unit is used to output a unified waveform of the set IP core; the set protocol model includes a model corresponding to the storage scenario model framework;

[0029] Custom protocol model IP core unit, used to simulate the waveform of user-defined data and automatically convert it into unified output waveform data;

[0030] Specifically, the IP core unit converts the received data into a voltage value according to preset rules and preset sampling rate, and stores the voltage value in a preset space in real time; extracts the voltage value in the preset space, and performs voltage regulation, signal filtering, slope adjustment, and white noise injection, and then stores it in the storage space; extracts the data in the storage space and outputs unified waveform data.

[0031] A method for a protocol customized scenario model based on FPGA provided by the present invention includes:

[0032] Step S1, integrating the hardware module into the FPGA function module, and sending an IP instruction to the FPGA function module;

[0033] Step S2, setting the parameter set generated by the scene model framework, transmitting it to the FPGA function module, and uniformly managing the scene model framework and data;

[0034] Step S3, based on the hardware module and the scenario model software module, an IP core of the protocol customized scenario model is formed, and the IP core data is transmitted to the bus, and the data is simultaneously transmitted to the hardware module and the scenario model software module for circuit protection.

[0035] Preferably, the step S1 comprises:

[0036] Step S1.1, making the high-speed board submodule match the received parameter configuration, obtaining the parameter configuration information corresponding to the FPGA, and sending the parameter configuration information and IP instructions, so that the FPGA function module forms a model IP core;

[0037] Step S1.2, based on the FPGA function module, the adjustable resistor card module generates signal data and transmits the data to the scene model software module;

[0038] The adjustable resistor clamp module also includes a circuit protection unit; the circuit protection unit is used to adjust the circuit breaking function of the input and output signals through a high-speed analog switch; to adjust the current limiting function through a resistor and a current detection chip; and to set the serial impedance and parallel impedance of the signal at the input end and adjust the differential signal impedance through a relay control array;

[0039] The signals of the high-speed card submodule and the adjustable resistor card submodule are connected in series and integrated inside the FPGA function module to control and protect the FPGA function module.

[0040] Preferably, step S2 comprises:

[0041] Step S2.1, the scene model library submodule stores the scene model framework and the customized improved scene model framework;

[0042] Step S2.2, the parameter setting submodule sets the signal mode parameters, automatic impedance parameters, signal physical layer parameters, signal electrical layer parameters, and signal protocol layer parameters corresponding to the scene model framework in the scene model library, and integrates all the settings into a parameter set and transmits it to the FPGA functional module.

[0043] Preferably, the step S3 comprises:

[0044] Step S3.1, instructing the receiving unit to receive the IP-based instructions and parameter configuration information of the hardware module, and at the same time receive the parameter set of the scene model software module;

[0045] Step S3.2, instructing the IP core unit to IP the received parameter configuration information and parameter set, obtain the IP core of the protocol customized scenario model, integrate the data of the IP core, and pass it to the scenario model software module and the adjustable resistance card submodule;

[0046] Step S3.3, instructing the interaction unit to transfer the data of the IP core to the bus and interact with the bus.

[0047] Preferably, the step S3.2 comprises:

[0048] The set protocol model IP core unit is made to output a unified waveform after the set IP core; the set protocol model includes a model corresponding to the storage scenario model framework;

[0049] Make the custom protocol model IP core unit simulate the waveform of user-defined data and automatically convert it into unified output waveform data;

[0050] Step S3.2.1, the IP core unit converts the received data into a voltage value according to a preset rule and a preset sampling rate;

[0051] Step S3.2.2, storing the voltage value into a preset space in real time;

[0052] Step S3.2.3, extracting the voltage value in the preset space, and performing voltage regulation, signal filtering, slope regulation, and white noise injection, and then storing it in the storage space;

[0053] Step S3.2.4, extracting data from the storage space and outputting unified waveform data.

[0054] Compared with the prior art, the present invention has the following beneficial effects:

[0055] 1. The present invention is applicable to most communication buses for embedded system measurement and control by reconfiguring communication protocols and customizing protocol types for signals; it provides a high-speed and efficient test and measurement method for general buses, dedicated IO, sensor measurement and control, data monitoring and detection;

[0056] 2. The present invention can use graphical development tools to modularize, model configuration and set each protocol bus, and all model parameters are sent to each integrated IP of the FPGA board through PCIE, thereby eliminating the need for compilation, downloading, debugging, etc.; unified management and post-data processing are performed at the software level;

[0057] 3. The present invention allows users to set and customize the scenario model framework and its parameters, including signal mode, automatic impedance, physical layer, electrical layer and protocol layer parameters, through the scenario model software module, so as to create a highly customized protocol scenario model; the FPGA function module can form an IP core based on these customized parameters, realize flexible customization of the protocol, and meet the needs of different application scenarios;

[0058] 4. The circuit protection unit in the adjustable resistor clip module of the present invention realizes the circuit breaking function adjustment and current limiting function adjustment of the input and output signals and the setting of the serial impedance, parallel impedance and differential signal impedance through high-speed analog switches, resistors, current detection chips and relay control arrays, which effectively protects the circuit and improves the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0060] Figure 1 A framework diagram of a system for customizing a protocol scenario model based on FPGA according to the present invention;

[0061] Figure 2 This is a framework diagram of a system for a protocol customized scenario model based on FPGA according to Embodiment 1 of the present invention;

[0062] Figure 3 Schematic diagram of the adjustable resistor card. DETAILED DESCRIPTION

[0063] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0064] The present invention provides a system for protocol customized scene model based on FPGA, comprising: a hardware module, an FPGA function module and a scene model software module;

[0065] The hardware module is integrated into the FPGA function module and is used to send IP instructions to the FPGA function module;

[0066] The scene model software module is used to set the parameters generated by the scene model framework, transmit them to the FPGA function module, and manage the scene model framework and data in a unified manner;

[0067] The FPGA functional module is used to form an IP core of a protocol customized scenario model based on the hardware module and the scenario model software module, and transmit the IP core data to the bus. At the same time, the data is transmitted to the hardware module and the scenario model software module for circuit protection.

[0068] Specifically, the scene model software module includes:

[0069] The scene model library submodule is used to store the scene model framework and the customized and improved scene model framework;

[0070] The parameter setting submodule is used to set the signal mode parameters, automatic impedance parameters, signal physical layer parameters, signal electrical layer parameters, and signal protocol layer parameters corresponding to the scene model framework in the scene model library, and integrate all the settings into a parameter set and transmit it to the FPGA function module.

[0071] Specifically, the hardware modules include:

[0072] The high-speed board submodule is used to match the received parameter configuration, obtain the parameter configuration information corresponding to the FPGA, and send the parameter configuration information and IP instructions to make the FPGA function module form a model IP core;

[0073] The adjustable resistor card submodule is used to generate signal data based on the FPGA function module and transmit the data to the scene model software module;

[0074] The adjustable resistor card module also includes a circuit protection unit; the circuit protection unit is used to adjust the circuit breaking function of the input and output signals through a high-speed analog switch; to adjust the current limiting function through a resistor and a current detection chip; and to set the serial impedance and parallel impedance of the input terminal signal and adjust the differential signal impedance through a relay control array;

[0075] The signals of the high-speed card submodule and the adjustable resistor card submodule are connected in series and integrated inside the FPGA function module to control and protect the FPGA function module.

[0076] Specifically, the FPGA functional modules include:

[0077] A receiving unit, used to receive IP instructions and parameter configuration information of the hardware module, and also receive a parameter set of the scene model software module;

[0078] The IP core unit is used to convert the received parameter configuration information and parameter set into IP, obtain the IP core of the protocol customized scenario model, integrate the data of the IP core, and pass it to the scenario model software module and the adjustable resistance card submodule;

[0079] The interaction unit transfers the data of the IP core to the bus for data interaction with the bus.

[0080] Specifically, the IP core unit includes:

[0081] The set protocol model IP core unit is used to output a unified waveform of the set IP core; the set protocol model includes a model corresponding to the storage scenario model framework;

[0082] Custom protocol model IP core unit, used to simulate the waveform of user-defined data and automatically convert it into unified output waveform data;

[0083] Specifically, the IP core unit converts the received data into a voltage value according to preset rules and preset sampling rate; stores the voltage value into a preset space in real time; extracts the voltage value in the preset space, and performs voltage regulation, signal filtering, slope adjustment, and white noise injection, and then stores it in the storage space; extracts the data in the storage space and outputs unified waveform data.

[0084] Example 1

[0085] The self-developed high-speed PXIE-ADDA board is used as the main FPGA implementation board of the CompactRIO model system. The board supports 4-channel ±25V / 125MHz / 16bits differential AD sampling, 4-channel ±25V / 125MHz / 16bits differential DA output, a Z7 series FPGA chip and various peripheral chips;

[0086] The PXIE-X4 interface is used to interact with the host at high speed, with a rate of up to 20Gbps. The FPGA chip has 4 external DDR3 (2GB) memories for large data cache, and 4 external differential ADs for analog signal sampling (±25V / 125MHz / 16bits), as well as 4 differential DA outputs (±25V / 125MHz / 16bits).

[0087] The design makes full use of PXIE's high-speed bandwidth and large-capacity cache to provide high-speed, long-term uninterrupted real-time signal simulation and real-time data acquisition and analysis in real simulation of user scenarios.

[0088] In addition, the use of high-speed and high-precision differential AD / DA chips can make the simulated voltage accuracy reach <1mV and the simulated waveform baud rate >20M; at the same time, the use of a wider differential voltage input and output range of ±25V can simulate various user scenarios, such as high-voltage DIO scenarios, low-voltage ARINC429 scenarios, differential RS422 scenarios, etc.

[0089] Adopting the self-developed PXIE-adjustable resistor card, the board supports dynamic signal resistance adjustment (serial impedance 0.25Ω~16KΩ), (parallel impedance 1Ω~265Ω); supports signal short circuit, open circuit, overcurrent, overvoltage and other protection functions;

[0090] The main FPGA chip integrates a variety of standard and customized protocols in the electrical layer, physical layer, and protocol layer. Dynamically configurable IP cores can be used to manage models, build scenarios, and configure configurations in a unified manner through software.

[0091] The CompactRIO model of the system includes:

[0092] Physical layer: supports single-ended / differential signal high-speed AD sampling and DA output, automatic impedance matching mechanism, voltage and current protection, short circuit and open circuit faults;

[0093] Electrical layer: signal voltage regulation, signal filtering, signal slope adjustment, white noise fault injection;

[0094] Protocol layer: RS232 protocol scenario model, RS422 protocol scenario model, RS485 protocol scenario model, SPI protocol scenario model, IIC protocol scenario model, ARINC429 protocol scenario model, 1553B protocol scenario model, CAN / CANFD protocol scenario model, TTL / DIO protocol scenario model, LVDS protocol scenario model, and custom protocol scenario model (custom protocols require secondary development, and IRIG-B\PWM\interrupt control signals have been developed).

[0095] User layer: data monitoring, data analysis, and custom algorithm scenario analysis.

[0096] FPGA-based protocol-customized CompactRIO model system, including:

[0097] 1) CompactRIO-Hardware Submodule:

[0098] a. High-speed PXIE-ADDA board:

[0099] As the main FPGA implementation board of the CompactRIO model system, this board supports 4-channel ±25V / 125MHz / 16bits differential AD sampling, 4-channel ±25V / 125MHz / 16bits differential DA output, a Z7 series FPGA chip and various peripheral chips. This board adopts the PXIE backplane protocol interface and can be inserted into the PXIE chassis. It interacts with the CPU for big data in real time through PCIE-GEN2x4.

[0100] b.PXIE-Adjustable Resistor Card:

[0101] The board supports dynamic signal resistance adjustment (serial impedance 0.25Ω~16KΩ), (parallel impedance 1Ω~265Ω); supports signal short circuit, open circuit, overcurrent, overvoltage and other protection functions; the board also uses the PXIE backplane protocol interface, can be inserted into the PXIE chassis, and interact with the CPU in real time with big data through PCIE-GEN2x4;

[0102] c.Signal connection:

[0103] By connecting the signals of the PXIE-ADDA board and the PXIE-adjustable resistor card in series, the electrical layer, physical layer, and impedance matching adjustment of single-ended signals / differential signals of most communication protocols can be realized; bidirectional signal data interaction can also be achieved through high-speed disconnection and short circuit; at the same time, it supports the monitoring and protection of each signal voltage and current.

[0104] 2) CompactRIO-FPGA protocol customized IP submodule:

[0105] The existing standardized protocols and customized protocol bus types are IP-based and integrated into the FPGA; currently integrated protocol types: RS232, RS422, RS485, ARINC429, CAN, CANFD, IIC, SPI, 1553B, TTL, DIO, LVDS, and some customized protocol types: IRIG-B\PWM\interrupt control signals, etc.

[0106] a.Signal mode setting module:

[0107] The configurable types include: single-ended signal and ground, differential signal and ground, bidirectional signal and output enable control.

[0108] b. Automatic impedance matching module for each protocol signal:

[0109] Automatically select and control the impedance matching type and signal impedance matching resistance value according to the standardized protocol, automatically set the voltage monitoring range and current monitoring range according to different protocol types, and set the overvoltage and overcurrent protection thresholds; for customized protocol types, the software will uniformly set the parameters.

[0110] c. Physical layer modules of each protocol signal:

[0111] The basic standardized protocol automatically sets the signal input and output voltage range, voltage recognition range, common mode voltage average, differential mode signal voltage average, and adds hardware filtering settings at the AD end; for customized protocol types, the software sets all parameters in a unified manner.

[0112] d.Electrical layer modules of each protocol signal:

[0113] Monitor the slope change of each signal (single-ended / differential). For special protocol buses, such as 1553B, optimize the Manchester encoding and decoding algorithm; for CANFD, separately identify the baud rate of the data area and the baud rate of the frame ID area; for SPI, add signal bidirectional signal control and separate processing, etc.; noise can also be injected into the output signal.

[0114] e. User layer modules for each protocol signal:

[0115] According to the standardized protocol, the baud rate recognition, data input decoding, data output encoding, check bit determination, and protocol data real-time upload and download are automatically performed; for customized protocol types, the parameters are uniformly set by the software.

[0116] 3) CompactRIO-Software Protocol Model Submodule:

[0117] The software is responsible for the model scenario design of each protocol type (signal mode, automatic impedance matching, signal physical layer, signal electrical layer, signal electrical layer); at the same time, it analyzes, parses, manages and parses the data uploaded by the hardware with custom algorithms; the scenario models currently include:

[0118] RS232 protocol scenario model, RS422 protocol scenario model, RS485 protocol scenario model, SPI protocol scenario model, IIC protocol scenario model, ARINC429 protocol scenario model, 1553B protocol scenario model, CAN / CANFD protocol scenario model, TTL / DIO protocol scenario model, LVDS protocol scenario model, and custom protocol scenario model (custom protocols require secondary development, and IRIG-B\PWM\interrupt control signals have been developed).

[0119] The receiving unit, IP core unit and interaction unit in the FPGA functional module of the present invention work together to realize the rapid reception, processing, IP coreization and interaction with the bus of data, thereby improving the data processing efficiency and performance of the system. The IP core unit can convert the bus level data into a voltage value according to the preset rules and sampling rate, and perform voltage regulation, signal filtering, slope regulation and white noise injection, etc., to ensure the uniformity and accuracy of the output waveform.

[0120] The modular design of the present invention makes each module relatively independent, which is convenient for function expansion and upgrading. The scene model library submodule and parameter setting submodule in the scene model software module enable users to conveniently manage and update the scene model and its parameters, thus reducing the maintenance cost of the system.

[0121] The present invention also provides an FPGA-based protocol customized scenario model method, which can be implemented by executing the FPGA-based protocol customized scenario model system, that is, those skilled in the art can understand the FPGA-based protocol customized scenario model system as a preferred implementation of the FPGA-based protocol customized scenario model method.

[0122] The present invention provides a method for a protocol customized scene model based on FPGA, comprising: step S1, integrating a hardware module into an FPGA function module, and sending an IP instruction to the FPGA function module; step S2, setting parameters generated by a scene model framework, transmitting them to the FPGA function module, and uniformly managing the scene model framework and data; step S3, forming an IP core of a protocol customized scene model based on the hardware module and the scene model software module, transmitting the IP core data to a bus, and transmitting the data to the hardware module and the scene model software module at the same time for circuit protection.

[0123] Specifically, the step S1 includes: step S1.1, making the high-speed board card submodule match the received parameter configuration, obtaining the parameter configuration information corresponding to the FPGA, and sending the parameter configuration information and IP instructions, so that the FPGA function module forms a model IP core; step S1.2, based on the FPGA function module, making the adjustable resistor card submodule generate signal data, and transmitting the data to the scene model software module; the adjustable resistor card submodule also includes a circuit protection unit; the circuit protection unit: is used to adjust the circuit breaking function of the input and output signals through a high-speed analog switch; is used to adjust the current limiting function through a resistor and a current detection chip; is used to set the serial impedance, parallel impedance and differential signal impedance of the signal at the input end through a relay control array;

[0124] In a preferred embodiment, Figure 3 As shown: Step 1: The application layer software selects the protocol type and sends it to the board through the PXIE bus; Step 2: The circuit breaker function of the input signal P / N is adjusted through the high-speed analog switch;

[0125] Step 3: Implement the current limiting function through a 0.02 ohm resistor and a current detection chip; Step 4: Set the serial impedance, parallel impedance and differential signal impedance of the P / N signal at the input end through BANK1 and BANK2; BANK1 is a 16-bit relay control array; BANK2 is an 8-bit relay control array; Step 5: Adjust the circuit breaker function of the output signal P / N through a high-speed analog switch;

[0126] The signals of the high-speed card submodule and the adjustable resistor card submodule are connected in series and integrated inside the FPGA function module to control and protect the FPGA function module.

[0127] Specifically, step S2 includes: step S2.1, the scene model library submodule stores the scene model framework and the customized improved scene model framework; step S2.2, the parameter setting submodule sets the signal mode parameters, automatic impedance parameters, signal physical layer parameters, signal electrical layer parameters, and signal protocol layer parameters corresponding to the scene model framework in the scene model library, and integrates all the set contents into a parameter set and transmits them to the FPGA functional module.

[0128] Specifically, the step S3 includes: step S3.1, instructing the receiving unit to receive the IP instructions and parameter configuration information of the hardware module, and at the same time receive the parameter set of the scene model software module; step S3.2, instructing the IP core unit to IP the received parameter configuration information and parameter set, obtain the IP core of the protocol customized scene model, integrate the data of the IP core, and pass it to the scene model software module and the adjustable resistor card submodule; step S3.3, instructing the interaction unit to transmit the data of the IP core to the bus, and interact with the bus for data.

[0129] Specifically, the step S3.2 includes: making the set protocol model IP core unit output a unified waveform passed through the set IP core; the set protocol model includes a model corresponding to the storage scenario model framework; making the custom protocol model IP core unit simulate the waveform of the user-defined data, and automatically convert the unified output waveform data; step S3.2.1, the IP core unit converts the received data into a voltage value according to preset rules and preset sampling rate; step S3.2.2, storing the voltage value into a preset space in real time; step S3.2.3, extracting the voltage value in the preset space, and performing voltage regulation, signal filtering, slope adjustment, and white noise injection, and then storing it in the storage space; step S3.2.4, extracting the data in the storage space, and outputting unified waveform data. Among them, the standard IP core is the existing IP core; the non-standard IP core is an improvement on the standard IP core; the custom IP core is an IP developed based on the actual needs of the user; all IP cores will generate bus signals in real time according to their own protocols, and convert this signal into a voltage value and store it in DDR3. Then the electrical layer FPGA logic will synchronously take out the data in DDR3, perform signal conditioning, and store it in FIFO, and then send the FIFO output to the board DA circuit in real time.

[0130] In a preferred embodiment, step 1: all standard, non-standard, and customized IP cores will convert bus level data into 16-bit precision voltage values ​​at a sampling rate of 125MHz according to their own protocol data; step 2: the hardware board FPGA logic stores the voltage value into the 1GB DDR3 space of the board in real time; step 3: the electrical layer function module takes out the waveform voltage value in the secondary DDR3 space, and performs voltage regulation, signal filtering, slope adjustment, and white noise injection, and then stores it in the FIFO memory space; step 4: the DA module takes out the FIFO space data and sends it to the board DA module.

[0131] Those skilled in the art know that, in addition to realizing the system and its various devices, modules, and units provided by the present invention in a purely computer-readable program code, it is entirely possible to realize the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered as a hardware component, and the devices, modules, and units included therein for realizing various functions can also be regarded as structures within the hardware component; the devices, modules, and units for realizing various functions can also be regarded as both software modules for realizing the method and structures within the hardware component.

[0132] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A system of protocol customized scenario model based on FPGA, characterized in that: include: Hardware module, FPGA function module and scenario model software module; The hardware module is integrated into the FPGA function module and is used to send IP instructions to the FPGA function module; The scene model software module is used to set the parameter set generated by the scene model framework, transmit it to the FPGA function module, and uniformly manage the scene model framework and data; The FPGA functional module is used to form an IP core of a protocol customized scenario model based on the hardware module and the scenario model software module, and transmit the IP core data to the bus, and at the same time transmit the data to the hardware module and the scenario model software module for circuit protection; The scene model software module includes: The scene model library submodule is used to store the scene model framework and the customized and improved scene model framework; The parameter setting submodule is used to set the signal mode parameters, automatic impedance parameters, signal physical layer parameters, signal electrical layer parameters, and signal protocol layer parameters corresponding to the scene model framework in the scene model library, and integrate all the settings into a parameter set and transmit it to the FPGA function module.

2. The system of protocol customized scenario model based on FPGA according to claim 1, characterized in that: The hardware module includes: The high-speed board submodule is used to match the received parameter configuration, obtain the parameter configuration information corresponding to the FPGA, and send the parameter configuration information and IP instructions to make the FPGA function module form a model IP core; The adjustable resistor card submodule is used to generate signal data based on the FPGA function module and transmit the data to the scene model software module; The adjustable resistor clamp module also includes a circuit protection unit; the circuit protection unit is used to adjust the circuit breaking function of the input and output signals through a high-speed analog switch; to adjust the current limiting function through a resistor and a current detection chip; and to set the serial impedance and parallel impedance of the signal at the input end and adjust the differential signal impedance through a relay control array; The signals of the high-speed card submodule and the adjustable resistor card submodule are connected in series and integrated inside the FPGA function module to control and protect the FPGA function module.

3. The system of protocol customized scenario model based on FPGA according to claim 1, characterized in that: The FPGA functional module includes: A receiving unit, used to receive IP instructions and parameter configuration information of the hardware module, and also receive a parameter set of the scene model software module; The IP core unit is used to convert the received parameter configuration information and parameter set into IP, obtain the IP core of the protocol customized scenario model, integrate the data of the IP core, and pass it to the scenario model software module and the adjustable resistance card submodule; The interaction unit transfers the data of the IP core to the bus for data interaction with the bus.

4. The system of protocol customized scenario model based on FPGA according to claim 3, characterized in that: The IP core unit includes: The set protocol model IP core unit is used to output a unified waveform of the set IP core; the set protocol model includes a model corresponding to the storage scenario model framework; Custom protocol model IP core unit, used to simulate the waveform of user-defined data and automatically convert it into unified output waveform data; Specifically, the IP core unit converts the received data into a voltage value according to preset rules and preset sampling rate, and stores the voltage value in a preset space in real time; extracts the voltage value in the preset space, and performs voltage regulation, signal filtering, slope adjustment, and white noise injection, and then stores it in the storage space; extracts the data in the storage space and outputs unified waveform data.

5. A method for protocol customization scenario model based on FPGA, characterized in that: The method is applied to the system of protocol customized scenario model based on FPGA according to claim 1, and the method comprises: Step S1, integrating the hardware module into the FPGA function module, and sending an IP instruction to the FPGA function module; Step S2, setting the parameter set generated by the scene model framework, transmitting it to the FPGA function module, and uniformly managing the scene model framework and data; Step S3, based on the hardware module and the scenario model software module, an IP core of the protocol customized scenario model is formed, and the IP core data is transmitted to the bus, and the data is simultaneously transmitted to the hardware module and the scenario model software module for circuit protection; The step S1 comprises: Step S1.1, making the high-speed board submodule match the received parameter configuration, obtaining the parameter configuration information corresponding to the FPGA, and sending the parameter configuration information and IP instructions, so that the FPGA function module forms a model IP core; Step S1.2, based on the FPGA function module, the adjustable resistor card module generates signal data and transmits the data to the scene model software module; The adjustable resistor clamp module also includes a circuit protection unit; the circuit protection unit is used to adjust the circuit breaking function of the input and output signals through a high-speed analog switch; to adjust the current limiting function through a resistor and a current detection chip; and to set the serial impedance and parallel impedance of the signal at the input end and adjust the differential signal impedance through a relay control array; The signals of the high-speed card submodule and the adjustable resistor card submodule are connected in series and integrated inside the FPGA function module to control and protect the FPGA function module.

6. The method of protocol customized scenario model based on FPGA according to claim 5, characterized in that: The step S2 comprises: Step S2.1, the scene model library submodule stores the scene model framework and the customized improved scene model framework; Step S2.2, the parameter setting submodule sets the signal mode parameters, automatic impedance parameters, signal physical layer parameters, signal electrical layer parameters, and signal protocol layer parameters corresponding to the scene model framework in the scene model library, and integrates all the settings into a parameter set and transmits it to the FPGA functional module.

7. The method of protocol customized scenario model based on FPGA according to claim 5, characterized in that: The step S3 comprises: Step S3.1, instructing the receiving unit to receive the IP-based instructions and parameter configuration information of the hardware module, and at the same time receive the parameter set of the scene model software module; Step S3.2, instructing the IP core unit to IP the received parameter configuration information and parameter set, obtain the IP core of the protocol customized scenario model, integrate the data of the IP core, and pass it to the scenario model software module and the adjustable resistance card submodule; Step S3.3, instructing the interaction unit to transfer the data of the IP core to the bus and interact with the bus.

8. The method of protocol customized scenario model based on FPGA according to claim 7, characterized in that: The step S3.2 comprises: The set protocol model IP core unit is made to output a unified waveform after the set IP core; the set protocol model includes a model corresponding to the storage scenario model framework; Make the custom protocol model IP core unit simulate the waveform of user-defined data and automatically convert it into unified output waveform data; Step S3.2.1, the IP core unit converts the received data into a voltage value according to a preset rule and a preset sampling rate; Step S3.2.2, storing the voltage value into a preset space in real time; Step S3.2.3, extracting the voltage value in the preset space, and performing voltage regulation, signal filtering, slope regulation, and white noise injection, and then storing it in the storage space; Step S3.2.4, extracting data from the storage space and outputting unified waveform data.

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