LLM-Agent-based integrated circuit back-end verification method

Abstract

The invention discloses a back-end verification method for an integrated circuit based on LLM-Agent. The method comprises the following steps: step 1, setting a proxy rule; 2, configuring a back-end verification tool; 3, enabling the LLM to learn an operation guide and a rule document; step 4, acquiring user input, extracting required parameters, and generating a command line instruction required by a calling tool; and 5, performing task planning on the large language model LLM, and calling a tool to realize back-end verification. According to the method, the user can use the back-end verification tool more intelligently, the learning cost of the user is reduced, meanwhile, the intelligent decision of the large language model LLM also enables the user to cope with a complex back-end verification task better, and the completion quality of the task is improved.

Description

Technical Field

[0001] The present invention relates to the field of electrical design automation (EDA), and in particular to an integrated circuit back-end verification method based on LLM-Agent. Background Art

[0002] As the complexity of integrated circuit (IC) design continues to increase, back-end verification becomes particularly important in ensuring that chip designs meet manufacturing process requirements and design specifications. Back-end verification of integrated circuits includes multiple steps, such as design rule checking (DRC), layout and schematic verification, etc. Figure 1 These verification steps are designed to ensure that the design works properly at the physical and electrical levels and meets the requirements of the production process.

[0003] Among them, DRC is a key step in verifying whether the design meets the manufacturing process design rules. These rules include the geometric dimensions of the layout, the distance between layers, the connection method, etc.; LVS check is used to verify whether the actual layout of the design is consistent with the circuit design in the schematic diagram. It is necessary to compare the circuit netlist in the layout with the netlist in the schematic diagram to identify inconsistencies in the design; RC Extraction involves extracting parasitic resistance and capacitance parameters from the physical layout of the design for more accurate circuit simulation and performance analysis.

[0004] Traditional technologies rely on manual configuration of parameters and manual analysis, and the process is complicated, with problems such as low efficiency, high error rate, and difficulty in getting started.

[0005] LLM-Agent is an intelligent agent with a large language model as its core. It has analysis, memory, planning, action and other modules, and aims to achieve some goals or tasks set by the user. The large language model LLM obtains feedback information and autonomously chooses to use preset or newly created tools (functions) to complete tasks in a self-dialogue and iterative manner. By configuring LLM-Agent to autonomously call tools to complete back-end verification tasks, a new back-end verification method based on LLM-Agent can be implemented. Summary of the invention

[0006] In view of the problems existing in the prior art, the present invention provides an integrated circuit back-end verification method based on LLM-Agent; the present invention can enable users to use back-end verification tools more intelligently, reducing the user's learning cost. At the same time, the intelligent decision-making of the large language model LLM also enables users to better cope with complex back-end verification tasks and improve the quality of task completion.

[0007] The technical solution of the present invention is specifically as follows.

[0008] The present invention provides an integrated circuit back-end verification method based on LLM-Agent, comprising the following steps: 1) Set proxy rules; 2) Configure the backend verification tool; 3) Let the large language model LLM learn the operation guide and rule documents; 4) Obtain user input, extract the parameters requested by the user, and generate the command line instructions required to call the tool; 5) The large language model (LLM) is used for task planning and tools are called to implement backend verification.

[0009] In the present invention, in step 1), the agent Agent is set to the ReACT paradigm, adopting the cycle of "thinking → action → observation", selecting a suitable backend verification tool and continuously iterating the results.

[0010] In the present invention, in step 2), the back-end verification tools include design rule checking DRC, LVS and RC parameter extraction; and a description is added to each tool in natural language as an action instruction. These action instructions serve as guiding principles to enable the agent to accurately select the most appropriate tool in the action phase.

[0011] In the present invention, in step 3), a local knowledge base path is set for the agent, and the user manual, rule file and process library of the back-end verification tool are input into the local knowledge base; the large language model LLM learns the operation guide and rule document; and the LLM-Agent is set to use RAG technology to obtain the operation guide, technical manual and rule document in the local knowledge base, including the manufacturing process rule manual, user manual, rule file writing specification, design specification document and device model document.

[0012] In the present invention, in step 4), the method for generating the command line instructions required for calling the tool is as follows: User requests are in natural language format, and these requests are converted into structured formats using predefined templates. The predefined templates contain the types, related parameters, and requirements required to call the backend verification tool through the command line interface. Among them, the types include "DRC", "LVS", "RC Extraction", etc., related parameters such as "-hier" (specify the tool to run cellhierarchy mode) and "-cpu" (specify the number of CPU cores required for the tool to run), etc., and related requirements such as the command input to the command line interface should be array type or string type.

[0013] In the present invention, in step 4), a task requested by a user is decomposed into several requirement lists, each list corresponding to a simple subtask, so as to limit the complexity of a single task and reduce errors.

[0014] In the present invention, in step 5), the large language model LLM plans the tools that need to be called in sequence to complete the task, and calls the tools through the command line interface. After the tool is executed, the agent outputs the original result report to the user, and autonomously iterates and calls the layout editing tool to repair, check or optimize until all errors are eliminated or the required optimization is completed, and then outputs the final result report to the user.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention enables users to use backend verification tools more intelligently, reducing users' learning costs. At the same time, the intelligent decision-making of the large language model also enables users to better cope with complex backend verification tasks and improve the quality of task completion. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flowchart of a back-end verification method based on LLM-Agent provided in an embodiment of the present invention.

[0017] Figure 2 It is a flowchart of obtaining user input and generating command line instructions provided by an embodiment of the present invention.

[0018] Figure 3 It is a flowchart of task planning, tool calling, backend verification, output of result report and subsequent iterative repair provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0020] The present invention provides an integrated circuit back-end verification method based on LLM-Agent, wherein LLM-Agent mainly includes LLM and tools, wherein Agent performs learning and memory, task planning, and content output through LLM, and Agent completes tasks through tools. The method includes: Step 1: Set up the agent rules so that they run according to the ReACT paradigm, which is the Thought → Action → Observation cycle.

[0021] Step 2: Configure the backend verification tools, including DRC, LVS, and RCExtraction. Attach descriptions to each tool in natural language as action instructions, which serve as guidelines to enable LLM-Agent to accurately select the most appropriate tool in the action phase.

[0022] ① Design rule check DRC: DRC can check every detail in the design to ensure that all design elements comply with the predetermined design rules, thus avoiding production problems caused by designs that do not meet specifications.

[0023] ②LVS (Layout Versus Schematics): LVS helps users quickly discover and correct inconsistencies in the design by accurately comparing the layout and schematic, ensuring the correctness and reliability of the design.

[0024] ③RC parameter extraction: RCExtraction automatically extracts parasitic parameters in the design, such as resistance and capacitance, which have a direct impact on the performance and stability of the circuit. By accurately extracting these parameters, users can more accurately evaluate the performance of the circuit and optimize the design accordingly.

[0025] Step 3: Configure operation guides and rule documents. Use the documents in the local knowledge base to enhance the large language model's ability to understand backend verification. Specify the knowledge base path for the model, which includes user manuals, rule files, process libraries, and other documents. The agent uses RAG technology to retrieve the required files from the library at runtime and extract the required information for subsequent generation of command line parameters.

[0026] Step 4: Get user input and generate command line instructions. Figure 2 ,The user input is in natural language form, and LLM-Agent normalizes and formats the user input, determines the ,tools to be called and the user requirements, and generates command line ,instructions in combination with the content in the local knowledge base.

[0027] Convert user requests into a structured format using a predefined template that contains the types, related parameters, and requirements required to call the backend verification tool through the command line interface. Types include "DRC", "LVS", "RCExtraction", etc., related parameters include "-hier" (specify the tool to run in cell hierarchy mode) and "-cpu" (specify the number of CPU cores required for the tool to run), and related requirements include that the command input to the command line interface should be of array type or string type.

[0028] The step of automatically formatting the requirements input by the user also includes: decomposing a task given by the user into several requirement lists, each of which corresponds to a simple subtask, so as to limit the complexity of a single task and reduce errors. For example, if the user describes the task in natural language: "Please help me call the DRC, LVS and RC Extraction tools in sequence", LLM-Agent will split it into three subtasks: calling DRC, calling LVS, and calling RC Extraction.

[0029] Step 5: LLM-Agent performs task planning, calls tools and implements backend verification. Figure 3 , plan the tools that need to be called in sequence to complete the task, call the tools through the command line interface, and after the tool is executed, the agent will output the original result report to the user, and autonomously iterate and call the layout editing tool for repair, inspection or optimization until all errors are eliminated or the required optimization is completed, and then output the final result report to the user.

[0030] ①DRC stage: Import the layout, import the DRC rule set, and start the DRC check using the command line parameters obtained in step 4). After the check is completed, error reporting and analysis are performed, and then the Agent attempts to perform automatic repairs and runs the DRC check again, iterating repeatedly until all errors are cleared.

[0031] ②LVS link: Extract the netlist of the layout file and the netlist of the schematic, perform LVS check, generate a result analysis report, and for inconsistent errors in the report, the Agent will try to determine the cause and fix the design problem, followed by iterative checks.

[0032] ③RC parameter extraction link: Input the layout file and process file, perform RCExtraction, extract the resistors, capacitors and other parasitic effects that may affect the circuit performance, and generate the extracted netlist and report. The Agent then performs circuit simulation and makes necessary design adjustments, including modifying the design to optimize the resistor and capacitor values ​​and adjusting the layout to reduce parasitic effects. Example

[0033] Deploy the Qwen-72B model on two NVIDIA A100s as the large language model (LLM) used by this agent. Set the local knowledge base path for the agent and enter the user manual, rule files, and process library of the backend verification tool in the local knowledge base.

[0034] The user inputs the layout file and describes the requirements in natural language, for example: "Please check whether this integrated circuit design complies with the DRC specification." The large language model parses the user input, identifies the task type as DRC verification, and determines that the DRC plug-in needs to be called.

[0035] The template of the DRC command is a list consisting of input parameters and rule files. The large language model LLM obtains documents such as DRC manuals and rule files from the local knowledge base, combines the document content, and generates a list ["-drc", "-hier", "-cpu", "1", "<DRC_Rule_File> ”], and then generate the command line parameters: PhysicalVerificationTool.exe -drc -hier -cpu 1<DRC_Rule_File> ; Call the DRC plug-in to start design rule checking.

[0036] After the DRC check is completed, a result report is generated, including the number of violations, specific violation locations, and other information. The original report is output to the user and fed back to the LLM-Agent itself. The large language model LLM automatically repairs the errors and performs the DRC check again. This step is repeated until all errors in the DRC check are fixed. The repaired results are generated into a report and output to the user again as the final result.

[0037] After testing, the present invention can correctly complete all DRC and LVS test cases, including correctly identifying user requirements, correctly generating command line parameters, successfully calling the tool to complete the task and outputting the results. The RC Extension tool has more optional parameters (including "-pdb", "-fmt", "-phdb", etc.), and the accuracy of parameter selection is about 90%. Users can help large models select the correct parameters and improve the accuracy by providing clearer task requirements.

[0038] The results show that the present invention can parse the user's natural language input, select the correct plug-in, and intelligently configure the required parameters to call the plug-in to complete the user's task. In addition, the present invention can perform automatic repair and iterative inspection without human intervention, further improving the efficiency and accuracy of the back-end verification link.

Claims

1. A LLM-Agent-based integrated circuit back-end verification method, characterized in that: The following steps are involved: 1) Set proxy rules; 2) Configure the backend verification tool; 3) Let the large language model LLM learn the operation guide and rule documents; 4) Obtain user input, extract the parameters requested by the user, and generate the command line instructions required to call the tool; 5) The large language model (LLM) is used for task planning and tools are called to implement backend verification.

2. The LLM-Agent-based integrated circuit back-end verification method according to claim 1, characterized in that: In step 1), set the agent to the ReACT paradigm, adopt the "think → act → observe" cycle, select the appropriate backend verification tool and continuously iterate the results.

3. The LLM-Agent-based integrated circuit back-end verification method according to claim 1, characterized in that: In step 2), the back-end verification tools include design rule checking (DRC), LVS, and RC parameter extraction; and a description is attached to each tool in natural language as an action instruction. These action instructions serve as guidelines to enable the agent to accurately select the appropriate tool in the action phase.

4. The LLM-Agent-based integrated circuit back-end verification method according to claim 1, characterized in that: In step 3), set the local knowledge base path for the agent, and enter the user manual, rule file and process library of the back-end verification tool in the local knowledge base; the large language model LLM learning operation guide and rule document; the agent uses RAG technology to obtain the operation guide, technical manual and rule document in the local knowledge base, including the manufacturing process rule manual, user manual, rule file writing specification, design specification document and device model document.

5. The LLM-Agent-based integrated circuit back-end verification method according to claim 1, characterized in that: In step 4), the method to generate the command line instructions required to call the tool is as follows: User requests are in natural language format, and the agent converts these requests into a structured format using predefined templates. The predefined templates contain the types, related parameters, and requirements required to call the backend verification tool through the command line interface.

6. The LLM-Agent-based integrated circuit back-end verification method according to claim 1, characterized in that: In step 4), a task requested by the user is decomposed into several requirement lists, each of which corresponds to a simple subtask, so as to limit the complexity of a single task and reduce errors.

7. The LLM-Agent-based integrated circuit back-end verification method according to claim 1, characterized in that: In step 5), the large language model LLM plans the tools that need to be called in sequence to complete the task, and calls the tools through the command line interface. After the tool is executed, the agent outputs the original result report to the user, and autonomously iterates and calls the layout editing tool for repair, inspection or optimization until all errors are eliminated or the required optimization is completed, and then outputs the final result report to the user.

8. The LLM-Agent-based integrated circuit back-end verification method according to claim 1, characterized in that: In step 5), the method of implementing the backend verification by the large language model LLM calling tool includes one or more of the following DRC link, LVS link, and RC parameter extraction link; wherein: The specific steps of the DRC link are: Import the layout file, import the DRC rule set, and start the DRC check using the command line parameters obtained in step 4). After the check is completed, perform error reporting and analysis; The agent attempts to perform automatic repairs and runs the DRC check again, iterating until all errors are cleared; The specific steps of the LVS link are: Extract the netlist of the layout file and the netlist of the schematic diagram, perform LVS check, generate result analysis report, and correct the inconsistent errors in the report; The agent attempts to identify the cause and fix the design problem, then iterates the inspection; The RC parameter extraction process is specifically as follows: Input layout files and process files, execute RCExtraction, extract parasitic effects that affect circuit performance, including resistors and capacitors, and generate extracted netlists and reports; The agent performs circuit simulation and makes corresponding design adjustments, including modifying the design to optimize resistance and capacitance values ​​and adjusting the layout to reduce parasitic effects.

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