Light-emitting unit driving circuit and method, pixel circuit and display device

Abstract

The present invention provides a light-emitting unit driving circuit and method, a pixel circuit and a display device, wherein the light-emitting unit driving circuit includes a first driving tube, a second driving tube, a light emission switch, a reset switch, a data switch, a first selection switch, a second selection switch and a flip circuit. In the reset period of each frame, a reset signal is written and the circuit is reset. At the same time, the flip circuit is triggered to switch the output level, so that when the frame is switched, the first selection switch and the second selection switch are triggered to be turned on alternately, and in the data writing period of each frame, a data signal is written and output to a driving tube through the corresponding selection switch. The corresponding driving tube is triggered by the data signal to generate a current signal, and the current signal is output to the light-emitting unit through the light emission switch during the light-emitting period. In adjacent frames, the driving tubes that generate current signals work alternately, which reduces the working time of each driving tube and improves the service life.

Description

Technical Field

[0001] The present invention belongs to the field of display technology, and in particular relates to a light-emitting unit driving circuit and method, a pixel circuit and a display device. Background Art

[0002] With the popularization of OLED (light-emitting diode) technology, display devices based on organic light-emitting diodes have begun to be used in various scenarios. The driver tube uses a thin film transistor. The driver tube generates a current signal based on the received data signal and drives the light-emitting diode to emit light. The driver tube is affected by factors such as process, light, current, temperature, and stress. When facing complex environments such as outdoor and vehicle-mounted, the aging cycle of the thin film transistor may be shortened, resulting in a decrease in service life. Summary of the invention

[0003] The object of the present invention is to provide a light emitting unit driving circuit, aiming to solve the problem of short life of a driving tube in a traditional light emitting unit driving circuit.

[0004] A first aspect of an embodiment of the present invention provides a light-emitting unit driving circuit, comprising:

[0005] A first driving tube, used for converting an input data signal into a first current signal during a data writing period;

[0006] A second driving tube, used for converting an input data signal into a second current signal during a data writing period;

[0007] a light emission switch, connected to the first driving tube and the second driving tube respectively, the light emission switch being configured to be triggered to turn on by the light emission signal during a light emission period and to transmit the first current signal or the second current signal to the light emitting unit;

[0008] A reset switch connected between the reset signal terminal and the first node, the reset switch being configured to be turned on by the first scanning signal during the reset period and to transmit the reset signal to reset the first node, the first node being further connected to the gate of the first driving tube and the gate of the second driving tube;

[0009] A data switch, connected to the data line, the first driving tube and the second driving tube respectively, the data switch is used to be triggered by the second scanning signal to turn on and transmit the data signal during a data writing period;

[0010] A storage capacitor connected between the positive voltage terminal and the first node;

[0011] A first gating switch connected between the first driving tube and the data switch, wherein the first gating switch is turned on by a first level signal and turned off by a second level signal;

[0012] A second gating switch connected between the second driving tube and the data switch, wherein the second gating switch is turned on by the second level signal and turned off by the first level signal;

[0013] The flip circuit is connected to the reset switch, the first selection switch and the second selection switch respectively, and the flip circuit is used to switch the polarity of the output level every time the reset signal is received.

[0014] Optionally, the optical emission switch comprises a first transistor and a second transistor;

[0015] The first end of the first transistor is connected to the positive voltage end, the second end of the first transistor is respectively connected to the first end of the first selection switch and the first end of the second selection switch, the first end of the second transistor is respectively connected to the second end of the first driving tube and the second end of the second driving tube, and the control end of the first transistor and the control end of the second transistor are connected to form the control end of the light emission switch.

[0016] Optionally, the first gating switch comprises a third transistor, a first end of the third transistor is connected to the second end of the first transistor, a second end of the third transistor is connected to the first end of the first driving transistor, and a control end of the third transistor is connected to the second end of the flip circuit;

[0017] The second selection switch includes a fourth transistor and a fifth transistor, the first end of the fourth transistor is connected to the second end of the first transistor, the second end of the fourth transistor is connected to the first end of the second driving tube, the first end of the fifth transistor is connected to the first node, the second end of the fifth transistor is connected to the control end of the second driving tube, the control end of the fourth transistor and the control end of the fifth transistor are also respectively connected to the second end of the flip circuit, and the first node is also connected to the second end of the reset switch and the control end of the first driving tube.

[0018] Optionally, the data switch includes a sixth transistor and a seventh transistor;

[0019] The first end of the sixth transistor is connected to the data line, the second end of the sixth transistor is respectively connected to the input end of the first selection switch and the input end of the second selection switch, the first end of the seventh transistor is connected to the first node, and the second end of the seventh transistor is respectively connected to the second end of the first driving tube and the second end of the second driving tube.

[0020] Optionally, the flip circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a resistor, a first capacitor, a second capacitor and an AND gate;

[0021] The first input end of the AND gate constitutes the input end of the flip circuit, the second input end of the AND gate, the first end of the first capacitor, the first end of the resistor and the first end of the eleventh transistor are connected, the output end of the AND gate is connected to the first end of the eighth transistor, the second end of the eighth transistor, the control end of the ninth transistor and the control end of the tenth transistor are connected, the first end of the ninth transistor is used to input the first level signal, the first end of the tenth transistor is used to input the second level signal, the second end of the ninth transistor, the second end of the tenth transistor, the first end of the second capacitor and the second end of the eleventh transistor are connected to constitute the output end of the flip circuit, the control end of the eleventh transistor is connected to the control end of the eighth transistor and is used to input a clock signal, and the second end of the first capacitor, the second end of the resistor and the second end of the second capacitor are grounded;

[0022] The phase of the clock signal is the same as the phase of the reset signal.

[0023] Optionally, the light-emitting unit driving circuit further includes a voltage-stabilizing capacitor, a first end of the voltage-stabilizing capacitor is connected to the output end of the flip circuit, and a second end of the voltage-stabilizing capacitor is grounded.

[0024] A second aspect of the embodiments of the present invention provides a pixel circuit, including a light-emitting unit and the light-emitting unit driving circuit as described above, wherein the light-emitting unit driving circuit is connected to the light-emitting unit.

[0025] A third aspect of an embodiment of the present invention provides a display device, comprising a driving circuit and the pixel circuit as described above, wherein the driving circuit is connected to the pixel circuit.

[0026] A fourth aspect of an embodiment of the present invention provides a light-emitting unit driving method, which is applied to the light-emitting unit driving circuit as described above. The light-emitting unit driving method includes:

[0027] In the reset period of each frame, a reset signal and a first scanning signal are output to the reset switch to reset the light-emitting unit driving circuit and trigger the flip circuit to switch the output level, and the first gating switch and the second gating switch are respectively alternately selected in the reset period of adjacent frames;

[0028] In a data writing period of each frame, outputting a data signal and the second scanning signal to a data switch, so as to output the data signal to the first driving tube through the first gate switch or to the second driving tube through the second gate switch;

[0029] During the light emitting period of each frame, a light emitting signal is output to the light emitting switch to transfer the first current signal generated by the first driving tube or the second current signal generated by the second driving tube to the light emitting unit.

[0030] Optionally, the light emitting unit driving method further includes:

[0031] Before the reset period of the j-th frame and subsequent frames, the reset signal and the first scanning signal are output to the reset switch, where j is 1 or 2.

[0032] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned light-emitting unit driving circuit includes a first driving tube, a second driving tube, a light emission switch, a reset switch, a data switch, a first selection switch, a second selection switch and a flip circuit. In the reset period of each frame, a reset signal is written and the circuit is reset. At the same time, the flip circuit is triggered to switch the output level, so that when the frame is switched, the first selection switch and the second selection switch are triggered to be turned on alternately, and in the data writing period of each frame, the data signal is written and output to a driving tube through the corresponding selection switch. The corresponding driving tube is triggered by the data signal to generate a current signal, and the current signal is output to the light-emitting unit through the light emission switch during the light-emitting period. In adjacent frames, the driving tubes that generate current signals work alternately, which reduces the working time of each driving tube and improves the service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0034] Figure 1 A schematic diagram of the structure of a light-emitting unit driving circuit provided in Embodiment 1 of the present invention;

[0035] Figure 2 A circuit diagram of a light-emitting unit driving circuit provided in Embodiment 2 of the present invention;

[0036] Figure 3 A signal timing diagram of the light-emitting unit driving circuit provided in Embodiment 1 and Embodiment 2 of the present invention;

[0037] Figure 4 A circuit diagram of a flip circuit provided in Embodiment 3 of the present invention;

[0038] Figure 5A schematic diagram of the signal timing of the flip circuit provided in the third embodiment of the present invention;

[0039] Figure 6 A schematic diagram of the structure of a pixel circuit provided in Embodiment 4 of the present invention;

[0040] Figure 7 A schematic diagram of the structure of a display device provided in Embodiment 5 of the present invention;

[0041] Figure 8 A schematic diagram of a first flow chart of a display panel driving method provided in Embodiment 6 of the present invention;

[0042] Fig. 9 A schematic diagram of a first signal timing sequence of a display panel driving method provided in Embodiment 6 of the present invention;

[0043] Fig.10 A second flow chart of the display panel driving method provided in Embodiment 6 of the present invention;

[0044] Fig.11 A schematic diagram of a second signal timing sequence of the display panel driving method provided in Embodiment 6 of the present invention;

[0045] Fig.12 This is a schematic diagram of a third signal timing sequence of the display panel driving method provided in the sixth embodiment of the present invention.

[0046] Among them, the reference numerals in the figures are:

[0047] 101, pixel circuit; 102, driving circuit; 10, light emitting unit driving circuit; 20, light emitting unit; 11, light reflection switch; 12, reset switch; 13, data switch; 14, first selection switch; 15, second selection switch; 16, flip circuit;

[0048] SD1, first drive tube; SD2, second drive tube; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; Cst, storage capacitor; Cboost, voltage stabilizing capacitor; OLED, light emitting diode; U1, AND gate; C1, first capacitor; C2, second capacitor; R1, resistor; Q1, first node;

[0049] ELVDD, positive voltage terminal; A1, anode of the light-emitting unit; Q2, upper plate of the first capacitor; A2, output terminal of the AND gate; B, upper plate of the second capacitor; Input, input terminal of the flip circuit; Output, output terminal of the flip circuit;

[0050] Data, data signal; Vint, reset signal; EM, light emission signal; Scan1, first scanning signal; Scan2, second scanning signal;

[0051] t1, reset period; t2, data writing period; t3, light-emitting period; t4, blank timing; t11, first timing; t12, second timing; t13, third timing; t14, fourth timing; t15, fifth timing; t16, sixth timing; t17, seventh timing; t18, eighth timing. DETAILED DESCRIPTION

[0052] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0053] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0054] Embodiment 1

[0055] A first aspect of an embodiment of the present invention proposes a light-emitting unit driving circuit 10, wherein the light-emitting unit driving circuit 10 and the light-emitting unit 20 form a pixel circuit 101, wherein the pixel circuit 101 is arranged in an array on an array substrate, and a plurality of data lines and scan lines are also provided on the array substrate, wherein each light-emitting unit driving circuit 10 is connected to a data line and a scan line, and the data line and the scan line are connected to a driving circuit 102, and the driving circuit 102 is used to output a scan signal row by row through a plurality of rows of scan lines and to output a data signal Data to each light-emitting unit driving circuit 10 in the pixel circuit 101 through a plurality of columns of data lines when each row is driven, and the light-emitting unit driving circuit 10 is triggered to work according to the received scan signal and data signal Data and generates a current signal to the light-emitting unit 20, wherein the light-emitting unit 20 is a light-emitting diode OLED.

[0056] Among them, Figure 1 As shown, the light emitting unit driving circuit 10 includes:

[0057] The first driving tube SD1 is used to convert the input data signal Data into a first current signal during the data writing period t2;

[0058] The second driving tube SD2 is used to convert the input data signal Data into a second current signal during the data writing period t2;

[0059] The light emission switch 11 is connected to the first driving tube SD1 and the second driving tube SD2 respectively. The light emission switch 11 is used to be triggered to turn on by the light emission signal EM during the light emission period t3 and transmit the first current signal or the second current signal to the light emitting unit 20;

[0060] A reset switch 12 is connected between the reset signal Vint terminal and the first node Q1. The reset switch 12 is used to be triggered by the first scan signal Scan1 to turn on during the reset period t1 and transmit the reset signal Vint to reset the first node Q1. The first node Q1 is also connected to the gate of the first drive tube SD1 and the gate of the second drive tube SD2.

[0061] The data switch 13 is connected to the data line, the first driving transistor SD1 and the second driving transistor SD2 respectively. The data switch 13 is used to be triggered by the second scanning signal Scan2 to conduct and transmit the data signal Data during the data writing period t2;

[0062] A storage capacitor Cst is connected between the positive voltage terminal ELVDD and the first node Q1;

[0063] The first selection switch 14 is connected between the first driving tube SD1 and the data switch 13. The first selection switch 14 is turned on by the first level signal VGH and turned off by the second level signal VGL.

[0064] The second selection switch 15 is connected between the second driving tube SD2 and the data switch 13. The second selection switch 15 is turned on by the second level signal VGL and turned off by the first level signal VGH.

[0065] The flip circuit 16 is connected to the reset switch 12, the first selection switch 14 and the second selection switch 15 respectively. The flip circuit 16 is used to switch the polarity of the output level every time a reset signal Vint is received.

[0066] In this embodiment, for each light emitting unit 20, when it is selected to work in each frame, Figure 3As shown, the light-emitting unit driving circuit 10 sequentially operates in the reset period t1, the data writing period t2 and the light-emitting period t3. In the reset period t1 of the i-th frame, the first scanning signal Scan1 triggers the reset switch 12 to turn on, and the reset signal Vint is written into the first node Q1 and the flip circuit 16. The flip circuit 16 outputs the first level signal VGH. The first level signal VGH triggers the first selection switch 14 to turn on, and triggers the second selection switch 15 to turn off. At the same time, the storage capacitor Cst, the first driving tube SD1 and the second driving tube SD2 are reset and cleared to zero, so as to avoid the residual charge of the circuit in the previous frame affecting the display effect of the current frame.

[0067] In the data writing period t2 of the i-th frame, the second scan signal Scan2 triggers the data switch 13 to turn on, and the data signal Data is written into the first drive tube SD1 through the data switch 13 and the first selection switch 14. The first drive tube SD1 generates a current signal based on the data signal Data. At the same time, the storage capacitor Cst is charged to maintain the voltage of the data signal Data.

[0068] In the light emitting period t3 of the i-th frame, the light emitting signal EM triggers the light emitting switch 11 to turn on, and the current signal generated by the first driving tube SD1 is output to the light emitting unit 20 through the light emitting switch 11. The light emitting unit 20 generates a light signal of corresponding magnitude based on the current signal.

[0069] And in the i+1th frame, in the reset period t1 of the i+1th frame, the reset signal Vint is output to the flip circuit 16, the flip circuit 16 switches the output level, and outputs the second level signal VGL, the second level signal VGL and the first level signal VGH are high and low level signals respectively, the second level signal VGL triggers the second selection switch 15 to turn on, and triggers the first selection switch 14 to turn off, at the same time, the first scan signal Scan1 triggers the reset switch 12 to turn on, the reset signal Vint is written to the first node Q1, and the storage capacitor Cst, the first drive tube SD1 and the second drive tube SD2 are reset and cleared to zero, so as to avoid the residual charge of the circuit in the previous frame affecting the display effect of the current frame.

[0070] In the data writing period t2 of the i+1th frame, the second scanning signal Scan2 triggers the data switch 13 to turn on, and the data signal Data is written into the second driving tube SD2 through the data switch 13 and the second selection switch 15. The second driving tube SD2 generates a current signal based on the data signal Data. At the same time, the storage capacitor Cst is charged to maintain the voltage of the data signal Data.

[0071] In the light emitting period t3 of the i+1th frame, the light emitting signal EM triggers the light emitting switch 11 to turn on, and the current signal generated by the second driving tube SD2 is output to the light emitting unit 20 through the light emitting switch 11. The light emitting unit 20 generates a light signal of corresponding magnitude based on the current signal.

[0072] And in subsequent frames, the gating of the gating switch and the driving operation of the corresponding driving tube are repeated, so that in each frame, the first driving tube SD1 and the second driving tube SD2 are alternately selected to generate a current signal based on the data signal Data, which reduces the working time of each driving tube and improves its service life.

[0073] The first driving tube SD1 works in odd frames, and the second driving tube SD2 works in even frames, or the first driving tube SD1 works in even frames, and the second driving tube SD2 works in odd frames.

[0074] And when one of the driving tubes works abnormally, it is possible to choose to output two reset signals Vint in the reset period t1, or first output a reset signal Vint in the blank timing t4 in the middle of the frame switching, and then normally output the reset signal Vint in the reset period t1 of the next frame, so as to skip the abnormal driving tube and select the normally working driving tube in each frame. For example, assuming that the first driving tube SD1 works in an odd frame, when the first driving tube SD1 is abnormal, it is possible to choose to output two reset signals Vint in the reset period t1 of the first frame, or first output a reset signal Vint in the blank timing t4 in the middle of the frame switching, and then normally output the reset signal Vint in the reset period t1 of the odd frame. The two reset signals Vint trigger the flip circuit 16 to output the first level signal VGH and the second level signal VGL in sequence, so that in the last period of the reset period t1, the flip circuit 16 outputs the second level signal VGL, and the second level signal VGL triggers the second driving tube SD2 to turn on, so as to skip the abnormal first driving tube SD1 and select the normal second driving tube SD2 to work.

[0075] And in the second frame and subsequent frames, two reset signals Vint are input before the data writing period t2, and the two reset signals Vint trigger the flip circuit 16 to output the first level signal VGH and the second level signal VGL in sequence, so that in the last period of the reset period t1, the flip circuit 16 outputs the second level signal VGL, and the second level signal VGL triggers the second drive tube SD2 to turn on, thereby skipping the abnormal first drive tube SD1 and selecting the normal second drive tube SD2 to work.

[0076] The first driving tube SD1 and the second driving tube SD2 are thin film transistors, and may be corresponding N-channel thin film transistors or P-channel thin film transistors.

[0077] The light emission switch 11, the reset switch 12, and the data switch 13 can select thin film transistors of corresponding types and numbers, and the flip circuit 16 can adopt corresponding logic circuits, such as latches, logic gates, etc.

[0078] The first selection switch 14 and the second selection switch 15 can use thin film transistors of opposite types, or use thin film transistors of the same type, wherein one of the selection switches is further connected to an inverter circuit, and the specific structure is not limited.

[0079] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned light-emitting unit driving circuit 10 includes a first driving tube SD1, a second driving tube SD2, a light emission switch 11, a reset switch 12, a data switch 13, a first selection switch 14, a second selection switch 15 and a flip circuit 16. In the reset period t1 of each frame, the reset signal Vint is written and the circuit is reset. At the same time, the flip circuit 16 is triggered to switch the output level, so that when the frame is switched, the first selection switch 14 and the second selection switch 15 are triggered to be alternately turned on, and in the data writing period t2 of each frame, the data signal Data is written and output to a driving tube through the corresponding selection switch. The corresponding driving tube is triggered by the data signal Data to generate a current signal, and the current signal is output to the light-emitting unit 20 through the light emission switch 11 in the light-emitting period t3. In adjacent frames, the driving tubes that generate current signals work alternately, which reduces the working time of each driving tube and improves the service life.

[0080] Embodiment 2

[0081] like Figure 2 As shown, in an optional embodiment, the optical emission switch 11 includes a first transistor T1 and a second transistor T2;

[0082] The first end of the first transistor T1 is connected to the positive voltage terminal ELVDD, the second end of the first transistor T1 is respectively connected to the first end of the first selection switch 14 and the first end of the second selection switch 15, the first end of the second transistor T2 is respectively connected to the second end of the first driving tube SD1 and the second end of the second driving tube SD2, and the control end of the first transistor T1 and the control end of the second transistor T2 are connected to form the control end of the light emission switch 11.

[0083] The first selection switch 14 includes a third transistor T3 , a first end of the third transistor T3 is connected to the second end of the first transistor T1 , a second end of the third transistor T3 is connected to the first end of the first driving transistor SD1 , and a control end of the third transistor T3 is connected to the second end of the flip circuit 16 .

[0084] The second selection switch 15 includes a fourth transistor T4 and a fifth transistor T5, wherein a first end of the fourth transistor T4 is connected to a second end of the first transistor T1, a second end of the fourth transistor T4 is connected to a first end of the second driving transistor SD2, a first end of the fifth transistor T5 is connected to a first node Q1, a second end of the fifth transistor T5 is connected to a control end of the second driving transistor SD2, a control end of the fourth transistor T4 and a control end of the fifth transistor T5 are also connected to a second end of the flip circuit 16, respectively, and the first node Q1 is also connected to a second end of the reset switch 12 and a control end of the first driving transistor SD1.

[0085] The data switch 13 includes a sixth transistor T6 and a seventh transistor T7;

[0086] A first end of the sixth transistor T6 is connected to the data line, a second end of the sixth transistor T6 is respectively connected to the input end of the first selection switch 14 and the input end of the second selection switch 15, a first end of the seventh transistor T7 is connected to the first node Q1, and a second end of the seventh transistor T7 is respectively connected to the second end of the first driving tube SD1 and the second end of the second driving tube SD2.

[0087] The reset switch 12 includes a twelfth transistor T12, a first end of the twelfth transistor T12 is connected to the reset signal Vint end and is used to input the reset signal Vint, a second end of the twelfth transistor T12 is connected to the first node Q1, and a control end of the twelfth transistor T12 is used to input the first scan signal Scan1.

[0088] In this embodiment, the first scan signal Scan1, the second scan signal Scan2 and the light emission signal EM may be low levels, and correspondingly, the twelfth transistor T12, the sixth transistor T6, the seventh transistor T7, the first transistor T1 and the second transistor T2 may correspond to P-channel thin film transistors, or the first scan signal Scan1, the second scan signal Scan2 and the light emission signal EM may be high levels, and correspondingly, the twelfth transistor T12, the sixth transistor T6, the seventh transistor T7, the first transistor T1 and the second transistor T2 may correspond to N-channel thin film transistors.

[0089] like Figure 2 and Figure 3As shown, taking the first scanning signal Scan1, the second scanning signal Scan2 and the light emission signal EM as low levels as an example, in the reset period t1 of the i-th frame, the reset signal Vint is output to the flip circuit 16, and the flip circuit 16 outputs the first level signal VGH. The first level signal VGH triggers the third transistor T3 to turn on, and triggers the fourth transistor T4 and the fifth transistor T5 to turn off. At the same time, the first scanning signal Scan1 triggers the twelfth transistor T12 to turn on, and the reset signal Vint is written into the first node Q1 through the twelfth transistor T12, and the charge of the first node Q1 is reset to zero, so as to avoid the residual charge of the circuit in the previous frame affecting the display effect of the current frame.

[0090] In the data writing period t2 of the i-th frame, the second scan signal Scan2 triggers the sixth transistor T6 and the seventh transistor T7 to turn on, and the data signal Data is written into the gate of the first driving tube SD1 through the sixth transistor T6, the third transistor T3, the seventh transistor T7 and the storage capacitor Cst. The first driving tube SD1 generates a current signal based on the data signal Data. At the same time, the storage capacitor Cst is charged to maintain the voltage of the data signal Data.

[0091] In the light-emitting period t3 of the i-th frame, the light emission signal EM triggers the first transistor T1 and the second transistor T2 to turn on, and the current signal generated by the first driving tube SD1 is output to the light-emitting unit 20 through the second transistor T2. The light-emitting unit 20 generates a light signal of corresponding size based on the current signal.

[0092] And in the i+1th frame, in the reset period t1 of the i+1th frame, the reset signal Vint is output to the flip circuit 16, the flip circuit 16 switches the output level, and outputs the second level signal VGL, the second level signal VGL and the first level signal VGH are high and low level signals respectively, the second level signal VGL triggers the fourth transistor T4 and the fifth transistor T5 to turn on, and triggers the third transistor T3 to turn off, at the same time, the first scan signal Scan1 triggers the twelfth transistor T12 to turn on, the reset signal Vint is written to the first node Q1, and the charge of the first node Q1 is reset and cleared to zero, so as to avoid the residual charge of the circuit in the previous frame affecting the display effect of the current frame.

[0093] In the data writing period t2 of the i+1th frame, the second scan signal Scan2 triggers the sixth transistor T6 and the seventh transistor T7 to turn on, and the data signal Data is written into the gate of the second driving tube SD2 through the sixth transistor T6, the seventh transistor T7, the fourth transistor T4, the fifth transistor T5 and the storage capacitor Cst. The second driving tube SD2 generates a current signal based on the data signal Data. At the same time, the storage capacitor Cst is charged to maintain the voltage of the data signal Data.

[0094] In the light-emitting period t3 of the i+1th frame, the light emission signal EM triggers the first transistor T1 and the second transistor T2 to turn on, and the current signal generated by the second driving tube SD2 is output to the light-emitting unit 20 through the second transistor T2. The light-emitting unit 20 generates a light signal of corresponding size based on the current signal.

[0095] And in subsequent frames, the selection of the third transistor T3, the fourth transistor T4 and the fifth transistor T5 and the driving operation of the corresponding driving tubes are repeated, so that in each frame, the first driving tube SD1 and the second driving tube SD2 are alternately selected to generate a current signal based on the data signal Data, thereby reducing the working time of each driving tube and improving the service life.

[0096] In order to maintain the output level of the flip circuit 16 in each frame, in an optional embodiment, as shown in FIG. Figure 2 As shown, the light-emitting unit driving circuit 10 also includes a voltage-stabilizing capacitor Cboost, a first end of the voltage-stabilizing capacitor Cboost is connected to the output end Output of the flip circuit 16, and a second end of the voltage-stabilizing capacitor Cboost is grounded. The voltage-stabilizing capacitor Cboost can be charged when the flip circuit 16 outputs different levels and maintains the continuous output of the first level signal VGH or the second level signal VGL in each frame.

[0097] Embodiment 3

[0098] like Figure 4 As shown, in an optional embodiment, the flip circuit 16 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a resistor R1, a first capacitor C1, a second capacitor C2 and an AND gate U1;

[0099] The first input end of the AND gate U1 constitutes the input end Input of the flip circuit 16, and is connected to the second input end of the AND gate U1, the first end of the first capacitor C1, the first end of the resistor R1 and the first end of the eleventh transistor T11, the output end of the AND gate U1 is connected to the first end of the eighth transistor T8, the second end of the eighth transistor T8, the control end of the ninth transistor T9 and the control end of the tenth transistor T10, the first end of the ninth transistor T9 is used to input the first level signal VGH, the first end of the tenth transistor T10 is used to input the second level signal VGL, the second end of the ninth transistor T9, the second end of the tenth transistor T10 and the first end of the second capacitor C2 and the second end of the eleventh transistor T11 are connected to constitute the output end Output of the flip circuit 16, the control end of the eleventh transistor T11 is connected to the control end of the eighth transistor T8 and is used to input the clock signal CK, the second end of the first capacitor C1, the second end of the resistor R1 and the second end of the second capacitor C2 are grounded;

[0100] The phase of the clock signal CK is the same as the phase of the reset signal Vint.

[0101] In this embodiment, Figure 5 As shown, at the first timing t11, when the input terminal Input of the flip circuit 16 inputs the first reset signal Vint, and the clock signal CK is at a high potential, the output terminal A2 of the AND gate U1 is at a low potential, the ninth transistor T9 and the eighth transistor T8 are turned on, and the tenth transistor T10 and the eleventh transistor T11 are turned off. At this time, the output terminal Output of the flip circuit 16 is at a high potential, and at the same time, the output terminal Output of the flip circuit 16 charges the second capacitor C2, and the upper plate B of the second capacitor C2 is at a high potential.

[0102] In the second timing t12, the clock signal CK is at a low potential, and the input of the flip circuit 16 is cut off. At this time, the eighth transistor T8 is cut off, the eleventh transistor T11 is turned on, the ninth transistor T9 and the tenth transistor T10 are suspended, the second capacitor C2 charges the first capacitor C1, and the potential of the upper plate Q2 of the first capacitor C1 gradually rises. The output terminal Output of the flip circuit 16 remains unchanged due to the action of the second capacitor C2.

[0103] In the third timing t13, when the input terminal Input of the flip circuit 16 inputs the second reset signal Vint and the clock signal CK is at a high potential, the upper plate Q2 of the first capacitor C1 is at a high potential, the output terminal A2 of the AND gate U1 is at a high potential, the tenth transistor T10 and the eighth transistor T8 are turned on, the eleventh transistor T11 and the ninth transistor T9 are turned off, and the output terminal Output of the flip circuit 16 is at a low potential. At the same time, the output terminal Output of the flip circuit 16 charges the second capacitor C2, and the upper plate B of the second capacitor C2 is at a low potential, that is, the level state of the output level is switched after receiving the second reset signal Vint.

[0104] In the fourth timing t14, the clock signal CK is at a low potential, and the input of the flip circuit 16 is cut off. At this time, the eighth transistor T8 is cut off, the eleventh transistor T11 is turned on, the ninth transistor T9 and the tenth transistor T10 are suspended, the second capacitor C2 charges the first capacitor C1, and the potential of the upper plate Q2 of the first capacitor C1 gradually decreases. The output terminal Output of the flip circuit 16 remains unchanged due to the action of the second capacitor C2.

[0105] In the fifth timing sequence t15, when the input terminal Input of the flip circuit 16 inputs the third reset signal Vint and the clock signal CK is at a high potential, the upper plate Q2 of the first capacitor C1 is at a low potential, the output terminal A2 of the AND gate U1 is at a low potential, the ninth transistor T9 and the eighth transistor T8 are turned on, the eleventh transistor T11 and the tenth transistor T10 are turned off, the output terminal Output of the flip circuit 16 is at a high potential, and at the same time, the output terminal Output of the flip circuit 16 charges the second capacitor C2, and the upper plate B of the second capacitor C2 is at a high potential, that is, the level state of the output level is switched after receiving the third reset signal Vint.

[0106] In the sixth timing sequence t16, the clock signal CK is at a low potential, and the input of the flip circuit 16 is cut off. At this time, the eighth transistor T8 is cut off, the eleventh transistor T11 is turned on, the ninth transistor T9 and the tenth transistor T10 are suspended, the second capacitor C2 charges the first capacitor C1, and the potential of the upper plate Q2 of the first capacitor C1 gradually rises. The output terminal Output of the flip circuit 16 remains unchanged due to the action of the second capacitor C2.

[0107] In the seventh timing sequence t17, when the input terminal Input of the flip circuit 16 inputs the third reset signal Vint and the clock signal CK is at a high potential, the upper plate Q2 of the first capacitor C1 is at a high potential, the output terminal A2 of the AND gate U1 is at a high potential, the tenth transistor T10 and the eighth transistor T8 are turned on, the eleventh transistor T11 and the ninth transistor T9 are turned off, and the output terminal Output of the flip circuit 16 is at a low potential. At the same time, the output terminal Output of the flip circuit 16 charges the second capacitor C2, and the upper plate B of the second capacitor C2 is at a low potential, that is, the level state of the output level is switched after receiving the fourth reset signal Vint.

[0108] In the eighth timing sequence t18, the clock signal CK is at a low potential, and the input of the flip circuit 16 is cut off. At this time, the eighth transistor T8 is cut off, the eleventh transistor T11 is turned on, the ninth transistor T9 and the tenth transistor T10 are suspended, the second capacitor C2 charges the first capacitor C1, and the potential of the upper plate Q2 of the first capacitor C1 gradually decreases. The output terminal Output of the flip circuit 16 remains unchanged due to the action of the second capacitor C2.

[0109] The flip circuit 16 switches the level state of the output every time it receives a reset signal Vint, thereby switching and controlling the alternating conduction of the first selection switch 14 and the second selection switch 15, and further selecting the first driving tube SD1 and the second driving tube SD2 to work alternately.

[0110] Embodiment 4

[0111] like Figure 6As shown, the present invention further proposes a pixel circuit 101, which includes a light-emitting unit 20 and a light-emitting unit driving circuit 10. The specific structure of the light-emitting unit driving circuit 10 refers to the above embodiment. Since the pixel circuit 101 adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the light-emitting unit driving circuit 10 is connected to the light-emitting unit 20.

[0112] The light-emitting unit 20 and the light-emitting unit driving circuit 10 form a single pixel circuit 101, and the pixel circuit 101 is arranged in an array to form a display module. The display module is connected to the data line, the scan line, the corresponding control signal terminal and the power terminal, and displays the corresponding image information under the drive of the data signal Data, the scan signal, multiple control signals and the voltage signal of the power terminal.

[0113] Embodiment 5

[0114] like Figure 7 As shown, the present invention further provides a display device, which includes a driving circuit 102 and a pixel circuit 101. The specific structure of the pixel circuit 101 refers to the above embodiment. Since the present display device adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the driving circuit 102 is connected to the pixel circuit 101.

[0115] The display device further includes an array substrate, on which a pixel circuit 101 is arrayed, and a plurality of data lines and scan lines are also provided on the array substrate. Each light-emitting unit driving circuit 10 is connected to a data line and a scan line, and the data line and the scan line are connected to the driving circuit 102. The driving circuit 102 is used to output scanning signals row by row through a plurality of rows of scanning lines and to output data signals Data to each light-emitting unit driving circuit 10 in the pixel circuit 101 through a plurality of columns of data lines when each row is driven. The light-emitting unit driving circuit 10 triggers operation and generates a current signal to the light-emitting unit 20 according to the received scanning signal and data signal Data, and displays corresponding image information.

[0116] Embodiment 6

[0117] A fourth aspect of the present invention provides a light-emitting unit driving method, which is applied to the light-emitting unit driving circuit 10. The light-emitting unit driving circuit 10 sequentially operates in a reset period t1, a data writing period t2, and a light-emitting period t3. Figure 8 As shown, the light-emitting unit driving method includes:

[0118] S10, in the reset period t1 of each frame, output the reset signal Vint and the first scan signal Scan1 to the reset switch 12 to reset the light-emitting unit driving circuit 10 and trigger the flip circuit 16 to switch the output level, and alternately select the first selection switch 14 and the second selection switch 15 in the reset period t1 of adjacent frames.

[0119] Among them, in the reset period t1 of the i-th frame, the reset signal Vint and the first scan signal Scan1 are output to the reset switch 12, the reset switch 12 is turned on, and the reset signal Vint is transmitted to the flip circuit 16 and the first node Q1 in the light-emitting unit driving circuit 10, triggering the flip circuit 16 to output the first level signal VGH, the first level signal VGH triggers the first selection switch 14 to turn on, and triggers the second selection switch 15 to turn off. At the same time, the reset signal Vint resets and clears the charge of the storage capacitor Cst, the first drive tube SD1 and the second drive tube SD2 to prevent the residual charge of the circuit in the previous frame from affecting the display effect of the current frame.

[0120] In the reset period t1 of the i+1th frame, another reset signal Vint and another first scan signal Scan1 are output to the reset switch 12, the reset switch 12 is turned on, and the reset signal Vint is transmitted to the flip circuit 16 and the first node Q1 in the light-emitting unit driving circuit 10, triggering the flip circuit 16 to switch and output the second level signal VGL, the second level signal VGL triggers the second selection switch 15 to turn on, and triggers the first selection switch 14 to turn off, and at the same time, the reset signal Vint resets and clears the storage capacitor Cst, the first drive tube SD1 and the second drive tube SD2 to prevent the residual charge in the circuit in the previous frame from affecting the display effect of the current frame.

[0121] And in the subsequent frames, the gating of the gating switch is repeated to achieve the alternating triggering and turning on of the first gating switch 14 and the second gating switch 15 .

[0122] S20, in the data writing period t2 of each frame, output the data signal Data and the second scan signal Scan2 to the data switch 13, so as to output the data signal Data to the first drive tube SD1 through the first selection switch 14 or to the second drive tube SD2 through the second selection switch 15.

[0123] In the data writing period t2 of the i-th frame, the second scanning signal Scan2 is output, the second scanning signal Scan2 triggers the data switch 13 to turn on, the data signal Data is written into the first driving tube SD1 through the data switch 13 and the first selection switch 14, the first driving tube SD1 generates a current signal based on the data signal Data, and at the same time, the storage capacitor Cst is charged to maintain the voltage of the data signal Data.

[0124] In the data writing period t2 of the i+1th frame, another second scanning signal Scan2 is output, and the second scanning signal Scan2 triggers the data switch 13 to turn on. The data signal Data is written into the second driving tube SD2 through the data switch 13 and the second selection switch 15. The second driving tube SD2 generates a current signal based on the data signal Data. At the same time, the storage capacitor Cst is charged to maintain the voltage of the data signal Data.

[0125] And in subsequent frames, the gating of the gating switch and the driving operation of the corresponding driving tube are repeated, so that in each frame, the first driving tube SD1 and the second driving tube SD2 are alternately selected to generate a current signal based on the data signal Data, which reduces the working time of each driving tube and improves its service life.

[0126] S30 , in the light emitting period t3 of each frame, outputting the light emitting signal EM to the light emitting switch 11 to transmit the first current signal generated by the first driving tube SD1 or the second current signal generated by the second driving tube SD2 to the light emitting unit 20 .

[0127] In the light-emitting period t3 of the i-th frame, the light emission signal EM is output, the light emission signal EM triggers the light emission switch 11 to turn on, and the current signal generated by the first driving tube SD1 is output to the light-emitting unit 20 through the light emission switch 11. The light-emitting unit 20 generates a light signal of corresponding size based on the current signal.

[0128] In the light-emitting period t3 of the i+1th frame, another light emission signal EM is output, the light emission signal EM triggers the light emission switch 11 to turn on, and the current signal generated by the second driving tube SD2 is output to the light-emitting unit 20 through the light emission switch 11, and the light-emitting unit 20 generates a light signal of corresponding size based on the current signal.

[0129] And in subsequent frames, the output operations of the above different current paths are repeated, and the light emitting unit 20 is driven to generate a light signal.

[0130] Among them, by outputting the corresponding reset signal Vint, data signal Data, light emission signal EM, first scan signal Scan1 and second scan signal Scan2 in different frames respectively, the first drive tube SD1 can be driven to work in odd frames and the second drive tube SD2 can be driven to work in even frames, or the first drive tube SD1 can be driven to work in even frames and the second drive tube SD2 can be driven to work in odd frames.

[0131] Further, when one of the driving tubes is abnormally damaged, the light-emitting unit 20 may emit light only in odd frames or even frames. To solve this problem, in an optional embodiment, Fig.10 As shown, the light-emitting unit driving method further includes:

[0132] Before the reset period t1 of the j-th frame and subsequent frames, a reset signal Vint and a first scan signal Scan1 are output to the reset switch 12 , where j is 1 or 2.

[0133] In this embodiment, it is assumed that the first driving transistor SD1 is damaged. Fig.11 As shown, a blank timing t4 can be inserted before the reset period t1 of the first frame, and a reset signal Vint and a first scanning signal Scan1 can be output, and then another reset signal Vint and another first scanning signal Scan1 can be normally output during the reset period t1, and the two reset signals Vint trigger the flip circuit 16 to output the first level signal VGH and the second level signal VGL in sequence, so that in the last period of the reset period t1, the flip circuit 16 outputs the second level signal VGL, and the second level signal VGL triggers the second drive tube SD2 to turn on, thereby skipping the abnormal first drive tube SD1 and selecting the normal second drive tube SD2 to work.

[0134] In the second frame and subsequent frames, a blank timing t4 is inserted between the two frames, and a reset signal Vint and a first scanning signal Scan1 are output at the blank timing t4, and then another reset signal Vint and another first scanning signal Scan1 are normally output during the reset period t1, and the two reset signals Vint trigger the flip circuit 16 to output the first level signal VGH and the second level signal VGL in sequence, so that in the last period of the reset period t1, the flip circuit 16 outputs the second level signal VGL, and the second level signal VGL triggers the first drive tube SD1 to turn off, and triggers the second drive tube SD2 to turn on, thereby skipping the abnormal first drive tube SD1 and selecting the normal second drive tube SD2 to work.

[0135] Or if the second drive tube SD2 is damaged, Fig.12 As shown, in the first frame, the flip circuit 16 outputs the first level signal VGH, inserts a blank timing t4 between the end of the first frame and the reset period t1 of the second frame, and outputs a reset signal Vint and a first scan signal Scan1 at the blank timing t4, and then normally outputs another reset signal Vint and another first scan signal Scan1 in the reset period t1, and the two reset signals Vint trigger the flip circuit 16 to output the second level signal VGL and the first level signal VGH in sequence, so that in the last period of the reset period t1, the flip circuit 16 outputs the first level signal VGH, and the first level signal VGH triggers the first drive tube SD1 to turn on, thereby skipping the abnormal second drive tube SD2 and selecting the normal second drive tube SD2 to work.

[0136] In the third frame and subsequent frames, a blank timing t4 is inserted between two frames, and a reset signal Vint and a first scanning signal Scan1 are output at the blank timing t4, and then another reset signal Vint and another first scanning signal Scan1 are normally output during the reset period t1, and the two reset signals Vint trigger the flip circuit 16 to output the second level signal VGL and the first level signal VGH in sequence, so that in the last period of the reset period t1, the flip circuit 16 outputs the first level signal VGH, and the first level signal VGH triggers the first driving tube SD1 to turn on, thereby skipping the abnormal second driving tube SD2 and selecting the normal second driving tube SD2 to work.

[0137] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0138] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A light-emitting unit driving circuit, characterized in that: include: A first driving tube, used for converting an input data signal into a first current signal during a data writing period; A second driving tube, used for converting an input data signal into a second current signal during a data writing period; a light emission switch, connected to the first driving tube and the second driving tube respectively, the light emission switch being configured to be triggered to turn on by the light emission signal during a light emission period and to transmit the first current signal or the second current signal to the light emitting unit; A reset switch connected between the reset signal terminal and the first node, the reset switch being configured to be turned on by the first scanning signal during the reset period and to transmit the reset signal to reset the first node, the first node being further connected to the gate of the first driving tube and the gate of the second driving tube; A data switch, connected to the data line, the first driving tube and the second driving tube respectively, the data switch is used to be triggered by the second scanning signal to turn on and transmit the data signal during a data writing period; A first gating switch connected between the first driving tube and the data switch, wherein the first gating switch is turned on by a first level signal and turned off by a second level signal; A storage capacitor connected between the positive voltage terminal and the first node; A second gating switch connected between the second driving tube and the data switch, wherein the second gating switch is turned on by the second level signal and turned off by the first level signal; The flip circuit is connected to the reset switch, the first selection switch and the second selection switch respectively, and the flip circuit is used to switch the polarity of the output level every time the reset signal is received.

2. The light emitting unit driving circuit according to claim 1, characterized in that: The optical emission switch includes a first transistor and a second transistor; The first end of the first transistor is connected to the positive voltage end, the second end of the first transistor is respectively connected to the first end of the first selection switch and the first end of the second selection switch, the first end of the second transistor is respectively connected to the second end of the first driving tube and the second end of the second driving tube, and the control end of the first transistor and the control end of the second transistor are connected to form the control end of the light emission switch.

3. The light emitting unit driving circuit according to claim 2, characterized in that: The first gating switch comprises a third transistor, a first end of the third transistor is connected to the second end of the first transistor, a second end of the third transistor is connected to the first end of the first driving transistor, and a control end of the third transistor is connected to the second end of the flip circuit; The second selection switch includes a fourth transistor and a fifth transistor, the first end of the fourth transistor is connected to the second end of the first transistor, the second end of the fourth transistor is connected to the first end of the second driving tube, the first end of the fifth transistor is connected to the first node, the second end of the fifth transistor is connected to the control end of the second driving tube, the control end of the fourth transistor and the control end of the fifth transistor are also respectively connected to the second end of the flip circuit, and the first node is also connected to the second end of the reset switch and the control end of the first driving tube.

4. The light emitting unit driving circuit according to claim 3, characterized in that: The data switch includes a sixth transistor and a seventh transistor; The first end of the sixth transistor is connected to the data line, the second end of the sixth transistor is respectively connected to the input end of the first selection switch and the input end of the second selection switch, the first end of the seventh transistor is connected to the first node, and the second end of the seventh transistor is respectively connected to the second end of the first driving tube and the second end of the second driving tube.

5. The light emitting unit driving circuit according to claim 1, characterized in that: The flip circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a resistor, a first capacitor, a second capacitor and an AND gate; The first input end of the AND gate constitutes the input end of the flip circuit, the second input end of the AND gate, the first end of the first capacitor, the first end of the resistor and the first end of the eleventh transistor are connected, the output end of the AND gate is connected to the first end of the eighth transistor, the second end of the eighth transistor, the control end of the ninth transistor and the control end of the tenth transistor are connected, the first end of the ninth transistor is used to input the first level signal, the first end of the tenth transistor is used to input the second level signal, the second end of the ninth transistor, the second end of the tenth transistor, the first end of the second capacitor and the second end of the eleventh transistor are connected to constitute the output end of the flip circuit, the control end of the eleventh transistor is connected to the control end of the eighth transistor and is used to input a clock signal, and the second end of the first capacitor, the second end of the resistor and the second end of the second capacitor are grounded; The phase of the clock signal is the same as the phase of the reset signal.

6. The light emitting unit driving circuit according to any one of claims 1 to 5, characterized in that: The light-emitting unit driving circuit further includes a voltage-stabilizing capacitor, a first end of the voltage-stabilizing capacitor is connected to the output end of the flip circuit, and a second end of the voltage-stabilizing capacitor is grounded.

7. A pixel circuit, characterized in that: It comprises a light-emitting unit and a light-emitting unit driving circuit as claimed in any one of claims 1 to 6, wherein the light-emitting unit driving circuit is connected to the light-emitting unit.

8. A display device, characterized in that: The invention comprises a driving circuit and the pixel circuit as claimed in claim 7, wherein the driving circuit is connected to the pixel circuit.

9. A light-emitting unit driving method, characterized in that: Applicable to the light-emitting unit driving circuit according to any one of claims 1 to 6, the light-emitting unit driving method comprising: In the reset period of each frame, a reset signal and a first scanning signal are output to the reset switch to reset the light-emitting unit driving circuit and trigger the flip circuit to switch the output level, and the first gating switch and the second gating switch are respectively alternately selected in the reset period of adjacent frames; In a data writing period of each frame, outputting a data signal and the second scanning signal to a data switch, so as to output the data signal to the first driving tube through the first gate switch or to the second driving tube through the second gate switch; During the light emitting period of each frame, a light emitting signal is output to the light emitting switch to transfer the first current signal generated by the first driving tube or the second current signal generated by the second driving tube to the light emitting unit.

10. The light emitting unit driving method according to claim 9, characterized in that: The light emitting unit driving method further includes: Before the reset period of the j-th frame and subsequent frames, the reset signal and the first scanning signal are output to the reset switch, where j is 1 or 2.

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