Memory device and operating method thereof

Abstract

A memory device includes a memory array including a plurality of word lines, each word line operably coupled to a respective group of memory cells, and a controller operably connected to the memory array. The controller is configured to receive a first address signal indicative of a first word line physically arranged at a first distance from the controller, assert the first word line by a first signal having a first pulse width, receive a second address signal indicative of a second word line physically arranged at a second distance from the controller, the second address signal indicates a second word line physically arranged at a second distance from the controller, asserts the second word line by a second signal having a second pulse width, and adjusts one of the first pulse width or the second pulse width based on the first distance and the second distance. The embodiment of the invention also discloses a method for operating the memory device.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory device and an operating method thereof. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In large part, the increase in integration density comes from the repeated reduction in the minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a memory array, comprising a plurality of word lines, each of the plurality of word lines being operably coupled to a corresponding group of memory cells; and a controller operably coupled to the memory array, wherein the controller is configured to: receive a first address signal, the first address signal indicating a first word line physically arranged at a first distance relative to the controller; assert the first word line by a first signal having a first pulse width; receive a second address signal, the second address signal indicating a second word line physically arranged at a second distance relative to the controller; assert the second word line by a second signal having a second pulse width; and adjust one of the first pulse width or the second pulse width based on the first distance and the second distance.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a memory array, comprising a plurality of word lines, each of the plurality of word lines being operably coupled to a corresponding group of memory cells; and a controller operably coupled to the memory array, wherein the controller is configured to: assert a first word line through a first signal according to a first address signal; assert a second word line through a second signal according to a second address signal; identify a difference in physical position between the first word line and the second word line based at least in part on the first address signal and the second address signal; and adjust a pulse width of at least one of the first signal or the second signal in response to determining that at least one of the first word line or the second word line is within a predetermined distance from the controller.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory device is provided, comprising: receiving, by a controller, a first address signal indicating a first word line among multiple word lines of a memory array; asserting, by the controller, the first word line through a first signal having a first pulse width; receiving, by the controller, a second address signal indicating a second word line among multiple word lines of the memory array; asserting, by the controller, the second word line through a second signal having a second pulse width; and in response to identifying that the first word line is physically closer to the controller than the second word line, adjusting, by the controller, one of the first pulse width or the second pulse width. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of a memory device according to some embodiments is shown.

[0008] Figure 2 Waveforms of various signals associated with the operation of an example memory device are shown according to various embodiments.

[0009] Figure 3 Example circuits in a memory device according to various embodiments and waveforms of various signals related to the operation of the circuits are shown.

[0010] Figure 4 Example circuits in a memory device according to various embodiments are shown.

[0011] Figure 5 Example circuits in a memory device according to various embodiments and waveforms of various signals related to the operation of the circuits are shown.

[0012] Figure 6 Example circuits in a memory device according to various embodiments are shown.

[0013] Fig. 7A , Figure 7B Example circuits in a memory device according to various embodiments are shown.

[0014] Fig. 8A , Figure 8B Example circuits in a memory device according to various embodiments are shown.

[0015] Fig. 9 A flow chart of an example method for operating a memory device according to some embodiments is shown. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0018] Static random access memory (SRAM) is a volatile semiconductor memory that uses a bistable circuit to store data bits without the need for refresh. An SRAM cell can be referred to as a bit cell because it stores one bit of information, represented by the logic state of two cross-coupled inverters. A memory array includes a plurality of bit cells arranged in rows and columns. Each bit cell in a memory array typically includes connections to a power supply voltage and a reference voltage. Logic signals on the bit lines control the reading and writing of the bit cells, and word lines control the connection of the bit lines to the inverters. Word lines can be coupled to the bit cells in a row of a memory array, providing different word lines for different rows.

[0019] Each successive bit cell along a bit line or word line has a characteristic input capacitance, and each conductor leg between bit cells has a resistance, resulting in signal propagation delays. Delays are longer for bit cells that are farther along the signal path than other bit cells starting at the memory addressing and control signal sources, such as the outputs of address decoding gates and line drivers coupled at the edge of the memory array. Delays affect the time required to access a bit cell and limit the highest frequency at which the memory can operate. For example, for a read / write operation, the time required to access an SRAM bit cell can vary depending on several factors, including the relative position of the bit cell being accessed within the SRAM array. Reliable estimates of SRAM timing characteristics are important to ensure consistent system component performance and high system performance.

[0020] In this regard, various techniques have been proposed to provide timing tracking functions to accurately and efficiently monitor SRAM devices. Timing tracking can determine when a bit cell completes a read or write operation. For example, a tracking bit line is usually selected from an existing bit line of a memory array to track or simulate the propagation time of a signal conducted through a normal bit line of the memory array. With the trend of continuous reduction in component size, the number of bit cells in the memory array has also increased accordingly, which results in each bit line being coupled to more and more word lines. In the prior art, all word lines on the memory array share the same tracking scheme, such as the same tracking bit line. However, since closer word lines share the same tracking timing (relative to the start of one or more control signal sources (e.g., a controller)) with farther word lines, a large amount of power is wasted for reading and / or programming the bit cells coupled to the closer word lines. Therefore, the existing timing tracking techniques or corresponding circuits for SRAM devices are not completely satisfactory in some aspects.

[0021] The present disclosure provides various embodiments of a memory device, which includes a controller and at least one memory array (including a plurality of bit cells) that are physically adjacent to each other and operably coupled. In various embodiments, the controller can adjust the pulse width of a word line signal based on how far the asserted word line is from the controller. For example, the controller can receive an address signal including a plurality of bits, one of which corresponds to a corresponding subset of word lines when provided in a specific logic state. After configuring such a bit to a logic state (which is configured to assert one of the word lines in the corresponding word line subset), the controller can adjust the pulse width of the corresponding word line signal (e.g., by adjusting the pulse width of a clock pulse). Therefore, a word line subset located closer to the controller can be asserted with a word line signal having a reduced pulse width compared to a word line subset located farther from the controller. Therefore, a narrower word line pulse width can be adaptively (or automatically) configured in a word line subset closer to the controller than a farther word line subset. Therefore, undesirable power consumption (when reading and / or programming closer bit cells) can be advantageously avoided.

[0022] Figure 1 1 is a block diagram of a memory device 100 according to various embodiments. For illustration purposes, Figure 1 The memory device 100 shown in FIG. 1 is simplified, and thus, it should be understood that the memory device 100 may include any of a variety of other components while still being within the scope of the present disclosure.

[0023] As shown, the memory device 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of storage circuits or memory cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 may be coupled to one or more corresponding word lines (WL) and one or more corresponding bit lines (BL). The memory controller 105 may write data to or read data from the memory array 120 based on electrical signals through the word lines WL and the bit lines BL. In addition, according to various embodiments of the present disclosure, the memory controller 105 may adjust the pulse width of the WL signal conducted through the corresponding asserted word line WL based on the physical distance between the asserted word line and the memory controller 105, which will be discussed in further detail below. In other embodiments, the memory device 100 includes a plurality of storage circuits or memory cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 may be coupled to one or more corresponding word lines (WL) and one or more corresponding bit lines (BL). The memory controller 105 may write data to or read data from the memory array 120 based on electrical signals through the word lines WL and the bit lines BL. In addition, according to various embodiments of the present disclosure, the memory controller 105 may adjust the pulse width of the WL signal conducted through the corresponding asserted word line WL based on the physical distance between the asserted word line and the memory controller 105, which will be discussed in further detail below. Figure 1 More, fewer or different components may be shown.

[0024] The memory array 120 is a hardware component for storing data. In one aspect, the memory array 120 includes a plurality of storage circuits or memory cells 125. The memory array 120 includes word lines WL0 ... WLJ and bit lines BL0 ... BLK, each word line WL0 ... WLJ extending in a first direction (e.g., X direction), and each bit line BL0 ... BLK extending in a second direction (e.g., Y direction). In some embodiments, the memory array 120 may be referred to as having a plurality of columns and a plurality of rows, wherein each column corresponds to a corresponding one of the bit lines BL, and each row corresponds to a corresponding one of the word lines WL. As shown, in some embodiments, the word line may include a plurality of subsets, each subset in the plurality of subsets including one or more word lines. That is, the memory array 120 may include K columns and J rows of memory cells 125. The word line WL and the bit line BL may be conductive metal or conductive rails. Each memory cell 125 is coupled to a corresponding word line WL and a corresponding bit line BL, and may be operated according to a voltage or current through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes a bit line BL / BLB coupled to one or more memory cells 125 in a group of memory cells 125 arranged along a second direction (e.g., Y direction). The bit lines BL, BLB may receive and / or provide a differential signal. Each memory cell 125 may include a volatile memory, a non-volatile memory, or a combination thereof. In some embodiments, each memory cell 125 is implemented as a static random access memory (SRAM) cell or other type of memory cell. In some embodiments, the memory array 120 includes additional lines (e.g., a select line, a reference line, a reference control line, a power rail, etc.).

[0025] In addition to memory cells 125 configured to store data (sometimes referred to as nominal memory cells), memory array 120 may also include one or more tracking columns 130 disposed adjacent to or integrated into memory array 120, such as Figure 1 As shown. Each tracking column 130 may include a plurality of tracking cells 135 and a plurality of dummy cells 140. The tracking cells 135 and dummy cells 140 may be configured in any corresponding number, with the total number of tracking cells 135 and dummy cells 140 being equal to the number of rows (J), while still being within the scope of the present disclosure. For example, the number of tracking cells 135 may be selected to simulate the worst case in a write and / or read operation.

[0026] In addition, the tracking column 130 may include at least one tracking word line 145 and at least one tracking bit line 150, wherein the tracking word line 145 is connected to each tracking cell 135, and the tracking bit line 150 is connected to each tracking cell 135 and the dummy cell 140. The tracking word line 145 and the tracking bit line 150 are configured to conduct tracking signals TKWL and TKBL, respectively. By conducting the TKWL and TKBL signals, the tracking word line 145 and the tracking bit line 150 may respectively simulate signal routing delays in a functional memory array (e.g., 120) for read or write operations at far edges. In addition, according to various embodiments of the present disclosure, the memory controller 105 may adjust the pulse width of the tracking signals TKWL and / or TKBL conducted through the corresponding assertion word line WL and / or bit line BL based on the physical distance between the assertion line and the memory controller 105, which will be discussed in further detail below. In other embodiments, the memory device 100 includes a tracking signal TKWL and / or a tracking signal TKBL. Figure 1 More, fewer or different components may be shown.

[0027] In some embodiments, tracking word line 145 may include Figure 1 120, and a (e.g., vertical) portion extending along a row (not explicitly shown) of the memory array 120. The length of the vertical portion of the tracking word line 145 may be approximately equal to the height of the memory array (e.g., according to Figure 1 145 ); and the length of the horizontal portion of the tracking word line 145 can be approximately equal to the width of the memory array 120 (e.g., according to Figure 1140). Thus, the sum of the lengths of the first and second portions of tracking word line 145 can cause metal wiring delays for accessing a cell at the upper right corner of memory array 120 to be simulated, for example, by delays propagating horizontally and vertically from a signal input at the lower left corner over a path distance equal to the path length from one corner to the diagonally opposite corner.

[0028] Generally speaking, the tracking cells 135 function differently from the (nominal) memory cells 125 in terms of storing data and supporting read / write operations. Instead, the tracking cells 135 may initially be a subset of the nominal memory cells 125, but may be registered or reused for timing tracking. For example, the tracking cells 135 are bit cells with fixed logic values ​​that are configured and coupled to each other so as to respond in a predictable manner when addressed by a test or tracking signal. The dummy cells 140 enable the capacitive and resistive environments to be closely matched so as to accurately model the environment of the nominal memory cells. The bit lines being tracked typically have two factors that determine the propagation delay of the transmitted signals, namely, series resistance and shunt capacitance. The dummy cells 140 have a real capacitive load and simulate the capacitance of the bit lines BL coupled to the nominal memory cells. If the dummy cells 140 are not provided, the length of the tracking bit lines will effectively appear shorter than the nominal bit lines BL that they are to simulate, which will reduce the resistance and capacitance and may cause the tracking circuit to determine that the read or write operation has ended prematurely.

[0029] The memory controller 105 is a hardware component configured to control various operations of the memory array 120, such as reading data bits from the memory cells 125, writing data bits to the memory cells 125, performing tracking schemes on various timings of read / write operations, adjusting the tracking timings of read / write operations, etc. In various embodiments, the memory controller 105 may include a plurality of circuits, each of which may be embodied as a logic circuit, an analog circuit, or a combination thereof, to perform these operations.

[0030] For example, the memory controller 105 may include a clock generator, a pulse generator, and an adaptive tracking circuit. The clock generator may receive or generate a clock signal and provide a clock signal to the pulse generator to generate a plurality of clock pulses. The pulse generator may rely on the clock pulse to control (e.g., pull up and / or pull down) a plurality of control signals (e.g., TKWL signals) conducted through the tracking word line. The adaptive tracking circuit may receive an address signal indicating at least one word line WL to be asserted. Based on the address signal indicating the physical location of the asserted word line, the adaptive tracking circuit may selectively adjust the timing of a plurality of control signals (e.g., TKBL signals) conducted through the tracking bit line. The selectively adjusted TKBL signal may be further received by the pulse generator, which causes the clock pulse to be adjusted. Such an adjusted clock pulse may be configured to adjust (e.g., shorten) the pulse width of the WL signal conducted through the asserted word line WL within the memory array 120.

[0031] In some embodiments, the memory device 100 may also include various other circuit components, such as a word line driver / controller 160, an input / output (I / O) circuit 170, etc., each of which may be embodied as a logic circuit, an analog circuit, or a combination thereof. The word line driver 160 may provide a voltage or current conducted through one or more word lines WL of the memory array 120. Such a voltage / current may sometimes be referred to as a WL signal. The controller 105 may adjust the pulse width of the WL signal using an adjusted clock pulse (as described above). The I / O circuit 170 may sense a voltage or current conducted through one or more bit lines BL of the memory array 120. For example, the I / O circuit 170 may include a plurality of sense amplifiers, each of which may be operably coupled to one or more bit lines BL within the memory array 120.

[0032] Figure 2 Waveforms 200 of various signals associated with the operation of an example memory device according to various embodiments are shown. For example, waveform 200 may be associated with memory device 100. Therefore, the following discussion of waveform 200 may refer to Figure 1 Some reference numbers used in FIG. 2 are provided as non-limiting examples. Furthermore, waveform 200 is shown only as an example and is not intended to limit the present disclosure.

[0033] The clock generator of the memory controller 105 may generate a clock signal (CLK) 210 and provide the CLK 210 to the pulse generator to generate a clock pulse (CKP) 230. Figure 2As shown, the rising edge 212 of CLK 210 can be substantially synchronized with the rising edge 232 of CKP 230. In response to CLK 210 and / or CKP 230, the memory controller 105 can assert the word line through the word line (WL) signal based on the address signal indicating the word line. For example, the memory controller 105 can receive the address signal ABOT 220 indicating the first word line and assert the first word line through the WL signal 250. For example, the memory controller 105 can receive the address signal ATOP 225 indicating the second word line and assert the second word line through the WL signal 240. Figure 2 As shown, the rising edge 232 of CKP 230 may be substantially synchronized with the rising edge 242 of WL signal 240, and the rising edge 234 of CKP 230 may be substantially synchronized with the rising edge 252 of WL signal 250. Based on WL signal 240 and WL signal 250, corresponding data may be processed (e.g., read / write). Figure 2 As shown, the data line (DL) and the inverted data line (DLB) can generate a DL signal 262 and a DLB signal 264 according to the WL signal 240 and the WL signal 250, respectively, indicating the data bits (1 or 0) associated with the corresponding memory cells.

[0034] The memory controller 105 may control one or more signals shown in the waveform 200. In some examples, the memory controller 105 may control one or more signals shown in the waveform 200 based on the physical location of the word line. The memory controller 105 may receive an address signal ATOP 225 indicating a first word line that is physically arranged at a first distance relative to the memory controller 105, and assert the first word line through a WL signal 250 having a first pulse width 256. For example, the WL signal 250 having the first pulse width 256 may be generated based on a corresponding portion of the CKP 230 having the first pulse width 238. The memory controller 105 may receive an address signal ABOT 220 indicating a second word line that is physically arranged at a second distance relative to the memory controller 105, and assert the second word line through a WL signal 240 having a second pulse width 246. For example, the WL signal 240 having the second pulse width 246 may be generated based on a corresponding portion of the CKP 230 having the second pulse width 236. The memory controller 105 may adjust one of the second pulse width 246 or the first pulse width 256 based on the first distance and the second distance (e.g., by adjusting the second pulse width 236 or the first pulse width 238 of the CKP 230). For example, when the first word line is physically closer to the memory controller 105 than the second word line (e.g., the first distance is less than the second distance), the memory controller 105 may adjust the first pulse width 238 of the CKP 230 (e.g., reduce the pulse width as shown) so that the first word line is asserted with the WL signal 250 of the shorter pulse width (e.g., pulse width 256). As shown by the DLB signal 264 having the shortened pulse width, unnecessary power consumption to access bits associated with the first word line may be prevented.

[0035] Figure 3 3 shows an example circuit 300 in a memory device 100 and waveforms 350 of various signals associated with the operation of the circuit 300 according to various embodiments. The circuit 300 may be Figure 1 Features of tracking column 130 shown in .

[0036] As shown, circuit 300 includes a plurality of tracking cells, including a first tracking cell 310 and a second tracking cell 320. The first tracking cell 310 may correspond to a first word line of a plurality of word lines, and the second tracking cell 320 may correspond to a second word line of a plurality of word lines. In some embodiments, each of the first tracking cell 310 and the second tracking cell 320 is located at a position physically corresponding to each of the first word line and the second word line, respectively. For example, the first word line and the first tracking cell 310 are physically closer to the controller 105 than the second word line and the second tracking cell 320.

[0037] Referring to the waveform 350, the circuit 300 may be controlled by the memory controller 105. The clock generator of the memory controller 105 may generate the CLK 360 and provide the CLK 360 to the pulse generator to generate the CKP 370. In response to the CLK 360 and / or the CKP 370, the memory controller 105 may assert the tracking unit through the tracking line signal based on the address signal indicating the tracking unit to be asserted. For example, the memory controller 105 may receive the address signal / A[MSB] (MSB: Most Significant Bit) indicating the first tracking unit 310 and assert the first tracking unit 310 through the tracking line signal TRKBL_BOT 385. For example, the memory controller 105 may receive the address signal A[MSB] 324 indicating the second tracking unit 320 and assert the second tracking unit 320 through the tracking line signal TRKBL_TOP 380.

[0038] The memory controller 105 may control one or more of the signals shown in the waveform 350. In some examples, the memory controller 105 may control one or more of the signals shown in the waveform 350 based on the physical location of the tracking unit. The memory controller 105 may receive an address signal / A[MSB] 314 indicating a first tracking unit 310 that is physically arranged at a first distance relative to the memory controller 105, and assert the first tracking unit 310 through a TRKBL_BOT 385 having a first slope 387. For example, the TRKBL_BOT 385 having the first slope 387 may be generated based on a corresponding portion of the CKP 370 having the first pulse width 374. The memory controller 105 may receive an address signal A[MSB] 324 indicating a second tracking unit 320 that is physically arranged at a second distance relative to the memory controller 105, and assert the second tracking unit 320 through a tracking signal TRKBL_TOP 380 having a second slope 382. For example, the tracking signal TRKBL_TOP 380 having the second slope 382 may be generated based on the corresponding portion of the CKP 370 having the second pulse width 372. The memory controller 105 may adjust one of the first pulse width 374 or the second pulse width 372 based on the first distance and the second distance (e.g., by adjusting the pulse width 372 or the pulse width 374 of the CKP 370). For example, when the first tracking unit 310 is physically closer to the memory controller 105 than the second tracking unit 320 (e.g., the first distance is less than the second distance), the memory controller 105 may adjust the pulse width 374 of the CKP 370 (e.g., reduce the pulse width as shown) so as to assert the first tracking unit 110 with the TRKBL_BOT 385 having the first slope 387.

[0039] Figure 4 An example circuit 400 is shown in the memory device 100 according to various embodiments. The circuit 400 may be a feature of the tracking column 130 .

[0040] As shown, the circuit 400 includes a plurality of tracking cells, including a first tracking cell 410, a second tracking cell 420, and a third tracking cell 430. The first tracking cell 410 may correspond to a first word line among a plurality of word lines, the second tracking cell 420 may correspond to a second word line among a plurality of word lines, and the third tracking cell 430 may correspond to a third word line among a plurality of word lines. In some embodiments, each of the first tracking cell 410, the second tracking cell 420, and the third tracking cell 430 is located at a position physically corresponding to the first word line, the second word line, and the third word line, respectively. For example, the first word line and the first tracking cell 410 are physically closer to the controller 105 than the second word line and the second tracking cell 420, and the second word line and the second tracking cell 420 are also physically closer to the controller 105 than the third word line and the third tracking cell 430.

[0041] The memory controller 105 may control the tracking line signals based on the physical locations of the tracking cells 410, 420, 430. The memory controller 105 may receive an address signal / A[MSB] 412 indicating a first tracking cell 410 physically arranged at a first distance relative to the memory controller 105, and assert the first tracking cell by a TRKBL_BOT 415 having a first slope. For example, the TRKBL_BOT 415 having the first slope may be generated based on a corresponding clock pulse having a first pulse width. The memory controller 105 may receive an address signal / A[MSB-1] 422 indicating a second tracking cell 420 physically arranged at a second distance relative to the memory controller 105, and assert the second tracking cell 420 by a tracking signal TRKBL_MID 425 having a second slope. For example, the tracking signal TRKBL_MID 425 having the second slope may be generated based on a corresponding clock pulse having a second pulse width. The memory controller 105 may receive an address signal A[MSB-1] 432 indicating a third tracking unit 430 physically arranged at a third distance relative to the memory controller 105, and assert the third tracking unit 430 through a tracking signal TRKBL_TOP 435 having a third slope. For example, the tracking signal TRKBL_TOP 435 having a third slope may be generated based on a corresponding clock pulse having a third pulse width. The memory controller 105 may adjust the pulse width (e.g., first pulse width, second pulse width, third pulse width) and / or the slope (e.g., first slope, second slope, third slope) based on the physical location of the tracking units 410, 420, 430. In some embodiments, the pulse width of the clock pulse may be proportional to the distance between the memory controller 105 and the tracking unit. For example, the first pulse width of the first tracking unit 410 may be shorter than the second pulse width of the second tracking unit 420, and the second pulse width of the second tracking unit 420 may be smaller than the third pulse width of the third tracking unit 430. For example, the slope of TRKBL_BOT 415 may be greater than the slope of TRKBL_MID 425, and the slope of TRKBL_MID 425 may be less than the slope of TRKBL_TOP 435. Although three logical tracking cells are depicted, circuit 400 may include any number of tracking cells.

[0042] Figure 5 An example circuit 500 in a memory device 100 is shown along with waveforms 550 of various signals associated with the operation of the circuit 500 in accordance with various embodiments. The circuit 500 may be a component of a tracking column 130.

[0043] The circuit 500 includes a delay circuit 510, which includes a first logic delay circuit 520 and a second logic delay circuit 530, and is configured to provide a logic delay and / or a reset signal. The first logic delay circuit 520 corresponds to a first word line and provides a first logic delay, and can generate a first reset signal based on the first logic delay. The second logic delay circuit 530 corresponds to a second word line and provides a second logic delay, and can generate a second reset signal based on the second logic delay.

[0044] Referring to waveform 550, circuit 500 may be controlled by memory controller 105. A clock generator of memory controller 105 may generate CLK 560 and provide CLK 560 to a pulse generator to generate CKP 570. In response to CLK 560 and / or CKP 570, memory controller 105 may generate a reset signal RSTCKB 590. Reset signal RSTCKB 590 may be generated based on signal RSTCK 580 and an address signal indicating a corresponding word line.

[0045] The memory controller 105 may control one or more of the signals shown in the waveform 550 based on the physical location of the word lines. The memory controller 105 may receive a first address signal indicating a first word line and a second address signal indicating a second word line, the first word line being physically arranged at a first distance relative to the memory controller 105, and the second word line being physically arranged at a second distance relative to the memory controller 105. Based on the first distance and the second distance, the memory controller 105 may adjust the pulse width of the CKP 570. For example, as shown, when the second distance is greater than the first distance, the memory controller 105 may provide the CKP 570 with a pulse width 572 for the second word line and provide the CKP 570 with a pulse width 574 for the first word line (as shown in FIG. 1 ). Figure 5 In response to CKP 570, circuit 500 may generate RSTCK 580 having a first pulse width 584 for the first word line and RSTCK 580 having a second pulse width 582 for the second word line.

[0046] The memory controller 105 can control the circuit 500 so that the RSTCK 580 can be transmitted through the delay circuit 510 based on the physical location of the word line. For example, the memory controller 105 can control the circuit 500 so that the RSTCK 580 with a pulse width 582 is transmitted through the second logic delay circuit 530, and the memory controller 105 can also control the circuit 500 so that the RSTCK 580 with a pulse width 584 is transmitted through the first logic delay circuit 520, thereby providing RSTCKB 590.

[0047] Figure 6An example circuit 600 is shown in the memory device 100 according to various embodiments. The circuit 600 may be a component of the tracking column 130.

[0048] like Figure 6 As shown, the circuit 600 includes a delay circuit 610, and the delay circuit 610 includes a first logic delay circuit 620, a second logic delay circuit 630, and a third logic delay circuit 640. The first logic delay circuit 620 may correspond to a first word line among a plurality of word lines, the second logic delay circuit 630 may correspond to a second word line among a plurality of word lines, and the third logic delay circuit 640 may correspond to a third word line among a plurality of word lines. In some embodiments, the first logic delay circuit 620, the second logic delay circuit 630, and the third logic delay circuit 640 provide logic delays and reset signals corresponding to physical positions of the first word line, the second word line, and the third word line, respectively. For example, when the first word line is located at a first distance from the memory controller 105, the second word line is located at a second distance from the memory controller 105, and the third word line is located at a third distance from the memory controller 105, and the third distance is greater than the second distance, and the second distance is greater than the first distance, the memory controller 105 can provide a signal RSTCK having a first pulse width for the first word line, a signal RSTCK having a second pulse width for the second word line, and a signal RSTCK having a third pulse width for the third word line, wherein the third pulse width is greater than the second pulse width, and the second pulse width is greater than the first pulse width. Based on RSTCK, the memory controller 105 can generate RSTCKB by a first logic delay circuit 620 for the first word line, a second logic delay circuit 630 for the second word line, and a third logic delay circuit 640 for the third word line. Although three logic delay circuits are depicted, the circuit 600 can include any number of logic delay circuits.

[0049] Fig. 7A An example circuit 700 in the memory device 100 according to various embodiments is shown. The circuit 700 may be a component of the memory device 100. Figure 7B An example circuit 750 in the memory device 100 is shown according to various embodiments. The circuit 750 may be a component of the memory device 100.

[0050] like Fig. 7A As shown, circuit 700 includes multiple rows of memory cells, including a first row group 710 and a second row group 720. Memory controller 105 may control a WL signal provided to each of first row group 710 and second row group 720 based on their physical locations.

[0051] In response to a clock signal (e.g., CLK 210) and / or a clock pulse (e.g., CKP 230), the memory controller 105 may assert a row group through a WL signal based on an address signal indicating a row group. For example, the memory controller 105 may receive a first address signal indicating a first row group 710 and assert the first row group 710 with a first WL signal through a first segment 712. For example, the memory controller 105 may receive a second address signal indicating a second row group 720 and assert the second row group 720 with a second WL signal through a second segment 722. As shown, the first row group 710 is closer to the memory controller 105 than the second row group 720 (e.g., the first segment 712 is shorter than the second segment 722). Based on this difference in the location of the memory cells, the memory controller 105 may adjust the pulse width of the clock pulse (e.g., shorten the pulse width of the clock pulse corresponding to the first row group 710) so as to assert the first row group with a shorter pulse width (e.g., a pulse width of 256). This prevents unnecessary power consumption for accessing bits associated with the first row group 710 .

[0052] Reference Figure 7B , circuit 750 includes multiple rows of memory cells, including a first row group 760, a second row group 770, and a third row group 780. Memory controller 105 may control the WL signal provided to each row of the multiple rows of memory cells based on the physical location of the memory cells.

[0053] In response to a clock signal (e.g., CLK 210) and / or a clock pulse (e.g., CKP 230), the memory controller 105 may assert row groups through WL signals based on address signals indicating row groups. For example, the memory controller 105 may receive a first address signal indicating a first row group 760, and assert the first row group 760 with a first WL signal through a first segment 762. For example, the memory controller 105 may receive a second address signal indicating a second row group 770, and assert the second row group 770 with a second WL signal through a second segment 772. For example, the memory controller 105 may receive a third address signal indicating a third row group 780, and assert the third row group 780 with a third WL signal through a third segment 782. As shown, the first row group 760 is closer to the memory controller 105 than the second row group 770 (e.g., the first segment 762 is shorter than the second segment 772), and the second row group 770 is closer to the memory controller 105 than the third row group 780 (e.g., the second segment 772 is shorter than the third segment 782). Based on this difference in the location of the memory cells, the memory controller 105 can adjust the pulse width of the clock pulse (e.g., adjust the clock pulse width to be proportional to the physical location and / or length of the segments 762, 772, 782) to assert each row of the multiple rows of memory cells with a different pulse width (e.g., shorter than the first row group 760, such as a pulse width of 256). This prevents unnecessary power consumption for accessing bits associated with the first row group 760. In some embodiments, the timing can be adjusted by tracking bit line and / or gate delays.

[0054] Fig. 8A An example circuit 800 in the memory device 100 according to various embodiments is shown. The circuit 800 may combine components of the circuit 700. For example, the circuit 800 further includes a tracking circuit 810. Figure 8B An example circuit 850 in the memory device 100 according to various embodiments is shown. The circuit 850 may be or be combined with a component of the circuit 750. For example, the circuit 850 also includes a tracking circuit 860.

[0055] Reference Fig. 8A, the tracking circuit 810 includes a plurality of rows of tracking arrays, including a first row group 820 of the tracking array and a second row group 830 of the tracking array. The first row group 820 of the tracking array may correspond to the first row group 710 (of the memory cells), and the second row group 830 of the tracking array may correspond to the second row group 720 (of the memory cells). In some embodiments, each of the first row group 820 of the tracking array and the second row group 830 of the tracking array is located at a position physically corresponding to each of the first row group 710 and the second row group 720, respectively. For example, when the first row group 710 is closer to the memory controller 105 than the second row group 720, the first row group 820 of the tracking array is closer to the memory controller 105 than the second row group 830 of the tracking array.

[0056] The memory controller 105 may control the tracking signal based on the physical location of the row group of the tracking array. The memory controller 105 may receive a first address signal indicating a first row group 820 of the tracking array, which is physically arranged at a first distance relative to the memory controller 105, and assert the first row group 820 of the tracking array by a tracking signal TRKBL_BOT 822 having a first slope and / or a first pulse width. For example, the TRKBL_BOT 822 having the first slope and / or the first pulse width may be generated based on a corresponding clock pulse having a first clock pulse width. The memory controller 105 may receive a second address signal indicating a second row group 830 of the tracking array, which is physically arranged at a second distance relative to the memory controller 105, and assert the second row group 830 of the tracking array by a tracking signal TRKBL_TOP 832 having a second slope and / or a second pulse width. For example, the TRKBL_TOP 832 having a second slope and / or a second pulse width may be generated based on a corresponding clock pulse having a second clock pulse width. The memory controller 105 may adjust one of the first clock pulse width or the second clock pulse width based on the first distance and the second distance (e.g., adjust the pulse width 372 or the pulse width 374 of the CKP 370). For example, as shown, when the first row group 820 of the tracking array is physically closer to the memory controller 105 than the second row group 830 of the tracking array (e.g., the first distance is less than the second distance), the memory controller 105 may adjust the first clock pulse width (e.g., reduce the pulse width) so that the first row group 820 of the tracking array is asserted with the first pulse width TRKBL_BOT 822 having a first slope and / or less than the second pulse width.

[0057] Reference Figure 8B, the tracking circuit 860 includes a plurality of rows of tracking arrays, including a first row group 870 of the tracking array, a second row group 880 of the tracking array, and a third row group 890 of the tracking array. The first row group 870 of the tracking array may correspond to the first row group 760 (of the memory cells), the second row group 880 of the tracking array may correspond to the second row group 770 (of the memory cells), and the third row group 890 of the tracking array may correspond to the third row group 780 (of the memory cells). In some embodiments, each of the first row group 870 of the tracking array, the second row group 880 of the tracking array, and the third row group 890 of the tracking array is located at a position physically corresponding to each of the first row group 760, the second row group 770, and the third row group 780, respectively. For example, when the first row group 760 is closer to the memory controller 105 than the second row group 770, the first row group 870 of the tracking array is closer to the memory controller 105 than the second row group 880 of the tracking array. When second row group 770 is closer to memory controller 105 than third row group 780 , second row group 880 of the tracking array is closer to memory controller 105 than third row group 890 of the tracking array.

[0058] The memory controller 105 may control the tracking signals based on the physical location of the row groups of the tracking array. The memory controller 105 may receive a first address signal indicating a first row group 870 of the tracking array physically arranged at a first distance relative to the memory controller 105, and assert the first row group 870 of the tracking array through a tracking signal TRKBL_BOT872 having a first slope and / or a first pulse width. For example, TRKBL_BOT 872 having a first slope and / or a first pulse width may be generated based on a corresponding clock pulse having a first clock pulse width. The memory controller 105 may receive a second address signal indicating a second row group 880 of the tracking array physically arranged at a second distance relative to the memory controller 105, and assert the second row group 880 of the tracking array through a tracking signal TRKBL_MID 882 having a second slope and / or a second pulse width. For example, TRKBL_MID 882 having a second slope and / or a second pulse width may be generated based on a corresponding clock pulse having a second clock pulse width. The memory controller 105 may receive a third address signal indicating a third row group 890 of the tracking array physically arranged at a third distance relative to the memory controller 105, and assert the third row group 890 of the tracking array via a tracking signal TRKBL_TOP 892 having a third slope and / or a third pulse width. For example, TRKBL_TOP 892 having a third slope and / or a third pulse width may be generated based on a corresponding clock pulse having a third clock pulse width.

[0059] The memory controller 105 may adjust at least one of the first clock pulse width, the second clock pulse width, or the third clock pulse width based on the first distance, the second distance, and the third distance. For example, as shown, when the first row group 870 of the tracking array is physically closer to the memory controller 105 than the second row group 880 of the tracking array (e.g., the first distance is less than the second distance), the memory controller 105 may adjust the first clock pulse width (e.g., reduce the pulse width) so that the first row group 870 of the tracking array is asserted with a first pulse width TRKBL_BOT 872 having a first slope and / or less than the second pulse width. As shown, when the second row group 880 of the tracking array is physically closer to the memory controller 105 than the third row group 890 of the tracking array (e.g., the second distance is less than the third distance), the memory controller 105 may adjust the second clock pulse width (e.g., reduce the pulse width) so that the second row group 880 of the tracking array is asserted with a second pulse width TRKBL_MID 882 having a second slope and / or less than the third pulse width.

[0060] Fig. 9 A method for operating a memory device (eg, Figure 1 Flowchart of an example method 900 of a memory device 100 of the present invention. The method 900 may be performed by a memory controller (e.g. Figure 1 It should be noted that method 900 is only an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 900 may be executed in Fig. 9 Additional operations are provided before, during, and after method 900, and some other operations may only be briefly described herein.

[0061] Briefly, method 900 begins at operation 910, where a controller (e.g., memory controller 105) receives a first address signal indicating a first word line (e.g., first address signal 120) of a plurality of word lines of a memory array (e.g., 220). Method 900 continues to operation 920, where the controller asserts the first word line via a first signal (e.g., first signal 250) having a first pulse width (e.g., pulse width 256). Method 900 continues to operation 930, where the controller receives a second address signal (e.g., second address signal 225) indicating a second word line of a plurality of word lines of the memory array. Method 900 continues to operation 940, where the controller asserts the second word line via a second signal (e.g., second signal 240) having a second pulse width (e.g., second pulse width 246). Method 900 continues to operation 950, where the controller adjusts one of the first pulse width or the second pulse width in response to identifying that the first word line is physically closer to the controller than the second word line.

[0062] At operation 910, the memory controller may receive an address signal indicating one or more word lines. The memory controller may identify a physical location of the one or more word lines. For example, the memory controller may identify a relative location of the one or more word lines. For example, the memory controller may identify that one of the word lines is physically closer to the memory controller than another word line.

[0063] At operation 920, the memory controller may assert the first word line via a first word line signal having a first pulse width. In some embodiments, operation 920 may include an operation 950 of adjusting the pulse width of the word line signal. The memory controller may adjust the pulse width of the first word line signal in response to receiving the address signal. For example, the memory controller may adjust (e.g., shorten) the pulse width of the first word line signal in response to identifying that the first word line is closer to the memory controller than at least one word line.

[0064] At operation 930, the memory controller may receive an address signal indicating one or more word lines. The memory controller may identify the physical location of the one or more word lines. For example, the memory controller may identify the relative location of the one or more word lines. For example, the memory controller may identify that one word line is physically closer to the memory controller than another word line. In some embodiments, operation 930 may be substantially similar or identical to operation 910.

[0065] At operation 940, the memory controller may assert the second word line via a second word line signal having a second pulse width. In some embodiments, operation 940 may include an operation 950 of adjusting the pulse width of the word line signal. The memory controller may adjust the pulse width of the second word line signal in response to receiving the address signal. For example, the memory controller may adjust (e.g., shorten) the pulse width of the second word line signal in response to identifying that the second word line is closer to the memory controller than at least one word line.

[0066] At operation 950, the memory controller may adjust the pulse width of the corresponding word line signal of at least one of the one or more word lines. The memory controller may adjust the pulse width of the clock pulse to adjust the pulse width of the corresponding word line signal. For example, the memory controller may adjust (e.g., shorten) the pulse width of the corresponding word line signal in response to identifying that the corresponding word line is closer to the memory controller than at least one word line. In some embodiments, the memory controller may adjust the pulse slope (e.g., 387) and / or pulse width of the tracking line signal (e.g., 385) according to the physical location of the corresponding tracking unit (e.g., 310). In some embodiments, the memory controller may adjust the logic delay and pulse width (e.g., 584) of the reset signal (e.g., 580, 590) based on the physical location of the corresponding word line.

[0067] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory array, the memory array includes a plurality of word lines, each of the plurality of word lines is operably coupled to a corresponding group of memory cells; and a controller operably coupled to the memory array. The controller is configured to: receive a first address signal, the first address signal indicating a first word line physically arranged at a first distance relative to the controller; assert the first word line by a first signal having a first pulse width; receive a second address signal, the second address signal indicating a second word line physically arranged at a second distance relative to the controller; assert the second word line by a second signal having a second pulse width; and adjust one of the first pulse width or the second pulse width based on the first distance and the second distance.

[0068] In some embodiments, the controller is configured to decrease the first pulse width in response to identifying that the first word line is physically closer to the controller than the second word line.

[0069] In some embodiments, the first pulse width is shorter than the second pulse width, and the first distance is shorter than the second distance.

[0070] In some embodiments, the controller is configured to adjust one of the first pulse width or the second pulse width by adjusting one of a pulse width of a first clock pulse associated with the first signal or a pulse width of a second clock pulse associated with the second signal.

[0071] In some embodiments, the memory device further includes: a first tracking unit among a plurality of tracking units, the first tracking unit corresponding to a first word line; and a second tracking unit among a plurality of tracking units, the second tracking unit corresponding to a second word line; wherein the first tracking unit and the second tracking unit are physically positioned corresponding to the first word line and the second word line, respectively.

[0072] In some embodiments, the controller is configured to: assert a first tracking unit through a first tracking signal according to a first address signal; assert a second tracking unit through a second tracking signal according to a second address signal; and adjust a pulse width of one of the first tracking signal or the second tracking signal based on the first address signal and the second address signal.

[0073] In some embodiments, the first tracking signal has a first slope, the second tracking signal has a second slope, and the second slope is greater than the first slope.

[0074] In some embodiments, the memory device further includes: a first logic delay circuit corresponding to a first word line, the first logic delay circuit being configured to provide a first reset signal; and a second logic delay circuit corresponding to a second word line, the second logic delay circuit being configured to provide a second reset signal; wherein the length of one of the first reset signal or the second reset signal is adjusted according to the first distance and the second distance.

[0075] In some embodiments, the first distance is shorter than the second distance, and a pulse width of the first reset signal is shorter than a pulse width of the second reset signal.

[0076] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory array, the memory array includes a plurality of word lines, each of the plurality of word lines is operably coupled to a corresponding group of memory cells; and a controller operably coupled to the memory array. The controller is configured to: assert a first word line through a first signal according to a first address signal; assert a second word line through a second signal according to a second address signal; identify a difference in physical position between the first word line and the second word line based at least in part on the first address signal and the second address signal; and in response to determining that at least one of the first word line or the second word line is within a predetermined distance from the controller, adjust a pulse width of at least one of the first signal or the second signal.

[0077] In some embodiments, the controller is configured to reduce a pulse width of the first signal based on the identified difference indicating that the first word line is physically closer to the controller than the second word line.

[0078] In some embodiments, the controller is configured to adjust a pulse width of at least one of the first signal or the second signal by adjusting one of a pulse width of a first clock pulse associated with the first signal or a pulse width of a second clock pulse associated with the second signal.

[0079] In some embodiments, the memory device further includes: a first tracking unit among a plurality of tracking units, the first tracking unit corresponding to a first word line; and a second tracking unit among a plurality of tracking units, the second tracking unit corresponding to a second word line; wherein the first tracking unit and the second tracking unit are physically positioned corresponding to the first word line and the second word line, respectively.

[0080] In some embodiments, the controller is configured to: assert a first tracking unit via a first tracking signal according to a first address signal; assert a second tracking unit via a second tracking signal according to a second address signal; and adjust a pulse width of one of the first tracking signal or the second tracking signal based on the identified difference.

[0081] In some embodiments, the first tracking signal has a first slope, the second tracking signal has a second slope, and the second slope is greater than the first slope.

[0082] In some embodiments, the memory device further includes: a first logic delay circuit corresponding to a first word line, the first logic delay circuit being configured to provide a first reset signal; and a second logic delay circuit corresponding to a second word line, the second logic delay circuit being configured to provide a second reset signal; wherein a pulse width of one of the first reset signal or the second reset signal is adjusted based on the identified difference.

[0083] In some embodiments, a pulse width of the first reset signal is shorter than a pulse width of the second reset signal.

[0084] In another aspect of the present disclosure, a method for operating a memory device is disclosed. The method includes: receiving, by a controller, a first address signal indicating a first word line among a plurality of word lines of a memory array; asserting, by the controller, the first word line through a first signal having a first pulse width; receiving, by the controller, a second address signal indicating a second word line among a plurality of word lines of the memory array; asserting, by the controller, the second word line through a second signal having a second pulse width; and in response to identifying that the first word line is physically closer to the controller than the second word line, adjusting, by the controller, one of the first pulse width or the second pulse width.

[0085] In some embodiments, the method further includes adjusting, by the controller, one of a first pulse width of the first tracking signal or a second pulse width of the second tracking signal in response to identifying that the first word line is physically closer to the controller than the second word line.

[0086] In some embodiments, the method further includes adjusting, by the controller, one of a first pulse width of the first reset signal or a second pulse width of the second reset signal in response to identifying that the first word line is physically closer to the controller than the second word line.

[0087] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary depending on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of a value (e.g., +10%, ±20%, or ±30% of a value).

[0088] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: a memory array comprising a plurality of word lines, each word line of the plurality of word lines being operably coupled to a respective group of memory cells; as well as a controller operably coupled to the memory array, wherein the controller is configured to: receiving a first address signal indicating a first word line physically arranged at a first distance relative to the controller; asserting the first word line by a first signal having a first pulse width; receiving a second address signal indicating a second word line physically arranged at a second distance relative to the controller; asserting the second word line by a second signal having a second pulse width; and One of the first pulse width or the second pulse width is adjusted based on the first distance and the second distance.

2. The memory device according to claim 1, wherein: The controller is configured to reduce the first pulse width in response to identifying that the first word line is physically closer to the controller than the second word line.

3. The memory device according to claim 1, wherein: The first pulse width is shorter than the second pulse width, and the first distance is shorter than the second distance.

4. The memory device according to claim 1, wherein: The controller is configured to adjust one of the first pulse width or the second pulse width by adjusting one of a pulse width of a first clock pulse associated with the first signal or a pulse width of a second clock pulse associated with the second signal.

5. The memory device according to claim 1, further comprising: a first tracking cell among a plurality of tracking cells, the first tracking cell corresponding to the first word line; as well as a second tracking cell of the plurality of tracking cells, the second tracking cell corresponding to the second word line; The first tracking unit and the second tracking unit are physically located corresponding to the first word line and the second word line respectively.

6. The memory device according to claim 5, wherein: The controller is configured to: asserting the first tracking unit via a first tracking signal according to the first address signal; asserting the second tracking unit by a second tracking signal according to the second address signal; and A pulse width of one of the first tracking signal or the second tracking signal is adjusted based on the first address signal and the second address signal.

7. The memory device according to claim 1, further comprising: a first logic delay circuit corresponding to the first word line, the first logic delay circuit being configured to provide a first reset signal; as well as a second logic delay circuit corresponding to the second word line, the second logic delay circuit being configured to provide a second reset signal; Wherein, the length of one of the first reset signal or the second reset signal is adjusted according to the first distance and the second distance.

8. A memory device comprising: a memory array comprising a plurality of word lines, each word line of the plurality of word lines being operably coupled to a respective group of memory cells; as well as a controller operably coupled to the memory array, wherein the controller is configured to: asserting a first word line via a first signal according to a first address signal; asserting a second word line via a second signal according to a second address signal; identifying a difference in physical location between the first word line and the second word line based at least in part on the first address signal and the second address signal; and In response to determining that at least one of the first word line or the second word line is within a predetermined distance from the controller, a pulse width of at least one of the first signal or the second signal is adjusted.

9. The memory device according to claim 8, wherein: The controller is configured to reduce a pulse width of the first signal based on the identified difference indicating that the first word line is physically closer to the controller than the second word line.

10. A method of operating a memory device, comprising: receiving, by a controller, a first address signal indicating a first word line among a plurality of word lines of a memory array; asserting, by the controller, the first word line via a first signal having a first pulse width; receiving, by the controller, a second address signal indicative of a second word line of the plurality of word lines of the memory array; asserting, by the controller, the second word line via a second signal having a second pulse width; as well as In response to identifying that the first word line is physically closer to the controller than the second word line, one of the first pulse width or the second pulse width is adjusted by the controller.

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