Digital jitter zero-offset frequency locking system and method

Abstract

The present invention discloses a digital jitter zero-offset frequency locking system and method, the system comprising: a laser processing unit optically mixes a reference laser transmitted by a reference laser and a frequency-jittered local oscillator laser, and inputs the mixed optical signal into a balanced detector; the balanced detector outputs a beat frequency signal to a digital phase-locked loop according to the mixed optical signal; the digital phase-locked loop processes the error signal in the beat frequency signal to obtain a low-frequency modulation signal and a high-frequency modulation signal, controls the working current of the local oscillator laser by the low-frequency modulation signal, and controls the working voltage of the phase modulator by the high-frequency modulation signal. The present invention does not generate a phase error due to the frequency offset between the reference light and the local oscillator light, thereby eliminating the transfer of the frequency offset to the phase noise, and then allows the error signal to be filtered and processed in a variety of ways by constructing a digital phase-locked loop, thereby improving the performance under low-power frequency locking and avoiding the degradation of long-term stability.

Description

Technical Field

[0001] The present invention relates to the technical field of laser frequency stabilization and frequency transfer, and in particular to a digital jitter zero-offset frequency locking system and method. Background Art

[0002] Optical frequency and phase locking are fundamental to many applications in optical metrology, sensing, and communications. Frequency locking can enhance the intensity and spectral purity of individual frequency comb lines and can be used for laser spectroscopy or time reference transfer transmission. Usually, optical frequency locking relies on optical coherent detection, that is, the frequency and phase locking of the local oscillator can suppress the additional phase noise generated by digital carrier recovery and allow real-time measurement of phase. Homodyne coherent optical frequency locking of lasers has been shown to enhance pump carrier regeneration during phase-sensitive amplification and improve the synthesis efficiency of laser coherent synthesis.

[0003] In most applications, the optical signal may have a reduced output power due to large optical losses, such as large fiber networks, free space channels, and power-inefficient frequency comb generation. In these applications, the reference laser power is low, but tight frequency or phase locking is still required.

[0004] In addition, Doppler frequency shift and additional phase noise from the transmission medium will affect the realization of locking, and how to deal with the random phase noise and frequency drift of the laser is a challenge for achieving tight lock. The combination of phase-sensitive amplification and optical phase-locked loop has been proven to be a feasible solution to improve the accuracy of frequency locking at the few-photon level, but it is limited by the operating wavelength of the phase-sensitive amplifier, which is usually an erbium-doped fiber amplifier and is difficult to use outside the C and L communication bands. In addition, additional jitter in the feedback loop and the transmission loop will cause the frequency lock to be lost or deteriorated, so it is necessary to provide a large-bandwidth, high-power and sensitive frequency locking technology to solve the above problems.

[0005] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0006] The main purpose of the present invention is to provide a digital jitter zero-offset frequency locking system and method, aiming to solve how to provide a large bandwidth, high power and sensitive frequency locking technology.

[0007] To achieve the above-mentioned object, the present invention provides a digital jitter zero-offset frequency locking system, the digital jitter zero-offset frequency locking system comprises a laser processing unit, a balanced detector and a digital phase-locked loop, the laser processing unit comprises a local oscillator laser, a reference laser and a phase modulator;

[0008] The laser processing unit is used to perform optical mixing on the reference laser transmitted by the reference laser and the frequency-dithered local oscillator laser, and input the mixed optical signal into the balanced detector;

[0009] The balanced detector is used to output a beat frequency signal to the digital phase-locked loop according to the mixed optical signal;

[0010] The digital phase-locked loop is used to process the error signal in the beat frequency signal to obtain a low-frequency modulation signal and a high-frequency modulation signal, control the operating current of the local oscillator laser through the low-frequency modulation signal, and control the operating voltage of the phase modulator through the high-frequency modulation signal.

[0011] Optionally, the laser processing unit further comprises an optical beam splitter, a jitter loader and an optical coupling beam splitter;

[0012] The phase modulator is used to input the optical frequency signal transmitted by the local oscillator laser into the optical beam splitter, so that the optical beam splitter splits the optical frequency signal to obtain a P component light and an S component light;

[0013] The optical beam splitter is used to transmit the P component light to the link and transmit the S component light to the jitter loader;

[0014] The jitter loader is used to apply a frequency jitter to the S component light to output a frequency-jittered local oscillator laser to the optical coupling beam splitter;

[0015] The optical coupling beam splitter is used to perform optical mixing on the reference laser transmitted by the reference laser and the frequency-dithered local oscillator laser, and input the mixed optical signal into the balanced detector.

[0016] Optionally, the balanced detector is used to debug the mixed optical signal to obtain a beat frequency signal;

[0017] The balanced detector is further used to determine the signal-to-noise ratio of the beat frequency signal, and when the signal-to-noise ratio is greater than a preset threshold, transmit the beat frequency signal to the digital phase-locked loop.

[0018] Optionally, the digital phase-locked loop includes a reference clock, a digital frequency synthesizer, a low-frequency divider, a power divider, a phase shifter and a digital phase detector;

[0019] The reference clock is connected to the digital frequency synthesizer so that the digital frequency synthesizer obtains a driving radio frequency signal;

[0020] The digital frequency synthesizer is used to divide the driving radio frequency signal in half and input the divided part of the driving radio frequency signal into the low-frequency divider;

[0021] The low-frequency divider is used to output a jitter modulation signal to the power divider according to the divided part of the driving RF signal, so that the power divider divides the jitter modulation signal equally;

[0022] The power divider is used to load the equally divided part of the jitter modulation signal onto the jitter loader to provide a modulation signal for zero offset locking;

[0023] The power divider is also used to load the equally divided residual jitter modulation signal onto the phase shifter to obtain a demodulation signal of a zero offset locked closed loop, and input the demodulation signal of the zero offset locked closed loop into the digital phase detector.

[0024] Optionally, the digital phase-locked loop further includes an analog-to-digital converter, a bandpass filter and a digital-to-analog converter;

[0025] The analog-to-digital converter is used to convert the radio frequency signal corresponding to the error signal in the beat frequency signal to obtain a digital signal, and input the digital signal into the bandpass filter;

[0026] The bandpass filter is used to filter the digital signal to obtain a filtered signal, and input the filtered signal into the digital phase detector;

[0027] The digital phase detector is used to modulate and demodulate the filtered signal and the demodulation signal of the zero-offset locked closed loop to eliminate the jitter modulation signal and obtain a phase error signal between the local oscillator laser and the reference laser;

[0028] The digital phase detector is further used to divide the phase error signal in half, and transmit the divided part of the phase error signal to the low-pass filter, so that the low-pass filter outputs a low-frequency error amount to the digital-to-analog converter;

[0029] The digital-to-analog converter is used to convert the low-frequency error amount to obtain a low-frequency modulation signal, so that the low-frequency modulation signal controls the working current of the local oscillator laser.

[0030] Optionally, the digital phase-locked loop further includes a high-frequency divider, a mixer and a driver;

[0031] The digital frequency synthesizer is further used to input the remaining driving radio frequency signal after being divided equally into the high frequency divider;

[0032] The high frequency divider is used to output a high frequency signal to the mixer according to the residual driving RF signal after the equal division;

[0033] The digital phase detector is further used to transmit the residual phase error signal after being divided equally to the mixer;

[0034] The mixer is used to mix the high-frequency signal and the residual phase error signal after being equally divided, and obtain a high-frequency modulation signal through the driver, so that the high-frequency modulation signal controls the operating voltage of the phase modulator.

[0035] In addition, to achieve the above object, the present invention also proposes a digital jitter zero offset frequency locking method, the digital jitter zero offset frequency locking method comprising:

[0036] The laser processing unit optically mixes the reference laser transmitted by the reference laser and the frequency-dithered local oscillator laser, and inputs the mixed optical signal into the balanced detector;

[0037] The balanced detector outputs a beat frequency signal to a digital phase-locked loop according to the mixed optical signal;

[0038] The digital phase-locked loop processes the error signal in the beat frequency signal to obtain a low-frequency modulation signal and a high-frequency modulation signal, controls the operating current of the local oscillator laser through the low-frequency modulation signal, and controls the operating voltage of the phase modulator through the high-frequency modulation signal.

[0039] In the present invention, the laser processing unit first performs optical mixing on the reference laser transmitted by the reference laser and the frequency-dithered local oscillator laser, and inputs the mixed optical signal into the balanced detector, and then the balanced detector outputs the beat frequency signal to the digital phase-locked loop according to the mixed optical signal, and then the digital phase-locked loop processes the error signal in the beat frequency signal to obtain a low-frequency modulation signal and a high-frequency modulation signal, and controls the working current of the local oscillator laser by the low-frequency modulation signal, and controls the working voltage of the phase modulator by the high-frequency modulation signal. The digital dithered zero-offset frequency locking technology provided by the present invention can improve its performance under low-power frequency locking. At the same time, zero-offset locking avoids long-term stability degradation due to its insensitivity to the instability of the dithered frequency, which is the technical difficulty faced by traditional optical phase-locked loops in frequency synthesis. Compared with optical injection locking, the present invention does not generate phase error due to the frequency offset between the reference and local oscillator lights, thereby eliminating the transfer of frequency offset to phase noise, and the digital phase-locked loop allows multiple filtering and processing of error signals, thereby improving system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a structural block diagram of the first embodiment of the digital jitter zero offset frequency locking system of the present invention;

[0041] Figure 2 It is a schematic diagram of the structure of the digital jitter zero offset frequency locking technology of the first embodiment of the digital jitter zero offset frequency locking system of the present invention;

[0042] Figure 3 It is a schematic diagram of the structure of a specific implementation scheme of a digital phase-locked loop of the first embodiment of the digital jitter zero-offset frequency locking system of the present invention;

[0043] Figure 4 It is a schematic diagram of a specific implementation scheme of the first embodiment of the digital jitter zero-offset frequency locking system of the present invention applied to the frequency locking of the 1550nm time-frequency transfer system;

[0044] Figure 5 FIG. 4 is a flow chart of a first embodiment of a digital jitter zero-offset frequency locking method according to the present invention.

[0045] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0046] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0047] Reference Figure 1 , Figure 1 It is a structural block diagram of the first embodiment of the digital jitter zero offset frequency locking system of the present invention.

[0048] It should be noted that the digital jitter zero-offset frequency locking system includes a laser processing unit A1 , a balanced detector A2 and a digital phase-locked loop A3 . The laser processing unit A1 includes a local oscillator laser 101 , a reference laser 105 and a phase modulator 102 .

[0049] In this embodiment, the local oscillator laser 101 outputs a single longitudinal mode laser for generating a signal of a single optical frequency and is connected to a phase modulator. The local oscillator laser 101 may be a single-frequency laser with an external modulation function such as a semiconductor laser, a solid-state laser, or a fiber laser.

[0050] The phase modulator 102, whose optical signal output port is connected to the beam splitter module, and whose electrical input port is connected to the high-frequency modulation signal output end of the digital phase-locked loop, is used for feedback control of the phase noise compensation capability outside the control bandwidth of the local oscillator laser, and can be an electro-optic phase modulator, a piezoelectric ceramic ring or a two-dimensional material (such as graphene) modulator.

[0051] Reference laser 105, the output laser is a single longitudinal mode, used to generate a signal of a single optical frequency, and its frequency is locked with a standard frequency source, which can be referenced on an optical frequency comb, an atomic absorption spectrum or an optical resonant cavity, and can be a single-frequency laser with an external modulation function such as a semiconductor laser, a solid laser, or a fiber laser.

[0052] The balanced detector A2 can convert the optical field differential signal of the two input optical signals into an electrical signal output, and is connected to the digital phase-locked loop A3.

[0053] The digital phase-locked loop A3, based on the FPGA structure, can be synchronized with an external clock and has three output ports for controlling the local oscillator laser 101, the phase modulator 102 and the jitter loader respectively.

[0054] Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation on the digital jitter zero-offset frequency locking system, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0055] The laser processing unit A1 is used to perform optical mixing on the reference laser transmitted by the reference laser 105 and the frequency-dithered local oscillator laser, and input the mixed optical signal to the balanced detector A2.

[0056] In the specific implementation, refer to Figure 2 , Figure 2 It is a schematic diagram of the digital jitter zero offset frequency locking technology structure of the first embodiment of the digital jitter zero offset frequency locking system of the present invention. Figure 2 In the embodiment, the laser processing unit A1 further includes an optical beam splitter 103 , a jitter loader 104 and an optical coupling beam splitter 106 .

[0057] The optical beam splitter 103 divides the input light into two beams according to the ratio. The polarization-dependent device can also be a polarization-independent device. The two output ports directly output frequency-stabilized signals and are connected to the jitter loader.

[0058] The jitter loader 104 can apply a frequency component near the local oscillator laser to generate a frequency sideband. Its optical output end is connected to the optical coupling beam splitter, and its electrical input end is connected to the digital phase-locked loop. It can be an electro-optical modulator, an IQ modulator, etc.

[0059] The optical coupling beam splitter 106 can couple two input signals together in the optical field and adjust the output light beam ratio, and is connected to the balanced detector 107 .

[0060] It should also be noted that Figure 1 The balanced detector A2 in Figure 2 The balanced detector 107 in FIG.

[0061] Furthermore, the phase modulator 102 inputs the optical frequency signal transmitted by the local oscillator laser 101 to the optical beam splitter 103, so that the optical beam splitter 103 splits the optical frequency signal to obtain P component light and S component light; the optical beam splitter 103 performs link transmission on the P component light, and transmits the S component light to the jitter loader 104; the jitter loader 104 is used to apply a frequency jitter amount to the S component light to output the frequency-jittered local oscillator laser to the optical coupling beam splitter 106; the optical coupling beam splitter 106 performs optical mixing on the reference laser transmitted by the reference laser 105 and the frequency-jittered local oscillator laser, and inputs the mixed optical signal to the balanced detector 107.

[0062] It should be understood that, generally, the PBS transmits the P component light and reflects the S component light. The P component light and the S component light are orthogonal.

[0063] In this embodiment, the local oscillator laser 101 is used as a locked laser with random frequency jitter. A modulator is installed inside it, which can quickly respond to voltage changes to adjust the laser frequency when different voltages are applied externally. Its output is connected to the phase modulator 102.

[0064] After receiving the optical frequency signal, the phase modulator 102 directly outputs the optical frequency signal without loading the driving signal, and its output end is connected to the input end (including the first output end and the second output end) of the optical beam splitter 103, and the first output end of the optical beam splitter is connected to the jitter loader 104, and the S component light is input to the jitter loader 104, and the frequency jitter is applied to the optical signal under the action of the driving voltage, which is manifested in the frequency domain as the generation of symmetrical frequency sidebands; the second output end directly outputs the P component light.

[0065] It should be understood that when the entire feedback loop operates stably, the second output terminal will directly output a laser signal with a stable frequency and a phase referenced to the reference laser 105 .

[0066] It should also be noted that the RF input end of the phase modulator 102 is connected to the digital phase-locked loop 108 (i.e., the digital phase-locked loop A3), which can change the phase of the input optical signal when receiving the driving voltage, so as to suppress the phase noise exceeding the internal modulation bandwidth of the local oscillator laser 101.

[0067] Furthermore, the reference laser of the reference laser 105 and the local oscillator laser with frequency jitter output by the jitter loader 104 are coupled to the two output ports of the optical coupling beam splitter 106 respectively, and optical mixing occurs inside the coupler, and the mixed optical signal is divided equally, and then the divided mixed optical signals are output to the receiving end of the balanced detector 107 respectively.

[0068] The balanced detector A2 is used to output a beat frequency signal to the digital phase-locked loop A3 according to the mixed optical signal.

[0069] Furthermore, the balanced detector adjusts the mixed optical signal to obtain a beat frequency signal; determines the signal-to-noise ratio of the beat frequency signal, and transmits the beat frequency signal to a digital phase-locked loop when the signal-to-noise ratio is greater than a preset threshold.

[0070] It should be understood that the beat frequency signal is also called a differential signal, and the differential signal includes three parts: a DC bias, a carrier, and an error signal.

[0071] In the specific implementation, during the debugging process, the balanced detector A2 needs to use the output signal of the balanced detector as a reference to make the signal-to-noise ratio of the beat frequency signal reach the optimal state (that is, the signal-to-noise ratio is greater than the preset threshold), and then input it into the FPGA digital phase-locked loop A3.

[0072] The digital phase-locked loop A3 is used to process the error signal in the beat frequency signal to obtain a low-frequency modulation signal and a high-frequency modulation signal, control the operating current of the local oscillator laser 101 through the low-frequency modulation signal, and control the operating voltage of the phase modulator 102 through the high-frequency modulation signal.

[0073] In this embodiment, reference Figure 3 , Figure 3 The digital phase-locked loop A3 of the first embodiment of the digital jitter zero-offset frequency locking system of the present invention comprises a reference clock 201, a digital frequency synthesizer 202, a low-frequency divider 203, a high-frequency divider 204, a power divider 205, a phase shifter 206, an analog-to-digital converter 207, a bandpass filter 208, a digital phase detector 209, a mixer 210, a low-pass filter 211, a driver 212, and a digital-to-analog converter 213.

[0074] Further, the reference clock 201 is connected to the digital frequency synthesizer 202 so that the digital frequency synthesizer 202 obtains a driving RF signal; the digital frequency synthesizer 202 divides the driving RF signal in half, and inputs the divided part of the driving RF signal into the low-frequency divider 203; the low-frequency divider 203 is used to output a jitter modulation signal to the power divider 205 according to the divided part of the driving RF signal, so that the power divider 205 divides the jitter modulation signal in half; the power divider 205 loads the divided part of the jitter modulation signal onto the jitter loader 104 to provide a modulation signal for zero offset locking; the power divider 205 loads the remaining jitter modulation signal after the division onto the phase shifter 206 to obtain a demodulation signal of a zero offset locked closed loop, and inputs the demodulation signal of the zero offset locked closed loop into the digital phase detector 209.

[0075] It should be noted that the reference clock 201 provides the basic clock signal required by the system. The clock signal can be synchronized with the external reference clock to ensure that the clock of the entire application system is consistent. Usually, the operating frequency of the reference clock 201 is usually 10MHz or 100MHz; the reference clock 201 is connected to the digital frequency synthesizer 202, whose main function is to provide a driving RF signal with a higher operating frequency to avoid the phase difference phenomenon caused by the use of multiple digital frequency synthesizers. The operating frequency is usually >1GHz; its output is divided into two parts, one part enters the low-frequency divider 203, that is, the division coefficient is greater than 50, and the output frequency is a jitter modulation signal below 20MHz to the power divider 205. A part of the output of the power divider 205 is loaded on the jitter loader 104 as a modulation signal (that is, the partial jitter modulation signal after being divided equally) to provide a modulation signal for zero offset locking, and the other part (that is, the remaining jitter modulation signal after being divided equally) is input into the phase shifter 206 as a demodulation signal of the zero offset locking closed loop.

[0076] Furthermore, the analog-to-digital converter 207 converts the radio frequency signal corresponding to the error signal in the beat frequency signal to obtain a digital signal, and inputs the digital signal to the bandpass filter 208; the bandpass filter 208 filters the digital signal to obtain a filtered signal, and inputs the filtered signal to the digital phase detector 209; the digital phase detector 209 modulates and demodulates the filtered signal and the demodulation signal of the zero-offset locked closed loop transmitted by the phase shifter 206 to eliminate the jitter modulation signal and obtain the phase error signal between the local oscillator laser 101 and the reference laser 105; the digital phase detector 209 is also used to divide the phase error signal in half, and transmit the divided part of the phase error signal to the low-pass filter 211, so that the low-pass filter 211 outputs a low-frequency error amount to the digital-to-analog converter 213; the digital-to-analog converter 213 is used to convert the low-frequency error amount to obtain a low-frequency modulation signal, so that the low-frequency modulation signal controls the working current of the local oscillator laser 101.

[0077] In a specific implementation, the radio frequency signal carrying the error signal output by the balanced detector 107 (i.e., the balanced detector A2) first passes through the analog-to-digital converter 207, is converted into a digital signal and input into the bandpass filter 208, whose filtering center frequency is the same as the jitter modulation signal; the filtered signal and the signal output by the phase shifter 206 enter the digital phase detector 209 for modulation and demodulation, and the jitter modulation signal is eliminated to obtain the phase error between the local oscillator laser 101 and the reference laser 105, and the phase error signal is evenly divided into two parts (i.e., the partial phase error signal after being divided equally and the remaining phase error signal after being divided equally), and one part (i.e., the partial phase error signal after being divided equally) directly passes through the low-pass filter 211, outputs the low-frequency error amount, and then passes through the digital-to-analog converter 213 to generate a feedback control signal (i.e., a low-frequency modulation signal) that can directly control the local oscillator laser 101, thereby achieving tracking and locking of the local oscillator laser 101.

[0078] Furthermore, the digital frequency synthesizer 202 inputs the remaining driving RF signal after the equal division into the high-frequency divider 204; the high-frequency divider 204 outputs a high-frequency signal to the mixer 210 according to the remaining driving RF signal after the equal division; the digital phase detector 209 is also used to transmit the remaining phase error signal after the equal division to the mixer 210; the mixer 210 mixes the high-frequency signal and the remaining phase error signal after the equal division, and obtains a high-frequency modulation signal through the driver 212, so that the high-frequency modulation signal controls the operating voltage of the phase modulator 102.

[0079] In a specific implementation, another part of the output of the digital frequency synthesizer 202 is connected to a high-frequency divider 204, whose division coefficient is relatively small, usually 1 or 2, and is used to generate an operating frequency for driving the phase modulator 102. The remaining phase error signal after being divided equally is mixed with the high-frequency signal output by the high-frequency divider 204 in the mixer 210 and directly input into the driver 212 to generate a frequency signal (i.e., a high-frequency modulation signal) for controlling the phase modulator 102, thereby compensating for high-frequency frequency jitter and achieving precise frequency locking.

[0080] In this embodiment, reference Figure 4 , Figure 4 FIG. 1 is a schematic diagram of a specific implementation scheme of the first embodiment of the digital jitter zero offset frequency locking system of the present invention applied to the frequency locking of the 1550nm time-frequency transmission system. Figure 2 and Figure 3 , Figure 4 Correspondingly, a method for implementing frequency locking of the 1550nm time-frequency transfer system is proposed. Figure 4In the figure, there is a local oscillator 1550nm single-frequency laser 301, a fiber phase modulator 302, a fiber-coupled polarization beam splitter 303, a fiber IQ modulator 304, a reference 1550nm single-frequency laser 305, a fiber-coupled beam splitter 306, wherein the fiber-coupled beam splitter 306 includes a fiber-coupled polarization beam splitter 306a, a polarization controller 306b and a fiber-coupled polarization beam splitter 306c, a balanced detector 307, an FPGA digital phase-locked loop 308, and a reference clock 309.

[0081] It should also be noted that the local oscillator laser 101 can be a local oscillator 1550nm single-frequency laser 301, the phase modulator 102 can be a fiber phase modulator 302, the optical beam splitter 103 can be a fiber coupled polarization beam splitter 303, the jitter loader 104 can be a fiber IQ modulator 304, the reference laser 105 can be a reference 1550nm single-frequency laser 305, the optical coupling beam splitter 106 can be a fiber coupled beam splitter 306, the balanced detector 107 can be a balanced detector 307, and the digital phase-locked loop 108 can be an FPGA digital phase-locked loop 308.

[0082] In a specific implementation, a local oscillator 1550nm single-frequency laser is connected to a fiber phase modulator 302 with an operating frequency of 1GHz, and the output end is connected to a fiber-coupled polarization beam splitter 303. The output light is divided into two parts, wherein the P component light is directly output, and the S component light is connected to a fiber IQ modulator 304; the fiber IQ modulator 304 generates a frequency component with a 100MHz interval from the center frequency under the action of a 100MHz frequency jitter signal.

[0083] It should be understood that the local oscillator laser is affected by the phase modulation during phase modulation, and a jitter signal will be loaded on the laser carrier frequency. The polarization direction of this signal is consistent with the S axis of the PBS, and the polarization state of the reference laser is consistent with the P axis. Only by rotating the wave plate and rotating the two orthogonal polarization states by 45°, can the beat frequency signal be generated when both P and S light have energy distribution along the orthogonal polarization. The local oscillator laser loaded with the frequency jitter signal is connected to the S axis of the fiber-coupled polarization beam splitter 306a, and the reference 1550nm single-frequency laser 305 is connected to the P optical axis of the fiber-coupled polarization beam splitter 306a. The two laser beams are transmitted along different optical axes respectively and will not generate a beat frequency signal. Subsequently, the reference light and the local oscillator light in the two polarization states are adjusted by the polarization controller 306b to be coupled to the balanced detector 307 through the P and S axis outputs of the fiber-coupled polarization beam splitter 306c. During the debugging process, the polarization control 306b needs to be adjusted based on the output signal of the balanced detector as a reference to make the signal-to-noise ratio of the beat frequency signal reach the optimal state, and then input into the FPGA digital phase-locked loop 308, whose reference end is connected to the reference clock 309, the low feedback bandwidth output end is connected to the local oscillator 1550nm single-frequency laser 301, and its working current is feedback controlled; the high feedback bandwidth output end is connected to the fiber phase modulator 302, and its working voltage is feedback controlled.

[0084] In this embodiment, first, the laser processing unit optically mixes the reference laser transmitted by the reference laser and the frequency-dithered local oscillator laser, and inputs the mixed optical signal into the balanced detector. Then, the balanced detector outputs the beat frequency signal to the digital phase-locked loop according to the mixed optical signal. After that, the digital phase-locked loop processes the error signal in the beat frequency signal to obtain a low-frequency modulation signal and a high-frequency modulation signal. The working current of the local oscillator laser is controlled by the low-frequency modulation signal, and the working voltage of the phase modulator is controlled by the high-frequency modulation signal. The digital jitter zero-offset frequency locking technology provided in this embodiment can improve its performance under low-power frequency locking. The laser to be locked is extracted before the digital jitter is loaded, so that stronger jitter can be loaded in subsequent transmissions, so that the laser to be locked can be locked at a lower power without any jitter loss; by enhancing the coherent detection gain of the laser to be locked, the weaker reference laser improves the sensitivity and avoids the problem of limited working wavelength caused by the use of optical amplification. At the same time, zero-offset locking avoids long-term stability degradation due to its insensitivity to the instability of jitter frequency, which is the technical difficulty faced by traditional optical phase-locked loops in frequency synthesis. Compared with optical injection locking, this embodiment will not produce phase error due to the frequency offset between the reference and local oscillator lights, thereby eliminating the transfer of frequency offset to phase noise. The digital phase-locked loop allows multiple filtering and processing of the error signal, thereby improving system performance.

[0085] Reference Figure 5 , Figure 5FIG. 4 is a flow chart of a first embodiment of a digital jitter zero-offset frequency locking method according to the present invention.

[0086] like Figure 5 As shown, the digital jitter zero offset frequency locking method proposed in the embodiment of the present invention includes:

[0087] Step S10: the laser processing unit performs optical mixing on the reference laser transmitted by the reference laser and the frequency-dithered local oscillator laser, and inputs the mixed optical signal into the balanced detector;

[0088] Step S20: the balanced detector outputs a beat frequency signal to a digital phase-locked loop according to the mixed optical signal;

[0089] Step S30: The digital phase-locked loop processes the error signal in the beat frequency signal to obtain a low-frequency modulation signal and a high-frequency modulation signal, controls the operating current of the local oscillator laser through the low-frequency modulation signal, and controls the operating voltage of the phase modulator through the high-frequency modulation signal.

[0090] Other embodiments or specific implementations of the digital jitter zero offset frequency locking method of the present invention may refer to the above-mentioned system embodiments, which will not be described in detail here.

[0091] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0092] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0093] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0094] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A digital jitter zero offset frequency locking system, characterized in that: The digital jitter zero-offset frequency locking system comprises a laser processing unit, a balanced detector and a digital phase-locked loop, wherein the laser processing unit comprises a local oscillator laser, a reference laser and a phase modulator; The laser processing unit is used to perform optical mixing on the reference laser transmitted by the reference laser and the frequency-dithered local oscillator laser, and input the mixed optical signal into the balanced detector; The balanced detector is used to output a beat frequency signal to the digital phase-locked loop according to the mixed optical signal; The digital phase-locked loop is used to process the error signal in the beat frequency signal to obtain a low-frequency modulation signal and a high-frequency modulation signal, control the operating current of the local oscillator laser through the low-frequency modulation signal, and control the operating voltage of the phase modulator through the high-frequency modulation signal.

2. The system according to claim 1, characterized in that The laser processing unit also includes an optical beam splitter, a jitter loader and an optical coupling beam splitter; The phase modulator is used to input the optical frequency signal transmitted by the local oscillator laser into the optical beam splitter, so that the optical beam splitter splits the optical frequency signal to obtain a P component light and an S component light; The optical beam splitter is used to transmit the P component light to the link and transmit the S component light to the jitter loader; The jitter loader is used to apply a frequency jitter to the S component light to output a frequency-jittered local oscillator laser to the optical coupling beam splitter; The optical coupling beam splitter is used to perform optical mixing on the reference laser transmitted by the reference laser and the frequency-dithered local oscillator laser, and input the mixed optical signal into the balanced detector.

3. The system according to claim 2, characterized in that The balanced detector is used to debug the mixed optical signal to obtain a beat frequency signal; The balanced detector is further used to determine the signal-to-noise ratio of the beat frequency signal, and when the signal-to-noise ratio is greater than a preset threshold, transmit the beat frequency signal to the digital phase-locked loop.

4. The system according to claim 1, characterized in that The digital phase-locked loop includes a reference clock, a digital frequency synthesizer, a low-frequency divider, a power divider, a phase shifter and a digital phase detector; The reference clock is connected to the digital frequency synthesizer so that the digital frequency synthesizer obtains a driving radio frequency signal; The digital frequency synthesizer is used to divide the driving radio frequency signal in half and input the divided part of the driving radio frequency signal into the low-frequency divider; The low-frequency divider is used to output a jitter modulation signal to the power divider according to the divided part of the driving RF signal, so that the power divider divides the jitter modulation signal equally; The power divider is used to load the equally divided part of the jitter modulation signal onto the jitter loader to provide a modulation signal for zero offset locking; The power divider is also used to load the equally divided residual jitter modulation signal onto the phase shifter to obtain a demodulation signal of a zero offset locked closed loop, and input the demodulation signal of the zero offset locked closed loop into the digital phase detector.

5. The system according to claim 4, characterized in that The digital phase-locked loop also includes an analog-to-digital converter, a bandpass filter and a digital-to-analog converter; The analog-to-digital converter is used to convert the radio frequency signal corresponding to the error signal in the beat frequency signal to obtain a digital signal, and input the digital signal into the bandpass filter; The bandpass filter is used to filter the digital signal to obtain a filtered signal, and input the filtered signal into the digital phase detector; The digital phase detector is used to modulate and demodulate the filtered signal and the demodulation signal of the zero-offset locked closed loop to eliminate the jitter modulation signal and obtain a phase error signal between the local oscillator laser and the reference laser; The digital phase detector is further used to divide the phase error signal in half, and transmit the divided part of the phase error signal to the low-pass filter, so that the low-pass filter outputs a low-frequency error amount to the digital-to-analog converter; The digital-to-analog converter is used to convert the low-frequency error amount to obtain a low-frequency modulation signal, so that the low-frequency modulation signal controls the working current of the local oscillator laser.

6. The system according to claim 5, characterized in that The digital phase-locked loop also includes a high-frequency divider, a mixer and a driver; The digital frequency synthesizer is further used to input the remaining driving radio frequency signal after being divided equally into the high frequency divider; The high frequency divider is used to output a high frequency signal to the mixer according to the residual driving RF signal after the equal division; The digital phase detector is further used to transmit the residual phase error signal after being divided equally to the mixer; The mixer is used to mix the high-frequency signal and the residual phase error signal after being equally divided, and obtain a high-frequency modulation signal through the driver, so that the high-frequency modulation signal controls the operating voltage of the phase modulator.

7. A digital jitter zero offset frequency locking method, characterized in that: The digital jitter zero offset frequency locking method comprises the following steps: The laser processing unit optically mixes the reference laser transmitted by the reference laser and the frequency-dithered local oscillator laser, and inputs the mixed optical signal into the balanced detector; The balanced detector outputs a beat frequency signal to a digital phase-locked loop according to the mixed optical signal; The digital phase-locked loop processes the error signal in the beat frequency signal to obtain a low-frequency modulation signal and a high-frequency modulation signal, controls the operating current of the local oscillator laser through the low-frequency modulation signal, and controls the operating voltage of the phase modulator through the high-frequency modulation signal.

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