Signal calibration circuit, OOK modulation circuit and signal processing method

Abstract

The invention discloses a signal calibration circuit, an OOK modulation circuit and a signal processing method. The signal calibration circuit comprises a phase discrimination module, a signal generation circuit, a time digital conversion module and a calibration module. The phase discrimination module generates a characterization signal for characterizing the phase difference between the data signal and the clock signal; the signal generation circuit is used for generating pulse signals based on data signals; the time-to-digital conversion module is used for detecting the characterization signal based on the pulse signal to generate a control signal; the calibration module is used for outputting a result clock signal based on the control signal. According to the signal calibration circuit, the OOK modulation circuit and the signal processing method provided by the invention, the control signal is generated by detecting the phase difference between the characterization data signal and the clock signal, so that the clock signal is calibrated to obtain the result clock signal, the result clock signal in the effective pulse width range of the data signal is kept synchronous, and the signal processing accuracy is improved. Therefore, the problem that the duty ratio difference of the finally demodulated signal is large can be solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a signal calibration circuit, an OOK modulation circuit and a signal processing method. Background Art

[0002] The transmitter of the digital isolator uses a modulation circuit to modulate the low-frequency data signal to a high frequency for transmission, which places certain requirements on the modulation circuit.

[0003] The common OOK modulation circuit is an AND gate, with two inputs, namely the clock signal CLK and the data signal DATA. Since the digital isolator needs to transmit the data signal DATA from 0Hz to tens of MHz, the frequency of the clock signal CLK cannot be designed to always be an integer multiple of the data signal DATA frequency. When the clock signal CLK frequency is not an integer multiple of the data signal DATA, signal jitter is likely to occur during modulation, especially for high-frequency data signals DATA. Figure 1 As shown, the data signal DATA is up-mixed, and the obtained signal CLKQ has different effective signal widths in different data cycles. Such a signal is filtered by an isolation capacitor, and the amplified signal CLKP after filtering is then received by the digital isolator. Finally, the demodulated signal CLKO will have inconsistent duty cycles in different data cycles.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a signal calibration circuit, an OOK modulation circuit and a signal processing method, which can make the duty cycle of the calibrated clock signal remain consistent in different data periods when the clock signal frequency is not an integer multiple of the data signal.

[0006] To achieve the above objective, a specific embodiment of the present invention provides a signal calibration circuit for calibrating a clock signal based on a data signal. The signal calibration circuit includes: a phase detection module, a signal generation circuit, a time-to-digital conversion module and a calibration module.

[0007] The phase detection module is used to perform phase detection on the data signal and the clock signal to generate a characterization signal representing the phase difference between the data signal and the clock signal;

[0008] The signal generating circuit is used to generate one or more pulse signals based on the data signal;

[0009] The time-to-digital conversion module is used to detect the pulse width of the characterization signal based on the pulse signal to generate a control signal;

[0010] The calibration module is used to calibrate the clock signal based on the control output of the control signal to obtain a resultant clock signal.

[0011] In one or more embodiments of the present invention, the phase detection module includes a first trigger, an inverting unit and a first logic unit, the input end of the first trigger is used to receive a data signal, the clock input end of the first trigger is used to receive a clock signal, the input end of the inverting unit is used to receive a data signal, the set end of the first trigger is connected to the output end of the inverting unit, the first input end of the second logic unit is connected to the output end of the first trigger, the second input end of the second logic unit is connected to the output end of the inverting unit, and the output end of the second logic unit is used to output a characterization signal.

[0012] In one or more embodiments of the present invention, the signal generating circuit comprises a pulse generating module, and the pulse generating module is used to generate a pulse signal based on an edge of a data signal; or

[0013] The signal generating circuit includes a pulse generating module and a first delay module. The pulse generating module is used to generate an initial pulse signal based on the edge of a data signal. The first delay module is used to delay the initial pulse signal once or multiple times to generate one or more subsequent pulse signals.

[0014] In one or more embodiments of the present invention, the time-to-digital conversion module includes one or more second triggers, the input end of the second trigger is used to receive the characterization signal, the clock input end of the second trigger is used to receive the corresponding pulse signal, and the output end of one or more of the second triggers is used to output the control signal.

[0015] In one or more embodiments of the present invention, the calibration module includes a connected buffer unit and an adjustment unit, the adjustment unit adjusts the delay time of the buffer unit based on the control of the control signal, and the buffer unit is based on the clock signal and the adjustment output result clock signal of the adjustment unit; or

[0016] The calibration module includes a connected second delay module and a gating module, wherein the second delay module is used to delay the clock signal once or multiple times, and the gating module is used to select the original clock signal and the delayed clock signal based on the control of the control signal to output the result clock signal.

[0017] The present invention also discloses an OOK modulation circuit, comprising a first logic unit and the signal calibration circuit, wherein the first logic unit is used to perform a logic operation on a result clock signal output by the signal calibration circuit and a data signal to generate a modulation signal.

[0018] The present invention also discloses a signal processing method. Based on the signal calibration circuit, the signal processing method includes:

[0019] Performing phase detection on the data signal and the clock signal to generate a characterization signal characterizing a phase difference between the data signal and the clock signal;

[0020] generating one or more pulse signals based on the data signal;

[0021] Detecting the pulse width of the characterizing signal based on the pulse signal to generate a control signal;

[0022] A resulting clock signal after calibrating the clock signal is output based on the control signal.

[0023] In one or more embodiments of the present invention, detecting the pulse width of the characterization signal based on the pulse signal to generate the control signal includes:

[0024] The effective number of bits of the control signal is obtained based on the number of edges of the pulse signal within the pulse width range of the characterizing signal.

[0025] In one or more embodiments of the present invention, the outputting of the resulting clock signal after calibrating the clock signal based on the control signal includes:

[0026] Adjust the delay time based on the control signal to output a result clock signal; or

[0027] The clock signal is delayed once or multiple times, and the original clock signal and the delayed clock signal are selected based on the control of the control signal to output the result clock signal.

[0028] In one or more embodiments of the present invention, the signal processing method further includes: performing a logic operation on the result clock signal and the data signal to generate a modulated signal.

[0029] Compared with the prior art, the signal calibration circuit, OOK modulation circuit and signal processing method of the present invention detect a signal representing the phase difference between a data signal and a clock signal through a pulse signal to generate a corresponding control signal, thereby calibrating the clock signal to obtain a result clock signal, so that the result clock signals within the effective pulse width range of the data signal are kept synchronized, which is helpful to solve the problem of large duty cycle difference of the finally demodulated signal caused by the influence of PVT or the clock frequency being non-integer multiples of the data signal frequency; the present invention is applicable to digital isolators with any number of channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 It is a signal modulation waveform diagram in the prior art.

[0032] Figure 2 This is a circuit schematic diagram of the OOK modulation circuit in Example 1.

[0033] Figure 3 The schematic diagram of the circuit of the phase detection module and the time-to-digital conversion module in the first embodiment.

[0034] Figure 4 This is a partial circuit schematic diagram of the calibration module in Example 1.

[0035] Figure 5 This is a circuit diagram of the switch control unit in the first embodiment.

[0036] Figure 6 FIG. 4 is a partial circuit schematic diagram of a calibration module in another embodiment.

[0037] Figure 7 FIG. 4 is a partial circuit schematic diagram of a calibration module in another embodiment.

[0038] Figure 8 4 is a signal modulation waveform diagram of the OOK modulation circuit in Example 1.

[0039] Fig. 9 This is a circuit schematic diagram of the OOK modulation circuit in Example 2.

[0040] Fig.10 This is a circuit schematic diagram of the second delay module in the second embodiment.

[0041] Fig.11 This is a circuit schematic diagram of the gating module in the second embodiment.

[0042] Fig.12 FIG. 4 is a circuit schematic diagram of a gating module in another embodiment. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0045] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0046] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0047] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0048] Various components and devices may be referred to or shown in the singular form herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular form may include multiple such elements in accordance with the teachings herein.

[0049] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.

[0050] Example 1

[0051] like Figure 2 As shown, a signal calibration circuit in an embodiment of the present invention is used to calibrate a clock signal CLK based on a data signal DATA. The signal calibration circuit includes: a phase detection module 10, a signal generating circuit, a time-to-digital conversion module 30 and a calibration module.

[0052] The phase detection module 10 is used to perform phase detection on the data signal DATA and the clock signal CLK to generate a characterizing signal Time length that characterizes the phase difference between the data signal DATA and the clock signal CLK. In one embodiment, the phase difference between each falling edge of the data signal DATA and the corresponding adjacent rising edge of the clock signal CLK (the rising edge of the clock signal CLK is located behind the falling edge of the data signal DATA, that is, the rising edge of the clock signal CLK is located outside the high level of the data signal DATA) constitutes each pulse width of the characterizing signal Time length, and the width of the pulse width characterizes the degree of deviation of the clock signal CLK relative to each falling edge of the data signal DATA.

[0053] In other embodiments, each pulse width of the signal Time length may be formed according to the phase difference between the falling edge of the data signal DATA and the adjacent falling edges corresponding to the clock signal CLK, or according to the phase difference between the rising edge of the data signal DATA and the adjacent falling edges corresponding to the clock signal CLK, or according to the phase difference between the rising edge of the data signal DATA and the adjacent rising edges corresponding to the clock signal CLK.

[0054] The signal generating circuit is used to generate one or more pulse signals based on the data signal DATA. In one embodiment, each falling edge of the data signal DATA is used as a reference to generate an initial pulse signal, and the initial pulse signal is delayed to generate the next pulse signal, and so on, multiple delays generate multiple pulse signals, the phases between the pulse signals are different, and the initial pulse signal also has a corresponding delay relative to the falling edge of the data signal DATA. The duration from the initial pulse signal to the end of the continuous generation of the pulse signal by the signal generating circuit is one cycle of the clock signal CLK, that is, from each falling edge of the data signal DATA to the end of one cycle of the clock signal CLK, each pulse signal is generated within this cycle range. In other embodiments, the rising and falling edges of the data signal DATA can also be used as a reference to generate the initial pulse signal.

[0055] The time-to-digital conversion module 30 is used to detect the pulse width of the characterizing signal Time length based on the pulse signal to generate a control signal. In one embodiment, within one clock cycle T_clk of the clock signal CLK, the number of pulse signals within the pulse width range of the characterizing signal Time length is obtained to determine the effective number of bits of the control signal, and the number of pulse signals outside the pulse width range of the characterizing signal Time length and within one clock cycle T_clk of the clock signal CLK is obtained to determine the invalid number of bits of the control signal. The effective number of bits (1 is effective, and the number of 1s is the effective number of bits) and the invalid number of bits (0 is invalid, and the number of 0s is the invalid number of bits) of the control signal constitute the total number of bits of the control signal, and the number of pulse signals can be determined by the number of rising edges of the pulse signal. The total number of bits of the control signal can be predetermined based on a clock cycle T_clk of the clock signal CLK and the delay time of each pulse signal. For example, if a clock cycle T_clk of the clock signal CLK is 1.6ns and the delay time between two adjacent pulse signals is 0.2ns, the total number of bits of the control signal is 8 bits. If the number of pulse signals within the pulse width range of the characterizing signal Time length is 2, and the number of pulse signals outside the pulse width range of the characterizing signal Time length and within a clock cycle T_clk of the clock signal CLK is 6, the control signal is 11000000; if the delay time between two adjacent pulse signals is 0.1ns, the total number of bits of the control signal is 16 bits, and the corresponding detection accuracy is also higher. In other embodiments, the number of pulse signals can be determined by the number of falling edges of the pulse signal.

[0056] The calibration module is used to output the result clock signal CLKnew after calibrating the clock signal CLK based on the control signal. In one embodiment, the delay time of the calibration module is adjusted by the control signal to output the result clock signal CLKnew. The fewer the number of pulse signals within the pulse width range of the characterizing signal Time length, that is, the narrower the pulse width of the characterizing signal Timelength, the fewer the effective bits of the control signal, and the longer the delay time of the clock signal CLK is required. If the pulse width of the characterizing signal Time length is 0 or equal to one clock cycle T_clk of the clock signal CLK, no delay calibration is required, and the original clock signal CLK is output, so that the result clock signal CLKnew within each effective pulse width (high level) of the data signal DATA is finally synchronized (phase consistent).

[0057] like Figure 3 As shown, in a specific example, the phase detection module 10 includes a first trigger D1, an inverting unit X and a first logic unit. In one embodiment, the first trigger D1 is a D trigger, and the first logic unit is an exclusive OR gate XNOR. The input end of the first trigger D1 is used to receive the data signal DATA, the clock input end of the first trigger D1 is used to receive the clock signal CLK, the input end of the inverting unit X is used to receive the data signal DATA, the set end SDN of the first trigger D1 is connected to the output end of the inverting unit X, the first input end of the second logic unit is connected to the output end of the first trigger D1, the second input end of the second logic unit is connected to the output end of the inverting unit X, and the output end of the second logic unit is used to output the characterizing signal Time length.

[0058] like Figure 2 As shown, in a specific example, the signal generating circuit includes a pulse generating module and a first delay module. The pulse generating module is used to generate an initial pulse signal read1 based on the edge (a falling edge in one embodiment) of the data signal DATA. The first delay module is used to delay the initial pulse signal read1 once or multiple times to generate one or more subsequent pulse signals. The multiple subsequent pulse signals are read2, read3...readn.

[0059] like Figure 3As shown, in a specific example, the time digital conversion module 30 includes a plurality of second triggers D21, D22...D2n, the second trigger is a D trigger, the input end of the second trigger is used to receive the characterization signal Time length, the clock input end of the second trigger D21, D22...D2n is used to receive the corresponding pulse signal read1, read2...readn, and the output end of the plurality of second triggers is used to output the control signal. The number of second triggers can be selected according to the number of pulse signals, the number of second triggers is equal to the number of pulse signals, and accordingly, the number of second triggers is equal to the number of bits of the control signal, and n second triggers correspond to nbit (n-bit) control signals.

[0060] In one embodiment, the calibration module includes a connected buffer unit and an adjustment unit. The adjustment unit adjusts the delay time of the buffer unit based on the control of a control signal. The buffer unit is based on a clock signal CLK and an adjustment output result clock signal CLKnew of the adjustment unit.

[0061] like Figure 4 As shown, in a specific example, the buffer unit includes a first inverter 41 and a second inverter 42, the adjustment unit is connected to the first inverter 41, the power supply and the ground voltage, the adjustment unit is used to adjust the current on the first inverter 41, the input end of the first inverter 41 is used to receive the clock signal CLK, the input end of the second inverter 42 is connected to the output end of the first inverter 41, and the output end of the second inverter 42 is used to output the result clock signal CLKnew. By adjusting the current on the first inverter 41, the speed at which the first inverter 41 responds to the clock signal CLK can be adjusted, thereby adjusting the delay time of the clock signal CLK.

[0062] The first inverter 41 includes a first transistor M1 and a second transistor M2, and the second inverter 42 includes a third transistor M3 and a fourth transistor M4. The first transistor M1 and the third transistor M3 are P-channel MOS transistors, and the second transistor M2 and the fourth transistor M4 are N-channel MOS transistors. The source of the first transistor M1 is connected to the adjustment unit, the gate of the first transistor M1 and the gate of the second transistor M2 are used to receive the clock signal CLK, the source of the second transistor M2 is connected to the adjustment unit, the drain of the first transistor M1 and the drain of the second transistor M2 are connected to the gate of the third transistor M3 and the gate of the fourth transistor M4, and the drain of the third transistor M3 is connected to the drain of the fourth transistor M4 to output the result clock signal CLKnew.

[0063] In other embodiments, the adjustment unit can be connected to the second inverter 42, the power supply and the ground voltage, and the adjustment unit is used to adjust the current on the second inverter 42. The number of first inverters 41 and second inverters 42 connected in series can be increased or decreased as needed. The adjustment unit can also be connected to the first inverter 41 and the second inverter 42, that is, the current on the first inverter 41 and the second inverter 42 is adjusted simultaneously.

[0064] like Figure 4 As shown, in a specific example, the regulating unit includes a first regulating module 43 and a second regulating module 44, the first regulating module 43 is connected to the first inverter 41 and the power supply, and the second regulating module 44 is connected to the first inverter 41 and the ground voltage. The first regulating module 43 and the second regulating module 44 both include a plurality of regulating branches, the first end of the regulating branch of the first regulating module 43 is connected to the power supply voltage, the second end of the regulating branch of the first regulating module 43 is connected to the source of the first transistor M1 of the first inverter 41, and the regulating branch of the first regulating module 43 is used to generate a current injected into the first inverter 41. The first end of the regulating branch of the second regulating module 44 is connected to the source of the second transistor M2 of the first inverter 41, the second end of the regulating branch of the second regulating module 44 is connected to the ground voltage, and the regulating branch of the second regulating module 44 is used to generate a current drawn from the first inverter 41.

[0065] Each regulating branch includes a control switch and a current source connected in series. Each control switch Kn, Kn-1...K1 is controlled by a regulating signal N, N-1...1. Each current source An, An-1...A1 generates a current of different magnitudes>>I, I...I / m (m is a positive integer greater than 1). In one embodiment, each current source An, An-1...A1 generates different currents, which can be gradually reduced in proportion. When the control switches (such as Kn) of the two corresponding regulating branches in the first regulating module 43 and the second regulating module 44 are closed, the current (>>I) generated by the corresponding current source (such as An) is injected into the first inverter 41 and extracted from the first inverter 41. The regulating signal N, N-1...1 is used to control which regulating branch is turned on, thereby adjusting the magnitude of the working current on the first inverter 41, that is, adjusting the opening speed of the first inverter 41, thereby adjusting the delay time.

[0066] like Figure 5As shown, the first regulating module 43 and the second regulating module 44 also include a switch control unit, which generates regulating signals N, N-1...1 based on the control signal to open one or more regulating branches in each regulating module. The switch control unit includes a first logic module and a second logic module, and the number of the second logic modules can be adjusted according to the number of bits of the control signal. The first logic module is used to generate the regulating signal N based on the first bit data signal of the control signal and the last bit data signal of the control signal, and each second logic module is used to generate the regulating signal N-1...1 based on the adjacent two bits of the control signal data signal.

[0067] Specifically, the first logic module includes a first NOT gate NO1 and an OR gate OR, the input end of the first NOT gate NO1 is used to receive the last bit of the data signal bitn of the control signal, the first input end of the OR gate OR is connected to the output end of the first NOT gate NO1, the second input end of the OR gate OR is used to receive the first bit of the data signal bit1 of the control signal, and the output end of the OR gate OR is used to output the adjustment signal N.

[0068] Each second logic module includes a second NOT gate and an AND gate. The input end of each second NOT gate NO2, NO3...NOn is used to respectively correspond to the data signals bit1, bit2...bitn-1 from the first bit to the second bit of the control signal. The first input end of each AND gate AND1, AND2...ANDn is correspondingly connected to the output end of each second NOT gate NO2, NO3...NOn. The second input end of each AND gate AND1, AND2...ANDn is used to respectively correspond to the data signals bit2, bit3...bitn from the second bit to the last bit of the control signal. The output end of each AND gate AND1, AND2...ANDn is used to output the adjustment signal N-1...1.

[0069] like Figure 6As shown, in another specific example, the adjustment unit is connected between the output end of the first inverter 41 and the input end of the second inverter 42, and the adjustment unit includes a resistor R0, a plurality of adjustment branches and a switch control unit, the first end of the adjustment branch is connected to the input end of the second inverter 42 and the first end of the resistor R0, the second end of the resistor R0 is connected to the output end of the first inverter 41, and the second end of the adjustment branch is connected to the ground voltage. In other embodiments, the position of the resistor R0 can be swapped. Each adjustment branch includes a control switch and a capacitor unit connected in series, each control switch Kn-1, Kn-2...1 is controlled by an adjustment signal N-1, N-2...1, and each capacitor unit C, 2*C...m*C has a different capacitance value, which can be gradually increased in proportion. The switch control unit includes a second logic module. The structure of the second logic module can be referred to above and will not be described in detail here. In this embodiment, the first logic module is no longer set, so the adjustment signal N is missing. Because when the control signal of each bit is 1 or 0, the adjustment signal N is 0. The adjustment signals N-1, N-2...1 are used to control one or more adjustment branches to be turned on to select which capacitor unit is connected to the circuit, or to adjust the number of capacitor units connected to the circuit, thereby adjusting the speed from the first inverter 41 to the second inverter 42, thereby adjusting the delay time.

[0070] like Figure 7 As shown, in another specific example, the regulating unit is connected between the output end of the first inverter 41 and the input end of the second inverter 42, and the regulating unit includes a capacitor C0, a plurality of regulating branches and a switch control unit, the first end of the regulating branch is connected to the output end of the first inverter 41, the second end of the regulating branch is connected to the input end of the second inverter 42 and the first end of the capacitor C0, and the second end of the capacitor C0 is connected to the ground voltage. In other embodiments, the position of the regulating branch can be swapped. Each regulating branch includes a control switch and a resistance unit connected in series, each control switch is controlled by a regulating signal N-1, N-2...1, and the resistance value of each resistance unit R, 2*R...m*R can be different and can be gradually increased in proportion. The switch control unit includes a first logic module and a second logic module. The structures of the first logic module and the second logic module can be referred to above and will not be repeated here. One or more adjustment branches are controlled to be turned on by adjusting signals N, N-1, N-2...1 to select which resistance unit is connected to the circuit or adjust the number of resistance units connected to the circuit, thereby adjusting the speed from the first inverter 41 to the second inverter 42, thereby adjusting the delay time.

[0071] Taking the 8-bit control signal as an example, the following is the corresponding truth table.

[0072] Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 8 7 6 5 4 3 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

[0073] Among them, Bit1, Bit2, Bit3, Bit4, Bit5, Bit6, Bit7, and Bit8 correspond to the 8-bit data signal of the control signal, and the 8-bit control signal also corresponds to the 8-bit adjustment signal 8, 7, 6, 5, 4, 3, 2, and 1.

[0074] It can be seen from the truth table that if the pulse width representing the signal Time length is wider, resulting in the rising edges of the eight pulse signals being within the pulse width range, the control signal is 11111111, which is equivalent to the clock signal CLK delaying the data signal DATA by one clock cycle, and no calibration is required. At this time, the switch control unit can obtain the adjustment signal N=8 as 1, the adjustment signal N-1=7 as 0, the adjustment signal N-2=6 as 0, the adjustment signal N-3=5 as 0…, and the adjustment signal 1 as 0. In one embodiment, only one adjustment signal is 1. Figure 4 It can be seen that the control switch K8 controlled by the adjustment signal N=8 is closed, and the corresponding series current source A8 generates a current of >>I (I is a reference current). At this time, it can be considered that the first inverter 41 is fully opened, and the delay of the calibration module can be ignored. The calibration module outputs a result clock signal CLKnew synchronized with the clock signal CLK.

[0075] If the rising edges of the seven pulse signals are all within the pulse width range, the control signal is 11111110. At this time, the switch control unit can obtain the adjustment signal N=8 is 0, the adjustment signal N-1=7 is 1, the adjustment signal N-2=6 is 0, the adjustment signal N-3=5 is 0... the adjustment signal 1 is 0. Figure 4 It can be seen that the control switch K7 controlled by the adjustment signal N-1=7 is closed, and the corresponding series current source A7 generates a reference current I. At this time, it can be considered that the current on the first inverter 41 is reduced compared to the current >>I, and the delay of the calibration module is increased. The calibration module outputs the result clock signal CLKnew after the first delay time.

[0076] If the rising edges of the six pulse signals are all within the pulse width range, the control signal is 11111100. At this time, the switch control unit can obtain the adjustment signal N=8 is 0, the adjustment signal N-1=7 is 0, the adjustment signal N-2=6 is 1, the adjustment signal N-3=5 is 0... the adjustment signal 1 is 0. Figure 4 It can be seen that the control switch K6 controlled by the adjustment signal N-2=6 is closed, and the corresponding series current source A6 generates a reference current I / 2. At this time, it can be considered that the current on the first inverter 41 is reduced compared to the reference current I, and the delay of the calibration module is further increased. The calibration module outputs the result clock signal CLKnew after the second delay time.

[0077] Similarly, if no rising edge of the pulse signal is within the pulse width range, the control signal is 00000000, that is, no pulse width representing the signal Time length is generated, and there is no need to calibrate the clock signal CLK. At this time, the switch control unit can obtain the adjustment signal N=8 is 1, the adjustment signal N-1=7 is 0, the adjustment signal N-2=6 is 0, the adjustment signal N-3=5 is 0... the adjustment signal 1 is 0, and the Figure 4 It can be seen that the control switch K8 controlled by the adjustment signal N=8 is closed, and the corresponding series current source A8 generates a current of >>I (I is a reference current). At this time, it can be considered that the first inverter 41 is fully opened, and the delay of the calibration module can be ignored. The calibration module outputs a result clock signal CLKnew synchronized with the clock signal CLK.

[0078] like Figure 8 As shown, first, phase detection is performed on the clock signal CLK and the data signal DATA, and the duration between the falling edge of the data signal DATA and the next rising edge of the clock signal CLK is detected to obtain the characterization signal Time length. The characterization signal Time length has pulse widths of different widths based on the phase difference between the clock signal CLK and the data signal DATA. It can be seen that the pulse width of the characterization signal Time length is within one clock cycle T_clk of the clock signal CLK.

[0079] A periodic initial pulse signal read1 is obtained according to the data signal DATA. The period of the pulse signal read1 is the same as that of the data signal DATA. The pulse signal read1 is after the falling edge of the data signal DATA. The pulse width of the pulse signal read1 cannot exceed the pulse width of the data signal DATA.

[0080] The pulse signal read1 is delayed n times, each delay time is Δt, and the pulse signals read2, read3...readn are obtained. The rising edges of the nbit pulse signals read1, read2, read3...readn in a single cycle are evenly distributed within a clock cycle T_clk after the falling edge of the data signal DATA. The nbit pulse signals read1, read2, read3...readn are used to read the characterization signal Time length within a clock cycle T_clk after the falling edge of the data signal DATA. The nbit pulse signals read1, read2, read3...readn and the characterization signal Time length are input into the time-to-digital conversion module 30 to obtain an nbit control signal. The nbit control signal controls the length of the delay required for the clock signal CLK after a clock cycle T_clk after the falling edge of the corresponding data signal DATA (see Figure 8The length of the thick line in the result clock signal CLKnew is obtained to obtain the calibrated result clock signal CLKnew. The result clock signal CLKnew is ANDed with the data signal DATA to obtain the modulation signal MIXERout. Figure 8 It can be seen from the timing diagram that after the first falling edge of the data signal DATA, the effective data width of the obtained modulation signal MIXERout remains consistent, and the effective data frequency is more converged.

[0081] Furthermore, the relationship between the delay length of the nbit control signal and the clock signal CLK in the corresponding period is as follows. Taking the clock signal CLK of 625MHz (clock period T_clk is 1.6ns), the 8-bit pulse signals read1, read2, read3...read8, and the delay time of each bit control signal is 0.2ns as an example, if the time between the falling edge of the data signal DATA and the rising edge of the next clock signal CLK is 0.3ns, the characterization signal Time The pulse width of timelength is 0.3ns, then the 8-bit control signal is 11000000 (0.2ns+0.2ns), and the clock signal CLK is delayed by 1.2ns (1.6ns-0.2ns-0.2ns) within the cycle; if the falling edge of the data signal DATA is 0.7ns away from the rising edge of the next clock signal CLK, the pulse width of the characterization signal Timelength is 0.7ns, then the 8-bit control signal is 11110000, and the clock signal CLK is delayed by 0.8ns within the cycle; if the falling edge of the data signal DATA is 1.4ns away from the rising edge of the next clock signal CLK; the pulse width of the characterization signal Timelength is 1.4ns, then the 8-bit control signal is 11111110, and the clock signal CLK is delayed by 0.2ns within the cycle; if the characterization signal Time If the pulse width of length is less than 0.1ns or greater than 1.5ns, the control signal is 00000000 or 11111111, and the clock signal CLK in this cycle does not need to be delayed. From this analysis, it can be seen that the more bits the pulse signal has, the more accurate the synchronization of the clock signal CLK and the data signal DATA is.

[0082] One clock cycle T_clk after the falling edge of the data signal DATA belongs to the time of using the pulse signal to detect the pulse width of the characterization signal Time length. Each cycle of the data signal DATA corresponds to a different delay time of the clock signal CLK, and the delay time is unstable. After the falling edge of the data signal DATA plus one clock cycle T_clk, the detection is completed, and a control signal is generated to generate a stable result clock signal CLKnew, which is maintained until the next falling edge of the data signal DATA, and re-detected after the next falling edge of the data signal DATA, and the control signal and the new delay time are re-generated.

[0083] like Figure 2 As shown, the present invention also discloses an OOK modulation circuit, including a first logic unit and the above-mentioned signal calibration circuit, wherein the first logic unit is used to perform a logic operation on the result clock signal CLKnew output by the signal calibration circuit and the data signal DATA to generate a modulation signal MIXERout. In one embodiment, the first logic unit is a logic AND gate &, and the logic AND gate & performs a logic AND operation on the result clock signal CLKnew and the data signal DATA to generate the modulation signal MIXERout. In other embodiments, the first logic unit can be other logic circuits.

[0084] This embodiment further discloses a signal processing method. Based on the above signal calibration circuit, the signal processing method includes:

[0085] Phase detection is performed on the data signal DATA and the clock signal CLK to generate a characterizing signal Time length that characterizes a phase difference between the data signal DATA and the clock signal CLK.

[0086] One or more pulse signals are generated based on the data signal DATA.

[0087] The pulse width of the characterizing signal Time length is detected based on the pulse signal to generate a control signal. Specifically, the effective number of bits of the control signal is obtained based on the number of edges of the pulse signal within the pulse width range of the characterizing signal Time length.

[0088] The control output based on the control signal calibrates the clock signal CLK to generate the resulting clock signal CLKnew. Specifically, the delay time is adjusted based on the control signal to output the resulting clock signal CLKnew.

[0089] The resulting clock signal CLKnew is logically operated with the data signal DATA to generate a modulation signal MIXERout.

[0090] For specific signal processing methods and signal processing principles, please refer to the above circuit principle description section.

[0091] Example 2

[0092] like Fig. 9 As shown, the difference between this embodiment and embodiment 1 is that the calibration module includes a second delay module and a gating module, the second delay module is used to delay the clock signal CLK multiple times, and the gating module is used to select the original clock signal and the delayed clock signal based on the control of the control signal to output the resulting clock signal CLKnew.

[0093] like Fig.10 As shown, the second delay module includes a plurality of buffer units a1, a2...a3 and current sources I1, I2...In connected to the buffer units a1, a2...a3. The number of buffer units can be adjusted as needed. Each buffer unit includes two groups of transistors (such as P-channel MOS tube M11 and N-channel MOS tube M12, P-channel MOS tube M13 and N-channel MOS tube M14; P-channel MOS tube M21 and N-channel MOS tube M22, P-channel MOS tube M23 and N-channel MOS tube M24; ... P-channel MOS tube Mn1 and N-channel MOS tube Mn2, P-channel MOS tube Mn3 and N-channel MOS tube Mn4); four groups or more transistors can also be set in the buffer unit. In other embodiments, the second delay module can be other circuit structures.

[0094] In one embodiment, each current source I1, I2...In is respectively connected to a group of transistors of the buffer unit, and the delay time of each buffer unit is changed by changing the current generated by the current source I1, I2...In. The larger the current, the faster the buffer unit is turned on and the shorter the delay time. Each buffer unit delays the clock signal CLK through different delay times to generate clock signals CLK1, CLK2...CLKn-1.

[0095] like Fig.11 As shown, in a specific example, the gating module includes a plurality of switch units controlled by adjustment signals N, N-1...1, and the adjustment signals N, N-1...1 are as follows Figure 5 The switch control unit shown is generated, each switch unit includes a control switch, the first end of each control switch Kn, Kn-1...K1 is used to receive the clock signal CLK0, CLK1, CLK2...CLKn-1, the clock signal CLK0 is the original clock signal, and the adjustment signal N, N-1...1 selects which control switch to turn on to output the corresponding clock signal CLKnew at the second end of the control switch.

[0096] like Fig.12As shown, in another specific example, the gating module includes a plurality of switch units controlled by adjustment signals N, N-1...1, some of the switch units include first control switches, and another part of the switch units include second control switches and inverters. Among them, the first end of the first control switch Kn, Kn-1...Kn / 2+1 receives the clock signal CLK0, CLK1, CLK2...CLKn / 2-1 and the adjustment signal N, N-1...N / 2+1 selects which first control switch to turn on to output the corresponding result clock signal CLKnew at the second end of the first control switch; the second control switch Kn-n / 2, Kn-(n / 2+1)...K1 is connected in series with the inverter X1, X2...Xn, and the clock signal CLK0, CLK1, CLK2...CLKn / 2-1 is inverted by the inverter X1, X2...Xn and the adjustment signal NN / 2, N-(N / 2+1)...1 selects which second control switch to turn on to output the corresponding result clock signal CLKnew. The number of the first control switches is equal to the number of the second control switches. In other embodiments, the number of the first control switches and the number of the second control switches can be selected separately as needed.

[0097] This embodiment further discloses a signal processing method. Based on the above signal calibration circuit, the signal processing method includes:

[0098] Phase detection is performed on the data signal DATA and the clock signal CLK to generate a characterizing signal Time length that characterizes a phase difference between the data signal DATA and the clock signal CLK.

[0099] One or more pulse signals are generated based on the data signal DATA.

[0100] The pulse width of the characterizing signal Time length is detected based on the pulse signal to generate a control signal. Specifically, the effective number of bits of the control signal is obtained based on the number of edges of the pulse signal within the pulse width range of the characterizing signal Time length.

[0101] The clock signal CLK is delayed once or multiple times.

[0102] Based on the control of the control signal, the original clock signal and the delayed clock signal are selected to output a result clock signal CLKnew.

[0103] The resulting clock signal CLKnew is logically operated with the data signal DATA to generate a modulation signal MIXERout.

[0104] For specific signal processing methods and signal processing principles, please refer to the above circuit principle description section.

[0105] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0106] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A signal calibration circuit, characterized in that: Used to calibrate a clock signal based on a data signal, the signal calibration circuit comprising: A phase detection module, used for performing phase detection on a data signal and a clock signal to generate a characterization signal characterizing a phase difference between the data signal and the clock signal; A signal generating circuit, used for generating one or more pulse signals based on the data signal; A time-to-digital conversion module, configured to detect a pulse width of a characterizing signal based on a pulse signal to generate a control signal; and The calibration module is used to calibrate the clock signal based on the control output of the control signal to obtain a resultant clock signal.

2. The signal calibration circuit according to claim 1, characterized in that: The phase detection module includes a first trigger, an inverting unit and a first logic unit, the input end of the first trigger is used to receive a data signal, the clock input end of the first trigger is used to receive a clock signal, the input end of the inverting unit is used to receive a data signal, the set end of the first trigger is connected to the output end of the inverting unit, the first input end of the second logic unit is connected to the output end of the first trigger, the second input end of the second logic unit is connected to the output end of the inverting unit, and the output end of the second logic unit is used to output a characterization signal.

3. The signal calibration circuit according to claim 1, characterized in that: The signal generating circuit comprises a pulse generating module, and the pulse generating module is used to generate a pulse signal based on an edge of a data signal; or The signal generating circuit includes a pulse generating module and a first delay module. The pulse generating module is used to generate an initial pulse signal based on the edge of a data signal. The first delay module is used to delay the initial pulse signal once or multiple times to generate one or more subsequent pulse signals.

4. The signal calibration circuit according to claim 1, characterized in that: The time-to-digital conversion module includes one or more second triggers, the input end of the second trigger is used to receive the characterization signal, the clock input end of the second trigger is used to receive the corresponding pulse signal, and the output end of one or more second triggers is used to output the control signal.

5. The signal calibration circuit according to claim 1, characterized in that: The calibration module includes a connected buffer unit and an adjustment unit, the adjustment unit adjusts the delay time of the buffer unit based on the control of the control signal, and the buffer unit is based on the clock signal and the adjustment output result clock signal of the adjustment unit; or The calibration module includes a connected second delay module and a gating module, wherein the second delay module is used to delay the clock signal once or multiple times, and the gating module is used to select the original clock signal and the delayed clock signal based on the control of the control signal to output the result clock signal.

6. An OOK modulation circuit, characterized in that: It comprises a first logic unit and the signal calibration circuit according to any one of claims 1 to 5, wherein the first logic unit is used for performing a logic operation on a result clock signal output by the signal calibration circuit and a data signal to generate a modulation signal.

7. A signal processing method, characterized in that: Based on the signal calibration circuit according to any one of claims 1 to 6, the signal processing method comprises: Performing phase detection on the data signal and the clock signal to generate a characterization signal characterizing a phase difference between the data signal and the clock signal; generating one or more pulse signals based on the data signal; Detecting the pulse width of the characterizing signal based on the pulse signal to generate a control signal; A resulting clock signal after calibrating the clock signal is output based on the control signal.

8. The signal processing method according to claim 7, characterized in that: The detecting the pulse width of the characterization signal based on the pulse signal to generate the control signal comprises: The effective number of bits of the control signal is obtained based on the number of edges of the pulse signal within the pulse width range of the characterizing signal.

9. The signal processing method according to claim 7, characterized in that: The clock signal obtained by calibrating the clock signal based on the control signal output comprises: Adjust the delay time based on the control signal to output a result clock signal; or The clock signal is delayed once or multiple times, and the original clock signal and the delayed clock signal are selected based on the control of the control signal to output the result clock signal.

10. The signal processing method according to claim 7, characterized in that: The signal processing method further includes: performing a logic operation on the result clock signal and the data signal to generate a modulation signal.

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