A pipeline-sar adc calibration method with variable parameter and variable step pseudo-random injection

Abstract

The present application relates to a kind of variable parameter variable step size pseudo-random injection's Pipeline-SAR ADC calibration method, belong to analog integrated circuit field.This method can calibrate the error caused by non-ideal factors such as capacitor mismatch, operational amplifier gain mismatch, comparator mismatch of Pipeline-SAR ADC, by injecting pseudo-random sequence to extract the error caused by non-ideal factors of ADC, then introduce variable parameter inverse hyperbolic tangent function to change the iteration step of calibration, so that the estimated gain value gradually approaches the actual gain value, to achieve the effect of calibration.Compared with the traditional pseudo-random injection calibration technology, the calibration convergence speed is faster, the accuracy is higher, and the consumption of hardware resources is reduced.The calibration timing and ADC conversion are independent of each other, and the conversion process of ADC is not affected during the calibration process, ensuring that the digital and analog systems operate independently, and enhancing the tracking ability of the calibration system.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of analog integrated circuits, and relates to a variable parameter variable step pseudo-random injection Pipeline-SAR ADC calibration method. BACKGROUND

[0002] With the rapid development of integrated circuit technology and the progress of low-voltage short-channel process technology, the power supply voltage of MOS devices is getting lower and lower, and the performance of many originally high-efficiency analog devices is limited, such as the inherent gain of MOS devices greatly reduced. In the design process of high-speed and high-precision Pipeline-SAR ADC, the loop gain error caused by the limited open-loop gain, limited bandwidth, parasitic capacitance, channel charge injection, clock overlap, clock feedthrough, clock jitter, and capacitance mismatch of the amplifier will greatly change the transmission characteristics of the ADC, becoming a bottleneck restricting the development of ultra-high-speed and high-precision ADC. In the Pipeline-SAR ADC, the bandwidth, gain, and power consumption of the operational amplifier cannot be simultaneously achieved. Therefore, the method of calibration by digital circuit can reduce the complexity of analog circuit, and also reduce the power consumption of the system, so that the performance of the entire system is improved.

[0003] With the development of digital circuit technology, the complexity of digital circuit modules increases, and the functions that can be achieved become more powerful,

[0004] Digital circuit calibration is usually divided into foreground calibration and background calibration. The foreground calibration method calibrates by interrupting the normal sampling period of the ADC, once or multiple periods of work, and connecting reference levels, reference DACs, etc. The chip only needs to be calibrated once, and the error factors are permanently saved. The foreground calibration method can avoid the interference of the input signal on the calibration process, and has a faster calibration speed. However, since the foreground calibration interrupts the normal work of the ADC, and the error coefficients may change with temperature, voltage, etc. in different temperature environments, the foreground calibration cannot be widely applied in ADCs. Background calibration refers to observing the ADC converter output digital code and known digital excitation in the normal working state of the ADC converter without interrupting the sampling period, and calibrating the output result in the background through a calibration algorithm. Compared with the foreground calibration method, the background calibration method has the advantages of not interrupting the sampling period and not adding too much analog circuit, and has a faster calibration rate and lower power consumption.

[0005] There are many background calibration structures, and there are two typical digital background calibration methods, one is a background calibration method based on deterministic balancing, referred to as a deterministic algorithm. The deterministic balancing method includes the following methods: a reference high-precision ADC converter design method, a mismatch double sampling method, a split ADC method, etc. The characteristic is to use the change of the analog unit to eliminate the interference of the input as much as possible, separate specific error factors for calibration, and generally has a faster calibration speed, but the analog unit of the whole chip is changed greatly. The other is a calibration method based on statistics, such as a pseudo-random injection (PN sequence injection) method, which has the characteristics of using pseudo-random codes and signal independence and the characteristics of pseudo-random code expectation value being zero, injecting analog signal paths, using statistical principles to separate error factors, and calibrating. It has less changes in the analog unit, can calibrate a wide range of error coefficients, is easy to implement, and its defect is that it needs too many sampling periods to separate interference terms, resulting in slow convergence speed of the algorithm. SUMMARY

[0006] Therefore, the purpose of the present application is to provide a variable parameter and variable step pseudo-random injection Pipeline-SAR ADC calibration method to improve the calibration convergence speed and accuracy of pseudo-random injection calibration and reduce the consumption of hardware resources.

[0007] To achieve the above purpose, the present application provides the following technical scheme:

[0008] A variable parameter and variable step pseudo-random injection Pipeline-SAR ADC calibration method, wherein the Pipeline-SAR ADC comprises a first stage SAR ADC, a second stage SAR ADC, an operational amplifier and a delay alignment unit; the operational amplifier is connected between the first stage SAR ADC and the second stage SAR ADC, and is used for amplifying the residual voltage of the first stage SAR ADC; and the delay alignment unit is used for delaying the digital code of the first stage SAR ADC and the second stage SAR ADC, and then adding the digital code according to the weight to obtain an output digital signal.

[0009] The method specifically comprises the following steps:

[0010] S1, sampling and converting the input analog signal into a first digital signal through the first stage SAR ADC; after the first stage SAR ADC completes the conversion, injecting a first PN sequence into the residual error signal of the first stage SAR ADC;

[0011] S2, transmitting the residual error signal injected with the first PN sequence to the second stage SAR ADC for fine quantization to obtain a second digital signal output by the second stage SAR ADC;

[0012] S3, injecting a second PN sequence identical to the first PN sequence into a second digital signal output by the second stage SAR ADC, so as to cancel out the first PN sequence;

[0013] S4, inputting the second digital signal with the cancelled PN signal into the delay alignment unit for delay operation, and then adding the first digital signal by weight to obtain a third digital signal output by the Pipeline-SAR ADC;

[0014] S5, performing correlation operation on the third digital signal and the first PN sequence or the second PN sequence to obtain an error coefficient between an actual inter-stage gain value and an estimated inter-stage gain value;

[0015] S6, based on the error coefficient, iteratively optimizing the estimated inter-stage gain value through an iterative process, introducing a variable parameter inverse hyperbolic tangent function, and adjusting an iteration step size according to the error coefficient in the iterative process, so as to realize fast convergence of the estimated inter-stage gain value to the actual inter-stage gain value;

[0016] S7, using the estimated inter-stage gain value adjusted through iteration for digital signal output of the Pipeline-SAR ADC, so as to calibrate the inter-stage gain error caused by non-ideal factors.

[0017] Further, the third digital signal D out is expressed as:

[0018]

[0019] In the formula, V in represents an input analog signal, PN represents a PN sequence signal injected, r represents an amplitude of the PN sequence signal injected, G represents an actual inter-stage gain value.

[0020] D out is correlated with the first or second PN sequence to obtain an error coefficient e(n) between the actual inter-stage gain value and the estimated inter-stage gain value:

[0021]

[0022] Further, the estimated inter-stage gain value is iteratively optimized through an iterative process shown in the following formula:

[0023]

[0024] In the formula, 1 / G represents an inverse of the estimated inter-stage gain value, and u(n) represents an iteration step size.

[0025] Further, by a variable parameter inverse hyperbolic tangent function, the iteration step length is adjusted according to the error coefficient in the iteration process, wherein the variable parameter inverse hyperbolic tangent function is represented as:

[0026]

[0027] In the formula, α1-α5, β, γ1-γ5 all represent control parameters, and n represents the iteration number.

[0028] The present application has the advantages that the present application can calibrate the errors of the Pipeline-SAR ADC caused by non-ideal factors such as capacitor mismatch, operational amplifier gain mismatch, comparator mismatch, etc. The errors caused by non-ideal factors of the ADC are extracted by injecting a pseudo-random sequence, and then a variable parameter inverse hyperbolic tangent function is introduced to change the iteration step length of calibration, so that the estimated gain value gradually approaches the actual gain value, and the calibration effect is achieved. Compared with the traditional pseudo-random injection calibration technology, the present application has faster calibration convergence speed and higher precision, and reduces the consumption of hardware resources. The calibration timing and ADC conversion are independent of each other, and the conversion process of the ADC is not affected in the calibration process, which ensures the independent operation of the digital and analog systems and enhances the tracking ability of the calibration system.

[0029] Other advantages, objects, and features of the present application will be apparent to those skilled in the art from the following specification, and will be learned from practice of the present application. The objects and other advantages of the present application can be achieved and obtained by the following specification. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to make the objects, technical solutions and advantages of the present application clearer, the preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings, in which:

[0031] Figure 1 The structural block diagram of the calibration method proposed by the present application is shown in the figure;

[0032] Figure 2 The structural block diagram of the PN sequence generator is shown in the figure;

[0033] Figure 3 The flowchart of introducing the variable parameter variable step length inverse hyperbolic tangent function for calibration is shown in the figure;

[0034] Figure 4 The five inverse hyperbolic tangent function curves selected by the embodiment of the present application are shown in the figure;

[0035] Figure 5 The schematic diagram of the change of the step length in the calibration process is shown in the figure;

[0036] Figure 6 The curve diagram of the calibration gain reciprocal value in the calibration process is shown in the figure;

[0037] Figure 7 The spectrum of the ADC output before calibration;

[0038] Figure 8 This is the spectrum of the ADC output after calibration. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0040] One embodiment of the present invention calibrates a 12-bit 100MS / s Pipeline-SAR ADC, which comprises two cascaded SAR ADCs. For example... Figure 1 As shown, a 6-bit SAR ADC serves as the first stage, and a 7-bit SAR ADC serves as the second stage, with the second-stage SAR ADC including one redundant bit. Furthermore, this pipeline-SAR ADC also includes a sample-and-hold circuit module, an operational amplifier, and a delay alignment unit. The sample-and-hold circuit module extracts instantaneous values ​​from continuous analog signals and stabilizes these values ​​over a certain time interval. The input sinusoidal signal, after passing through the sample-and-hold circuit, is transmitted to the ADC for signal conversion. The two-stage SAR ADC uses a differential sampling structure, successively approximating the common-mode voltage at the differential terminals to convert the sampled analog signal into a digital level. The operational amplifier amplifies the residual voltage after coarse quantization by the first-stage SAR ADC and transmits it to the second-stage SAR ADC for fine quantization. The delay alignment unit performs a certain delay operation on the digital codes of the two SAR ADCs and then adds them according to their weights.

[0041] The core idea of pseudo-random noise calibration is to use the introduced pseudo-random noise signal to identify and compensate the error introduced by the non-ideal performance factors in the ADC. The operation steps of this method include introducing a PN sequence at a certain node of the circuit, and merging it with the analog input signal at this node. The merged signal is then sampled and converted by the ADC. Since the ADC does not automatically calibrate the PN signal during processing, this will produce a non-linear error in the final digital output, which reflects the influence of the non-ideal factors of the circuit on the PN signal and is irrelevant to the original input signal, especially when the PN sequence is long enough.

[0042] When the PN sequence is long enough, it is approximately white noise, has randomness and non-repeatability, and therefore the PN sequence is irrelevant to the Vin signal. The digital code D out output by the ADC is correlated with the PN sequence to obtain the difference between the actual gain value and the estimated gain value, i.e. the error coefficient e(n). In order to obtain the error information, the correlation between the original input PN sequence and the digital code D out output by the ADC can be calculated by using the characteristics of the PN sequence. In this way, the error caused by the non-ideal factors of the circuit can be accurately extracted, and the corresponding calibration processing can be performed. Among them, the ADC output D out is expressed as follows:

[0043]

[0044] The error coefficient e(n) of the actual gain value and the estimated gain value is expressed as follows:

[0045]

[0046] where D1 and D2 represent the first and second level SAR ADC output digital code signals respectively, PN is the injected PN sequence signal, r is the amplitude of the PN sequence signal injection, represents the correlation operation, represents the estimated gain value reciprocal, the estimated gain value, G represents the actual gain value, and n represents the calibration times.

[0047] As Figure 2 shown, the linear feedback sequence shift register is used to generate the PN sequence, which is composed of a plurality of registers connected in series, and the output of each register is directly supplied to the input of the subsequent register, forming a data shift chain. Ai represents the value of each shift register, i.e. 0 or 1, where i=0, 1, 2, …, n-1. In addition, the linear feedback sequence shift register also contains a set of feedback lines (C0, C1, …, C n-1These registers, based on their respective states (1 for connected, 0 for disconnected), determine whether to feed the output of a specific register back to the start input of the chain, thus forming a feedback loop. Figure 2 It can be seen that different C i The value of C will result in different connection states of the feedback line, and consequently, different periods of the m-sequence generated by the shift register. In summary, the period of the m-sequence generated by the linear shift register is determined by C. i The value of C determines this. i Combinations of values ​​will form different feedback structures, which can be distinguished by the characteristic polynomial f(x), the expression of which is:

[0048]

[0049] This invention introduces a variable-parameter inverse hyperbolic tangent function to achieve a variable-step-size calibration process, as follows: Figure 3 As shown, the introduced variable-parameter inverse hyperbolic tangent function is as follows:

[0050]

[0051] Where u(n) represents the iteration step size, and β1, α2, α3, α4, α5, γ1, γ2, γ3, γ4, γ5, and β all represent control parameters. The above equation contains five functions, divided into five intervals based on the number of calibrations, named curve 1, curve 2, curve 3, curve 4, and curve 5 from top to bottom. According to the above equation, the relationship between the iteration step size and the error coefficient is as follows: Figure 4 As shown in the figure. Among them, α1, α2, α3, α4, and α5 are 0.4, 0.3, 0.25, 0.2, and 0.15, respectively, and γ1, γ2, γ3, γ4, and γ5 are 0.05, 0.07, 0.09, 0.1, and 0.3, respectively.

[0052] like Figure 4 As shown, the step size u(n) increases with increasing parameter α and decreases with increasing parameter γ. In the initial stage of calibration, the error coefficient e(n) is generally large, while in the later stage it is small. Therefore, we make α1 > α2 > α3 > α4 > α5, and γ1 < γ2 < γ3 < γ4 < γ5, making the step size function a piecewise function. It should be noted that the step size u(n) also increases with increasing parameter β, but this does not change in the later stages of calibration. Figure 4 As shown in the image.

[0053] Applying a variable parameter, variable step size function to the Pipeline-SAR ADC, the final calibration step size is as follows: Figure 5 As shown, the step size varies significantly depending on the number of calibration cycles. Simultaneously, within the same interval, the step size function can be adjusted slightly based on the error coefficient e(n), thus achieving rapid convergence and calibration. The division of the calibration interval can be dynamically adjusted according to actual conditions.

[0054] The iteration formula for estimating the inter-stage gain is as follows:

[0055]

[0056] The positive or negative of the error coefficient e(n) determines the direction of real-time updating of the estimated gain value, i.e. increasing or decreasing the gain calibration value compared with the current iteration number. The step factor u(n) determines the step length of real-time updating of the estimated gain value, is the gain used for calculation of the current iteration number ADC, is the calibration gain value obtained according to the error coefficient and the step factor, which is used for gain calculation of the next ADC calibration. The foregoing process is one calibration loop, and the estimated gain value is updated once in each loop. The final gain calibration result is as shown in Figure 6 , wherein the loop convergence number is determined as 85, at which time the reciprocal of the estimated gain value is stabilized at 0.0658, and the finally calibrated inter-stage gain is 15.1.

[0057] As shown in Figure 7 is the output result spectrum diagram of the uncalibrated 12-bit Pipeline-SAR ADC, the input signal frequency of the ADC is (4077 / 2 16 )*100M, with non-ideal factors such as gain mismatch, capacitor mismatch and comparator mismatch. As can be seen from Figure 7 , the ENOB of the ADC is 9.26 bits, the SFDR is 75.88 dB, and the SNDR is 57.5 dB.

[0058] As shown in Figure 8 is the output spectrum diagram after calibration by the variable parameter inverse hyperbolic tangent function. It can be seen that the ENOB is 11.68 bits, the SFDR is 75.88 dB, and the SNDR is 72.05 dB.

[0059] As can be seen from Figure 7 and Figure 8 , under the non-ideal factors such as gain mismatch and capacitor mismatch, the ENOB decreases from 12 bits to 9.26 bits, and after introducing the variable parameter inverse hyperbolic tangent function for calibration, the ENOB increases from 9.26 bits to 11.68 bits, and the SNDR increases from 57.5 dB to 72.05 dB.

[0060] Finally, it should be pointed out that the above embodiments are only used to illustrate the technical solutions of the present application and not to limit it. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the purpose and scope of the technical solutions, which should be covered in the scope of the claims of the present application.

Claims

1. A variable parameter and variable step size pseudo-random injection Pipeline-SAR ADC calibration method, the Pipeline-SAR ADC comprising a first stage SAR ADC, a second stage SAR ADC, an operational amplifier and a delay alignment unit; the operational amplifier is connected between the first stage SAR ADC and the second stage SAR ADC, and is used for amplifying the residual voltage of the first stage SAR ADC; the delay alignment unit is used for performing a delay operation on the digital codes of the first stage SAR ADC and the second stage SAR ADC, and then adding according to weights to obtain an output digital signal; characterized in that, The method comprises: sampling and converting an input analog signal into a first digital signal by a first-stage SAR ADC; after the first-stage SAR ADC completes conversion, injecting a first PN sequence into a residual error signal of the first-stage SAR ADC; transmitting the residual error signal injected with the first PN sequence to a second-stage SAR ADC for fine quantization, to obtain a second digital signal output by the second-stage SAR ADC; injecting a second PN sequence identical to the first PN sequence into the second digital signal output by the second-stage SAR ADC, so as to cancel out the first PN sequence; inputting the second digital signal from which the PN signal is eliminated into the delay alignment unit for delay operation, and then adding the first digital signal according to a weight to obtain a third digital signal output by the Pipeline-SAR ADC; performing correlation operation on the third digital signal and the first PN sequence or the second PN sequence, to obtain an error coefficient between an actual inter-stage gain value and an estimated inter-stage gain value; based on the error coefficient, iteratively optimizing the estimated inter-stage gain value through an iteration process, while introducing a variable parameter inverse hyperbolic tangent function, and adjusting an iteration step size according to the error coefficient in the iteration process, to realize fast convergence of the estimated inter-stage gain value to the actual inter-stage gain value; specifically, iteratively optimizing the estimated inter-stage gain value through an iteration process shown in the following formula: wherein, represents the inverse of the estimated inter-stage gain value, represents the iteration step size, represents the error coefficient between the actual inter-stage gain value and the estimated inter-stage gain value, represents the iteration number; and the iteration step size is adjusted according to the error coefficient during the iteration process by a variable parameter inverse hyperbolic tangent function, which is expressed as: ​ wherein , , each represents a control parameter, , ; using the estimated inter-stage gain value adjusted through iteration for digital signal output of the Pipeline-SAR ADC, so as to calibrate an inter-stage gain error caused by non-ideal factors.

2. The method of claim 1, wherein: a third digital signal output from the Pipeline-SAR ADC is represented as: wherein represents an input analog signal, represents an injected PN sequence signal, r represents an amplitude of the PN sequence signal injection, represents an estimated inter-stage gain value, represents an actual inter-stage gain value; Will By performing correlation operations with the first or second PN sequence, the error coefficient between the actual interstage gain value and the estimated interstage gain value is obtained. : In the formula, n denotes the number of iterations.

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