Clock bias digital calibration method based on similar triangles

Abstract

The application relates to a clock deviation digital calibration method based on similar triangles, and belongs to the field of clock interlaced digital-to-analog conversion circuits. Firstly, a sub-channel output is preliminarily calibrated through a dislocation and gain mismatch calibration module; then a clock deviation calibration module is used for clock deviation calibration, a selected sub-channel is taken as a reference, a sampling point difference value of a to-be-calibrated channel and the reference channel is compared, a correlation coefficient and a deviation percentage are calculated, a sampling error value is calculated according to the deviation percentage by using a similar triangle principle, an output code is compensated, and thus an accurate output after calibration is obtained. The calibration method does not need an additional reference channel, directly takes the selected sub-channel as the reference channel, is relatively simple in calculating the clock deviation percentage size, can quickly calibrate the clock deviation of the clock interlaced ADC with small resource consumption and power consumption.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of clock interleaved digital-to-analog conversion circuits, and relates to a clock deviation digital calibration method based on similar triangles. BACKGROUND

[0002] With the rapid progress of wireless communication technology, especially under the impetus of 5G, Internet of Things and future 6G technology, the requirement for circuit processing speed has reached an unprecedented height. This trend has directly driven the development of high-speed analog-to-digital converters (ADCs), making them key components in modern communication systems. In the fields of high-speed signal processing, radio frequency communication, radar systems, and high-precision measuring instruments, the demand for high-performance ADCs is growing to meet the requirements for higher data rates, lower power consumption, and smaller package sizes.

[0003] As an innovative solution, the time-interleaved (TI) technology has emerged to break through the performance bottleneck of a single ADC, especially in terms of sampling rate. A TI ADC system connects multiple identical sub-ADCs in parallel, and each sub-ADC samples the input signal in turn according to a predetermined timing, thereby synthesizing an output data stream that appears to be sampled at a higher frequency. This design cleverly takes advantage of parallel processing to significantly increase the sampling rate with relatively small individual ADC units, at the cost of increased circuit area and moderate power consumption, meeting the needs of high-speed application scenarios.

[0004] However, the advantages of TI ADC architecture come at a cost. In actual applications, due to factors such as manufacturing process differences, temperature changes, power supply fluctuations, and other factors, there will inevitably be mismatches between the sub-ADC channels. These mismatches are key factors that constrain the performance of TI ADCs. Specifically, the inter-channel mismatches mainly include three types: offset mismatch, gain mismatch, and sampling time mismatch.

[0005] Offset mismatch refers to the inconsistency of the output level of each sub-ADC at zero input, which is a fixed DC offset and can usually be corrected by simple calibration methods such as one-time calibration or periodic calibration. Gain mismatch refers to the difference in amplification of the same input signal between sub-ADCs, which is also a static error. Its calibration method is relatively mature, and it can be compensated by accurately measuring the gain characteristics of each channel and applying digital signal processing algorithms.

[0006] Sampling time mismatch, also known as clock skew or time-interleaved error, is one of the most difficult problems in TI ADC. It is caused by the non-ideal synchronization of the sampling clock of each sub-ADC, resulting in the shift of the sampling point on the actual time axis, and then introducing high-frequency noise and harmonic distortion, which seriously reduces the key dynamic performance indicators of TI ADC, such as signal-to-noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR). SUMMARY

[0007] Therefore, the purpose of the present application is to provide a clock skew digital calibration method based on similar triangles to improve the influence of sampling time mismatch on TI ADC.

[0008] To achieve the above purpose, the present application provides the following technical solutions:

[0009] A clock skew digital calibration method based on similar triangles, first, the digital codes output by the sub-channel ADC are calibrated for offset mismatch and gain mismatch by the offset mismatch calibration module and the gain mismatch calibration module of the clock interleaved digital-to-analog conversion circuit, and then the clock skew calibration is completed by the clock skew calibration module, wherein the clock skew calibration module includes a clock skew percentage detection module and an error calculation module. The clock skew percentage detection module selects two sub-channel ADCs, one of which is used as a reference channel and the other is used as a calibration channel. The difference between the sampling point of the calibration channel and the adjacent two sampling points of the reference channel is used to calculate the correlation coefficient containing the clock skew ΔT information, and the clock skew value percentage of the calibration channel is obtained according to the difference ratio between the correlation coefficients. Then, the error calculation module calculates the digital code sampling error value to be compensated according to the clock skew value percentage by similar triangles, and calculates the calibrated output code by the output code corresponding to the calibration channel and the compensation value.

[0010] Further, the clock skew percentage detection module calculates the clock skew between the reference channel and the calibration channel as follows:

[0011] The k-1th sampling output of the reference channel is represented as y1(k-1), the kth sampling output of the reference channel is represented as y1(k), the k-1th sampling output of the calibration channel is represented as y2(k-1), and the k-1th sampling of the calibration channel is between the k-1th and kth samplings of the reference channel in the time domain; T is the sampling period of the clock interleaved ADC, and the sampling time skew of the calibration channel relative to the reference channel is ΔT, then:

[0012] The sampling interval between the (k-1)th sample of the reference channel and the (k-1)th sample of the channel to be calibrated is T+ΔT. The result is obtained by calculating the interval (T+ΔT) based on the outputs y1(k-1) and y2(k-1) of the two samples. 2 The correlation coefficient of the information, R(T+ΔT):

[0013]

[0014] The sampling interval between the (k-1)th sample of the channel to be calibrated and the kth sample of the reference channel is T+ΔT. The result is obtained by calculating the interval (T-ΔT) based on the outputs y2(k-1) and y1(k) of the two samples. 2 The correlation coefficient of the information R(T-ΔT):

[0015]

[0016] The sampling interval between the (k-1)th and kth samples of the reference channel is 2T. The result is obtained by calculating the range (2T) based on the outputs y2(k-1) and y1(k) of the two samples. 2 The correlation coefficient R(T) of the information:

[0017]

[0018] In the formula, α is the proportionality coefficient; R(T+ΔT) is the cumulative average of the squares of the differences between one sampling point and the previous sampling point, and R(T-ΔT) is the cumulative average of the squares of the differences between the sampling point and the next sampling point. The clock deviation ΔT between channels causes a difference between R(T+ΔT) and R(T-ΔT).

[0019] R(T+ΔT)-R(T-ΔT)=4αTΔT

[0020] The correlation coefficient between this difference and the sampling period is R(T) = 4αT 2 The ratio is the percentage of the clock skew of that channel, D. ΔT It is represented as:

[0021]

[0022] Where ΔT is the clock offset between channels, and D ΔT This represents the percentage of clock skew.

[0023] Furthermore, the error calculation module solves for the compensation value e of the digital code to be compensated by utilizing the similarity characteristics of the right triangle A formed in the time domain by the values ​​of the two samples from the reference channel and the sampling interval, as well as the right triangle B formed in the time domain by the difference between the ideal sampling point and the actual sampling point and the clock deviation, where:

[0024]

[0025] The compensation value e is expressed as:

[0026]

[0027] After the compensation value e is calculated, the digital code output by the corresponding sampling point is added with the compensation value e to obtain the calibrated output code. Through the method based on similar triangles, the clock deviation percentage is obtained according to the correlation coefficient, and the calculation can be applied to any input signal, so that the TI ADC calibrated by using the algorithm has no requirement on the input signal, and the applicability is better. The correlation coefficient of the algorithm is calculated through the discrete sequences sampled by the channels, the calculated result is more accurate, and the process of calculating the clock deviation percentage is very simple.

[0028] Further, the offset mismatch calibration module obtains the offset value of each channel by accumulating and averaging the digital codes output by each channel, then the offset of the remaining sub-channels is subtracted from the offset of the reference channel to obtain the offset value of each channel relative to the reference channel, and finally each channel is subtracted from the offset value relative to the reference channel to complete the offset mismatch calibration.

[0029] Further, the gain mismatch calibration module first obtains the gain value of each channel by accumulating and averaging the absolute values of the digital codes output by each channel, then obtains the gain ratio of each to-be-calibrated channel relative to the reference channel by the ratio between the gain value of the reference channel and the gain value of each to-be-calibrated channel, and finally multiplies the digital code output by each to-be-calibrated channel by the corresponding gain ratio to complete the gain mismatch calibration.

[0030] Further, the calibration method is used for clock deviation calibration in a TI-ADC with 2 N channels, and N is a positive integer. First, the 2 N-1 +1 channel is taken as a to-be-calibrated channel to perform calibration with the first channel as a reference channel; then the 2 N-2 +1 channel is taken as a to-be-calibrated channel to perform calibration with the first channel and the 2 N-1 +1 channel that has completed calibration as reference channels, the 3 N-2 +1 channel is taken as a to-be-calibrated channel to perform calibration with the 2 N-1 +1 channel and the first channel as reference channels; and the calibration is performed in this way until the calibration of all channels is completed.

[0031] Further, the operation steps of the calibration method are as follows:

[0032] S1, the entire circuit is powered on and reset, so that all register values in the calibration system are zeroed;

[0033] The output digital codes of the TI-ADC are subjected to offset mismatch calibration and gain mismatch calibration respectively, and the calibrated digital codes are input into a clock offset calibration module for final calibration.

[0034] S3, the clock offset percentage detection module in the clock offset calibration module detects the clock offset percentage D between the channels through the relationship between the correlation coefficients ΔT The calculated clock offset percentage D ΔT is input into an error calculation module for error calculation.

[0035] S4, the error value e to be compensated is calculated through the error calculation module based on the similar triangle, and the clock offset calibration of the TI-ADC is completed by subtracting the compensation value e from the actually sampled output code.

[0036] The present application has the following advantages:

[0037] The present application directly extracts the correlation coefficients between the two channels through the digital codes output by the two-channel ADC, and the difference of the calculated correlation coefficients is caused by the clock offset. The difference is used to divide the correlation coefficient corresponding to the sampling time to obtain the percentage of the clock offset between the two channels. Then, the value to be compensated is calculated through the characteristics that the right triangle formed by the difference of the two sampling times of the reference channel and the sampling interval in the time domain is similar to the triangle formed by the error value to be calculated and the clock offset in the time domain. Finally, the output result after final calibration is obtained by subtracting the compensation value from the sampled digital code. The calibration method does not need an additional reference channel, directly takes the first channel as the reference channel, and is relatively simple in calculating the clock offset percentage. The clock offset of the clock interleaved ADC can be quickly calibrated with small resource consumption and power consumption.

[0038] Other advantages, objects, and features of the present application will be apparent to those skilled in the art from the following specification, and will be learned from the practice of the present application. The objects and other advantages of the present application can be achieved and obtained by the following specification. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to make the objects, technical solutions and advantages of the present application clearer, the preferred detailed description of the present application will be combined with the drawings as follows, wherein:

[0040] Figure 1 The overall flowchart of the clock offset digital calibration method of the present application;

[0041] Figure 2 The clock offset calculation flowchart of the present application;

[0042] Figure 3 Fig. 1 is a schematic diagram of the compensation value calculation principle based on similar triangles of the present application;

[0043] Figure 4 Fig. 4 is a schematic diagram of the calibration effect of the present application in the case of 10bit, 16 channels;

[0044] Figure 5 Fig. 5 is a schematic diagram of the simulation result of the present application, wherein, Figure 5 (a) is the FFT spectrum diagram of the output signal before calibration, Figure 5 (b) is the FFT spectrum diagram of the output signal after calibration. DETAILED DESCRIPTION

[0045] The present application can be implemented or applied in other different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the diagrams provided in the following examples only illustrate the basic concept of the present application in a schematic manner, and the following examples and features in the examples can be combined with each other without conflict.

[0046] The accompanying drawings are only used for exemplary illustration, and the representation is only a schematic diagram, not a physical diagram, and should not be understood as a limitation of the present application; in order to better illustrate the embodiments of the present application, some components in the drawings may be omitted, enlarged or reduced, and do not represent the actual product size; it is understandable to those skilled in the art that some well-known structures and their descriptions in the drawings may be omitted.

[0047] The same or similar reference numerals in the drawings of the embodiments of the present application correspond to the same or similar components; in the description of the present application, it should be understood that if the terms "upper", "lower", "left", "right", "front", "back" and the like indicate the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the terms describing the positional relationship in the drawings are only used for exemplary illustration, and should not be understood as a limitation of the present application, and for those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0048] Please refer to Figures 1-5 , a clock offset digital calibration method based on similar triangles.

[0049] Embodiments

[0050] A clock deviation digital calibration method based on similar triangles. In a clock interleaving digital-to-analog conversion circuit, as shown in Figure 1 the digital codes output by the sub-ADCs after sampling and quantization need to undergo offset mismatch calibration and gain mismatch calibration before clock deviation calibration. Two-channel clock interleaving ADCs are usually selected for clock deviation calibration. The clock deviation digital calibration method based on similar triangles proposed in the present application takes one of the two-channel ADCs as a reference channel and the other as a calibration channel, and calculates the clock deviation percentage of the calibration channel based on the reference channel.

[0051] Offset mismatch can be obtained by accumulating and averaging the digital codes output by each channel to obtain the offset value of each channel, and then subtracting the offset of the first channel from the offsets of the remaining channels to obtain the offset value of each channel relative to the reference channel. Finally, each channel is subtracted from its offset relative to the reference channel to complete offset mismatch calibration. Gain mismatch calibration requires taking the absolute value of the output code of each channel and accumulating and averaging it to obtain the gain value of each channel. The gain value of the first channel is divided by the gain value of each channel to obtain the gain ratio of each channel relative to the first channel. Finally, the output code of each channel is multiplied by its corresponding gain ratio to complete gain mismatch calibration.

[0052] In the clock deviation digital calibration process, the first channel is usually selected as the reference channel, and the remaining channels are calibrated with the first channel. Similarly, any other channel can be selected as the reference channel, and the remaining channels can be calibrated with the reference channel. The difference between the sampling points of the calibration channel and the adjacent two sampling points of the reference channel is used to calculate the correlation coefficient containing clock deviation ΔT information. The result of directly accumulating and averaging the digital codes after offset mismatch calibration and gain mismatch calibration will be zero, so the correlation coefficient needs to be squared to obtain two correlation coefficients containing clock deviation. The difference between them divided by the correlation coefficient containing sampling time T can obtain the clock deviation percentage of the calibration channel. Finally, the characteristic of similar triangles is used to calculate the digital code sampling error value that needs to be compensated. The clock deviation digital calibration of the calibration channel is completed by subtracting the compensation value from the corresponding output code of the calibration channel. Finally, the digital codes of each channel are output in parallel, and after interleaving, they form the output code of the TI-ADC.

[0053] The parameters are calculated by subtracting square and then calculating average value by using sliding average, which can effectively reduce the difference between the calculated results of adjacent two clock deviations, so as to reduce the possibility of distortion after calibration and ensure the continuity of the calibrated data ΔT Only one division is needed, and no other complex calculation is needed, so that the circuit implementation will be more resource-saving and power-saving.

[0054] The calibration module mainly comprises a clock deviation percentage detection module and an error calculation module, and the specific calculation process of the clock deviation percentage detection module from the digital output code of the two-channel TI-ADC comprises:

[0055] As shown in Figure 2 the k-1th sampling output of the reference channel is represented as y1(k-1), the k-1th sampling output of the channel to be calibrated is represented as y2(k-1), and the kth sampling output of the reference channel is represented as y1(k). The k-1th sampling of the channel to be calibrated is between the k-1th and kth samplings of the reference channel in the time domain. Assuming that T is the sampling period of the clock interleaved ADC, the sampling time deviation of the channel to be calibrated relative to the reference channel is ΔT. Therefore, the interval between y1(k-1) and y2(k-1) is T+ΔT, and the result of subtracting square of them will have (T+ΔT) 2 related information. Similarly, the interval between y2(k-1) and y1(k) is T-ΔT, and the result of subtracting square of them will have (T-ΔT) 2 related information. The interval between y1(k) and y1(k-1) is 2T, and the result of subtracting square of them will have (2T) 2 related information. It can be known from the following specific calculation expressions of the related parameters that:

[0056]

[0057]

[0058] Wherein α is a proportional coefficient, since the calculation method is the same, the proportion of the three coefficients to the square of the sampling interval will also be the same, that is, the proportional coefficients α in the three parameters are the same.

[0059] By calculating the cumulative average value R(T+ΔT) and R(T-ΔT) of the square of the difference between one sampling point and the sampling point at the previous time and the square of the difference between one sampling point and the sampling point at the next time, the clock deviation ΔT between the channels will cause a difference between R(T+ΔT) and R(T-ΔT), that is, R(T+ΔT)-R(T-ΔT)=4αTΔT, and the difference is used to remove the related coefficient R(T) corresponding to the sampling period, that is, R(T)=4αT 2The clock deviation percentage D of the channel can be obtained ΔT The specific calculation formula is:

[0060]

[0061] Wherein, ΔT is the clock deviation between channels, D ΔT is the clock deviation percentage.

[0062] As Figure 3 shown, the error calculation module mainly obtains the value e that needs to be compensated on the digital code through the similar characteristics of the right triangle A formed by the two sampling values of the reference channel and the sampling interval in the time domain and the right triangle B formed by the difference between the ideal sampling point and the actual sampling point and the clock deviation in the time domain. The ratio of the height to the base of the two right triangles is the same, and has:

[0063]

[0064] The deformation is:

[0065]

[0066] After the size of the compensation value e is calculated, the digital code output by the corresponding sampling point can be added with the compensation value e to obtain the calibrated output code. The method can efficiently solve the performance degradation problem of TI-ADC caused by clock deviation.

[0067] The application is a background calibration method, which does not need to interrupt the normal work of TI-ADC during the calibration process. The method mainly includes a mismatch calibration module, a gain mismatch calibration module and a clock deviation calibration module. According to the number of sub-channels of TI-ADC design, the number of clock deviation calibration modules will also increase, but the internal circuit of the clock deviation calibration module will not change.

[0068] After the chip is powered on and reset, TI-ADC starts sampling and quantizing and outputs the quantized digital code. The digital code will pass through the mismatch calibration, gain mismatch calibration and then reach the clock deviation calibration module. In the clock deviation calibration module, the clock deviation percentage D ΔT is calculated by the clock deviation percentage detection module, and the value e that needs to be compensated is calculated by the error calculation module. The calculation principle is to obtain the compensation value through the characteristics of similar triangles. Finally, the digital code of the channel with clock deviation is subtracted by the corresponding compensation value e to complete the clock deviation calibration.

[0069] The algorithm can also be used for clock deviation calibration in TI-ADC with other channel numbers of 2 N , wherein N is a positive integer, and the calibration method is similar to that of the 2-channel, the first step is to calculate the second N-1The first channel is calibrated with the first channel as the reference channel; the second step is to calibrate the second channel with the first channel and the third channel as the reference channels N-2 The first channel is calibrated with the first channel and the second channel as the reference channels N-1 The first channel is calibrated with the first channel and the second channel as the reference channels, the third channel is calibrated with the second channel and the next first channel as the reference channels N-2 The first channel is calibrated with the second channel and the first channel as the reference channels N-1 The first channel is calibrated with the second channel and the first channel as the reference channels; and so on until the calibration of all channels is completed.

[0070] Taking a four-channel TI ADC as an example, the first step is to calibrate the third channel with the first channel as the reference channel, to extract the clock deviation percentage with the first channel and the third channel and the third channel and the next first channel, and to calculate the compensation value in the error calculation module, and then to add the output code of the third channel to the error value corresponding to the third channel to complete the calibration of the three channels. The second step is to calibrate the second channel with the first channel and the third channel as the reference, and to calibrate the fourth channel with the third channel and the first channel as the reference, that is, the two adjacent channels are calibrated with the first channel and the third channel as the reference, and the calibration method is the same as that of the third channel.

[0071] The calibration of an eight-channel TI-ADC is similar to that of a four-channel TI-ADC, the first step is to calibrate the fifth channel with the first channel and the next first channel as the reference channel; the second step is to calibrate the third channel with the first channel and the fifth channel as the reference channel, and to calibrate the seventh channel with the fifth channel and the next first channel as the reference channel; the third step is to calibrate the second channel with the first channel and the third channel as the reference channel, to calibrate the fourth channel with the third channel and the fifth channel as the reference channel, to calibrate the sixth channel with the fifth channel and the seventh channel as the reference channel, and to calibrate the eighth channel with the seventh channel and the next first channel as the reference channel, and thus the digital calibration of the clock deviation of the eight-channel TI-ADC is completed.

[0072] The embodiment also provides a calibration operation step of a clock deviation digital calibration method based on similar triangles, which comprises:

[0073] Step one, the entire circuit is powered on and reset, so that all register values in the calibration system are zeroed;

[0074] Step two, the output digital codes of the TI-ADC are subjected to offset mismatch calibration and gain mismatch calibration, and the calibrated digital codes are input into a clock deviation calibration module for final calibration;

[0075] Step three, the clock deviation percentage detection module in the clock deviation calibration module extracts the clock deviation percentage D ΔT between channels through the relationship between the correlation coefficients, and the calculated clock deviation percentage D ΔT is input into an error calculation module for error calculation.

[0076] Step four, use the error calculation module based on similar triangles to calculate the error value e that needs to be compensated, and subtract the compensation value e from the actual sampled output code to complete the clock offset calibration of the TI-ADC.

[0077] Based on the above calibration operation steps, the corresponding simulation results of the embodiment are obtained.

[0078] As Figure 4 shown, it is a simulation effect diagram of the calibration method designed by the application, which is a comparison diagram of effective number of bits ENOB of a 10bit, 16-channel TI-ADC before and after calibration, the clock offset is set to be random 2%T~ -2%T, the offset error and the dispute error are also set to be positive and negative 2%, and it can be seen from Figure 4 that with the increase of the input signal frequency, under the condition that the clock offset is unchanged, if the TI-ADC is not calibrated for offset mismatch and gain mismatch, the effective number of bits thereof can be only 6.8bit at most, after the offset mismatch calibration and the gain mismatch calibration are completed, the effective number of bits of the TI-ADC can reach 9.6bit at most, and when the input signal frequency increases, if the clock offset calibration is not performed, the effective number of bits of the TI-ADC will also decrease to about 5.9bit, and when the clock offset calibration is performed, the effective number of bits of the TI-ADC can be maintained at about 9.5bit, so after the TI-ADC is calibrated by using the algorithm of the application, the clock offset is always maintained at about 9.5bit, and the dynamic performance of the TI-ADC is obviously improved.

[0079] As Figure 5 shown, it is a simulation result of the calibration algorithm designed by the application in a 16-channel TI-ADC, the frequency of the input signal is (incoherent sampling), fs is the sampling frequency of the TI-ADC, wherein, Figure 5 (a) is an FFT frequency spectrum diagram of the output signal before calibration, Figure 5 (b) is an FFT frequency spectrum diagram of the output signal after calibration, under the clock offset of 2%T~ -2%T, the SNDR before calibration is 37.6dB, the ENOB is 5.9bit, and the SFDR is 43.5dB, after the calibration is completed, the SNDR of the entire TI-ADC is improved from 37.6dB to 57.3dB, the ENOB is improved from 5.9bit to 9.2bit, and the SFDR is improved from 43.5dB to 61.3dB. The performance of the TI-ADC after calibration is significantly improved, and the effective number of bits is improved by 3.3bit, and the problem of performance decline of the TI-ADC caused by clock offset is effectively solved.

[0080] The systems, apparatuses, modules or units disclosed in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0081] Finally, it should be pointed out that the above embodiments are only used to illustrate the technical solutions of the present application but not to limit the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or equivalently replaced without departing from the spirit and scope of the present application, and all these modifications and equivalents should be included in the scope of the claims of the present application.

Claims

1. A digital clock skew calibration method based on similar triangles, characterized in that: Firstly, the digital codes output by the sub-channel ADCs are calibrated by the offset mismatch calibration module and the gain mismatch calibration module of the clock interleaved analog-to-digital conversion circuit, and then the clock deviation calibration module is used to complete the clock deviation calibration, wherein, The clock deviation calibration module comprises a clock deviation percentage detection module and an error calculation module. The clock deviation percentage detection module selects two sub-channel ADCs, one of which is used as a reference channel and the other is used as a channel to be calibrated. The difference between the sampling points of the channel to be calibrated and the adjacent two sampling points of the reference channel is used to calculate the correlation coefficient containing the clock deviation ΔT information. The clock deviation percentage of the channel to be calibrated is obtained according to the difference ratio between the correlation coefficients. Then, the error calculation module calculates the digital code sampling error value to be compensated according to the clock deviation percentage through a similar triangle. The output code corresponding to the channel to be calibrated is calculated with the compensation value to obtain the calibrated output code. The clock deviation percentage detection module calculates the clock deviation between the reference channel and the channel to be calibrated as follows: The (k-1) th sampling output of the reference channel is represented as y1(k-1), the k th sampling output of the reference channel is represented as y1(k), and the (k-1) th sampling output of the channel to be calibrated is represented as y2(k-1). The (k-1) th sampling of the channel to be calibrated is between the (k-1) th and k th samplings of the reference channel in the time domain. T is the sampling period of the clock interleaved ADC, and the sampling time deviation of the channel to be calibrated relative to the reference channel is ΔT. Therefore: The sampling interval between the k-1th sample of the reference channel and the k-1th sample of the channel to be calibrated is T+ΔT, and the correlation coefficient R(T+ΔT) of the information is obtained by operating the outputs y1(k-1) and y2(k-1) of the two samples. 2 the correlation coefficient R(T+ΔT) of the information: The sampling interval between the k-1th sampling of the channel to be calibrated and the kth sampling of the reference channel is T+ΔT, and the correlation coefficient R(T-ΔT) of the information is obtained by operating the outputs y2(k-1) and y1(k) of the two samplings. 2 The correlation coefficient R(T-ΔT) of the information: The sampling interval between the (k-1)th and kth samples of the reference channel is 2T, and the correlation coefficient R(T) of the information is obtained by operating the outputs y2(k-1) and y1(k) of the two samples. 2 the correlation coefficient R(T) of the information: In the formula, α is a proportional coefficient; R(T+ΔT) is the cumulative average of the square of the difference between one sampling point and the sampling point at the previous time, and R(T-ΔT) is the cumulative average of the square of the difference between the sampling point and the sampling point at the next time. The clock deviation ΔT between the channels causes a difference between R(T+ΔT) and R(T-ΔT): R(T+ΔT)-R(T-ΔT)=4αTΔT The difference value and the correlation coefficient R(T) = 4aT corresponding to the sampling period 2 The ratio of the difference value and the correlation coefficient R(T) = 4aT corresponding to the sampling period ΔT which is expressed as: where ΔT is the clock skew that exists between the channels, D ΔT is the clock skew percentage.

2. The method of claim 1, wherein: The error calculation module solves the compensation value e of the digital code to be compensated through the similar characteristics of the right triangle A formed by the values of two samplings of the reference channel and the sampling interval in the time domain and the right triangle B formed by the difference between the ideal sampling point and the actual sampling point and the clock deviation in the time domain. Wherein: The compensation value e is represented as: After the size of the compensation value e is calculated, the digital code output by the corresponding sampling point is added to the compensation value e to obtain the calibrated output code.

3. The method of claim 1, wherein: The offset mismatch calibration module calculates the offset value of each channel by accumulating and averaging the digital codes output by each channel. Then, the offset of the remaining sub-channels is subtracted from the offset of the reference channel to obtain the offset value of each channel relative to the reference channel. Finally, each channel is subtracted by its offset value relative to the reference channel to complete the offset mismatch calibration.

4. The method of claim 1, wherein: The gain mismatch calibration module first accumulates the absolute values of the digital codes output by each channel to obtain the gain value of each channel, then obtains the gain ratio of each to-be-calibrated channel relative to the reference channel by the ratio between the gain value of the reference channel and the gain value of each to-be-calibrated channel, and finally multiplies the digital code output by each to-be-calibrated channel by the corresponding gain ratio to complete the gain mismatch calibration.

5. The method of claim 1, wherein: The calibration method is for a TI-ADC with a channel number of 2 N In the clock offset calibration of a TI-ADC with N being a positive integer, first, the 2 N-1 +1 channel is taken as a channel to be calibrated and the first channel is taken as a reference channel to perform calibration; then, the 2 N-2 +1 channel is taken as a channel to be calibrated and the first channel and the 2 N-1 +1 channel which has completed calibration are taken as reference channels to perform calibration, the 3×2 N-2 +1 channel is taken as a channel to be calibrated and the 2 N-1 +1 channel and the first channel are taken as reference channels to perform calibration; and the process is repeated until calibration of all channels is completed.

6. A method for digital calibration of clock offset based on similar triangles according to any one of claims 1-5, characterized in that: The operation steps of the calibration method are as follows: S1, the entire circuit is powered on and reset, so that all register values in the calibration system are cleared; S2, the output digital code of the TI-ADC is subjected to offset mismatch calibration and gain mismatch calibration respectively, and the calibrated digital code is input into the clock deviation calibration module for final calibration; S3, the clock bias percentage detection module in the clock bias calibration module detects the clock bias percentage D between channels through the relationship between the correlation coefficients ΔT The clock bias percentage D calculated by the extraction is input into the error calculation module for error calculation ΔT The clock bias percentage D calculated by the extraction is input into the error calculation module for error calculation S4, the error value e to be compensated is calculated by the error calculation module based on the similar triangle, and the actual sampled output code is subtracted by the compensation value e to complete the clock deviation calibration of the TI-ADC.

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