Semiconductor structure and its preparation method

Abstract

This application relates to a semiconductor structure and its fabrication method. The semiconductor structure includes: a substrate; a stacked structure located on the substrate, including alternately stacked semiconductor doped layers and a first isolation layer, with semiconductor doped layers on both sides of the first isolation layer; a control gate structure extending from the stacked structure to the substrate, including a control gate dielectric layer and a control gate line, the control gate dielectric layer surrounding the control gate line; a floating gate structure located between adjacent semiconductor doped layers, including a tunneling layer and a floating gate, the floating gate surrounding the control gate structure, and the tunneling layer surrounding the floating gate; and a channel layer located between adjacent semiconductor doped layers, surrounding the tunneling layer and surrounded by the first isolation layer. Embodiments of this application can effectively improve the performance of flash memory devices.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Flash memory is a type of non-volatile memory, meaning data is not lost when power is off. It has advantages such as high read / write speeds and low power consumption. To improve device integration density and reduce manufacturing costs, 3D flash memory devices have emerged as a related technology.

[0003] However, the performance of existing flash memory devices still needs to be improved. Summary of the Invention

[0004] Based on this, embodiments of this application provide a semiconductor structure and its fabrication method to improve the performance of flash memory devices.

[0005] A semiconductor structure, comprising:

[0006] Base;

[0007] A stacked structure, located on the substrate, includes alternating stacked semiconductor doped layers and a first isolation layer, wherein the first isolation layer has the semiconductor doped layer on both sides along the stacking direction;

[0008] A control gate structure extending from the stacked structure to the substrate includes a control gate dielectric layer and control gate lines, wherein the control gate dielectric layer surrounds the control gate lines.

[0009] A floating gate structure, located between adjacent semiconductor doped layers, includes a tunneling layer and a floating gate, the floating gate surrounding the control gate structure, and the tunneling layer surrounding the floating gate;

[0010] The channel layer is located between adjacent semiconductor doped layers, surrounds the tunneling layer, and is enclosed by the first isolation layer.

[0011] In one embodiment, the control gate line has a protrusion extending between adjacent semiconductor doped layers in the portion opposite to the first isolation layer.

[0012] In one embodiment, the stacked structure has a non-stepped region and a stepped region, the stepped region exposing a portion of the upper surface of each of the semiconductor doped layers to form a stepped plane, and the control gate structure extending through the non-stepped region of the stacked structure.

[0013] In one embodiment, the semiconductor structure further includes a metal silicide and sidewalls, the metal silicide being located on the step plane and the sidewalls being located on the step sidewalls of the stacked structure.

[0014] In one embodiment, the semiconductor structure further includes a passivation layer, bit line plugs, and select line plugs. The passivation layer covers the stacked structure and the control gate structure. The bit line plugs and select line plugs penetrate the passivation layer and are alternately distributed on each of the semiconductor doped layers.

[0015] In one embodiment, the thickness of each of the semiconductor doped layers corresponding to the bit line plug increases sequentially from top to bottom, and / or the thickness of each of the semiconductor doped layers corresponding to the select line plug increases sequentially from top to bottom.

[0016] In one embodiment, the substrate includes a second isolation layer, and the stacked structure and the control gate structure are located on the second isolation layer.

[0017] A method for fabricating a semiconductor structure, comprising:

[0018] A substrate is provided, and a stacked material layer is formed on the substrate, the stacked material layer comprising alternating semiconductor doped material layers and a first isolation material layer, wherein the number of layers of the first isolation material layer is greater than or equal to 1, and the first isolation material layer has the semiconductor doped material layer on both sides along the stacking direction;

[0019] The stacked material layer is etched to form control gate wire holes that extend to the substrate;

[0020] The first isolation material layer of each layer is etched back through the control gate hole to form a surrounding groove around the control gate hole;

[0021] A channel layer and a floating gate structure are sequentially formed within the surrounding groove. The floating gate structure includes a tunneling layer and a floating gate, with the tunneling layer located between the floating gate and the channel layer.

[0022] A control gate structure is formed within the control gate wire hole. The control gate structure includes a control gate dielectric layer and control gate wires. The control gate dielectric layer is located on the sidewall of the control gate wire hole and surrounds the control gate wires.

[0023] In one embodiment, forming a control gate structure within the control gate wire hole includes:

[0024] The control gate structure is formed within the control gate wire hole and the surrounding groove.

[0025] In one embodiment, forming the control gate structure within the control gate wire hole and the surrounding groove includes:

[0026] A control gate dielectric layer is formed on the sidewall of the control gate via, the sidewall of the surrounding groove, and the surface of the floating gate.

[0027] A control gate line is formed on the surface of the control gate dielectric layer, and the control gate line fills the remaining control gate line holes and the remaining surrounding grooves.

[0028] In one embodiment, the stacked structure has a non-stepped region and a stepped region, and the control gate wire hole is formed in the non-stepped region.

[0029] After forming the control gate structure within the control gate wire hole, the method further includes:

[0030] The stacked material layers located in the step region are etched to form a stacked structure with steps in the step region. The remaining semiconductor doped material layers after etching form semiconductor doped layers, and the remaining first isolation material layers form first isolation layers. After etching, the step region exposes a portion of the upper surface of each semiconductor doped layer to form a step plane.

[0031] In one embodiment, after etching the stacked material layer located in the step region to form a stacked structure having steps in the step region, the process further includes:

[0032] Metal silicide is formed on the surface of the semiconductor doped layer exposed in the step region.

[0033] In one embodiment, forming a metal silicide on the surface of the semiconductor doped layer exposed in the step region includes:

[0034] A sidewall is formed on the sidewall of the step area;

[0035] Metal silicides are formed on the step plane.

[0036] In one embodiment, after forming a metal silicide on the surface of the semiconductor doped layer exposed in the step region, the method further includes:

[0037] A passivation material layer is formed covering the metal silicide, the stacked structure, and the control gate structure;

[0038] The passivation material layer is etched to form alternating bit line contact holes and select line contact holes that extend to each layer of metal silicide, and the remaining passivation material layer forms a passivation layer.

[0039] A bit line plug is formed in the bit line contact hole, and a select line plug is formed in the select line contact hole.

[0040] In one embodiment, the thickness of each of the semiconductor doped layers corresponding to the bit line plug increases sequentially from top to bottom, and / or the thickness of each of the semiconductor doped layers corresponding to the select line plug increases sequentially from top to bottom.

[0041] The aforementioned semiconductor structure and its fabrication method simultaneously form a channel layer and a floating gate structure between adjacent semiconductor doped layers. The portion of the control gate line opposite to the floating gate structure can form a memory cell with the floating gate structure and the channel layer. Simultaneously, the semiconductor doped layers on both sides of the channel layer are connected to the channel layer, thereby forming the source and drain of the memory cell, respectively. When the semiconductor structure has multiple channel layers to form multiple memory cells, adjacent memory cells in the stacking direction can share either the source or the drain.

[0042] Meanwhile, the source and drain of the same memory cell can be effectively isolated by the first isolation layer, thereby effectively preventing leakage between the source and drain and improving the performance of the flash memory device. Furthermore, when the semiconductor structure has multiple channel layers to form multiple memory cells, the sources (or drains) of adjacent memory cells can be effectively isolated by the two first isolation layers between them, thereby effectively preventing crosstalk between adjacent memory cells.

[0043] Simultaneously, by forming the channel layer and floating gate structure between adjacent semiconductor doped layers, effective isolation of the floating gate structure within the memory cell can be achieved, thereby improving device performance. Furthermore, when the semiconductor structure has multiple channel layers to form multiple memory cells, the charge storage nodes of adjacent memory cells can be effectively disconnected, further preventing crosstalk between adjacent memory cells and thus improving flash memory device performance. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0046] Figures 2 to 9 This is a schematic cross-sectional view of the structure obtained in each step of the fabrication process of the semiconductor structure provided in one embodiment, wherein, Figure 9 This is a schematic cross-sectional view of a semiconductor structure provided in one embodiment.

[0047] Explanation of reference numerals in the attached figures:

[0048] 100 - Substrate, 110 - Second isolation layer, 200 - Stacked structure, 210 - Semiconductor doped layer, 220 - First isolation layer, 201 - Stacked material layer, 211 - Semiconductor doped material layer, 221 - First isolation material layer, 300 - Channel layer, 301 - Channel material layer, 400 - Floating gate structure, 410 - Tunneling layer, 420 - Floating gate, 500 - Control gate structure, 510 - Control gate dielectric layer, 512 - Barrier layer, 511 - High dielectric constant layer, 520 - Control gate line, 521 - Bump, 600 - Metal silicide, 700 - Sidewall, 800 - Passivation layer, 910 - Bit line plug, 920 - Select line plug, 10 - Control gate line via, 20 - Surround groove. Detailed Implementation

[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] In one embodiment, see Figure 1 This invention provides a method for fabricating a semiconductor structure that can be used to fabricate flash memory devices. Flash memory devices may include, but are not limited to, NOR devices. For example, flash memory devices may also be NAND devices.

[0055] The method includes the following steps:

[0056] Step S10: A substrate 100 is provided, and a stacked material layer 201 is formed on the substrate 100. The stacked material layer 201 includes alternating semiconductor doped material layers 211 and first isolation material layers 221, wherein the number of layers of the first isolation material layer 221 is greater than or equal to 1, and the first isolation material layer 221 has semiconductor doped material layers 211 on both sides along the stacking direction. Please refer to [link to previous steps]. Figure 2 ;

[0057] Step S20: Etch the stacked material layer 201 to form a control gate via 10 penetrating to the substrate 100. (See also...) Figure 3 Figure (a) in the middle;

[0058] Step S30: The first isolation material layer 221 of each layer is etched back through the control gate hole 10 to form a surrounding groove 20 around the control gate hole 10. Please refer to [link to relevant documentation]. Figure 3 Figure (b) in the middle;

[0059] In step S40, a channel layer 300 and a floating gate structure 400 are sequentially formed within the surrounding trench 20. The floating gate structure 400 includes a tunneling layer 410 and a floating gate 420. The tunneling layer 410 is located between the floating gate 420 and the channel layer 300. Please refer to [link to relevant documentation]. Figure 5 ;

[0060] In step S50, a control gate structure 500 is sequentially formed within the control gate wire hole 10. The control gate structure 500 includes a control gate dielectric layer 510 and control gate wires 520. The control gate dielectric layer 510 is located on the sidewall of the control gate wire hole 10 and surrounds the control gate wires 520. Please refer to [link to relevant documentation]. Figure 6 .

[0061] In step S10, the substrate 100 may include a substrate (not shown). The substrate may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the substrate may include a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may also include Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrates.

[0062] Meanwhile, the substrate 100 can be a single-layer structure or a multi-layer structure. When the substrate 100 includes a multi-layer structure, it can include a substrate and other structures or films formed on the substrate.

[0063] For example, please refer to Figure 2 The substrate 100 may include a substrate (not shown) and a second isolation layer 110 formed on the substrate. A stacked material layer 201 may be formed on the second isolation layer 110, thereby effectively isolating the substrate from subsequently formed memory cells through the second isolation layer 110. The material of the second isolation layer 110 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0064] When forming a stacked material layer 201 on the substrate 100, a semiconductor doped material layer 211 and a first isolation material layer 221 can be repeatedly and alternately formed on the substrate 100 by a deposition process.

[0065] The deposition process may include, but is not limited to, one or more of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD).

[0066] As an example, both the top and bottom layers of the stacked material layer 201 can be semiconductor doped material layers 211.

[0067] Meanwhile, the material of the semiconductor doped material layer 211 may include, but is not limited to, polycrystalline silicon. The material of the first isolation material layer 221 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0068] In step S20, please refer to Figure 3 In Figure (a), a first patterned photoresist can first be formed on the stacked material layer 201. The first patterned photoresist has a first opening. The first opening can define the size and position of the control gate hole 10, etc. Then, based on the first patterned photoresist, the stacked material layer 201 is subjected to dry etching or the like to form the control gate hole 10. Afterwards, the first patterned photoresist can be removed.

[0069] It should be noted that, in order to make the graphics clear, Figures 3 to 9 The diagram only shows a partial cross-sectional view of the control gate hole 10 and related structures obtained during the semiconductor structure fabrication process.

[0070] In step S30, please refer to Figure 3 In Figure (b), the first isolation material layer 221 between the semiconductor doped material layer 211 can be etched back by the control gate hole 10 through wet etching or the like, thereby forming a surrounding groove 20 around the control gate hole 10.

[0071] In step S40, a channel layer 300 is first formed within the surrounding trench 20. The channel layer 300 is made of a semiconductor material, which may be the same as or different from the material of the semiconductor doped material layer 211.

[0072] Please see Figure 4When forming the channel layer 300, homogeneous epitaxial growth can be performed on the surface of the semiconductor doped material layer 211 exposed by the self-controlled gate hole 10 and the surrounding trench 20, thereby forming a channel material layer 301 with the same material as the semiconductor doped material layer 211. For example, when the material of the semiconductor doped material layer 211 is polysilicon, the channel material layer 301 can be a semiconductor silicon layer.

[0073] Alternatively, when forming the channel layer 300, heteroepitaxial growth can be performed on the surface of the semiconductor doped material layer 211 exposed by the control gate hole 10 and the surrounding trench 20 to form a channel material layer 301 with a material different from that of the semiconductor doped material layer 211. For example, when the material of the semiconductor doped material layer 211 is polysilicon, the channel material layer 301 can be a semiconductor germanium silicon layer, etc.

[0074] After epitaxial growth, the channel material layer 301 can fill the surrounding trench 20 and cover the sidewalls of the control gate via 10. Simultaneously, the channel material layer 301 can also be located on the upper surface of the top semiconductor doped material layer 211 (not shown).

[0075] Subsequently, the channel material layer 301 located on the upper surface of the top semiconductor doped material layer 211, the channel material layer 301 located on the sidewall of the control gate via 10, and a portion of the channel material layer 301 located within the surrounding trench 20 can be etched away together. After etching, the remaining channel material layer 301 within the surrounding trench 20 forms the channel layer 300.

[0076] By using epitaxial growth, a channel layer 300 with the same or similar structure as the semiconductor doped material layer 211 can be effectively formed, thereby effectively reducing the contact resistance between the two. Of course, the channel layer 300 can also be formed by other methods. For example, the channel material layer 301 can be formed by chemical vapor deposition or atomic layer deposition, and then the channel material layer 301 outside the surrounding trench 20 and part of the channel material layer 301 inside the surrounding trench 20 can be removed by wet etching or other processes to form the channel layer 300.

[0077] Please see Figure 5 After the channel layer 300 is formed, a tunneling layer 410 and a floating gate 420 can be formed sequentially on the sidewall of the channel layer 300 in the surrounding groove 20, thereby forming a floating gate structure 400.

[0078] When forming the tunneling layer 410, a tunneling material layer can first be formed by a deposition process to fill the surrounding trench 20 and cover the sidewalls of the control gate via 10, the bottom of the control gate via 10, and the upper surface of the top semiconductor doped material layer 211. Then, the tunneling material layer outside the surrounding trench 20 and a portion of the tunneling material layer inside the surrounding trench 20 can be removed by processes such as wet etching to form the tunneling layer 410.

[0079] The material of the tunneling layer 410 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0080] When forming the floating gate 420, a floating gate material layer can first be formed by deposition, filling the surrounding trench 20 and covering the sidewalls of the control gate via 10, the bottom of the control gate via 10, and the upper surface of the top semiconductor doped material layer 211. Then, the floating gate material layer outside the surrounding trench 20 and a portion of the floating gate material layer inside the surrounding trench 20 can be removed by processes such as wet etching to form the floating gate 420. At this point, after forming the floating gate 420, the surrounding trench 20 is not completely filled.

[0081] Of course, after the floating gate 420 is formed, the surrounding trench 20 can also be filled. In this case, after the floating gate material layer is formed by the deposition process, the floating gate material layer located outside the surrounding trench 20 can be removed by processes such as wet etching, thereby forming the floating gate 420 that fills the surrounding trench 20. Here, the degree of filling of the floating gate structure 400 in the surrounding trench 20 is not limited.

[0082] The material of the floating gate 420 can be, but is not limited to, metallic materials such as Co, Ni, Ti, W, Cu, and Al. The floating gate structure 400 can store charge through the floating gate 420.

[0083] In step S50, please refer to Figure 6 When forming the control gate structure 500, the control gate dielectric layer 510 can be formed first, and then the control gate line 520 can be formed.

[0084] The control gate dielectric layer 510 can be a single-layer structure or a multi-layer structure.

[0085] The material of the control gate line 520 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0086] The portion of the control gate line 520 opposite to the floating gate structure 400 can form a memory cell with the floating gate structure 400 within the surrounding trench 20 and the channel layer 300. Simultaneously, the semiconductor doped material layers 211 on both sides of the channel layer 300 along the stacking direction are connected to the channel layer 300, thereby forming the source and drain of the memory cell respectively. In this case, adjacent memory cells in the stacking direction can share either the source or the drain.

[0087] In this embodiment, the channel layer 300 can form a memory cell with the floating gate structure 400 and the control gate line 520. Simultaneously, the source and drain of the same memory cell can be effectively isolated by the first isolation material layer 221, thereby effectively preventing leakage between the source and drain and improving the performance of the flash memory device. Furthermore, when multiple channel layers are formed by forming multiple first isolation material layers, a three-dimensional stacked multilayer memory cell can be formed. The sources (or drains) of adjacent memory cells can be effectively isolated by the two first isolation material layers 221 between them, thereby effectively preventing crosstalk between adjacent memory cells.

[0088] Furthermore, by simultaneously forming the channel layer 300 and the floating gate structure 400 within the surrounding groove 20 formed by etching back the first isolation material layer 221, effective isolation of the floating gate structure 400 within the memory cell can be achieved, thereby improving device performance. Moreover, when multiple channel layers are formed by forming multiple first isolation material layers 221, and a three-dimensionally stacked multilayer memory cell is thus formed, the charge storage nodes of adjacent memory cells can be effectively disconnected, thereby more effectively preventing crosstalk between adjacent memory cells.

[0089] In one embodiment, step S50 may include:

[0090] Step S51: A control grid structure 520 is formed in the control grid wire hole 10 and the surrounding groove 20.

[0091] The surrounding trench 20 can be filled after the control gate dielectric layer 510 of the control gate structure 520 is formed, or it can be filled after the control gate line 520 of the control gate structure 520 is formed. However, before the control gate structure 520 is formed, that is, after the floating gate 420 is formed, the surrounding trench 20 may not be filled. This allows the floating gate material layer outside the surrounding trench 20 to be removed during the formation of the floating gate 420, reducing the difficulty of etching the floating gate material layer.

[0092] In one embodiment, see Figure 6 Step S51 includes:

[0093] Step S511: A control gate dielectric layer 510 is formed on the sidewall of the control gate via 10, the sidewall of the surrounding groove 20, and the surface of the floating gate 420.

[0094] In step S512, a control gate line 520 is formed on the surface of the control gate dielectric layer 510 to fill the remaining space of the control gate line hole 10 and the remaining space of the surrounding groove 20. The control gate line 520 fills the remaining control gate line hole 10 and the remaining surrounding groove 20.

[0095] In step S511, when forming the control gate dielectric layer 510, a control gate dielectric material layer (not shown) can first be formed on the surface of the floating gate 420, the sidewall of the surrounding trench 20, the sidewall of the control gate via 10, the bottom of the control gate via 10, and the upper surface of the top semiconductor doped material layer 211. Then, the control gate dielectric material layer located at the bottom of the control gate via 10 and the control gate dielectric material layer located on the upper surface of the top semiconductor doped material layer 211 can be removed by processes such as dry etching, thereby forming the control gate dielectric layer 510. After the control gate dielectric layer 510 is formed, the surrounding trench 20 is not completely filled.

[0096] As an example, the control gate dielectric material layer may include a high dielectric constant material layer and a barrier material layer. Accordingly, the control gate dielectric layer 510 may include a high dielectric constant layer 511 formed based on the high dielectric constant material layer and a barrier layer 512 formed based on the barrier material layer.

[0097] The high dielectric constant layer 511 can be made of materials including, but not limited to, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). The barrier layer 512 can be made of materials including, but not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). The barrier layer 512 can be used to prevent charge diffusion from the control gate line 520 to the floating gate 420.

[0098] In step S512, when forming the control gate line 520, a control gate material layer (not shown) can first be formed inside the control gate hole 10 and on the upper surface of the top semiconductor doped material layer 211. Then, the control gate material layer located on the upper surface of the top semiconductor doped material layer 211 is removed by a chemical mechanical polishing (CMP) process, thereby forming the control gate line 520.

[0099] At this point, the control gate line 520 can fill the remaining space of the control gate line hole 10 and surround the remaining space of the slot 20. Therefore, the control gate line 520 has a protrusion 521 extending between adjacent semiconductor doped layers in the portion opposite to the first isolation material layer 221.

[0100] Each bump 521 of the control gate line 520 can serve as the control gate of each memory cell, thereby increasing the effective length of the control gate line 520 and thus improving the gate control capability.

[0101] In one embodiment, the stacked structure 200 has a non-stepped region and a stepped region, and the control grid hole 10 is formed in the non-stepped region.

[0102] After step S50, the following is also included:

[0103] For step S60, please refer to... Figure 7 The stacked material layer 201 located in the step region is etched to form a stacked structure 200 with steps in the step region. After etching, the remaining semiconductor doped material layer 211 forms a semiconductor doped layer 210, and the remaining first isolation material layer 221 forms a first isolation layer 220. After etching, the step region exposes part of the upper surface of each semiconductor doped layer 210 to form a step plane.

[0104] At this point, the semiconductor doped material layer 211 and the first isolation material layer 221 located in the step region can be etched sequentially from top to bottom using photolithography to form multiple steps.

[0105] When forming each step, a second patterned photoresist layer can be formed first; then, a semiconductor doped material layer 211 is etched based on the second patterned photoresist to form the semiconductor doped layer 210 of that step. Next, a first isolation material layer 221 is etched based on the second patterned photoresist and the semiconductor doped layer 210 of that step to form the first isolation layer 220 of that step. Then, the second patterned photoresist is removed.

[0106] When the bottom layer of the stacked material layers is a semiconductor doped material layer 211, the last step can be formed after etching the semiconductor doped material layer 211, that is, after forming the bottommost step.

[0107] Understandably, during the formation of each step, when forming a step that is not at the top layer, the second patterned photoresist can cover the non-step area and the previously formed upper step, thereby protecting the upper step.

[0108] At this point, due to the significant material difference between the semiconductor doped material layer 211 and the first isolation material layer 221, they can act as etching stop layers for each other during the etching process to form multiple steps. When etching the semiconductor doped material layer 211, the first isolation material layer 221 located below it serves as the etching stop layer, and vice versa. This effectively ensures the etching stop position and prevents over-etching. Therefore, the step plane can be effectively positioned on the semiconductor doped layer 210 at this time.

[0109] In one embodiment, after step S60, the method further includes:

[0110] For step S70, please refer to... Figure 8 Metal silicide 600 is formed on the surface of the semiconductor doped layer 210 exposed in the step region.

[0111] Metal silicide 600 can effectively reduce the contact resistance between the semiconductor doped layer 210 and the subsequently formed bit line plugs and select line plugs.

[0112] As an example, step S70 may include:

[0113] Step S71: Form a sidewall 700 on the sidewall of the step area;

[0114] Step S72, metal silicide 600 is formed on the step plane.

[0115] In step S71, a sidewall material layer (not shown) can be formed on the surface of the structure obtained in the previous step by a deposition process such as atomic layer deposition or chemical vapor deposition. Then, the sidewall material layer on the horizontal plane is removed by anisotropic etching such as dry etching, that is, the sidewall material layers on the upper surface of the structure and on the step plane are removed, thereby forming the sidewall 700 on the sidewall of the step.

[0116] The material of the sidewall 700 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0117] After the sidewall 700 is formed on the step sidewall, only the semiconductor doped layer 210 located on the step plane is exposed.

[0118] In step S72, a metal material layer can be formed on the surface of the structure after the sidewall 700 is formed by physical vapor deposition (such as magnetron sputtering) to cover each step plane. Then, the structure with the metal material layer is thermally annealed, causing the metal atoms in the metal material layer to diffuse with the silicon atoms in the semiconductor doped layer 210, thereby forming a metal silicide 600. Afterwards, any remaining unreacted metal material layer can be removed.

[0119] At this point, by first forming the sidewalls 700, the metal silicide 600 is formed only on the step plane, which can more effectively prevent leakage between adjacent semiconductor doped layers 210.

[0120] Of course, since the adjacent semiconductor doped layers 210 located in the step region are isolated by the first isolation layer 220, in some examples, the sidewalls 700 may not be formed before the metal silicide 600 is formed, and this is not a limitation.

[0121] In one embodiment, see Figure 9 After step S70, the following steps are also included:

[0122] Step S81: A passivation material layer covering the metal silicide 600, the stacked structure 200, and the control gate structure 500 is formed.

[0123] Step S82: Etch the passivation material layer to form bit line contact holes and select line contact holes that are alternately arranged and extend to each layer of metal silicide 600. The remaining passivation material layer forms the passivation layer 800.

[0124] In step S83, a bit line plug 910 is formed in the bit line contact hole, and a select line plug 920 is formed in the select line contact hole.

[0125] In step S81, a passivation material layer can be formed by a deposition process. The material of the passivation material layer may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0126] In step S82, a third patterned photoresist can first be formed on the surface of the passivation material layer. The third patterned photoresist has multiple third openings. Each third opening can be positioned opposite to a step plane.

[0127] Then, based on a third patterned photoresist, a passivation material layer is etched to form a plurality of vias extending onto the metal silicide 600 located on each step plane. These vias include alternating bit line contact holes and select line contact holes.

[0128] After etching the passivation material layer, the remaining passivation material layer forms the passivation layer 800.

[0129] In step S83, a conductive material layer can be formed on the surface of the bit line contact hole, the select line contact hole, and the passivation material layer by processes such as magnetron sputtering, electroplating, or chemical vapor deposition.

[0130] The materials of the conductive material layer may include, but are not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0131] Then, the conductive material layer on the upper surface of the passivation material layer can be removed by methods such as chemical mechanical polishing (CMP). The remaining conductive material layer located in the bit line contact hole forms the bit line plug 910, and the conductive material layer located in the select line contact hole forms the select line plug 920.

[0132] As an example, in step S82, while etching the passivation material layer to form bit line contact holes and select line contact holes, word line interconnect holes extending to the control gate line 520 can also be formed. In step S83, while forming bit line plugs 910 and select line plugs 920, word line plugs 930 filling the word line interconnect holes can also be formed.

[0133] Bit line plug 910 and select line plug 920 can be connected to the bit line and select line of a certain routing layer, respectively, and word line plug 930 can be connected to the word line of another routing layer.

[0134] At this point, each layer of memory cells can be connected to the bit line via the bit line plug 910, which facilitates the formation of a 3D NOR device.

[0135] Meanwhile, when a stacked structure 200 with steps is formed in the step region, the passivation layer 800 fills the area of ​​the step region that has been etched away, thereby allowing the bit line plug 910 and the select line plug 920 to be formed within the passivation layer 800. At this time, the passivation layer 800 can effectively isolate the bit line plugs 910 from each other, the select line plugs 920 from each other, and the bit line plugs 910 and the select line plugs 920 from each other.

[0136] Of course, in other embodiments, a stacked structure 200 without steps can also be formed.

[0137] At this point, for example, after forming the control gate line 520 in step S50, the stacked material layer 201 can be etched to form bit line contact holes and select line contact holes that penetrate to each semiconductor doped material layer 211. The remaining stacked material layer 201 after etching forms the stacked structure 200. Among them, the remaining semiconductor doped material layer 211 forms the semiconductor doped layer 210, and the remaining first isolation material layer 221 forms the first isolation layer 220.

[0138] Next, an oxide or other sidewall protective layer is formed on the sidewalls of the bit line contact hole and the select line contact hole. Then, metal silicide is formed at the bottom of the bit line contact hole and the select line contact hole. Finally, bit line plugs 910 and select line plugs 920 are filled into the bit line contact hole and select line contact hole, respectively.

[0139] In one embodiment, see Figure 9 The thickness of each semiconductor doped layer 210 corresponding to the bit line plug 910 increases sequentially from top to bottom, and / or the thickness of each semiconductor doped layer 210 corresponding to the select line plug 920 increases sequentially from top to bottom.

[0140] The lower the number of semiconductor doped layers 210 corresponding to the bit line plug 910, the closer it is to the substrate, and the longer the bit line plug 910 is, the greater the resistance of the bit line plug 910.

[0141] At this time, the thickness of each semiconductor doped layer 210 corresponding to the bit line plug 910 is increased from top to bottom, so that the semiconductor doped layer 210 with a lower number of layers has a larger cross-sectional area for transmitting current, and thus the semiconductor doped layer 210 with a lower number of layers has a lower resistance, which can compensate for the resistance difference between each bit line plug 910.

[0142] Meanwhile, the lower the number of semiconductor doped layers 210 corresponding to the select line plug 920, the longer the select line plug 920 is, resulting in a higher resistance of the select line plug 920.

[0143] At this time, the thickness of each semiconductor doped layer 210 corresponding to the selection line plug 920 is increased from top to bottom, so that the semiconductor doped layer 210 with a lower number of layers has a larger cross-sectional area for transmitting current, and thus the semiconductor doped layer 210 with a lower number of layers has a lower resistance, which can compensate for the resistance difference between each selection line plug 920.

[0144] Furthermore, as an example, when the thickness of each semiconductor doped layer 210 connected by the bit line plug 910 increases sequentially from top to bottom, and the thickness of each semiconductor doped layer 210 connected by the selection line plug 920 also increases sequentially from top to bottom, it is also possible to configure all semiconductor doped layers 210 in the stacked structure 200 to group every two semiconductor doped layers 210 from top to bottom (or from bottom to top), and the semiconductor doped layers 210 in the same group have the same thickness. Of course, in other examples, the thickness of the semiconductor doped layers 210 in the same group can also be different. For example, it is also possible to configure all semiconductor doped layers 210 in the stacked structure 200 to have the thickness of each semiconductor doped layer 210 increase sequentially from top to bottom.

[0145] In other embodiments, the diameters of the bit line contact holes corresponding to the different semiconductor doped layers 210 from top to bottom can be gradually increased, thereby increasing the diameter of the bit line plugs 910 corresponding to the different semiconductor doped layers 210 from top to bottom, and thus compensating for the resistance difference between each bit line plug 910. And / or, the diameters of the select line contact holes corresponding to the different semiconductor doped layers 210 from top to bottom can be gradually increased, thereby increasing the diameter of the select line plugs 920 corresponding to the different semiconductor doped layers 210 from top to bottom, and thus compensating for the resistance difference between each select line plug 920.

[0146] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0147] In one embodiment, a semiconductor structure is also provided, which can be used to fabricate a flash memory device. The flash memory device may include, but is not limited to, a NOR device. For example, the flash memory device may also be a NAND device.

[0148] Please see Figure 9 The semiconductor structure includes a substrate 100, a stacked structure 200, a control gate structure 500, a floating gate structure 400, and a channel layer 300.

[0149] The substrate 100 may include a substrate. The substrate may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, the substrate may include a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, the substrate may also include Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrates.

[0150] Meanwhile, the substrate 100 can be a single-layer structure or a multi-layer structure. When the substrate 100 includes a multi-layer structure, it can include a substrate and other structures or films formed on the substrate.

[0151] The stacked structure 200 is located on the substrate 100 and includes alternating stacked semiconductor doped layers 210 and a first isolation layer 220. The first isolation layer 220 has a number of layers greater than or equal to 1, and both sides of the first isolation layer 220 have semiconductor doped layers 210.

[0152] The material of the semiconductor doped layer 210 may include, but is not limited to, polycrystalline silicon. The material of the first isolation layer 220 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0153] The control gate structure 500 includes a control gate dielectric layer 510 and a control gate line 520, both of which are extended through the stacked structure 200 to the substrate 100.

[0154] The material of the control gate line 520 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0155] The control gate dielectric layer 510 surrounds the control gate line 520. The control gate dielectric layer 510 can be a single-layer structure or a multi-layer structure.

[0156] The floating gate structure 400 includes a tunneling layer 410 and a floating gate 420.

[0157] A floating gate 420 is located between adjacent semiconductor doped layers 210, surrounding the control gate structure 500. The material of the floating gate 420 can be, but is not limited to, metallic materials such as Co, Ni, Ti, W, Cu, and Al. The floating gate structure 400 can store charge through the floating gate 420.

[0158] The tunneling layer 410 is located between adjacent semiconductor doped layers 210 and surrounds the floating gate 420. The material of the tunneling layer 410 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0159] The channel layer 300 is located between adjacent semiconductor doped layers 210, surrounded by the first isolation layer 220, and surrounds the tunnel layer 410.

[0160] The material of the channel layer 300 can be the same as or different from the material of the semiconductor doped layer 210. For example, when the material of the semiconductor doped layer 210 is polysilicon, the channel layer 300 can be a semiconductor silicon layer or a semiconductor germanium silicon layer, etc.

[0161] In this embodiment, the portion of the control gate line 520 opposite to the floating gate structure 400 can form a memory cell with the floating gate structure 400 and the channel layer 300. Simultaneously, the semiconductor doped layers 210 on both sides of the channel layer 300 are connected to the channel layer 300, thereby forming the source and drain of the memory cell, respectively. When the semiconductor structure has multiple channel layers 300 to form multiple memory cells, adjacent memory cells in the stacking direction can share a source or drain.

[0162] Meanwhile, the source and drain of the same memory cell can be effectively isolated by the first isolation layer 220, thereby effectively preventing leakage between the source and drain and improving the performance of the flash memory device. Furthermore, when the semiconductor structure has multiple channel layers 300 to form multiple memory cells, the sources (or drains) of adjacent memory cells can be effectively isolated by the two first isolation layers 220 between them, thereby effectively preventing crosstalk between adjacent memory cells.

[0163] Furthermore, by simultaneously forming the channel layer 300 and the floating gate structure 400 between adjacent semiconductor doped layers 210, effective isolation of the floating gate structure 400 within the memory cell can be achieved, thereby improving device performance. Moreover, when a semiconductor structure has multiple channel layers 300 to form multiple memory cells, the charge storage nodes of adjacent memory cells can be effectively disconnected, further preventing crosstalk between adjacent memory cells.

[0164] In one embodiment, the control gate line 520 has a protrusion 521 extending between adjacent semiconductor doped layers in the portion opposite to the first isolation layer 221.

[0165] Each bump 521 of the control gate line 520 can serve as the control gate of each memory cell, thereby increasing the effective length of the control gate line 520 and thus improving the gate control capability.

[0166] In one embodiment, the stacked structure 200 has a non-stepped region and a stepped region, the stepped region exposing a portion of the upper surface of each semiconductor doped layer 210 to form a stepped plane, and the control gate structure 500 penetrates the stacked structure 200 through the non-stepped region.

[0167] In one embodiment, the semiconductor structure further includes a metal silicide 600 and a sidewall 700, the metal silicide 600 being located on a step plane and the sidewall 700 being located on the step sidewall of the stacked structure 200.

[0168] The material of the sidewall 700 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0169] The sidewall 700 can more effectively prevent leakage between adjacent semiconductor doped layers 210.

[0170] In one embodiment, the semiconductor structure further includes a passivation layer 800, a bit line plug 910, and a select line plug 920.

[0171] The passivation layer 800 covers the stacked structure 200 and the control gate structure 500. The material of the passivation layer 800 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). Bit line plugs 910 and select line plugs 920 penetrate the passivation layer 800 and are alternately distributed on each semiconductor doped layer 210.

[0172] When the stacked structure has steps, and the step plane has metal silicide 600, and the step sidewalls have sidewalls 700, the passivation layer 800 also covers the metal silicide 600 and the sidewalls 700. Furthermore, bit line plugs 910 and select line plugs 920 can be alternately distributed on each layer of metal silicide 600. Of course, the stacked structure may also not have steps.

[0173] Bit line plug 910 can be connected to a bit line. The material of bit line plug 910 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).

[0174] Select line plug 920 can be connected to a select line. The material of select line plug 920 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). As an example, the material of select line plug 920 may be the same as that of bit line plug 910.

[0175] At this point, each layer of memory cells can be connected to the bit line via the bit line plug 910, thus facilitating the formation of a 3D NOR device. Simultaneously, the passivation layer 800 can effectively isolate the bit line plugs 910 from each other, the select line plugs 920 from each other, and the bit line plugs 910 from each other.

[0176] In one embodiment, the thickness of each semiconductor doped layer 210 corresponding to the bit line plug 910 increases sequentially from top to bottom, and / or, the thickness of each semiconductor doped layer 210 corresponding to the select line plug 920 increases sequentially from top to bottom.

[0177] The lower the number of semiconductor doped layers 210 corresponding to the bit line plug 910, the longer the bit line plug 910 is, resulting in a higher resistance of the bit line plug 910.

[0178] At this time, the thickness of each semiconductor doped layer 210 corresponding to the bit line plug 910 is increased from top to bottom, so that the semiconductor doped layer 210 with a lower number of layers has a larger cross-sectional area for transmitting current, and thus the semiconductor doped layer 210 with a lower number of layers has a lower resistance, which can compensate for the resistance difference between each bit line plug 910.

[0179] Meanwhile, the lower the number of semiconductor doped layers 210 corresponding to the select line plug 920, the longer the select line plug 920 is, resulting in a higher resistance of the select line plug 920.

[0180] At this time, the thickness of each semiconductor doped layer 210 corresponding to the selection line plug 920 is increased from top to bottom, so that the semiconductor doped layer 210 with a lower number of layers has a larger cross-sectional area for transmitting current, and thus the semiconductor doped layer 210 with a lower number of layers has a lower resistance, which can compensate for the resistance difference between each selection line plug 920.

[0181] Furthermore, as an example, when the thickness of each semiconductor doped layer 210 connected by the bit line plug 910 increases sequentially from top to bottom, and the thickness of each semiconductor doped layer 210 connected by the selection line plug 920 also increases sequentially from top to bottom, it is also possible to configure all semiconductor doped layers 210 in the stacked structure 200 to group every two semiconductor doped layers 210 from top to bottom (or from bottom to top), and the semiconductor doped layers 210 in the same group have the same thickness. Of course, in other examples, the thickness of the semiconductor doped layers 210 in the same group can also be different. For example, it is also possible to configure all semiconductor doped layers 210 in the stacked structure 200 to have the thickness of each semiconductor doped layer 210 increase sequentially from top to bottom.

[0182] In one embodiment, the substrate 100 includes a second isolation layer 110. The material of the second isolation layer 110 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON). The material of the second isolation layer 110 may be the same as or different from the material of the first isolation layer 220.

[0183] As an example, the substrate 100 may also include a substrate on which the second isolation layer 110 may be located. The stacked structure 200 and the control gate structure 500 are located on the second isolation layer 110, thereby effectively isolating the substrate from the memory cells through the second isolation layer 110.

[0184] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0185] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A stacked structure, located on the substrate, includes alternating stacked semiconductor doped layers and a first isolation layer, wherein the first isolation layer has the semiconductor doped layer on both sides along the stacking direction; A control gate structure extending from the stacked structure to the substrate includes a control gate dielectric layer and a control gate line, the control gate dielectric layer surrounding the control gate line, and the control gate line having a protrusion extending between adjacent semiconductor doped layers in a portion opposite to the first isolation layer. A floating gate structure, located between adjacent semiconductor doped layers, includes a tunneling layer and a floating gate, the floating gate surrounding the control gate structure, and the tunneling layer surrounding the floating gate; The channel layer is located between adjacent semiconductor doped layers, surrounds the tunneling layer, and is enclosed by the first isolation layer.

2. The semiconductor structure according to claim 1, characterized in that, The stacked structure has a non-stepped region and a stepped region. The stepped region exposes a portion of the upper surface of each of the semiconductor doped layers to form a stepped plane. The control gate structure penetrates the stacked structure through the non-stepped region.

3. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure further includes a metal silicide and sidewalls, the metal silicide being located on the step plane and the sidewalls being located on the step sidewalls of the stacked structure.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a passivation layer, bit line plugs, and select line plugs. The passivation layer covers the stacked structure and the control gate structure. The bit line plugs and select line plugs penetrate the passivation layer and are alternately distributed on each of the semiconductor doped layers.

5. The semiconductor structure according to claim 4, characterized in that, The thickness of each semiconductor doped layer corresponding to the bit line plug increases sequentially from top to bottom, and / or the thickness of each semiconductor doped layer corresponding to the select line plug increases sequentially from top to bottom.

6. The semiconductor structure according to claim 1, characterized in that, The substrate includes a second isolation layer, and the stacked structure and the control gate structure are located on the second isolation layer.

7. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a stacked material layer is formed on the substrate, the stacked material layer comprising alternating semiconductor doped material layers and a first isolation material layer, wherein the number of layers of the first isolation material layer is greater than or equal to 1, and the first isolation material layer has the semiconductor doped material layer on both sides along the stacking direction; The stacked material layer is etched to form control gate wire holes that extend to the substrate; The first isolation material layer of each layer is etched back through the control gate hole to form a surrounding groove around the control gate hole; A channel layer and a floating gate structure are sequentially formed within the surrounding groove. The floating gate structure includes a tunneling layer and a floating gate, with the tunneling layer located between the floating gate and the channel layer. A control gate structure is formed within the control gate wire hole. The control gate structure includes a control gate dielectric layer and control gate wires. The control gate dielectric layer is located on the sidewall of the control gate wire hole and surrounds the control gate wires.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The process of forming a control gate structure within the control gate wire hole includes: The control gate structure is formed within the control gate wire hole and the surrounding groove.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The process of forming the control gate structure within the control gate wire hole and the surrounding groove includes: A control gate dielectric layer is formed on the sidewall of the control gate via, the sidewall of the surrounding groove, and the surface of the floating gate. A control gate line is formed on the surface of the control gate dielectric layer, and the control gate line fills the remaining control gate line holes and the remaining surrounding grooves.

10. The method for preparing a semiconductor structure according to claim 7, characterized in that, The stacked structure has a non-stepped region and a stepped region, and the control gate wire hole is formed in the non-stepped region. After forming the control gate structure within the control gate wire hole, the method further includes: The stacked material layers located in the step region are etched to form a stacked structure with steps in the step region. The remaining semiconductor doped material layers after etching form semiconductor doped layers, and the remaining first isolation material layers form first isolation layers. After etching, the step region exposes a portion of the upper surface of each semiconductor doped layer to form a step plane.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, After etching the stacked material layer located in the stepped region to form a stacked structure having steps in the stepped region, the process further includes: Metal silicide is formed on the surface of the semiconductor doped layer exposed in the step region.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The formation of a metal silicide on the surface of the semiconductor doped layer exposed in the step region includes: A sidewall is formed on the sidewall of the step area; Metal silicides are formed on the step plane.

13. The method for preparing a semiconductor structure according to claim 11, characterized in that, After forming a metal silicide on the surface of the semiconductor doped layer exposed in the step region, the method further includes: A passivation material layer is formed covering the metal silicide, the stacked structure, and the control gate structure; The passivation material layer is etched to form alternating bit line contact holes and select line contact holes that extend to each layer of metal silicide, and the remaining passivation material layer forms a passivation layer. A bit line plug is formed in the bit line contact hole, and a select line plug is formed in the select line contact hole.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The thickness of each semiconductor doped layer corresponding to the bit line plug increases sequentially from top to bottom, and / or the thickness of each semiconductor doped layer corresponding to the select line plug increases sequentially from top to bottom.

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