Semiconductor device structure and forming method thereof

Abstract

The invention relates to the field of semiconductor device design and manufacturing, in particular to a semiconductor device structure and a forming method thereof. The method comprises the following steps: forming an injection mask on an epitaxial layer of a substrate, and respectively forming an N + region, a P well region, a P + region and a JFET region on the injection mask; forming a gate oxide layer; forming a polycrystalline silicon carbide film layer; performing P-type doping on the polycrystalline silicon carbide film layer; and carrying out patterning on the polycrystalline silicon carbide film layer after P-type doping so as to form a gate electrode. Compared with P-type polycrystalline silicon, the semiconductor device structure based on the P-type polycrystalline silicon carbide gate material can further improve threshold voltage, and other key characteristics such as on resistance are not sacrificed.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device design and manufacturing, and in particular to a semiconductor device structure and a method for forming the same. Background Art

[0002] Compared with silicon-based IGBTs, the threshold voltage of silicon carbide (SiC) MOSFET devices is relatively low, especially planar SiC MOSFET devices, and the typical threshold voltage of commercial products is usually 2-3 V. Too low a threshold voltage will bring hidden dangers at the application level such as false start-up.

[0003] N-type polysilicon is the most commonly used gate material for MOSFET devices. Using P-type polysilicon can increase the threshold voltage by 0.5-1V. However, it is expected that the threshold voltage can be further increased compared to P-type polysilicon. Summary of the invention

[0004] In order to solve the above problems in the prior art, the present application provides a semiconductor device structure and a method for forming the same.

[0005] In a first aspect, the present application provides a method for forming a semiconductor device structure, the method comprising:

[0006] An implantation mask is formed on the epitaxial layer of the substrate, and an N+ region, a P well region, a P+ region and a JFET region are respectively formed on the implantation mask;

[0007] forming a gate oxide layer;

[0008] forming a polycrystalline silicon carbide film layer;

[0009] Performing P-type doping on the polycrystalline silicon carbide film layer;

[0010] The P-type doped polycrystalline silicon carbide film layer is patterned to form a gate electrode.

[0011] In a possible implementation of the first aspect, the method further includes:

[0012] forming a dielectric layer on the gate electrode;

[0013] Removing part of the dielectric layer to form sidewall structures on both sides of the gate electrode;

[0014] An alloy layer is formed on the gate electrode and the source region of the semiconductor device structure by utilizing the spacer structure.

[0015] In a possible implementation of the first aspect above, a CVD process is used to form the polycrystalline silicon carbide film layer.

[0016] In a possible implementation of the first aspect, the P-type doping is performed by in-situ doping in a CVD process or P-type ion implantation.

[0017] In a possible implementation of the first aspect above, a dry etching process is used to perform the patterning.

[0018] In a possible implementation of the first aspect, the dielectric layer is a silicon dioxide dielectric layer, and the thickness of the silicon dioxide dielectric layer is

[0019] In a possible implementation of the first aspect above, an isotropic etching process is used to form the sidewall structure.

[0020] In a possible implementation of the first aspect above, the alloy layer is a silicon carbide-nickel alloy layer, and a nickel secondary annealing process is used to form the silicon carbide-nickel alloy layer.

[0021] In a possible implementation of the first aspect, the method further includes:

[0022] An insulating dielectric layer and a source metal are formed.

[0023] In a second aspect, the present application further provides a semiconductor device structure, which is formed according to the method of the first aspect.

[0024] Compared with P-type polysilicon, the semiconductor device structure based on P-type polycrystalline silicon carbide gate material of the present application can further increase the threshold voltage without sacrificing the on-resistance (R dson ) and other key features. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The energy band structure diagram of a SiC MOSFET device based on a P-type polysilicon gate material according to the prior art is shown;

[0026] Figure 2 An energy band structure diagram of a SiC MOSFET device based on a P-type polycrystalline silicon carbide gate material according to some embodiments of the present application is shown;

[0027] Figure 3 A flow chart showing a method for forming a semiconductor device structure according to some embodiments of the present application;

[0028] Figures 4a to 4d A schematic diagram showing a process flow of a semiconductor device structure according to some embodiments of the present application;

[0029] Figure 5 Another flow chart showing a method for forming a semiconductor device structure according to some embodiments of the present application;

[0030] Figure 6a to Figure 6g Another schematic diagram showing a process flow of a semiconductor device structure according to some embodiments of the present application;

[0031] Figure 7 The diagram shows the TCAD (Tool for Circuit / Device Simulation) simulation results of the semiconductor device structure according to some embodiments of the present application. DETAILED DESCRIPTION

[0032] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0033] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0034] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0035] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0036] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0037] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0038] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0039] Figure 1 The energy band structure diagram of a SiC MOSFET device based on a P-type polysilicon gate material (P-Type Polysilicon Gate) according to the prior art is shown.

[0040] like Figure 1 As shown, the Fermi level of heavily doped N-type polysilicon is approximately equal to the conduction band bottom E C The Fermi level of P-type polysilicon is close to the valence band top E V , which is about 1eV lower than the Fermi level of N-type polysilicon. The threshold voltage (V th ) and the work function difference between the gate material and the semiconductor material Taking P-type silicon carbide (P-Type 4H-Sic) semiconductor material as an example, P-type polysilicon is used as the gate material, and its work function difference Compared with N-type polysilicon, the use of P-type polysilicon can increase the work function difference between the gate material and P-type silicon carbide by about 1eV, thereby increasing the threshold voltage by about 1V. The specific threshold voltage increment is related to the Fermi level position of P-type polysilicon.

[0041] However, it is expected that the threshold voltage can be further increased compared to P-type polysilicon.

[0042] Figure 2 The energy band structure diagram of a SiC MOSFET device based on a P-type polycrystalline silicon carbide gate material (P-Type Poly-3C-SiC Gate) according to some embodiments of the present application is shown.

[0043] like Figure 2 As shown in Figure 2, in SiC MOSFET devices, P-type polycrystalline silicon carbide is used as the gate material, and its work function is different. Compared with using P-type polysilicon as the gate material, the work function difference is increased by 0.2+1.47=1.67eV. Therefore, in theory, under the condition that other process conditions remain unchanged, the present application changes the gate material from P-type polysilicon to P-type polycrystalline silicon carbide, which can increase the threshold voltage by 1.67V without sacrificing other key characteristics such as on-resistance.

[0044] Figure 3 A flow chart of a method for forming a semiconductor device structure according to some embodiments of the present application is shown.

[0045] like Figure 3 As shown, the forming method includes:

[0046] Step 301, forming an implantation mask on the epitaxial layer of the substrate, and forming an N+ region, a P well region, a P+ region and a JFET region on the implantation mask respectively;

[0047] Step 302, forming a gate oxide layer;

[0048] Step 303, forming a polycrystalline silicon carbide film layer;

[0049] Step 304, performing P-type doping on the polycrystalline silicon carbide film layer;

[0050] Step 305 , patterning the P-type doped polycrystalline silicon carbide film layer to form a gate electrode.

[0051] According to steps 301 to 305, the embodiment of the present application forms a semiconductor device structure based on a P-type polycrystalline silicon carbide gate material, such as a SiC MOSFET device based on a P-type polycrystalline silicon carbide gate material, which can further increase the threshold voltage compared to P-type polycrystalline silicon.

[0052] Figures 4a to 4d A schematic diagram showing a process flow of a semiconductor device structure according to some embodiments of the present application is shown.

[0053] In one example, if Figure 4a As shown, a substrate 401 of a semiconductor device structure may be prepared first, and then an epitaxial layer 402 may be grown on the substrate 401, or the substrate 401 may be directly used as the epitaxial layer 402. The epitaxial layer 402 may be a silicon carbide epitaxial layer.

[0054] In one example, if Figure 4aAs shown, an injection mask can be formed on the epitaxial layer 402 of the substrate 401 according to step 301. The specific type of the injection mask is not limited in the embodiment of the present application. For example, the injection mask can be a photoresist or a hard mask. The specific implementation method of forming the injection mask is not limited in the embodiment of the present application. For example, those skilled in the art can form a photoresist using a photolithography process in the relevant technology, or can generate a hard mask using a chemical vapor deposition process.

[0055] In one example, if Figure 4a As shown, an N+ region, a P-well (P-Well) region, a P+ region, and a JFET region (not shown) can be formed on the implantation mask respectively according to step 301. The specific implementation method of forming each region is not limited in the embodiment of the present application. For example, those skilled in the art can form an N+ region by N-type ion implantation, can form a P-well region by P-type ion implantation, can form a P+ region and a JFET region by P+ implantation and JFET implantation, and then high temperature annealing can be performed to activate the implanted ions.

[0056] In one example, if Figure 4a As shown, a gate oxide layer 403 may be formed according to step 302. The specific implementation method of forming the gate oxide layer 403 is not limited in the present embodiment. For example, those skilled in the art may form the gate oxide layer 403 by performing conventional planar VDMOS processes such as sacrificial oxidation, photolithography and etching of the active region, and gate oxide formation.

[0057] In one example, if Figure 4b As shown, a polycrystalline silicon carbide film layer 404 may be formed according to step 303. For example, a CVD process may be used to form the polycrystalline silicon carbide film layer 404.

[0058] In one example, if Figure 4c As shown, the polycrystalline silicon carbide film layer 404 may be P-type doped according to step 304. For example, the P-type doping may be performed by in-situ doping in a CVD process or P-type ion implantation, and then activation annealing may be performed.

[0059] In one example, if Figure 4d As shown, the P-type doped polycrystalline silicon carbide film layer 404 can be patterned according to step 305 to form a gate electrode 405. For example, the P-type doped polycrystalline silicon carbide film layer 404 can be patterned by dry etching to form a gate electrode pattern.

[0060] In one example, returning to Figure 3 , the forming method further comprises:

[0061] Step 306: forming an insulating dielectric layer and a source metal.

[0062] In one example, if Figure 4d As shown, an insulating dielectric layer 406 and a source metal 407 may be formed according to step 306. The specific implementation of forming the insulating dielectric layer 406 and the source metal 407 is not limited in the embodiment of the present application. For example, those skilled in the art may form the insulating dielectric layer 406 and the source metal 407 by performing conventional planar VDMOS processes such as ILD deposition, ILD patterning, and deposition of surface metal.

[0063] Thus, the embodiment of the present application finally forms the following Figure 4d The VDMOS cell structure shown.

[0064] Figure 5 Another flow chart of a method for forming a semiconductor device structure according to some embodiments of the present application is shown.

[0065] like Figure 5 As shown, the forming method includes:

[0066] Step 501, forming an implantation mask on the epitaxial layer of the substrate, and forming an N+ region, a P well region, a P+ region and a JFET region on the implantation mask respectively;

[0067] Step 502, forming a gate oxide layer;

[0068] Step 503, forming a polycrystalline silicon carbide film layer;

[0069] Step 504, performing P-type doping on the polycrystalline silicon carbide film layer;

[0070] Step 505, patterning the P-type doped polycrystalline silicon carbide film layer to form a gate electrode;

[0071] Step 506, forming a dielectric layer on the gate electrode;

[0072] Step 507, removing part of the dielectric layer to form a sidewall structure on both sides of the gate electrode;

[0073] Step 508 , forming an alloy layer on the gate electrode and the source region of the semiconductor device structure by using the spacer structure.

[0074] According to steps 501 to 508, the embodiment of the present application forms a semiconductor device structure based on a P-type polycrystalline silicon carbide gate material, such as a SiC MOSFET device based on a P-type polycrystalline silicon carbide gate material, which can further increase the threshold voltage compared to P-type polycrystalline silicon.

[0075] Figure 6a to Figure 6gAnother schematic diagram showing a process flow of a semiconductor device structure according to some embodiments of the present application.

[0076] In one example, if Figure 6a As shown, a substrate 601 of a semiconductor device structure may be prepared first, and then an epitaxial layer 602 may be grown on the substrate 601, or the substrate 601 may be directly used as the epitaxial layer 602. The epitaxial layer 602 may be a silicon carbide epitaxial layer.

[0077] In one example, if Figure 6a As shown, an injection mask can be formed on the epitaxial layer 602 of the substrate 601 according to step 501. The specific type of the injection mask is not limited in the embodiment of the present application. For example, the injection mask can be a photoresist or a hard mask. The specific implementation method of forming the injection mask is not limited in the embodiment of the present application. For example, those skilled in the art can form a photoresist using a photolithography process in the relevant technology, or can generate a hard mask using a chemical vapor deposition process.

[0078] In one example, if Figure 6a As shown, an N+ region, a P-well (P-Well) region, a P+ region, and a JFET region (not shown) can be formed on the implantation mask respectively according to step 501. The specific implementation method of forming each region is not limited in the embodiment of the present application. For example, those skilled in the art can form an N+ region by N-type ion implantation, can form a P-well region by P-type ion implantation, can form a P+ region and a JFET region by P+ implantation and JFET implantation, and then high temperature annealing can be performed to activate the implanted ions.

[0079] In one example, if Figure 6a As shown, a gate oxide layer 603 may be formed according to step 502. The specific implementation method of forming the gate oxide layer 603 is not limited in the present embodiment. For example, those skilled in the art may form the gate oxide layer 603 by performing conventional planar VDMOS processes such as sacrificial oxidation, photolithography and etching of the active region, and gate oxide formation.

[0080] In one example, if Figure 6b As shown, a polycrystalline silicon carbide film layer 604 may be formed according to step 503. For example, a CVD process may be used to form the polycrystalline silicon carbide film layer 604.

[0081] In one example, if Figure 6c As shown, the polycrystalline silicon carbide film layer 604 may be P-type doped according to step 504. For example, the P-type doping may be performed by in-situ doping in a CVD process or P-type ion implantation, and then activation annealing may be performed.

[0082] In one example, if Figure 6d As shown, the P-type doped polycrystalline silicon carbide film layer 604 can be patterned according to step 505 to form a gate electrode 605. For example, the P-type doped polycrystalline silicon carbide film layer 604 can be patterned by dry etching to form a gate electrode pattern.

[0083] In one example, if Figure 6d As shown, a dielectric layer 606 may be formed on the gate electrode 605 according to step 506. For example, the dielectric layer 606 may be a silicon dioxide (SiO2) dielectric layer, and the thickness of the silicon dioxide dielectric layer may be

[0084] In one example, if Figure 6e As shown, part of the dielectric layer 606 may be removed according to step 507 to form a spacer structure 607 on both sides of the gate electrode 605. For example, an isotropic etching process may be used to form the spacer structure 607, and the spacer structure 607 may be a silicon dioxide spacer structure.

[0085] In one example, if Figure 6f As shown, an alloy layer 608 can be formed on the gate electrode 605 and the source region of the semiconductor device structure using the spacer structure 607 according to step 508. For example, the alloy layer 608 can be a silicon carbide-nickel alloy (NiSilicide) layer, and the silicon carbide-nickel alloy layer can be formed by a nickel secondary annealing process.

[0086] In one example, returning to Figure 5 , the forming method further comprises:

[0087] Step 509: forming an insulating dielectric layer and a source metal.

[0088] In one example, if Figure 6g As shown, an insulating dielectric layer 609 and a source metal 610 may be formed according to step 506. The specific implementation of forming the insulating dielectric layer 609 and the source metal 610 is not limited in the embodiment of the present application. For example, those skilled in the art may form the insulating dielectric layer 609 and the source metal 610 by performing conventional planar VDMOS processes such as ILD deposition, ILD patterning, and deposition of surface metal.

[0089] Thus, the embodiment of the present application finally forms the following Figure 6g The VDMOS cell structure shown.

[0090] Figure 7 The TCAD simulation results of the semiconductor device structure according to some embodiments of the present application are shown.

[0091] like Figure 7As shown, case 1 is the transfer characteristic curve (Id-Vg curve) under the standard process of using P-type polysilicon gate, case 2 is the transfer characteristic curve under the standard process of using P-type polycrystalline silicon carbide gate, and case 3 is the transfer characteristic curve under the process of using P-type polycrystalline silicon carbide gate and reducing the P-well doping concentration by 50%. The following Table 1 is from Figure 7 The key characteristic parameters extracted from the simulation results. Combined with Table 1, it can be seen that the threshold voltage (Vth) of case 1 is 3.0V and the specific on-resistance (Rsp) is 2.4mΩ·cm 2 In case 2, when the gate material is replaced with P-type polycrystalline silicon carbide, the threshold voltage increases to 4.6 V, while the specific on-resistance increases only slightly to 2.6 mΩ·cm 2 In case 3, after the P-well doping concentration is reduced by 50%, the threshold voltage is 3.4V, which is still higher than that in case 1, and the specific on-resistance is reduced to 1.7mΩ·cm 2 , a 30% decrease compared to Case 1.

[0092] It can be seen that the present application uses P-type polycrystalline silicon carbide as the gate material, which can simultaneously reduce the channel P-type doping concentration, and the channel mobility increases accordingly, thereby bringing about a significant reduction in on-resistance, achieving a better trade-off between threshold voltage and on-resistance.

[0093]

[0094] Table 1 Key characteristic parameters of TCAD simulation results of semiconductor device structure

[0095] It can be understood that the above-mentioned various method embodiments mentioned in this application can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, this application will not go into details. Those skilled in the art can understand that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined by its function and possible internal logic.

[0096] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for forming a semiconductor device structure, characterized in that: The method comprises: An implantation mask is formed on the epitaxial layer of the substrate, and an N+ region, a P well region, a P+ region and a JFET region are respectively formed on the implantation mask; forming a gate oxide layer; forming a polycrystalline silicon carbide film layer; Performing P-type doping on the polycrystalline silicon carbide film layer; The P-type doped polycrystalline silicon carbide film layer is patterned to form a gate electrode.

2. The method according to claim 1, characterized in that The method further comprises: forming a dielectric layer on the gate electrode; Removing part of the dielectric layer to form sidewall structures on both sides of the gate electrode; An alloy layer is formed on the gate electrode and the source region of the semiconductor device structure by utilizing the spacer structure.

3. The method according to claim 1 or 2, characterized in that: The polycrystalline silicon carbide film layer is formed by a CVD process.

4. The method according to claim 1 or 2, characterized in that: The P-type doping is performed by in-situ doping in a CVD process or P-type ion implantation.

5. The method according to claim 1 or 2, characterized in that: The patterning is performed by using a dry etching process.

6. The method according to claim 2, characterized in that The dielectric layer is a silicon dioxide dielectric layer, and the thickness of the silicon dioxide dielectric layer is 7. The method according to claim 2, characterized in that The sidewall structure is formed by an isotropic etching process.

8. The method according to claim 2, characterized in that: The alloy layer is a silicon carbide-nickel alloy layer, and a nickel secondary annealing process is used to form the silicon carbide-nickel alloy layer.

9. The method according to claim 1 or 2, characterized in that: The method further comprises: An insulating dielectric layer and a source metal are formed.

10. A semiconductor device structure, characterized in that: The semiconductor device structure is formed by the method according to any one of claims 1-9.

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