Super junction MOSFET with good avalanche resistance and preparation method and chip thereof

Abstract

The present application belongs to the technical field of power devices, and provides a super junction MOSFET with good anti-avalanche capability, a preparation method thereof, and a chip thereof. A first P column, a first P-type well region, and a first P-type base region are formed on a first side of an N-type drift region, which are stacked on an N-type substrate; a second P column, a second P-type well region, and a second P-type base region are formed on a second side of the N-type drift region, which are stacked on an N-type substrate; and a concentration of P-type doped ions in the first P-type well region is set to be greater than a concentration of P-type doped ions in the first P-type base region, a width of the first P-type well region is smaller than a width of the first P-type base region, a concentration of P-type doped ions in the second P-type well region is greater than a concentration of P-type doped ions in the second P-type base region, and a width of the second P-type well region is smaller than a width of the second P-type base region, thereby changing the electric field around the P-type base region inside the device, suppressing the conduction of a parasitic BJT in the device, and improving the anti-avalanche capability of the device.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular, relates to a super junction MOSFET with good avalanche resistance, a preparation method thereof, and a chip. Background Art

[0002] In recent years, Super Junction MOSFET (Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor, SJMOSFET) has been widely used in high-voltage power semiconductor devices due to its excellent performance such as high voltage resistance and low on-resistance. In actual use, the failure of super junction MOSFET is usually due to thermal failure caused by avalanche. Therefore, improving the avalanche resistance of super junction MOSFET is of great significance to improving its reliability. Summary of the invention

[0003] In order to solve the above technical problems, the embodiments of the present application provide a super junction MOSFET with good avalanche resistance and a preparation method and chip thereof, which can improve the avalanche resistance of the super junction MOSFET device.

[0004] In a first aspect, an embodiment of the present application provides a super junction MOSFET with good avalanche resistance, the super junction MOSFET comprising:

[0005] N-type substrate;

[0006] A first P column, a first P-type well region, and a first P-type base region, wherein the first P column, the first P-type well region, and the first P-type base region are sequentially stacked on the N-type substrate; a concentration of P-type doping ions in the first P-type well region is greater than a concentration of P-type doping ions in the first P-type base region, and a width of the first P-type well region is less than a width of the first P-type base region;

[0007] A second P column, a second P-type well region, and a second P-type base region, wherein the second P column, the second P-type well region, and the second P-type base region are sequentially stacked on the N-type substrate; a concentration of P-type doping ions in the second P-type well region is greater than a concentration of P-type doping ions in the second P-type base region, and a width of the second P-type well region is less than a width of the second P-type base region;

[0008] An N-type drift region is formed on the N-type substrate, and the first P column, the first P-type well region, and the first P-type base region are located on a first side of the N-type drift region, and the second P column, the second P-type well region, and the second P-type base region are located on a second side of the N-type drift region; the first P-type base region and the second P-type base region are both in a concave shape;

[0009] A first N-type source region and a second N-type source region, wherein the first N-type source region is formed in a concave structure of the first P-type base region; and the second N-type source region is formed in a concave structure of the second P-type base region;

[0010] a gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on the N-type drift region, contacts the first P-type base region, the second P-type base region, the first N-type source region, and the second N-type source region, and the gate dielectric layer wraps the gate polysilicon layer;

[0011] a source layer, covering the gate dielectric layer and contacting the first N-type source region, the second N-type source region, the first P-type base region, and the second P-type base region;

[0012] The drain layer is formed on the back side of the N-type substrate.

[0013] In some embodiments, the first P-type well region has a rectangular structure; and / or the second P-type well region has a rectangular structure.

[0014] In some embodiments, the width of the first P-type well region is equal to the width of the first P-pillar; and / or the width of the second P-type well region is equal to the width of the second P-pillar.

[0015] In some embodiments, the first P-type well region has a trapezoidal structure, and the width of the first P-type well region gradually decreases from the drain layer to the source layer;

[0016] and / or,

[0017] The second P-type well region has a trapezoidal structure, and a width of the second P-type well region gradually decreases from the drain layer to the source layer.

[0018] In some embodiments, the concentration of the P-type doping ions in the first P-type well region gradually decreases from the drain layer to the source layer; and / or,

[0019] The concentration of the P-type doping ions in the second P-type well region gradually decreases from the drain layer to the source layer.

[0020] In some embodiments, the first P-type well region includes a plurality of first sub-P-type well regions stacked in sequence, each first sub-P-type well region has a rectangular structure, and the concentration of P-type doping ions in each first sub-P-type well region is different.

[0021] In some embodiments, the second P-type well region includes a plurality of second sub-P-type well regions stacked in sequence, each second sub-P-type well region has a rectangular structure, and the concentration of P-type doping ions in each second sub-P-type well region is different.

[0022] In some embodiments, an N-type doping point region is disposed in the first P-type well region; and / or an N-type doping point region is disposed in the second P-type well region.

[0023] A second aspect of the embodiment of the present application further provides a method for preparing a super junction MOSFET with good avalanche resistance, the preparation method comprising:

[0024] Epitaxially forming an N-type drift layer on the front side of the N-type substrate;

[0025] Forming a first deep trench and a second deep trench extending into the N-type substrate on both sides of the N-type drift layer by an etching process, so that an N-type drift region is formed between the first deep trench and the second deep trench;

[0026] forming a first P column in the first deep trench, and forming a second P column in the second deep trench;

[0027] Performing P-type dopant ion implantation on the first P column to form a first P-type well region, and performing P-type dopant ion implantation on the second P column to form a second P-type well region;

[0028] Epitaxially growing the N-type drift region, and implanting P-type dopant ions on both sides of the N-type drift region to form a first P-type base region on the first P-type well region, and a second P-type base region on the second P-type well region; the concentration of the P-type dopant ions in the first P-type well region is greater than the concentration of the P-type dopant ions in the first P-type base region, the width of the first P-type well region is less than the width of the first P-type base region, the concentration of the P-type dopant ions in the second P-type well region is greater than the concentration of the P-type dopant ions in the second P-type base region, and the width of the second P-type well region is less than the width of the second P-type base region;

[0029] Implanting N-type dopant ions into the central region of the first P-type base region to form a first N-type source region, and implanting N-type dopant ions into the central region of the second P-type base region to form a second N-type source region;

[0030] forming a gate dielectric layer and a gate polysilicon layer on the N-type drift region, wherein the gate dielectric layer is in contact with the first P-type base region, the second P-type base region, the first N-type source region, and the second N-type source region, and the gate dielectric layer wraps the gate polysilicon layer;

[0031] forming a source layer on the gate dielectric layer, the source layer being in contact with the first N-type source region, the second N-type source region, the first P-type base region, and the second P-type base region;

[0032] A drain layer is formed on the back side of the N-type substrate.

[0033] A third aspect of the embodiments of the present application further provides a chip, comprising a super junction MOSFET with good avalanche resistance as described in any of the above embodiments.

[0034] The beneficial effects of the embodiments of the present application are as follows: by setting a first P-type well region between the first P-pillar and the first P-type base region; setting a second P-type well region between the second P-pillar and the second P-type base region, and the concentration of P-type doped ions in the first P-type well region is greater than the concentration of P-type doped ions in the first P-type base region, and the width of the first P-type well region is less than the width of the first P-type base region; the concentration of P-type doped ions in the second P-type well region is greater than the concentration of P-type doped ions in the second P-type base region, and the width of the second P-type well region is less than the width of the second P-type base region, thereby reducing the high electric field of the parasitic transistor composed of the N-type source region, the P-type base region, and the N-type drift region of the traditional planar super junction MOSFET, suppressing its misconduction under large current, and improving the device's avalanche resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 1 is a schematic diagram of a first structure of a super junction MOSFET with good avalanche resistance provided by an embodiment of the present application;

[0036] Figure 2 This is a comparison diagram of the electric field distribution simulation results of the super junction MOSFET with good avalanche resistance provided by the embodiment of the present application and the traditional super junction MOSFET when the voltage between the drain and the source is equal to the breakdown voltage;

[0037] Figure 3 It is a UIS test waveform diagram of a super junction MOSFET with good avalanche resistance provided by an embodiment of the present application and a conventional super junction MOSFET under an avalanche current of 4.1A;

[0038] Figure 4 This is a comparison chart of the hole current density simulation results of the super junction MOSFET with good avalanche resistance provided by the embodiment of the present application and the traditional super junction MOSFET under an avalanche current of 4.1A;

[0039] Figure 5 This is a UIS test waveform diagram of a super junction MOSFET having a first P-type well region and a second P-type well region with different widths provided in an embodiment of the present application;

[0040] Figure 6 is a second structural schematic diagram of a super junction MOSFET with good avalanche resistance provided by an embodiment of the present application;

[0041] Figure 7 3 is a schematic diagram of the third structure of a super junction MOSFET with good avalanche resistance provided in an embodiment of the present application;

[0042] Figure 8 4 is a schematic diagram of the structure of a super junction MOSFET with good avalanche resistance provided by an embodiment of the present application;

[0043] Fig. 9 It is a schematic flow chart of a method for preparing a super junction MOSFET with good avalanche resistance provided in an embodiment of the present application;

[0044] Fig.10 is a schematic diagram of forming an N-type drift layer on an N-type substrate layer provided by an embodiment of the present application;

[0045] Fig.11 It is a schematic diagram of forming a first P column, a second P column, and an N-type drift region provided in an embodiment of the present application;

[0046] Fig.12 is a schematic diagram of forming a first P-type well region and a second P-type well region provided in an embodiment of the present application;

[0047] Fig.13 It is a schematic diagram of forming a first P-type base region, a second P-type base region, a first N-type source region, and a second N-type source region provided by an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0049] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0050] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0052] Super Junction MOSFET (Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor, SJMOSFET) is widely used in high-voltage power semiconductor devices due to its excellent performance such as high voltage resistance and low on-resistance. In actual use, the failure of super junction MOSFET is usually due to thermal failure caused by avalanche. Therefore, improving the avalanche resistance of super junction MOSFET is of great significance to improving its reliability.

[0053] See also Figure 1 As shown, an embodiment of the present application provides a super junction MOSFET with good avalanche resistance, which includes an N-type substrate 110, a first P-column 120, a first P-type well region 121, a first P-type base region 122, a second P-column 130, a second P-type well region 131, a second P-type base region 132, a first N-type source region 123, a second N-type source region 133, an N-type drift region 140, a gate dielectric layer 150, a gate polysilicon layer 151, a source layer 160 and a drain layer 170.

[0054] Among them, the first P column 120, the first P-type well region 121, and the first P-type base region 122 are sequentially stacked on the N-type substrate 110; the concentration of P-type doped ions in the first P-type well region 121 is greater than the concentration of P-type doped ions in the first P-type base region 122, and the width of the first P-type well region 121 is smaller than the width of the first P-type base region 122; the second P column 130, the second P-type well region 131, and the second P-type base region 132 are sequentially stacked on the N-type substrate 110; the concentration of P-type doped ions in the second P-type well region 131 is greater than the concentration of P-type doped ions in the second P-type base region 132, and the width of the second P-type well region 131 is smaller than the width of the second P-type base region 132; the N-type drift region 140 is formed on the N-type substrate 110, and the first P column 120, the first P-type well region 121, and the first P-type base region 122 are located on the first side of the N-type drift region 140. The second P column 130, the second P-type well region 131, and the second P-type base region 132 are located on the second side of the N-type drift region 140; the first P-type base region 122 and the second P-type base region 132 are both in a concave structure; the first N-type source region 123 is formed in the concave structure of the first P-type base region 122; the second N-type source region 133 is formed in the concave structure of the second P-type base region 132; the gate dielectric layer 150 is formed on the N-type drift region 140 , in contact with the first P-type base region 122, the second P-type base region 132, the first N-type source region 123, and the second N-type source region 133, and the gate dielectric layer 150 wraps the gate polysilicon layer 151; the source layer 160 covers the gate dielectric layer 150 and is in contact with the first N-type source region 123, the second N-type source region 133, the first P-type base region 122, and the second P-type base region 132; the drain layer 170 is formed on the back side of the N-type substrate 110.

[0055] In the embodiment of the present application, a first P-type well region 121 is set between the first P-pillar 120 and the first P-type base region 122; a second P-type well region 131 is set between the second P-pillar 130 and the second P-type base region 132, and the concentration of P-type doped ions in the first P-type well region 121 is greater than the concentration of P-type doped ions in the first P-type base region 122, and the width of the first P-type well region 121 is less than the width of the first P-type base region 122; the concentration of P-type doped ions in the second P-type well region 131 is greater than the concentration of P-type doped ions in the second P-type base region 132, and the width of the second P-type well region 131 is less than the width of the second P-type base region 132, thereby changing the electric field around the P-type base region inside the device, reducing the high electric field of the parasitic transistor in the device composed of the N-type source region, the P-type base region, and the N-type drift region 140 of the traditional planar super junction MOSFET, suppressing the misconduction of the parasitic transistor in the device under large current, and improving the device's avalanche resistance.

[0056] In practical applications, the unclamped inductive switching (UIS) test is used to simulate the avalanche resistance of the super junction MOSFET under large current. The UIS failure (Unclamped Inductive Switching failure) is caused by the mis-conduction of the parasitic transistor (BJT) in the device. The parasitic transistor in the device is composed of an N-type source region, a P-type base region, and an N-type drift region 140. In order to improve the avalanche resistance of the super junction MOSFET, the present application sets a first P-type well region 121 between the first P column 120 and the first P-type base region 122; sets a second P-type well region 131 between the second P column 130 and the second P-type base region 132, and the concentration of the P-type doped ions in the first P-type well region 121 is greater than the concentration of the P-type doped ions in the first P-type base region 122, and the width of the first P-type well region 121 is less than the width of the second P-type well region 121. The width of a P-type base region 122; the concentration of P-type doped ions in the second P-type well region 131 is greater than the concentration of P-type doped ions in the second P-type base region 132, the width of the second P-type well region 131 is less than the width of the second P-type base region 132, the upper boundary of the first P-type well region 121 contacts the lower boundary of the first P-type base region 122, and the upper boundary of the second P-type well region 131 contacts the lower boundary of the second P-type base region 132, so as to change the electric field around the first P-type base region 122 and the second P-type base region 132, suppress the conduction of the parasitic transistor in the device, improve the device's anti-avalanche capability, and improve the reliability of the device under large current.

[0057] Specifically, Figure 2 As shown, when the voltage (VDS) between the drain and the source is equal to the breakdown voltage (BV), compared with the traditional super junction MOSFET (traditional structure), the super junction MOSFET (improved structure) proposed in the present application transfers the high electric field generated at the contact position of the P-type base region (i.e., the first P-type base region 122 and the second P-type base region 132) and the N drift region to the place where the newly added first P-type well region 121 contacts the N drift region, and the place where the second P-type well region 131 contacts the N drift region, thereby reducing the high electric field at the parasitic BJT, thereby suppressing the mis-conduction of the parasitic BJT of the device in the UIS test, and improving the device's avalanche resistance.

[0058] like Figure 3 and Figure 4As shown, under the same test conditions, facing an avalanche current of 4.1A, the traditional super junction MOSFET (traditional structure) suffered thermal failure, while the super junction MOSFET structure (improved structure) proposed in the present application remained robust and did not fail. Specifically, under an avalanche current of 4.1A, the structure proposed in the present application reduces the high electric field of the parasitic BJT, causing the first P-type base region 122 and the second P-type base region 132 to gather less hole current, making the BJT less likely to turn on, and thus did not fail. However, due to the high electric field of the parasitic BJT in the traditional super junction MOSFET, a large amount of hole current is gathered in the P-type base region, resulting in mis-conduction of the parasitic BJT, leading to thermal failure. Moreover, the super junction MOSFET structure proposed in the present application does not significantly reduce the static characteristics of the device. Among them, Figure 3 The IDS in the figure is the drain current of the device.

[0059] In some embodiments, Figure 1 As shown, the first P-type well region 121 has a rectangular structure.

[0060] In some embodiments, Figure 1 As shown, the second P-type well region 131 is in a rectangular structure.

[0061] In some embodiments, Figure 1 As shown, the width of the first P-type well region 121 is greater than the width of the first P-pillar 120 ; and the width of the second P-type well region 131 is greater than the width of the second P-pillar 130 .

[0062] In the embodiment of the present application, a first P-type well region 121 with a rectangular structure is provided between the first P-pillar 120 and the first P-type base region 122; a second P-type well region 131 with a rectangular structure is provided between the second P-pillar 130 and the second P-type base region 132, and the concentration of the P-type doping ions in the first P-type well region 121 is greater than the concentration of the P-type doping ions in the first P-type base region 122, and the width of the first P-type well region 121 is less than the width of the first P-type base region 122; the concentration of the P-type doping ions in the second P-type well region 131 is greater than the concentration of the P-type doping ions in the second P-type base region 132. The concentration of type doping ions is increased, the width of the second P-type well region 131 is smaller than the width of the second P-type base region 132, and the width of the first P-type well region 121 is larger than the width of the first P column 120; the width of the second P-type well region 131 is larger than the width of the second P column 130, which changes the electric field around the P-type base region inside the device, reduces the high electric field of the parasitic transistor in the device composed of the N-type source region, the P-type base region, and the N-type drift region 140 of the traditional planar super junction MOSFET, suppresses the misconduction of the parasitic transistor in the device under large current, and improves the device's anti-avalanche capability.

[0063] In some embodiments, the width of the first P-type well region 121 may be equal to the width of the first P-pillar 120 ; and the width of the second P-type well region 131 may be equal to the width of the second P-pillar 130 .

[0064] For example, as shown in Table 1 and Figure 5 As shown, when the width of the first P-type base region 122 is 4.8um, the width of the first P-pillar 120 is 3um, and the width of the first P-type well region 121 is designed to be 3um, the overall effect is better. Wherein, Ron in Table 1 is the on-resistance of the device, BV is the breakdown voltage of the device, and Vth is the threshold voltage of the device. Figure 5 The IDS in the figure is the drain current of the device.

[0065] Table 1:

[0066]

[0067] In some embodiments, the first P-type well region 121 has a trapezoidal structure, and the width of the first P-type well region 121 gradually decreases from the drain layer 170 to the source layer 160 .

[0068] like Figure 6 As shown, when the first P-type well region 121 has a trapezoidal structure, the width of the contact surface between the first P-type well region 121 and the first P-type base region 122 is smaller than the width of the contact surface between the first P-type well region 121 and the first P column 120 .

[0069] In some embodiments, the second P-type well region 131 has a trapezoidal structure, and the width of the second P-type well region 131 gradually decreases from the drain layer 170 to the source layer 160 .

[0070] like Figure 6 As shown, when the second P-type well region 131 is in a trapezoidal structure, the width of the contact surface between the second P-type well region 131 and the second P-type base region 132 is smaller than the width of the contact surface between the second P-type well region 131 and the second P column 130 .

[0071] In some embodiments, the concentration of the P-type doping ions in the first P-type well region 121 gradually decreases from the drain layer 170 to the source layer 160 .

[0072] For example, Figure 7 As shown, the first P-type well region 121 may include a plurality of first sub-P-type well regions 1211 stacked in sequence, each of the first sub-P-type well regions 1211 is in a rectangular structure, and the concentrations of the P-type doping ions in each of the first sub-P-type well regions 1211 are different. The concentration of the P-type doping ions in the first sub-P-type well region 1211 close to the first P-type base region 122 is less than the concentration of the P-type doping ions in the first sub-P-type well region 1211 close to the first P column 120.

[0073] In some embodiments, the concentration of the P-type doping ions in the second P-type well region 131 gradually decreases from the drain layer 170 to the source layer 160 .

[0074] For example, Figure 7 As shown, the second P-type well region 131 includes a plurality of second sub-P-type well regions 1311 stacked in sequence, each second sub-P-type well region 1311 is in a rectangular structure, and the concentration of P-type doping ions in each second sub-P-type well region 1311 is different. The concentration of P-type doping ions in the second sub-P-type well region 1311 close to the second P-type base region 132 is less than the concentration of P-type doping ions in the second sub-P-type well region 1311 close to the second P column 130.

[0075] In some embodiments, an N-type doped region is disposed in the first P-type well region 121 .

[0076] like Figure 8 As shown, in this embodiment, by setting the first N-type doping point region 124 in the first P-type well region 121, the reverse recovery peak current of the device during reverse recovery can be reduced, the electric field between the first P-type base region 122 and the first P-type well region 121 can be balanced, and the robustness of the device during reverse recovery can be improved.

[0077] In some embodiments, an N-type doped region is disposed in the second P-type well region 131 .

[0078] like Figure 8 As shown, in this embodiment, a second N-type doping point region 134 is set in the second P-type well region 131, which can reduce the reverse recovery peak current of the device during reverse recovery, balance the electric field between the second P-type base region 132 and the second P-type well region 131, and improve the robustness of the device during reverse recovery.

[0079] In some embodiments, a plurality of first N-type doping point regions 124 are disposed in the first P-type well region 121 , and the density of the plurality of first N-type doping point regions 124 may gradually decrease from the interface between the first P-type base region 122 and the first P-type well region 121 toward the N-type substrate 110 .

[0080] In some embodiments, a plurality of second N-type doping point regions 134 are disposed in the second P-type well region 131 , and the density of the plurality of second N-type doping point regions 134 may gradually decrease from the interface between the second P-type base region 132 and the second P-type well region 131 toward the N-type substrate 110 .

[0081] In one embodiment, Figure 1As shown, the gate dielectric layer 150 is in contact with the first P-type base region 122 , the second P-type base region 132 , the first N-type source region 123 , and the second N-type source region 133 .

[0082] In one embodiment, the widths of the first P-type base region 122 and the second P-type base region 132 gradually increase in a direction toward the gate polysilicon layer 151 .

[0083] In this embodiment, the electric field strength in the area close to the gate of the device is relatively large, and the first P-type base region 122 and the second P-type base region 132 are arranged relatively to each other. By setting the widths of the first P-type base region 122 and the second P-type base region 132 to gradually increase in the direction toward the gate polysilicon layer 151, the hole extraction of the device during reverse recovery can be slowed down and the softness of reverse recovery can be improved.

[0084] In one embodiment, the width of the first P-type base region 122 gradually increases in the direction toward the gate polysilicon layer 151 , which means that the first P-type base region 122 gradually increases in the direction toward the center point between the first P-type base region 122 and the second P-type base region 132 .

[0085] In one embodiment, the width of the second P-type base region 132 gradually increases in the direction toward the gate polysilicon layer 151 , which may be that the second P-type base region 132 gradually increases in the direction toward the center point between the first P-type base region 122 and the second P-type base region 132 .

[0086] In one embodiment, the N-type ion doping concentration of the N-type drift region 140 is the same as the P-type ion doping concentration of the first P column 120 and the second P column 130 .

[0087] In one embodiment, Figure 1 As shown, the sum of the widths of the first P column 120 and the second P column 130 is equal to the width of the N-type drift region 140 located between the first P column 120 and the second P column 130 .

[0088] In one embodiment, the N-type doping ion concentration of the N-type substrate 110 may be 1e20 cm -3 , the N-type doping ion concentration of the N-type drift region 140 may be 1e15 cm -3 -1e17cm -3 The thickness of the N-type substrate 110 may be 3 um-10 um.

[0089] See also Fig. 9 As shown, this embodiment also provides a method for preparing a super junction MOSFET with good avalanche resistance, and the preparation method includes steps S100 to S900.

[0090] In step S100 , an N-type drift layer is epitaxially formed on the front surface of the N-type substrate 110 .

[0091] In step S200 , a first deep trench and a second deep trench extending into the N-type substrate 110 are formed on both sides of the N-type drift layer by an etching process, so that an N-type drift region 140 is formed between the first deep trench and the second deep trench.

[0092] In step S300 , a first P column 120 is formed in the first deep trench, and a second P column 130 is formed in the second deep trench.

[0093] like Fig.10 and Fig.11 As shown, a silicon material can be epitaxially grown on a silicon substrate, and N-type doping ions can be implanted into the epitaxial silicon material to form an N-type substrate 110. Then, an N-type drift layer 141 can be epitaxially generated on the front side of the N-type substrate 110. A first deep trench and a second deep trench that penetrate into the N-type substrate 110 are formed on both sides of the N-type drift layer by an etching process, so that an N-type drift region 140 is formed between the first deep trench and the second deep trench. A first P column 120 is formed in the first deep trench, and a second P column 130 is formed in the second deep trench, so that the N-type drift region 140 is located between the first P column 120 and the second P column 130.

[0094] In some embodiments, the thickness of the first P column 120 is the same as that of the second P column 130 . The sum of the widths of the first P column 120 and the second P column 130 is equal to the width of the N-type drift region 140 .

[0095] In this embodiment, the N-type doping ion concentration of the N-type drift region 140 is lower than the N-type doping ion concentration of the N-type substrate 110. The N-type doping ion concentration in the N-type substrate 110 may be 1e20cm-3, and the N-type doping ion concentration in the N-type drift region 140 may be 5e15cm-3-7e15cm-3.

[0096] In some embodiments, the thickness of the N-type substrate 110 may be 3 um-10 um.

[0097] In some embodiments, the thickness of the N-type drift region 140 may be 30 um-50 um.

[0098] In step S400 , P-type dopant ions are implanted into the first P column 120 to form a first P-type well region 121 , and P-type dopant ions are implanted into the second P column 130 to form a second P-type well region 131 .

[0099] like Fig.12 As shown, the width of the first P-type well region 121 is greater than the width of the first P-pillar 120 , and the width of the second P-type well region 131 is greater than the width of the second P-pillar 130 .

[0100] In step S500 , the N-type drift region 140 is epitaxially grown, and P-type dopant ions are implanted on both sides of the N-type drift region 140 to form a first P-type base region 122 on the first P-type well region 121 and a second P-type base region 132 on the second P-type well region 131 .

[0101] In the embodiment of the present application, the concentration of P-type doped ions in the first P-type well region 121 is greater than the concentration of P-type doped ions in the first P-type base region 122, the width of the first P-type well region 121 is smaller than the width of the first P-type base region 122, the concentration of P-type doped ions in the second P-type well region 131 is greater than the concentration of P-type doped ions in the second P-type base region 132, and the width of the second P-type well region 131 is smaller than the width of the second P-type base region 132.

[0102] like Fig.13 As shown, in one embodiment, the widths of the first P-type base region 122 and the second P-type base region 132 gradually increase in a direction toward the gate polysilicon layer 151 .

[0103] In this embodiment, the electric field strength in the area close to the gate of the device is relatively large, and the first P-type base region 122 and the second P-type base region 132 are arranged relatively to each other. By setting the widths of the first P-type base region 122 and the second P-type base region 132 to gradually increase in the direction toward the gate polysilicon layer 151, the hole extraction of the device during reverse recovery can be slowed down and the softness of reverse recovery can be improved.

[0104] In one embodiment, the width of the first P-type base region 122 gradually increases in the direction toward the gate polysilicon layer 151 , which means that the first P-type base region 122 gradually increases in the direction toward the center point between the first P-type base region 122 and the second P-type base region 132 .

[0105] In one embodiment, the width of the second P-type base region 132 gradually increases in the direction toward the gate polysilicon layer 151 , which may be that the second P-type base region 132 gradually increases in the direction toward the center point between the first P-type base region 122 and the second P-type base region 132 .

[0106] In step S600 , N-type dopant ions are implanted into the central region of the first P-type base region 122 to form a first N-type source region 123 , and N-type dopant ions are implanted into the central region of the second P-type base region 132 to form a second N-type source region 133 .

[0107] In step S700 , a gate dielectric layer 150 and a gate polysilicon layer 151 are formed on the N-type drift region 140 .

[0108] In the embodiment of the present application, the gate dielectric layer 150 is in contact with the first P-type base region 122 , the second P-type base region 132 , the first N-type source region 123 , and the second N-type source region 133 , and the gate dielectric layer 150 wraps the gate polysilicon layer 151 ;

[0109] In step S800 , a source layer 160 is formed on the gate dielectric layer 150 , the source layer 160 being in contact with the first N-type source region 123 , the second N-type source region 133 , the first P-type base region 122 , and the second P-type base region 132 .

[0110] In step S900 , a drain layer 170 is formed on the back surface of the N-type substrate 110 .

[0111] like Figure 1 As shown, in the embodiment of the present application, a first P-type well region 121 is set between the first P-pillar 120 and the first P-type base region 122; a second P-type well region 131 is set between the second P-pillar 130 and the second P-type base region 132, and the concentration of P-type doped ions in the first P-type well region 121 is greater than the concentration of P-type doped ions in the first P-type base region 122, and the width of the first P-type well region 121 is less than the width of the first P-type base region 122; the concentration of P-type doped ions in the second P-type well region 131 is greater than the concentration of P-type doped ions in the second P-type base region 132, and the width of the second P-type well region 131 is less than the width of the second P-type base region 132, thereby reducing the high electric field of the parasitic transistor composed of the N-type source region, the P-type base region, and the N-type drift region 140 of the traditional planar super junction MOSFET, suppressing its misconduction under large current, and improving the device's avalanche resistance.

[0112] An embodiment of the present application also provides a chip, comprising a super junction MOSFET with good avalanche resistance as in any of the above embodiments.

[0113] In this embodiment, the chip includes a chip substrate, on which one or more super junction MOSFETs with good avalanche resistance are arranged. The super junction MOSFET can be prepared by the preparation method in any of the above embodiments, or the super junction MOSFET with good avalanche resistance in any of the above embodiments can be arranged on the chip substrate.

[0114] In a specific application embodiment, other related semiconductor devices and super junction MOSFETs can also be integrated on the chip substrate to form an integrated circuit.

[0115] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0116] The beneficial effects of the embodiments of the present application are as follows: by setting a first P-type well region between the first P-pillar and the first P-type base region; setting a second P-type well region between the second P-pillar and the second P-type base region, and the concentration of P-type doped ions in the first P-type well region is greater than the concentration of P-type doped ions in the first P-type base region, and the width of the first P-type well region is less than the width of the first P-type base region; the concentration of P-type doped ions in the second P-type well region is greater than the concentration of P-type doped ions in the second P-type base region, and the width of the second P-type well region is less than the width of the second P-type base region, thereby reducing the high electric field of the parasitic transistor composed of the N-type source region, the P-type base region, and the N-type drift region of the traditional planar super junction MOSFET, suppressing its misconduction under large current, and improving the device's avalanche resistance.

[0117] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0118] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0119] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0120] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0121] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A super junction MOSFET with good avalanche resistance, characterized in that: include: N-type substrate; A first P column, a first P-type well region, and a first P-type base region, wherein the first P column, the first P-type well region, and the first P-type base region are sequentially stacked on the N-type substrate; a concentration of P-type doping ions in the first P-type well region is greater than a concentration of P-type doping ions in the first P-type base region, and a width of the first P-type well region is less than a width of the first P-type base region; a second P-pillar, a second P-type well region, and a second P-type base region, wherein the second P-pillar, the second P-type well region, and the second P-type base region are sequentially stacked on the N-type substrate; the concentration of P-type doping ions in the second P-type well region is greater than the concentration of P-type doping ions in the second P-type base region, and the width of the second P-type well region is less than the width of the second P-type base region; the first P-type well region is in a trapezoidal structure, and the width of the first P-type well region gradually decreases from the drain layer to the source layer, and the width of the contact surface between the first P-type well region and the first P-type base region is less than the width of the contact surface between the first P-type well region and the first P-pillar; and / or the second P-type well region is in a trapezoidal structure, and the width of the second P-type well region gradually decreases from the drain layer to the source layer, and the width of the contact surface between the second P-type well region and the second P-type base region is less than the width of the contact surface between the second P-type well region and the second P-pillar; An N-type drift region is formed on the N-type substrate, and the first P column, the first P-type well region, and the first P-type base region are located on a first side of the N-type drift region, and the second P column, the second P-type well region, and the second P-type base region are located on a second side of the N-type drift region; the first P-type base region and the second P-type base region are both in a concave shape; A first N-type source region and a second N-type source region, wherein the first N-type source region is formed in a concave structure of the first P-type base region; and the second N-type source region is formed in a concave structure of the second P-type base region; a gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on the N-type drift region, contacts the first P-type base region, the second P-type base region, the first N-type source region, and the second N-type source region, and the gate dielectric layer wraps the gate polysilicon layer; a source layer, covering the gate dielectric layer and contacting the first N-type source region, the second N-type source region, the first P-type base region, and the second P-type base region; The drain layer is formed on the back side of the N-type substrate.

2. The super junction MOSFET according to claim 1, wherein: The concentration of the P-type doping ions in the first P-type well region gradually decreases from the drain layer to the source layer; and / or, The concentration of the P-type doping ions in the second P-type well region gradually decreases from the drain layer to the source layer.

3. The super junction MOSFET according to claim 1 or 2, characterized in that: An N-type doping point region is disposed in the first P-type well region; and / or an N-type doping point region is disposed in the second P-type well region.

4. A method for preparing a super junction MOSFET with good avalanche resistance, characterized in that: The preparation method comprises: Epitaxially forming an N-type drift layer on the front side of the N-type substrate; Forming a first deep trench and a second deep trench extending into the N-type substrate on both sides of the N-type drift layer by an etching process, so that an N-type drift region is formed between the first deep trench and the second deep trench; forming a first P column in the first deep trench, and forming a second P column in the second deep trench; Performing P-type dopant ion implantation on the first P column to form a first P-type well region, and performing P-type dopant ion implantation on the second P column to form a second P-type well region; Epitaxially growing the N-type drift region, and implanting P-type dopant ions on both sides of the N-type drift region to form a first P-type base region on the first P-type well region, and a second P-type base region on the second P-type well region; the concentration of the P-type dopant ions in the first P-type well region is greater than the concentration of the P-type dopant ions in the first P-type base region, the width of the first P-type well region is less than the width of the first P-type base region, the concentration of the P-type dopant ions in the second P-type well region is greater than the concentration of the P-type dopant ions in the second P-type base region, and the width of the second P-type well region is less than the width of the second P-type base region; Implanting N-type dopant ions into the central region of the first P-type base region to form a first N-type source region, and implanting N-type dopant ions into the central region of the second P-type base region to form a second N-type source region; A gate dielectric layer and a gate polysilicon layer are formed on the N-type drift region, the gate dielectric layer is in contact with the first P-type base region, the second P-type base region, the first N-type source region, and the second N-type source region, and the gate dielectric layer wraps the gate polysilicon layer; the first P-type well region is in a trapezoidal structure, and the width of the first P-type well region gradually decreases from the drain layer to the source layer, and the width of the contact surface between the first P-type well region and the first P-type base region is smaller than the width of the contact surface between the first P-type well region and the first P-pillar; and / or the second P-type well region is in a trapezoidal structure, and the width of the second P-type well region gradually decreases from the drain layer to the source layer, and the width of the contact surface between the second P-type well region and the second P-type base region is smaller than the width of the contact surface between the second P-type well region and the second P-pillar; forming a source layer on the gate dielectric layer, the source layer being in contact with the first N-type source region, the second N-type source region, the first P-type base region, and the second P-type base region; A drain layer is formed on the back side of the N-type substrate.

5. A chip, characterized in that: Comprising the super junction MOSFET as described in any one of claims 1-3.

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