A high-speed TDI image sensor pixel unit and an image sensor

Abstract

The present invention relates to the technical field of semiconductor image sensors, and specifically provides a high-speed TDI image sensor pixel unit and an image sensor. The pixel unit is composed of a polysilicon gate, a buried channel, and a photodiode. The active region of the photodiode is trapezoidal, and the long bottom side of the trapezoidal active region is connected to the buried channel. The active region includes multiple levels of n-type implantation regions. From the buried channel implantation region to the short bottom side of the trapezoidal active region, the built-in potential decreases successively. The present invention adds a clamping photodiode to the traditional TDI image sensor pixel unit, and the photodiode adopts a combined design of a trapezoid and multiple levels of n-type implantation regions, making the potential increase step by step towards the polysilicon gate, improving the flow rate of charges towards the polysilicon gate and reducing the flow time. Without increasing power consumption, it can be applied to high-speed scenarios. Based on the above pixel unit design of the image sensor, the power consumption can be effectively reduced, the information acquisition speed can be increased, and the problem of image aliasing can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor image sensors, and specifically provides a high-speed TDI image sensor pixel unit and an image sensor based on CMOS process and with scalable size. Background Art

[0002] Linear image sensors are usually applied to fields that require high-speed imaging, such as industrial inspection, high-speed moving object detection, assembly line product detection, etc. They have a simple structure and low cost. Generally, a linear image sensor has only one row of photosensitive pixels, and each exposure can only capture a line in the scene. A complete two-dimensional image needs to be obtained through continuous scanning. However, in high-speed detection applications, the object moves too fast, the exposure time is short, the effective signal is small, and the signal-to-noise ratio is low. Even increasing the light intensity cannot make up for the signal-to-noise ratio loss.

[0003] In order to increase the signal-to-noise ratio of the linear image sensor, it is necessary to increase the exposure time of the high-speed moving object and enhance the signal response ability. CMOS TDI (Time Delay Integration) image sensor pixels can be used. In the TDI pixel array, there are multiple rows of pixels, and a time delay is introduced between each row of pixels, so that the exposure of each row of pixels is synchronized with the movement of the object. Each line of the object is integrated row by row, which can effectively improve the signal-to-noise ratio of the image sensor. Different from the interline transfer CCD pixels in traditional CCD image sensors, traditional CCD image sensors use a photodiode and multiple polysilicon gates to achieve the global exposure function. The photodiode of the interline transfer CCD pixel is only used to collect the exposure signal and cannot perform continuous signal transfer (otherwise, the signal stored and read in the previous frame will be aliased), while the polysilicon gate is only used to store and transfer the signal in the previous frame. After the exposure ends, the signal collected by the photodiode needs to be completely horizontally transferred to the polysilicon gate at one time, and this transfer is only performed once in one imaging. This process cannot meet the requirement of synchronously performing the vertical transfer of charges and the movement of the object in TDI, so the TDI function cannot be realized. In addition, after the transfer is completed, the photodiode of the interline transfer CCD performs the exposure of the next frame. After receiving the effective signal, the polysilicon gate performs storage and reading. During this process, the signal collected by the polysilicon gate itself belongs to the parasitic signal. Therefore, it is necessary to strictly avoid the polysilicon gate from collecting signals, otherwise the stored and read signals will be aliased. Therefore, it is required that the polysilicon gate be strictly shaded, and usually, metal shielding is performed on the polysilicon gate, which also makes the quantum efficiency of general interline transfer CCD pixels relatively low.

[0004] Current advanced TDI image sensors all adopt the standard CMOS process, which can achieve high line frequency, and at the same time, high-speed drive circuits and readout circuits are integrated on the chip. CMOS TDI pixels usually consist of some polysilicon gate units such as Figure 1As shown in the figure. By designing reasonable polysilicon gate spacing and implantation conditions, efficient charge transfer in the vertical direction is achieved. In TDI operation, the drive circuit generates a high-speed clock drive signal, which acts on each phase of the polysilicon gate. In high-speed applications, the clock signal needs to be established quickly. However, the gate capacitance introduced by the polysilicon gate is relatively large, and usually a larger drive current is required to ensure the normal establishment of the clock signal for each phase. Therefore, high-speed TDI image sensors usually have relatively high power consumption, which affects the cost of the imaging system. Summary of the Invention

[0005] To solve the above problems, the present invention provides a pixel unit of a high-speed TDI image sensor. By adopting a multi-stage trapezoidal implantation region structure, the built-in potential of the photodiode increases towards the polysilicon gate, which can effectively increase the electric field strength for the charge to flow towards the polysilicon gate, thereby enhancing the speed of the charge flowing from the photodiode to the polysilicon gate. Without increasing the drive current, a higher-speed TDI operation can be achieved, which is beneficial to the ultra-high-speed and low-power application of the image sensor. And by expanding the size and arranging and combining the pixel units, TDI pixels of different sizes can be realized. Compared with the pixels of traditional TDI image sensors, the pixels adopting this pixel unit are more suitable for high-speed and low-power applications.

[0006] On the one hand, the pixel unit of the high-speed TDI image sensor provided by the present invention includes: a polysilicon gate and a buried channel, and a photodiode arranged horizontally along with the buried channel. The buried channel is arranged below the polysilicon gate; the active region of the photodiode is trapezoidal, and the long bottom side of the trapezoidal active region is connected to the buried channel. A P-well region for isolating adjacent pixel units is arranged outside the active region.

[0007] The active region includes an n-type implantation region distributed along the height direction of the trapezoid. The built-in potential of the buried channel is higher than the built-in potential of the n-type implantation region in the active region, and the potential at the long bottom side position of the trapezoidal active region is higher than the potential at the short bottom side position.

[0008] Preferably, the buried channel includes a zero-th n-type implantation region and a zero-th p-type implantation region, and the zero-th p-type implantation region is arranged on the upper surface of the zero-th n-type implantation region.

[0009] Preferably, the active region includes at least two n-type implantation regions distributed along the height direction of the trapezoid and with the built-in potential decreasing successively from the long bottom side to the short bottom side of the trapezoidal active region.

[0010] Preferably, the active region includes an n-type implantation region distributed along the height direction of the trapezoid.

[0011] Preferably, the n-type implantation region of the active region and the zero-th n-type implantation region of the buried channel are integrally designed.

[0012] Preferably, in the active region, the lengths of different n-type implantation regions along the trapezoidal height direction are equal; or in the active region, at least two n-type implantation regions have unequal lengths along the trapezoidal height direction.

[0013] Preferably, the active region of the photodiode is an isosceles trapezoid.

[0014] Preferably, a p-type implantation region is provided above the n-type implantation region of the active region. By adjusting the implantation conditions of the p-type implantation region and / or the n-type implantation region, the built-in potential can be changed.

[0015] Preferably, the number of n-type implantation regions in the active region is the same as that of the p-type implantation regions, and their relative positions correspond one by one; or the number of n-type implantation regions in the active region is different from that of the p-type implantation regions, and their relative positions are not in a one-to-one correspondence.

[0016] Preferably, along the trapezoidal height direction, the length of the polysilicon gate is less than half of the length of the pixel unit.

[0017] Preferably, the built-in potential gradient in the buried channel and the n-type implantation region of the active region needs to satisfy that the time for the charge to flow horizontally from the short bottom side of the trapezoidal active region to the buried channel is less than one-tenth of the time for the charge to flow vertically from the buried channel to the polysilicon gate.

[0018] Preferably, it further includes an anti-overflow structure. The anti-overflow structure includes an anti-overflow gate and an anti-overflow drain. The anti-overflow structure is provided on one side or both sides of the n-type implantation region with the highest potential of the photodiode.

[0019] Preferably, two symmetrical photodiodes are provided on both sides of the buried channel.

[0020] On the other hand, an image sensor is provided with a high-speed TDI image sensor pixel unit.

[0021] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0022] The present invention adds a photodiode to the CMOS TDI image sensor pixel unit, reduces the area of the polysilicon gate, reduces the gate capacitance, improves the clock driving ability of the TDI gate driving circuit, can achieve faster TDI charge transfer at the same power consumption, that is, improves the line array row frequency; or at the same row frequency application, significantly reduces the power consumption; in addition, the photodiode adopts a combined design of a trapezoid and a multi-stage n-type implantation region, generating a stepped increasing potential change towards the polysilicon gate, increasing the potential inclination degree towards the polysilicon gate, enabling the charge collected by the photodiode to be quickly transferred to the polysilicon gate, ensuring that the introduction of the photodiode will not cause image aliasing problems, and can achieve low-power and high-speed applications without increasing the driving current.

[0023] The present invention designs multi - level p - type implantation regions corresponding to multi - level n - type implantation regions, improving the adjustment accuracy of the built - in potential, avoiding problems such as signal retention and pixel full - well, facilitating the rapid and continuous flow of TDI charges, facilitating speed matching with moving objects, and achieving good TDI functions in altitude applications. In addition, since edge effects occur at the junction of the photodiode and the P - well region, reducing the built - in potential of the photodiode, the length of the short base of the trapezoidal active region can also be adjusted, that is, the included angle of the short base of the trapezoidal active region is adjusted. The narrower the short base of the trapezoidal active region, the greater the proportion of the edge effect and the more the potential decreases, which can further make the potential tilt towards the polysilicon gate.

[0024] The pixel units in the present invention can be scaled in size and arranged and combined in different ways, enabling TDI pixels of different sizes. Compared with traditional TDI image sensor pixels, the structure design is simpler, the performance is better, and the flexibility is higher.

[0025] According to application requirements, the present invention adds an anti - overflow structure, which can effectively improve the anti - overflow ability of pixels.

[0026] Under the condition of keeping the length of the pixel unit unchanged, the present invention can respectively set photodiodes on both sides of the polysilicon gate, reduce the length of the single - side photodiode, shorten the single - side charge horizontal flow distance, reduce the flow time, which is beneficial to realizing a higher - speed TDI operation and greatly improving the anti - aliasing ability of large - size pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic structural diagram of a traditional TDI pixel in the background art;

[0028] Figure 2 is a horizontal cross - sectional top view of a high - speed TDI image sensor pixel unit provided in Embodiment 1 of the present invention;

[0029] Figure 3 is along the Figure 2 in a cross - sectional view of a high - speed TDI image sensor pixel unit provided in Embodiment 1 of the present invention;

[0030] Figure 4 is along the Figure 2 in a cross - sectional view of a high - speed TDI image sensor pixel unit provided in Embodiment 1 of the present invention;

[0031] Figure 5 is along the Figure 2 in a cross - sectional view of a high - speed TDI image sensor pixel unit provided in Embodiment 1 of the present invention;

[0032] Figure 6 is a potential contrast diagram according to Design 1 of the trapezoidal active region or the multi-stage implantation region alone and Design 2 of the trapezoidal active region and the multi-stage implantation region simultaneously provided in Embodiment 1 of the present invention;

[0033] Figure 7 is a schematic diagram of the charge collection and transfer path according to Embodiment 1 of the present invention;

[0034] Figure 8 is a schematic diagram of the pixel unit size expansion according to Embodiment 2 of the present invention;

[0035] Figure 9 is a schematic diagram of the structure of a high-speed TDI image sensor pixel unit provided with an anti-overflow structure according to Embodiment 3 of the present invention;

[0036] Figure 10 is a schematic diagram of the structure of a high-speed TDI image sensor pixel unit provided with a dual photodiode according to Embodiment 4 of the present invention;

[0037] Figure 11 is a high-speed TDI image sensor pixel unit and a stepped potential gradient change diagram according to Embodiment 5 of the present invention;

[0038] Figure 12 is a 5 μm × 5 μm pixel structure design diagram according to Embodiment 6 of the present invention;

[0039] Figure 13 is a 6 μm × 6 μm pixel structure design diagram according to Embodiment 7 of the present invention;

[0040] Figure 14 is a 10 μm × 10 μm pixel structure design diagram according to Embodiment 8 of the present invention.

[0041] The reference numerals therein include:

[0042] polysilicon gate 1, buried channel 2, photodiode 3, photodiode 、P-well region 4, gate oxide insulating layer 5, substrate 6, anti-overflow drain 7, anti-overflow gate 8. Detailed Embodiments

[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same modules are denoted by the same reference numerals. In the case of the same reference numerals, their names and functions are also the same. Therefore, their detailed descriptions will not be repeated.

[0044] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation to the present invention.

[0045] Embodiment 1:

[0046] As Figure 1 shown, traditional TDI pixels usually consist of only polysilicon gate cells. The length of the polysilicon gate cells is relatively large, and the gate capacitance is relatively high, making it impossible to achieve low-power and high-speed applications. Based on the traditional TDI pixel unit, in Embodiment 1 of the present invention, a photodiode is added. One polysilicon gate 1 corresponds to one photodiode 3. Through the joint continuous collection and transfer of charges by the polysilicon gate 1 and the photodiode 3, the size of the polysilicon gate is reduced, facilitating applications in low-power and high-speed scenarios. Specifically, as Figure 2 , Figure 3 , Figure 4 and Figure 5 shown, the high-speed TDI image sensor pixel unit provided in Embodiment 1 of the present invention includes: a polysilicon gate 1, a buried channel 2, a photodiode 3, a P-well region 4, and a gate oxide insulating layer 5 prepared on a substrate 6 through semiconductor processing techniques. Among them, the buried channel 2 is disposed below the polysilicon gate 1, and the photodiode 3 is arranged horizontally in the same layer as the buried channel 2.

[0047] The buried channel 2 below the polysilicon gate 1 has appropriately implanted n-type implanted regions and p-type implanted regions, namely the zero-th n-type implanted region and the zero-th p-type implanted region, denoted as n<0> and p<0> respectively. p<0> is disposed on the upper surface of n<0>. Among them, the implantation conditions of n<0> and p<0> need to meet: making the built-in potential of the buried channel 2 higher than the built-in potential of other implanted regions in the pixel unit, and the built-in potential of the buried channel 2 greater than the built-in potential of any implanted region of the photodiode 3, that is, the potential at the long bottom edge position of the trapezoidal active region is higher than the potential at the short bottom edge position. This design can, firstly, ensure that the signal charges collected by the photodiode 3 can continuously flow to the buried channel 2; secondly, collect the signal charges near the potential well below the polysilicon gate 1; thirdly, perform vertical TDI signal transfer on all charges received in the buried channel 2.

[0048] The active region of the photodiode 3 is an isosceles trapezoid. The short base of the trapezoidal active region is away from the polysilicon gate 1, and the long base is close to the polysilicon gate 1, that is, the long base of the trapezoidal active region is connected to the buried channel 2. The direction along the height of the trapezoid is defined as the length of the active region, and the direction perpendicular to the trapezoid height is defined as the width of the active region. The photodiode 3 is a clamped photodiode. The region outside the trapezoidal active region is a heavily doped P-well region 4. The P-well region 4 can isolate adjacent pixel units, and an edge effect will occur at the junction of the active region and the P-well region 4, which can reduce the built-in potential of the photodiode 3. The narrower the width of the active region, the greater the proportion of the edge effect, so the more the built-in potential is reduced. Designing the active region as a trapezoid can make the built-in potential of the photodiode 3 tilt and increase towards the polysilicon gate 1 side.

[0049] The active region of the photodiode 3 adopts a multi-stage n-type injection region design. Along the length direction of the active region, starting from the long base of the trapezoid close to the buried channel 2 to the short base of the trapezoidal active region, the different n-type injection regions are sequentially denoted as n<1>, n<2>, …, n <n-1> ，n <n>, N≥2. Define the length of the n-type implanted region in the active region along the direction of the trapezoidal height. The lengths of each n-type implanted region can be equal or unequal. All the lengths of the n-type implanted regions can be unequal, or at least two of the lengths of the n-type implanted regions are unequal. By controlling the implantation conditions such as the implantation energy, dose, and angle of different implanted regions, the built-in potential of different implanted regions can be adjusted. From the buried channel 2 to the n at the short bottom side of the trapezoidal active region <n>, the built-in electric potential decreases successively, that is: the electric potential of n<0> > the electric potential of n<1> > the electric potential of n<2> >,..., > n <n-1>The electric potential of > n <n>The electric potential. This electric potential design requirement can ensure that the charges collected by the photodiode 3 flow quickly and continuously towards the buried channel 2, and perform vertical TDI charge transfer from the buried channel 2 to the polysilicon gate 1.

[0050] As a preferred embodiment, the active region can also adopt a single-stage n-type implantation region design, that is, the trapezoidal region of the active region is designed as an n-type implantation region. Further, the zero n-type implantation region n<0> of the buried channel 2 and the n-type implantation region of the active region can be designed as a whole to form an n-type implantation region with the same overall implantation conditions. At this time, the electric potential gradient is realized only through the trapezoidal design of the active region.

[0051] In addition, p-type implantation exists on the silicon-based surface of the n-type implantation region of the photodiode 3, that is, a p-type implantation region is provided above the n-type implantation region. The number of p-type implantation regions can be the same as the number of n-type implantation regions, and the sizes and positions correspond one by one; in addition, the number of p-type implantation regions can also be designed to be different from the number of n-type implantation regions. At this time, the p-type implantation region and the n-type implantation region are in a non-one-to-one correspondence structure, that is, the position and size of one n-type implantation region correspond to the overall size and position of multiple p-type implantation regions; or the positions and sizes of multiple n-type implantation regions correspond to the overall sizes and positions of different numbers of p-type implantation regions. Similar to the design of the n-type implantation region, along the length direction of the active region, starting from the long bottom side of the trapezoid close to the buried channel 2 to the short bottom side of the trapezoidal active region, the different p-type implantation regions are sequentially denoted as p<1>, p<2>, …, p <n-1> ，p <n>. The p-type injection region can prevent the surface defects of the silicon substrate of the photodiode 3 from affecting charge collection and optimize the dark current. In addition, by adjusting the injection conditions of the p-type injection region, the magnitude, distribution of the stepped built-in potential of the photodiode 3 and the potential difference between adjacent injection regions can also be controlled. The n-type injection region and the p-type injection region of the photodiode 3 can be adjusted together to change the built-in potential, or the injection conditions of the n-type injection region or the p-type injection region can be adjusted separately. The stepped potential adjustment flexibility and precision can be improved through the n-type injection region and the p-type injection region. In addition, a gate oxide insulating layer 5 is provided on the upper surface of the p-type injection region to protect the photodiode 3.

[0052] As Figure 6 shown, in order to meet the high-altitude application, the photodiode 3 of the present invention adopts a combined design of a trapezoidal active region and a multi-stage injection region, which can effectively increase the potential difference between adjacent injection regions, thereby increasing the n<0> of the buried channel 2 to the n of the photodiode 3 <n>The potential difference between them increases the built-in potential towards the polysilicon gate 1. Compared with only using a trapezoidal active region or a multi-stage injection region or a traditional design, the combined design of the present invention can increase the amount of potential change, and the effect of increasing the built-in potential towards the polysilicon gate 1 is more obvious. The increase in the built-in potential can effectively increase the electric field strength for the charge to flow towards the polysilicon gate 1, thereby increasing the speed of the charge flowing from the photodiode 3 towards the polysilicon gate 1, enabling the TDI to work properly without signal retention, and avoiding the problem of image aliasing in high-speed application scenarios. During the operation of the TDI pixel unit, for the charge collected by the photodiode of the current pixel unit, under the drive of the clock signal, it is transferred to the next pixel unit through the polysilicon gate 1 to achieve sequential accumulation of signals. However, if the combined design of the trapezoidal active region and the multi-stage injection region is not adopted, the charge collection and flow speeds in the TDI pixel unit cannot match the high-speed movement of the object, and the charge transfer speed cannot keep up with the clock drive speed, that is, before the charge has time to be completely transferred to the polysilicon gate 1 of the current pixel unit, new signal charges have already started to form and transfer in the photodiode 3, resulting in signal retention. The new signal charges will be mixed with the residual signal charges from the previous stage, leading to distortion of the image signal. This distortion will reduce the clarity and quality of the image and affect the dynamic modulation transfer function of the TDI image sensor.

[0053] As Figure 7 shown, based on the traditional TDI pixel unit, the embodiment of the present invention adds a photodiode 3. Charge collection can be carried out simultaneously through the buried channel 2 under the polysilicon gate 1 and the photodiode 3, reducing the size of the polysilicon gate 1, and thus reducing the gate capacitance of the polysilicon gate 1. During the horizontal flow of the charge from the photodiode 3 to the buried channel 2, with the help of the stepped and inclined built-in potential, the charge collected by the photodiode 3 can be quickly flowed to the buried channel 2. In the vertical direction, the charge vertically flows in the buried channels 2 under different polysilicon gates 1. The entire charge collection and transfer process is continuous and fast, and can effectively match the speed of the moving object to achieve good TDI function.

[0054] The above high-speed TDI image sensor pixel unit can be applied to prepare a CMOS TDI image sensor. The sensor is prepared by stacking pixel units. The pixel units in the sensor can be prepared using a back-illumination process. Since both the polysilicon gate 1 and the photodiode 3 need to collect charges during operation, there is no metal shielding on the back-illumination surfaces of the polysilicon gate 1 and the photodiode 3, so that the light signal can be received to the maximum extent. The back-illumination design and the strategy of no metal shielding can significantly improve the quantum efficiency. High quantum efficiency means that more incident photons are converted into charges, thereby improving the sensitivity and dynamic range of the image sensor.

[0055] Embodiment 2:

[0056] Based on Embodiment 1, the dimensions of the TDI pixel unit of the present invention in the length and width directions can be extended later. First, for the length dimension of the TDI pixel unit, without changing the length of each injection region in the active region of the photodiode 3, the number of injection regions can be increased or decreased, that is, the length extension of the TDI pixel unit is achieved. The length of the TDI pixel unit will affect the charge flow time. Therefore, the length of the TDI pixel unit should not be too long. If the length of the TDI pixel unit is too long, a signal retention problem may occur. In addition, the length of the TDI pixel unit will also affect the potential gradient between adjacent injection regions. When the potential difference between adjacent injection regions in the photodiode 3 is too large, it will reduce the potential difference of the buried channel 2 under the polysilicon gate 1, thereby reducing the full well capacity of the pixel. Reducing the full well capacity means that the pixel unit may not be able to store enough charge, resulting in a limited image dynamic range. Therefore, it is necessary to balance the built-in potential gradient in the n-type injection region of the buried channel 2 and the active region, as well as the length of the short bottom side of the trapezoidal active region, to ensure that the built-in potential gradient reaches the optimal effect, that is: it does not affect the effective signal storage potential difference under the polysilicon gate 1, and at the same time, the time for the charge at the far end of the photodiode 3 to flow to under the polysilicon gate 1 can be short enough. Therefore, during the design of the multi-stage n-type injection region and the trapezoidal active region, it is necessary to make the time for the charge to flow horizontally from the short bottom side of the trapezoidal active region to the buried channel 2 less than one-tenth of the time for the charge to flow vertically from the buried channel 2 to the polysilicon gate 1. As Figure 8 shown, for the convenience of subsequent description, different n-type injection regions n<1>, n<2>, …, n <n-1> ，n <n>The lengths are denoted as A1, A2, …, An-1, An, the total length of all n-type injection regions is denoted as Xn, the length of polysilicon gate 1 is denoted as X, and the width of polysilicon gate 1 is denoted as Y. When several consecutive or non-consecutive n-type injection regions can be arbitrarily selected to form a new active region scheme that meets the above conditions, a new scheme with variable pixel size in the length direction can be realized. For example, if A1, A2, and A3 are selected, the pixel horizontal size is (X + A1 + A2 + A3); if A2, A4, and A6 are selected, the pixel horizontal size is (X + A2 + A4 + A6).

[0057] For the width direction size of the TDI pixel unit, the width design of polysilicon gate 1 needs to consider the trade-off between charge transfer efficiency and full well. Generally, the narrower polysilicon gate 1 is, the higher the charge transfer efficiency is. However, an overly narrow polysilicon gate 1 will lead to a decrease in signal storage capacity and full well capacity. Generally, the width of polysilicon gate 1 in the CMOS-TDI process is between 1 and 3 microns, which can achieve better charge transfer efficiency and at the same time meet the requirements of full well capacity. The specific width Y of polysilicon gate 1 needs to be simulated and experimentally verified according to requirements, and appropriate width parameters of polysilicon gate 1 and buried channel 2 are designed to ensure good charge transfer efficiency. It is preferred that the charge transfer efficiency is greater than 0.9999. Based on the obtained width Y, the size of photodiode 3 can be designed.

[0058] In addition, pixel units with the same width can be combined and stacked. The polysilicon gate 1 in each pixel unit corresponds to one clock phase of the TDI pixel. Each TDI pixel can contain multiple stacked pixel units. For example, the stacked width of 2 pixel units is 2Y, the stacked width of 3 pixel units is 3Y, …, the stacked width of m pixel units is mY.

[0059] Embodiment 3:

[0060] Based on Embodiment 1, as Figure 9 As shown, an anti-overflow structure can be added according to the requirements of the application to improve the anti-overflow ability of the pixels. When designing a TDI image sensor, the location selection of the anti-overflow structure is crucial for ensuring the performance of the sensor. Since the pixel unit of the present invention adopts a trapezoidal active region and a multi-stage injection region design, resulting in an inclined potential from the photodiode 3 to the buried channel 2, therefore, the anti-overflow structure should not be placed in the low-potential region at the far end of the photodiode 3, which will prevent it from achieving an effective anti-overflow function; on the contrary, the anti-overflow structure should be placed on the side of the photodiode 3 with the highest potential, that is, the side close to the polysilicon gate 1 and the buried channel 2, which can optimize the collection and transfer of charges, reduce signal retention, and improve the dynamic modulation transfer function level of the pixel unit. Specifically, the anti-overflow structure includes an anti-overflow drain 7 and an anti-overflow gate 8, and the anti-overflow structure can be set on one or both sides of the n-type injection region with the highest potential of the photodiode 3, or the anti-overflow structure can be set on one or both sides of the zero n-type injection region.

[0061] Embodiment 4:

[0062] Based on Embodiment 1, as Figure 10 shown, not only can a photodiode 3 be set on one side of the buried channel 2, but also a symmetric photodiode can be added on the other side of the buried channel 2 , and the photodiode 3 and the photodiode are symmetric about the buried channel 2. Specifically, a photodiode can be added without changing the length of the photodiode 3; or the total length of the charge collection region can be evenly distributed to the photodiode 3 and the photodiode , that is, the lengths of the photodiode 3 and the photodiode on one side of the buried channel 2 are reduced, such a design can effectively shorten the path of the charge flowing from the photodiode 3 and the photodiode on one side to the buried channel 2 under the polysilicon gate 1, thereby reducing the charge flow time, meeting a higher-speed TDI operation, and being beneficial to the ultra-high-speed application of the pixel unit of the high-speed TDI image sensor.

[0063] Embodiment 5:

[0064] Based on Embodiment 1, as Figure 11 As shown in the figure, Embodiment 5 of the present invention shows a pixel unit of 1 micron × 10 microns. The width of the polysilicon gate 1 and the long bottom side of the active region of the photodiode 3 are both 1 micron, the short bottom side of the active region of the photodiode 3 is 0.5 micron, the lengths of the polysilicon gate 1 and the buried channel 2 are both 2 microns, and the active region of the photodiode 3 is designed with 8 n-type implantation regions in total. The lengths of each n-type implantation region are equal, all being 1 micron, that is, A1 = A2 = … = A7 = A8. By adjusting the implantation concentration of each n-type implantation region, the potential of each n-type implantation region increases from 0.6V at the most distal end to 2.0V at the buried channel 2. The potential under the polysilicon gate 1 is 3V at high gate voltage and 2.2V at low gate voltage. Through simulation verification, during the TDI operation, the charge circulation path is unobstructed. The flow time of the charge from the most distal n-type implantation region to the buried channel 2 is 100 nanoseconds, and the time for vertical TDI transfer from the buried channel 2 to the polysilicon gate 1 is 1 microsecond. The time for the charge collected by the photodiode 3 to continuously flow to the buried channel 2 is less than 1 / 10 of the vertical transfer time, and the design reaches the optimization.

[0065] Embodiment 6:

[0066] Based on Embodiment 5, as Figure 12 shown, Embodiment 6 of the present invention shows a pixel of 5 microns × 5 microns. Five pixel units are stacked side by side in the width direction, and each pixel unit corresponds to 1 phase. Through the timing control of 5 phases, the charge transfer of different polysilicon gates 1 is realized. Adjacent pixel units are isolated by the P-well region 4. The lengths of the polysilicon gate 1 and the buried channel 2 are both 2 microns, and the width of the polysilicon gate 1 and the long bottom side of the active region of the photodiode 3 are both 1 micron. In the length direction of the photodiode 3, select Figure 10 the n-type implantation regions numbered A1, A3, and A5 in width, and the length of the active region of the photodiode 3 is 3 microns. This 5 microns × 5 microns pixel can directly meet the requirement of continuous and rapid charge flow with a short time, without the need for additional simulation optimization, simplifies the design complexity, can be quickly integrated into the pixel array of the new pixel, and has low power consumption and good performance.

[0067] Embodiment 7:

[0068] Based on Embodiment 5, as Figure 13 shown, Embodiment 7 of the present invention shows a pixel of 6 microns × 6 microns. Six pixel units are stacked side by side in the width direction, and each pixel unit corresponds to 1 phase. Through the timing control of 6 phases, the charge transfer of different polysilicon gates 1 is realized. Adjacent pixel units are isolated by the P-well region 4. The lengths of the polysilicon gate 1 and the buried channel 2 are both 2 microns, and the width of the polysilicon gate 1 and the long bottom side of the active region of the photodiode 3 are both 1 micron. In the length direction of the photodiode 3, select Figure 10 N-type injection regions with width numbers A1, A2, A3, and A5, and the active region length of the photodiode 3 is 4 microns. At the same time, an anti-overflow structure is added at the position of the n-type injection region with width number A1 close to the polysilicon gate 1 and the buried channel 2, and an anti-overflow structure is respectively arranged on both sides of the photodiode 3, which can effectively improve the anti-overflow ability of the pixel. This 6-micron × 6-micron pixel can directly meet the requirement that the charge continuously flows rapidly with a short time, without the need for additional simulation optimization, simplifies the design complexity, can be quickly integrated into the pixel array of the new pixel, and has low power consumption and good performance.

[0069] Example 8:

[0070] Based on Example 7, as Figure 14 shown, Example 8 of the present invention shows a 10-micron × 10-micron pixel, which is formed by stacking 10 pixel units side by side in the width direction. Every 2 pixel units correspond to 1 phase, that is, each phase controls the charge transfer of two polysilicon gates 1. The number of phases in the pixel is less than the number of polysilicon gates 1, which can save the area of the phase control circuit and simplify the design complexity. Through the timing control of 5 phases, the charge transfer of different polysilicon gates 1 is realized. On both sides of each polysilicon gate 1, a photodiode 3 and a photodiode are symmetrically arranged to shorten the charge horizontal flow distance and improve the anti-signal aliasing ability of large-size pixels. Adjacent pixel units are isolated by the P-well region 4. The lengths of the polysilicon gate 1 and the buried channel 2 are both 2 microns, and the width of the polysilicon gate 1 and the long bottom side of the active region of the photodiode 3 are both 1 micron. In the length direction of the photodiode 3 and the photodiode , select Figure 10 n-type injection regions with width numbers A1, A2, A3, and A5, and the active region lengths of the photodiode 3 and the photodiode are both 4 microns. This 10-micron × 10-micron pixel can directly meet the requirement that the charge continuously flows rapidly with a short time, without the need for additional simulation optimization, simplifies the design complexity, can be quickly integrated into the pixel array of the new pixel, and has low power consumption and good performance.

[0071] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

[0072] The above specific embodiments of the present invention do not constitute a limitation to the protection scope of the present invention. Any other corresponding changes and deformations made according to the technical concept of the present invention should be included in the protection scope of the claims of the present invention.< / n> < / n-1> < / n> < / n> < / n-1> < / n> < / n> < / n> < / n-1>

Claims

1. A high-speed TDI image sensor pixel unit, comprising: A polysilicon gate and a buried channel, wherein the buried channel is arranged below the polysilicon gate, and is characterized in that it also includes a photodiode arranged in a horizontal direction with the buried channel, the active area of ​​the photodiode is trapezoidal, and the long bottom side of the trapezoidal active area is connected to the buried channel, and a P well area for isolating adjacent pixel units is provided around the active area; The active region includes an n-type implantation region distributed along the height direction of the trapezoid, the built-in potential of the buried channel is higher than the built-in potential of the n-type implantation region of the active region, and the potential at the long bottom side of the trapezoidal active region is higher than the potential at the short bottom side; The active area includes at least two n-type implantation areas distributed along the height direction of the trapezoid, and the built-in potential decreases from the long bottom side to the short bottom side of the trapezoidal active area; the built-in potential gradient of the n-type implantation area of ​​the buried channel and the active area must satisfy: the time for the charge to flow horizontally from the short bottom side of the trapezoidal active area to the buried channel is less than one tenth of the time for the charge to flow vertically from the buried channel to the polysilicon gate; A p-type injection region is provided above the n-type injection region of the active region, and the built-in potential can be changed by adjusting the injection conditions of the p-type injection region and the n-type injection region; The number of n-type injection regions and p-type injection regions in the active region is the same, and their relative positions correspond to each other; or the number of n-type injection regions and p-type injection regions in the active region is different, and their relative positions are not in a one-to-one correspondence; By expanding the size and arranging and combining pixel units, TDI pixels of different sizes are realized. Pixel units of the same width are combined and superimposed. The polysilicon gate in each pixel unit corresponds to a clock phase of the TDI pixel. Each TDI pixel contains multiple superimposed pixel units. The lengths of different n-type injection regions are represented as A1, A2, ..., An-1, An, and several continuous or discontinuous n-type injection regions can be arbitrarily selected to form a new active region to achieve variable pixel size in the length direction.

2. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: The buried channel includes a zeroth n-type implantation region and a zeroth p-type implantation region, and the zeroth p-type implantation region is arranged on an upper surface of the zeroth n-type implantation region.

3. The high-speed TDI image sensor pixel unit according to claim 2, characterized in that: The n-type implantation region of the active region and the zeroth n-type implantation region of the buried channel are designed as one body.

4. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: In the active region, different n-type implantation regions have the same length along the height direction of the trapezoid; or in the active region, at least two n-type implantation regions have unequal lengths along the height direction of the trapezoid.

5. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: The active area of ​​the photodiode is an isosceles trapezoid.

6. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: In the height direction of the trapezoid, the length of the polysilicon gate is less than half of the length of the pixel unit.

7. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: It also includes an anti-overflow structure, which includes an anti-overflow gate and an anti-overflow drain. The anti-overflow structure is provided on one side or both sides of the n-type injection region with the highest potential of the photodiode.

8. The high-speed TDI image sensor pixel unit according to claim 1, characterized in that: Two symmetrical photodiodes are arranged on both sides of the buried channel.

9. An image sensor, characterized in that: A high-speed TDI image sensor pixel unit as claimed in any one of claims 1 to 8 is provided.

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