Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device. The display panel comprises a substrate, a plurality of conductive layers arranged on one side of the substrate in a stacked mode and at least one pixel circuit, and the pixel circuit comprises a driving transistor and a first capacitor; the multiple conductive layers arranged on one side of the substrate in a stacked mode comprise the first conductive layer and the second conductive layer, the second conductive layer is located on the side, away from the substrate, of the first conductive layer, the active layer is arranged on the side, away from the substrate, of the second conductive layer, a first pole plate of the first capacitor is located on the first conductive layer, and a second pole plate of the first capacitor is located on the second conductive layer. The first capacitor is located below the driving transistor, so that the first polar plate of the first capacitor can perform bottom shading on the driving transistor, the adverse effect of illumination on the driving transistor is improved, the screen body stability is enhanced, and the display effect is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, people have higher and higher requirements on the display performance of display panels.

[0003] Currently, the display effect of display panels is relatively poor and cannot meet the demand for high-quality display. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device to improve the display effect of the display panel.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising:

[0006] substrate;

[0007] A plurality of conductive layers stacked on one side of the substrate;

[0008] at least one pixel circuit, the pixel circuit comprising a driving transistor and a first capacitor;

[0009] The multi-layer conductive layer comprises a first conductive layer and a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the substrate, the first electrode plate of the first capacitor is located on the first conductive layer, the second electrode plate of the first capacitor is located on the second conductive layer, and the second electrode plate of the first capacitor is connected to the first gate of the driving transistor;

[0010] An active layer is located on a side of the second conductive layer away from the substrate.

[0011] Optionally, the first gate of the driving transistor is located in the second conductive layer, and the second electrode plate of the first capacitor is reused as the first gate of the driving transistor;

[0012] Optionally, the active layer includes a first active layer, the first active layer extends along a first direction, the channel region of the driving transistor is located in the first active layer, and the orthographic projection of the second electrode plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate;

[0013] Optionally, the active layer includes a first active layer, the first active layer extends along a first direction, the channel region of the driving transistor is located in the first active layer, and the orthographic projection of the second electrode plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate;

[0014] Optionally, an orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with an orthographic projection of the second plate of the first capacitor on the substrate.

[0015] Optionally, the first electrode plate of the first capacitor includes a hole area, and the overlapping position of the orthographic projection of the first electrode plate of the first capacitor on the substrate and the orthographic projection of the second electrode plate of the first capacitor on the substrate at least partially covers the orthographic projection of the hole area on the substrate.

[0016] Optionally, the multi-layer conductive layer further includes a third conductive layer, the third conductive layer is located on a side of the active layer away from the substrate, the second gate of the driving transistor is located in the third conductive layer, and the second gate of the driving transistor is connected to the first electrode of the driving transistor;

[0017] Optionally, the multi-layer conductive layer further includes a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, the fourth conductive layer includes a first connecting line, and the second gate of the driving transistor is connected to the first electrode of the driving transistor through the first connecting line;

[0018] Optionally, the second gate of the driving transistor is connected to one end of the first connecting line through a first type via hole, and the first electrode of the driving transistor is connected to the other end of the first connecting line through the first type via hole;

[0019] Optionally, the orthographic projection of the first connecting line on the substrate at least partially covers the orthographic projection of the second gate of the driving transistor on the substrate;

[0020] Optionally, an orthographic projection of the second gate of the driving transistor on the substrate at least partially covers an orthographic projection of the channel region of the driving transistor on the substrate.

[0021] Optionally, the multi-layer conductive layer further includes a third conductive layer, the third conductive layer is located on a side of the active layer away from the substrate, and the first gate of the driving transistor is located on the third conductive layer;

[0022] Optionally, the active layer includes a first active layer, the first active layer extends along a first direction, the channel region of the driving transistor is located in the first active layer, and the orthographic projection of the first gate of the driving transistor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate;

[0023] Optionally, an orthographic projection of the second plate of the first capacitor on the substrate does not overlap with an orthographic projection of the channel region of the driving transistor on the substrate.

[0024] Optionally, the multi-layer conductive layer further includes a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, the fourth conductive layer includes a second connecting line, and the first gate of the driving transistor is connected to the second plate of the first capacitor through the second connecting line;

[0025] Optionally, the first gate of the driving transistor is connected to one end of the second connecting line through a first type via hole, and the second plate of the first capacitor is connected to the other end of the second connecting line through a second type via hole;

[0026] Optionally, an orthographic projection of the second plate of the first capacitor on the substrate does not overlap with an orthographic projection of the channel region of the driving transistor on the substrate;

[0027] Optionally, the orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate;

[0028] Optionally, an orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with an orthographic projection of the second plate of the first capacitor on the substrate;

[0029] Optionally, the orthographic projection of the first plate of the first capacitor on the substrate covers the orthographic projection of the second plate of the first capacitor on the substrate.

[0030] Optionally, the pixel circuit further includes a first transistor, a gate of the first transistor is located in the third conductive layer, the active layer further includes a second active layer, the second active layer extends along a second direction, the first direction intersects with the second direction, the second active layer is in the same layer as the first active layer and is not connected, and a channel region of the first transistor is located in the second active layer;

[0031] Optionally, the first direction intersects the second direction perpendicularly;

[0032] Optionally, the channel region of the first transistor is located at a positive projection position of the gate of the first transistor on the second active layer, the fourth conductive layer further includes a third connecting line and a fourth connecting line, the first electrode of the first transistor is connected to the first gate of the driving transistor through the third connecting line, and the second electrode of the first transistor is connected to the second electrode of the driving transistor through the fourth connecting line;

[0033] Optionally, the first electrode of the first transistor is connected to one end of the third connection line through a first type via, and the first gate of the driving transistor is connected to the other end of the third connection line through the first type via or the second type via; the second electrode of the first transistor is connected to one end of the fourth connection line through the first type via, and the second electrode of the driving transistor is connected to the other end of the fourth connection line through the first type via;

[0034] Optionally, the first transistor is used to compensate for a threshold voltage of the driving transistor;

[0035] Optionally, the display panel further includes a first scan signal line, the first scan signal line is located in the fourth conductive layer, and the first scan signal line is connected to the gate of the first transistor through the first type of via hole;

[0036] Optionally, the first scanning signal line is arranged to cross the gate of the first transistor, and at the crossing position of the first scanning signal line and the gate of the first transistor, the first scanning signal line is connected to the gate of the first transistor through the first type of via hole;

[0037] Optionally, the first scanning signal line extends along a first direction;

[0038] Optionally, the first conductive layer further includes a first shading layer, which is in the same layer as the first plate of the first capacitor and is not connected, and the orthographic projection of the first shading layer on the substrate at least partially covers the orthographic projection of the channel region of the first transistor on the substrate.

[0039] Optionally, the display panel further includes a first initialization signal line, the pixel circuit further includes a second transistor, a gate of the second transistor is located in the third conductive layer, the active layer further includes a third active layer, the third active layer extends along the second direction, the third active layer, the second active layer and the first active layer are in the same layer and are not connected, and a channel region of the second transistor is located in the third active layer;

[0040] Optionally, the second active layer and the third active layer are located on one side of the first active layer;

[0041] Optionally, the channel region of the second transistor is located at the positive projection position of the gate of the second transistor on the third active layer, the first electrode of the second transistor is connected to the first initialization signal line through the first type via hole, the fourth conductive layer further includes a fifth connecting line, the second electrode of the second transistor is connected to the first plate of the first capacitor through the fifth connecting line, and the gate of the second transistor is connected to the first scanning signal line through the first type via hole.

[0042] Optionally, the second electrode of the second transistor is connected to one end of the fifth connection line through the first type via hole, and the first electrode plate of the first capacitor is connected to the other end of the fifth connection line through the second type via hole;

[0043] Optionally, an orthographic projection of the third active layer on the substrate overlaps with an orthographic projection of the first initialization signal line on the substrate;

[0044] Optionally, at a position where the first initialization signal line crosses the third active layer, the first initialization signal line is connected to the first electrode of the second transistor through the first type via hole;

[0045] Optionally, the first scan signal line is arranged to intersect with the gate of the second transistor, and at a position where the first scan signal line intersects with the gate of the second transistor, the gate of the second transistor is connected to the first scan signal line through the first type of via hole;

[0046] Optionally, the first initialization signal line is located in the fourth conductive layer, and the first initialization signal line extends along the first direction;

[0047] Optionally, an orthographic projection of the first light-shielding layer on the substrate at least partially covers an orthographic projection of a channel region of the second transistor on the substrate.

[0048] Optionally, the display panel further includes a second initialization signal line, the orthographic projection of the second initialization signal line on the substrate is located on a side of the orthographic projection of the first gate of the driving transistor on the substrate away from the orthographic projection of the first scanning signal line on the substrate;

[0049] Optionally, the pixel circuit further includes a second capacitor and a third transistor, the gate of the third transistor is located in the third conductive layer, the active layer further includes a fourth active layer, the fourth active layer extends along the second direction, the fourth active layer is in the same layer as the third active layer, the second active layer, and the first active layer and is not connected, and the channel region of the third transistor is located in the fourth active layer;

[0050] Optionally, the channel region of the third transistor is located at the positive projection position of the gate of the third transistor on the fourth active layer, the first electrode of the third transistor is connected to the second initialization signal line through the first type of via, the fourth conductive layer further includes a sixth connecting line and a seventh connecting line, the second electrode of the third transistor is connected to the first electrode plate of the second capacitor through the sixth connecting line, and the second electrode plate of the second capacitor is connected to the second electrode of the driving transistor through the seventh connecting line; the third transistor is used to transmit a fixed voltage to the first electrode plate of the second capacitor;

[0051] Optionally, the second electrode of the third transistor is connected to one end of the sixth connection line through the first type via, the first electrode plate of the second capacitor is connected to the other end of the sixth connection line through the second type via, the second electrode plate of the second capacitor is connected to one end of the seventh connection line through the second type via, and the second electrode of the driving transistor is connected to the other end of the seventh connection line through the first type via;

[0052] Optionally, the orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially covers the orthographic projection of the channel region of the third transistor on the substrate;

[0053] Optionally, an orthographic projection of the fourth active layer on the substrate overlaps with an orthographic projection of the second initialization signal line on the substrate;

[0054] Optionally, at a crossing position between the fourth active layer and the second initialization signal line, the first electrode of the third transistor is connected to the second initialization signal line through the first type via hole;

[0055] Optionally, the display panel further includes a first light-emitting control signal line, the first light-emitting control signal line is located in the fourth conductive layer, and the first light-emitting control signal line is connected to the gate of the third transistor through the first type of via hole;

[0056] Optionally, the first light-emitting control signal line is arranged to cross the gate of the third transistor, and at the intersection of the first light-emitting control signal line and the gate of the third transistor, the first light-emitting control signal line is connected to the gate of the third transistor through the first type of via hole;

[0057] Optionally, the first light emitting control signal line extends along the first direction, and the second initialization signal line extends along the first direction;

[0058] Optionally, the second initialization signal line is located in the fourth conductive layer;

[0059] Optionally, the first light emitting control signal line is located on a side of the second initialization signal line away from the first active layer.

[0060] Optionally, the display panel further includes a data line, the pixel circuit further includes a fourth transistor, a gate of the fourth transistor is located in the third conductive layer, and a channel region of the fourth transistor is located in the fourth active layer;

[0061] Optionally, the channel region of the fourth transistor is located at a positive projection position of the gate of the fourth transistor on the fourth active layer, the fourth conductive layer further includes an eighth connecting line, the first electrode of the fourth transistor is connected to the data line via the eighth connecting line, and the second electrode of the fourth transistor is connected to the second electrode of the third transistor via the fourth active layer; the fourth transistor is used to transmit a data voltage to the first electrode plate of the second capacitor, and the second capacitor is used to write voltage information associated with the data voltage into the first gate of the driving transistor;

[0062] Optionally, the first electrode of the fourth transistor is connected to one end of the eighth connection line through the first type via hole, and the data line is connected to the other end of the eighth connection line through the third type via hole;

[0063] Optionally, the display panel further includes a second scan signal line, the second scan signal line is located in the fourth conductive layer, and the second scan signal line is connected to the gate of the fourth transistor through the first type via hole;

[0064] Optionally, the second scan signal line is arranged to cross the gate of the fourth transistor, and at the intersection of the second scan signal line and the gate of the fourth transistor, the second scan signal line is connected to the gate of the fourth transistor through the first type of via hole;

[0065] Optionally, the first conductive layer further includes a second light shielding layer, the second light shielding layer is in the same layer as the first light shielding layer and the first electrode plate of the first capacitor and is not connected, and an orthographic projection of the second light shielding layer on the substrate at least partially covers an orthographic projection of a channel region of the fourth transistor on the substrate;

[0066] Optionally, the second light shielding layer and the first electrode plate of the second capacitor are in the same layer and connected to form an integrated structure;

[0067] Optionally, the multi-layer conductive layer further includes a fifth conductive layer, the fifth conductive layer is located on a side of the fourth conductive layer away from the substrate, and the data line is located in the fifth conductive layer;

[0068] Optionally, the second scanning signal line extends along the first direction;

[0069] Optionally, the orthographic projection of the first light emitting control signal line on the substrate is located between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate;

[0070] Optionally, along the second direction, the first light emitting control signal line, the second scanning signal line and the second initialization signal line are located on the same side of the first active layer, and the first initialization signal line and the first scanning signal line are located on the other side of the first active layer.

[0071] Optionally, the first electrode plate of the second capacitor is located on the first conductive layer, and the second electrode plate of the second capacitor is located on the second conductive layer;

[0072] Optionally, the second electrode plate of the second capacitor is L-shaped;

[0073] Optionally, an orthographic projection of the second plate of the second capacitor on the substrate at least partially overlaps with an orthographic projection of the second initialization signal line on the substrate;

[0074] Optionally, the second electrode plate of the second capacitor includes a main body extending along the first direction and a branch extending along the second direction, the orthographic projection of the branch on the substrate overlaps with the orthographic projection of the second initialization signal line on the substrate, and the orthographic projection of the main body on the substrate is located between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the first active layer on the substrate;

[0075] Optionally, the branch portion and the main body portion are an integral structure.

[0076] Optionally, the pixel circuit further includes a fifth transistor, a gate of the fifth transistor is located in the third conductive layer, the active layer further includes a fifth active layer, the fifth active layer is in the same layer as the fourth active layer, the third active layer, the second active layer, and the first active layer and is not connected, and a channel region of the fifth transistor is located in the fifth active layer;

[0077] Optionally, the channel region of the fifth transistor is located at a positive projection position of the gate of the fifth transistor on the fifth active layer, the second electrode of the fifth transistor is connected to the first electrode of the second transistor through a ninth connecting line, the first electrode of the fifth transistor is connected to the second electrode of the second transistor through a tenth connecting line, and the gate of the fifth transistor is connected to the second scan signal line through the first type via hole;

[0078] Optionally, the second scan signal line is arranged to intersect with the gate of the fifth transistor, and at the intersection of the second scan signal line and the gate of the fifth transistor, the gate of the fifth transistor is connected to the second scan signal line through the first type of via hole;

[0079] Optionally, an orthographic projection of the second light-shielding layer on the substrate at least partially covers an orthographic projection of the channel region of the fifth transistor on the substrate.

[0080] Optionally, the fourth conductive layer further includes an eleventh connecting line, a twelfth connecting line, a thirteenth connecting line and a fourteenth connecting line, the second pole of the fifth transistor is connected to one end of the eleventh connecting line via the first type via, the other end of the eleventh connecting line is connected to one end of the ninth connecting line via the third type via, the other end of the ninth connecting line is connected to one end of the twelfth connecting line via the third type via, and the other end of the twelfth connecting line is connected to the first pole of the second transistor via the first type via; the first pole of the fifth transistor is connected to one end of the thirteenth connecting line via the first type via, the other end of the thirteenth connecting line is connected to one end of the tenth connecting line via the third type via, the other end of the tenth connecting line is connected to one end of the fourteenth connecting line via the third type via, and the other end of the fourteenth connecting line is connected to the second pole of the second transistor via the first type via;

[0081] Optionally, the ninth connecting line and the tenth connecting line are both located in the fifth conductive layer;

[0082] Optionally, the fifth transistor is used to transmit the first initialization voltage on the first initialization signal line to the light emitting element;

[0083] The fifth active layer and the fourth active layer are located on the other side of the first active layer.

[0084] Optionally, the first initialization signal line includes a first sub-signal line extending along the first direction and a second sub-signal line extending along the second direction, and the first sub-signal line and the second sub-signal line are connected at least at one crossing position to form a mesh structure;

[0085] Optionally, the first sub-signal line and the second sub-signal line are arranged in different layers;

[0086] Optionally, the first sub-signal line is located in the fourth conductive layer, and the second sub-signal line is located in the fifth conductive layer;

[0087] Optionally, the orthographic projection of the first sub-signal line on the substrate is located on a side where the orthographic projection of the first scanning signal line on the substrate is away from the orthographic projection of the first gate of the driving transistor on the substrate;

[0088] Optionally, the orthographic projection of the second sub-signal line on the substrate covers the orthographic projection of a channel region of a portion of the transistor on the substrate;

[0089] Optionally, the second sub-signal line is multiplexed as the ninth connecting line.

[0090] Optionally, the pixel circuit further includes a sixth transistor and a seventh transistor, a gate of the sixth transistor and a gate of the seventh transistor are both located in the third conductive layer, a channel region of the sixth transistor is located in the second active layer, and a channel region of the seventh transistor is located in the fifth active layer;

[0091] Optionally, the display panel further includes a power line, the fourth conductive layer further includes a fifteenth connecting line, the second electrode of the sixth transistor is connected to the power line through the first type of via hole, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor through the fourth connecting line; the second electrode of the seventh transistor is connected to the first electrode of the driving transistor through the fifteenth connecting line, and the first electrode of the seventh transistor is connected to the thirteenth connecting line;

[0092] Optionally, the power line is arranged to cross the second active layer, and at the crossing position of the power line and the second active layer, the second electrode of the sixth transistor is connected to the power line through the first type of via hole;

[0093] Optionally, the first electrode of the sixth transistor is connected to one end of the fourth connection line through the first type via hole, and the second electrode of the driving transistor is connected to the other end of the fourth connection line through the first type via hole; the second electrode of the seventh transistor is connected to one end of the fifteenth connection line through the first type via hole, the first electrode of the driving transistor is connected to the other end of the fifteenth connection line through the first type via hole, and the first electrode of the seventh transistor is connected to the thirteenth connection line through the first type via hole;

[0094] Optionally, the display panel further includes a second light emitting control signal line extending along the first direction, and an orthographic projection of the first light emitting control signal line on the substrate and an orthographic projection of the second light emitting control signal line on the substrate are respectively located on both sides of an orthographic projection of the first active layer on the substrate;

[0095] Optionally, the orthographic projection of the second light emitting control signal line on the substrate is located on a side of the orthographic projection of the first initialization signal line on the substrate away from the orthographic projection of the first scanning signal line on the substrate;

[0096] Optionally, the gate of the sixth transistor is connected to the second light-emitting control signal line through the first type via hole, and the gate of the seventh transistor is connected to the first light-emitting control signal line through the first type via hole;

[0097] Optionally, the second light-emitting control signal line is arranged to cross the gate of the sixth transistor, and at the intersection of the second light-emitting control signal line and the gate of the sixth transistor, the gate of the sixth transistor is connected to the second light-emitting control signal line through the first type of via hole;

[0098] Optionally, the first light-emitting control signal line is arranged to cross the gate of the seventh transistor, and at the intersection of the first light-emitting control signal line and the gate of the seventh transistor, the gate of the seventh transistor is connected to the first light-emitting control signal line through the first type of via hole;

[0099] Optionally, the orthographic projection of the power line on the substrate is located on a side of the orthographic projection of the second light emitting control signal line on the substrate away from the orthographic projection of the first initialization signal line on the substrate;

[0100] Optionally, the orthographic projection of the first light shielding layer on the substrate at least partially covers the orthographic projection of the channel region of the sixth transistor on the substrate;

[0101] Optionally, an orthographic projection of the first plate of the second capacitor on the substrate at least partially covers an orthographic projection of the channel region of the seventh transistor on the substrate.

[0102] The power line includes a third sub-signal line extending along the first direction and a fourth sub-signal line extending along the second direction, the third sub-signal line and the fourth sub-signal line are located in different conductive layers, and the third sub-signal line and the fourth sub-signal line are connected to form a mesh structure at least at one intersection position;

[0103] Optionally, the second electrode of the sixth transistor is connected to the third sub-signal line through the first type via hole;

[0104] Optionally, the orthographic projection of the fourth sub-signal line on the substrate covers the orthographic projection of a channel region of a portion of the transistor on the substrate;

[0105] Optionally, the third sub-signal line is located in the fourth conductive layer, and the fourth sub-signal line is located in the fifth conductive layer.

[0106] Optionally, the display panel further includes a light-emitting element, the light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode that are stacked, and the first electrode is located on a side of the fifth conductive layer away from the substrate;

[0107] The first electrode is connected to one end of the tenth connecting line through a fourth type via hole;

[0108] Optionally, the orthographic projection of the first electrode on the substrate at least covers a portion of the orthographic projection of the channel region of the transistor on the substrate.

[0109] Optionally, the display panel further includes:

[0110] a capacitor insulating layer, the capacitor insulating layer being located between the first conductive layer and the second conductive layer, and an orthographic projection of the capacitor insulating layer on the substrate covering an orthographic projection of the first conductive layer on the substrate;

[0111] a first gate insulating layer, wherein the first gate insulating layer is located between the second conductive layer and the active layer, and an orthographic projection of the first gate insulating layer on the substrate covers an orthographic projection of the second conductive layer on the substrate;

[0112] a second gate insulating layer, wherein the second gate insulating layer is located between the active layer and the third conductive layer, and an orthographic projection of the second gate insulating layer on the substrate covers an orthographic projection of the active layer on the substrate;

[0113] an interlayer insulating layer, wherein the interlayer insulating layer is located between the third conductive layer and the fourth conductive layer, and an orthographic projection of the interlayer insulating layer on the substrate covers an orthographic projection of the third conductive layer on the substrate;

[0114] a first planarization layer, wherein the first planarization layer is located between the fourth conductive layer and the fifth conductive layer, and an orthographic projection of the first planarization layer on the substrate covers an orthographic projection of the fourth conductive layer on the substrate;

[0115] a second planarization layer, wherein the second planarization layer is located on a side of the fifth conductive layer away from the substrate, and an orthographic projection of the second planarization layer on the substrate covers an orthographic projection of the fifth conductive layer on the substrate;

[0116] Optionally, the first type via hole penetrates the interlayer insulating layer, or the first type via hole penetrates the interlayer insulating layer and the second gate insulating layer;

[0117] The second type via hole penetrates the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer and the capacitor insulating layer;

[0118] The third type via hole penetrates the first planarization layer;

[0119] The fourth type via hole penetrates the second planarization layer.

[0120] Optionally, the material of the active layer includes metal oxide.

[0121] According to another aspect of the present invention, a display device is provided. The display device includes the display panel provided by any embodiment of the present invention.

[0122] The technical solution provided by the embodiment of the present invention is that the multilayer conductive layers stacked on one side of the substrate include a first conductive layer and a second conductive layer, the second conductive layer is located on the side of the first conductive layer away from the substrate, the active layer is arranged on the side of the second conductive layer away from the substrate, and the first plate of the first capacitor is arranged on the first conductive layer, and the second plate is arranged on the second conductive layer, so that the first capacitor is located below the driving transistor, so that the first plate of the first capacitor can perform bottom light shielding for the driving transistor, which is beneficial to improving the adverse effects of light on the driving transistor, enhancing the stability of the screen, and further improving the display effect.

[0123] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0124] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0125] Figure 1 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0126] Figure 2 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0127] Figure 3 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0128] Figure 4 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0129] Figure 5 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0130] Figure 6 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0131] Figure 7 A schematic diagram of the structure of a pixel circuit provided by an embodiment of the present invention;

[0132] Figure 8 A schematic diagram of a layout structure of a first capacitor provided in an embodiment of the present invention;

[0133] Fig. 9 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0134] Fig.10 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0135] Fig.11 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0136] Fig.12 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0137] Fig.13 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0138] Fig.14 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0139] Fig.15 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0140] Fig.16 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0141] Fig.17 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0142] Fig.18 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0143] Fig.19 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0144] Fig. 20 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0145] Fig.21 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0146] Fig. 22 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0147] Fig.23 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0148] Fig.24A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention;

[0149] Fig.25 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0150] Fig.26 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0151] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0152] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0153] Figure 1 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 2 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, specifically comprising Figure 1 The cross-sectional structure of the display panel shown along the cutting line AA' is shown in FIG. Figure 1 and Figure 2 , the display panel provided in this embodiment includes:

[0154] Substrate 10;

[0155] A plurality of conductive layers stacked on one side of the substrate 10;

[0156] At least one pixel circuit, the pixel circuit comprising a driving transistor T0 and a first capacitor C1;

[0157] The multi-layer conductive layer includes a first conductive layer and a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the substrate 10, the first electrode 11 of the first capacitor C1 is located on the first conductive layer, the second electrode 21 of the first capacitor C1 is located on the second conductive layer, and the second electrode 21 of the first capacitor C1 is connected to the first gate G1 of the driving transistor T0;

[0158] The active layer 30 is located on a side of the second conductive layer away from the substrate 10 .

[0159] Specifically, the substrate 10 is used to provide protection and support for the display panel, wherein the substrate 10 may be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or may be a hard substrate formed of materials such as glass. A multi-layer conductive layer is provided on one side of the substrate 10, and the multi-layer conductive layers are isolated from each other by an insulating layer. A plurality of pixel circuits are formed in the display panel, and the pixel circuit is used to drive the light-emitting element to emit light. Among them, the pixel circuit includes a driving transistor T0 and a first capacitor C1, and the first capacitor C1 is used to store the gate voltage of the driving transistor T0.

[0160] The first gate G1 of the driving transistor T0 is connected to the second plate 21 of the first capacitor C1, which means that the first gate G1 of the driving transistor T0 and the second plate 21 of the first capacitor C1 can be reused in the same layer, or can be independently arranged in layers and then connected through vias. Figure 1 and Figure 2 As shown, the driving transistor T0 can be a bottom gate driving type, that is, the first gate G1 of the driving transistor T0 is used as the control electrode. In this embodiment, the second plate 21 of the first capacitor C1 is reused as the first gate G1 of the driving transistor T0, and the second plate 21 of the first capacitor C1 is used as the bottom gate of the driving transistor T0. A first metal wire 51 is provided on the side of the active layer 30 away from the substrate 10, and the first metal wire 51 is used for the second gate G2 of the driving transistor T0, and the second gate G2 is used as the top gate of the driving transistor T0.

[0161] For another example, the driving transistor T0 may also be a top gate driving type. Figure 3 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention, Figure 4 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically comprising Figure 3 The cross-sectional structure of the display panel shown along the cutting line BB' is shown in FIG. Figure 3 and Figure 4The driving transistor T0 is not provided with a second gate G2, but only with a first metal wire 51. Here, the first metal wire 51 is used as the first gate G1 of the driving transistor T0, and the first gate G1 of the driving transistor T0 is connected to the second electrode 21 of the first capacitor C1 through a via.

[0162] The technical solution provided by the embodiment of the present invention is that the multilayer conductive layers stacked on one side of the substrate 10 include a first conductive layer and a second conductive layer, the second conductive layer is located on the side of the first conductive layer away from the substrate 10, the active layer 30 is arranged on the side of the second conductive layer away from the substrate, and the first electrode 11 of the first capacitor C1 is arranged on the first conductive layer, and the second electrode 21 is arranged on the second conductive layer, so that the first capacitor C1 is located below the driving transistor T0, so that the first electrode 21 of the first capacitor C1 can perform bottom shading for the driving transistor T0, which is beneficial to improving the adverse effects of light on the driving transistor T0, enhancing the stability of the screen, and thus improving the display effect.

[0163] The following describes the dual-gate and single-gate structures of the driving transistor T0 respectively.

[0164] Continue to refer Figure 1 and Figure 2 , the first gate G1 of the driving transistor T0 is located in the second conductive layer, and the second plate 21 of the first capacitor C1 is reused as the first gate G1 of the driving transistor T0. The first plate 11 and the second plate 21 of the first capacitor C1 are respectively located in different conductive layers, such as the first plate 11 of the first capacitor C1 is located in the first conductive layer, and the second plate 21 of the first capacitor C1 is located in the second conductive layer. The orthographic projection of the first plate 11 of the first capacitor C1 on the substrate 10 and the orthographic projection of the second plate 21 of the first capacitor C1 on the substrate 10 at least partially overlap, and the overlapping area of ​​the two constitutes the effective capacitance of the first capacitor C1. Among them, the active layer 30 includes a first active layer 31, the first active layer 31 extends along the first direction X, the channel region of the driving transistor T0 is located in the first active layer 31, the source region and the drain region of the driving transistor T0 are respectively located on both sides of the channel region, and the first gate G1 of the driving transistor T0 is overlapped with the channel region of the driving transistor T0, that is, the second plate 21 of the first capacitor C1 is projected on the substrate 10 to at least partially cover the projected channel region of the driving transistor T0 on the substrate 10.

[0165] Optionally, the orthographic projection of the first electrode plate 11 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the channel region of the driving transistor T0 on the substrate 10. In this way, the first electrode plate 11 located on the first conductive layer can serve as both the lower electrode plate of the first capacitor C1 and the light shielding layer of the driving transistor T0, which can save layout space and improve layout space utilization. At the same time, it can also avoid changes in the electrical performance of the driving transistor T0 caused by light, which is conducive to improving the reliability of the pixel circuit and thus improving the reliability of the screen.

[0166] Optionally, the material of the active layer 30 includes metal oxide, which is beneficial to reducing the leakage current of the pixel circuit.

[0167] Optionally, the multilayer conductive layer further includes a third conductive layer, the third conductive layer is located on the side of the active layer 30 away from the substrate 10, the second gate G2 of the driving transistor T0 is located in the third conductive layer, the second gate G2 of the driving transistor T0 is connected to the first electrode of the driving transistor T0, and the positive projection of the second gate G2 of the driving transistor T0 on the substrate 10 at least partially covers the positive projection of the channel region of the driving transistor T0 on the substrate 10. Among them, the first electrode of the driving transistor T0 can be a source electrode. Here, the first gate G1 of the driving transistor T0 is used as the bottom gate, the second gate G2 of the driving transistor T0 is used as the top gate, and the bottom gate is used as the control electrode to realize the driving control of the driving transistor T0. By adopting a dual-gate transistor, the control ability of the gate over the channel region can be enhanced, which is beneficial to improving the subthreshold swing of the driving transistor T0, which is beneficial to grayscale development and improving the uniformity of display brightness.

[0168] Optionally, Figure 5 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention, Figure 6 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically comprising Figure 5 The cross-sectional structure of the display panel shown along the cutting line CC' is shown in FIG. Figure 5 and Figure 6 The multi-layer conductive layer further includes a fourth conductive layer, which is located on the side of the third conductive layer away from the substrate 10 . The fourth conductive layer includes a first connecting line 111 , and the second gate G2 of the driving transistor T0 is connected to the first electrode of the driving transistor T0 through the first connecting line 111 .

[0169] Specifically, multiple conductive layers are isolated from each other by insulating layers, such as a capacitor insulating layer 110 is arranged between the first conductive layer and the second conductive layer, a first gate insulating layer 120 is arranged between the second conductive layer and the active layer 30, a second gate insulating layer 130 is arranged between the active layer 30 and the third conductive layer, an interlayer insulating layer 140 is arranged between the third conductive layer and the fourth conductive layer, and a first planarization layer 150 is arranged on the side of the fourth conductive layer away from the substrate 10.

[0170] The first connection line 111 is located in the fourth conductive layer, and is used to connect the second gate G2 and the first electrode of the driving transistor T0, that is, to connect the first metal line 51 and the source of the driving transistor T0. For example, the second gate G2 of the driving transistor T0 is connected to one end of the first connection line 111 through the first type via K1, and the first electrode of the driving transistor T0 is connected to the other end of the first connection line 111 through the first type via K1, that is, the second gate G2 and the first electrode of the driving transistor T0 are connected together in a bridge manner through the first connection line 111. The first type via K1 is a via that penetrates the interlayer insulating layer 140 or penetrates the interlayer insulating layer 140 and the second gate insulating layer 130.

[0171] Optionally, the orthographic projection of the first connection line 111 on the substrate 10 at least partially covers the orthographic projection of the second gate G2 of the driving transistor T0 on the substrate 10 to achieve connection between the first connection line 111 as the second gate G2 of the driving transistor T0 and the first electrode of the driving transistor T0.

[0172] like Figure 6 As shown, in this embodiment, on the first active layer 31, the area covered by the second gate G2 of the driving transistor T0 is used as the channel region of the driving transistor T0 (the portion within the dotted box on the first active layer 31), and the orthographic projection of the second gate G2 of the driving transistor T0 on the substrate 10 covers the orthographic projection of the channel region of the driving transistor T0 on the substrate 10.

[0173] Figure 7 A schematic diagram of a pixel circuit according to an embodiment of the present invention is provided. Figure 5 and Figure 7 On the basis of the above embodiments, the first gate G1 of the driving transistor T0 is connected to the second plate 21 of the first capacitor C1 (the second plate 21 of the first capacitor C1 here is reused as the first gate G1 of the driving transistor T0), the first plate 11 of the first capacitor C1 is connected to the second node N2, and the first capacitor C1 is used to store the voltage of the first gate G1 of the driving transistor T0.

[0174] Figure 8 A schematic diagram of a layout structure of a first capacitor provided in an embodiment of the present invention, referring to Figure 8On the basis of the above embodiments, optionally, the first electrode plate 11 of the first capacitor C1 includes a hole area K0, and the overlapping position of the orthographic projection of the first electrode plate 11 of the first capacitor C1 on the substrate 10 and the orthographic projection of the second electrode plate 21 of the first capacitor C1 on the substrate 10 at least partially covers the orthographic projection of the hole area K0 on the substrate 10. That is, on the first electrode plate 11 of the first capacitor C1, the first conductive layer at the position of the hole area K0 is removed to reduce the overlapping area between the first electrode plate 11 of the first capacitor C1 and the second electrode plate 21 of the first capacitor C1.

[0175] Specifically, according to the capacitance calculation formula, the capacitance of the capacitor is related to the overlapping area of ​​the upper and lower plates. Therefore, by setting the hole area K0 on the first plate 11 of the first capacitor C1, the capacitance of the first capacitor C1 can be adjusted to meet different functional requirements of the pixel circuit.

[0176] Continue to refer Figure 7 The pixel circuit further includes a first transistor T1, which is connected between a first gate electrode G1 of the driving transistor T0 and a first node N1 (a second electrode of the driving transistor T0 and a first electrode of the first transistor T1 are connected to the first node N1). The gate electrode of the first transistor T1 is connected to a first scanning signal line S1, and the first transistor T1 is used to compensate for a threshold voltage of the driving transistor T0 in response to the first scanning signal line S1.

[0177] Fig. 9 A schematic diagram of a planar structure of another display panel provided in an embodiment of the present invention, referring to Figure 7 and Fig. 9 Optionally, the active layer 30 further includes a second active layer 32, and the second active layer 32 extends along a second direction Y. The first direction X and the second direction Y intersect, specifically, intersect vertically. The second active layer 32 is in the same layer as the first active layer 31 and is not connected thereto, and the channel region of the first transistor T1 is located on the second active layer 32.

[0178] Among them, the channel region of the first transistor T1 is located at the positive projection position of the gate of the first transistor T1 on the second active layer 32, and the gate of the first transistor T1 is located in the third conductive layer. For example, the second metal wire 52 located in the third conductive layer is the gate of the first transistor T1, and on the second active layer 32, the position where the second active layer 32 and the second metal wire 52 intersect is the channel region of the first transistor T1.

[0179] Fig.10 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention, Fig.11 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, Fig.12 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, wherein: Fig.11 Specifically Fig.10 The cross-sectional structure of the display panel along the cutting line DD' is shown. Fig.12 Specifically Fig.10 The cross-sectional structure of the display panel shown along the cutting line EE' is shown in FIG. Fig.10 , Fig.11 and Fig.12 The fourth conductive layer further includes a third connection line 113 and a fourth connection line 114. The first electrode of the first transistor T1 is connected to the first gate G1 of the driving transistor T0 through the third connection line, and the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T0 through the fourth connection line 114. The second electrode of the driving transistor T0 may be a drain.

[0180] Specifically, the third connection line 113 and the fourth connection line 114 are both located in the fourth conductive layer, and both extend along the second direction Y. Fig.11 As shown, the first electrode of the first transistor T1 (located on the second active layer 32) is connected to one end of the third connection line 113 through the first type via K1, and the first gate G1 of the driving transistor T0 is connected to the other end of the third connection line 113 through the second type via K2, thereby realizing the connection between the first electrode of the first transistor T1 and the first gate G1 of the driving transistor T0. The second type via K2 is a via that penetrates the interlayer insulating layer 140, the second gate insulating layer 130, the first gate insulating layer 120 and the capacitor insulating layer 110. Fig.12 As shown, the second electrode of the first transistor T1 (located on the second active layer 32) is connected to one end of the fourth connection line 114 via the first type via K1, and the second electrode of the driving transistor T0 (located on the first active layer 31) is connected to the other end of the fourth connection line 114 via the first type via K1, so as to realize the connection between the second electrode of the first transistor T1 and the second electrode of the driving transistor T0. In this embodiment, the cross-bridge connection between the first transistor T1 and the driving transistor T0 is realized by using the third connection line 113 and the fourth connection line 114 located on the fourth conductive layer, which is conducive to optimizing the circuit layout and reducing the parasitic capacitance in the circuit.

[0181] Continue to refer Figure 7 The pixel circuit further includes a second transistor T2, which is connected to a second node N2, which is also connected to the light emitting diode D1, and the second transistor T2 is used to initialize the first electrode (anode) of the light emitting diode D1.

[0182] Specifically, combined Fig. 9 and Fig.10The active layer 30 further includes a third active layer 33, the third active layer 33 extends along the second direction Y, the first active layer 31, the second active layer 32 and the third active layer 33 are in the same layer and are not connected, and the channel region of the second transistor T2 is located in the third active layer 33. Optionally, the second active layer 32 and the third active layer 33 are located on the same side of the first active layer 31 to optimize the layout.

[0183] The channel region of the second transistor T2 is located at the positive projection position of the gate of the second transistor T1 on the third active layer 33, and the gate of the second transistor T2 is located in the third conductive layer. For example, the second metal wire 52 located in the third conductive layer serves as the gate of the second transistor T2.

[0184] Fig.13 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, wherein: Fig.13 Specifically Fig.10 The cross-sectional structure of the display panel shown along the cutting line FF' is combined with Fig.10 and Fig.13 The fourth conductive layer also includes a fifth connecting line 115, the display panel also includes a first initialization signal line VRE1, the first electrode of the second transistor T2 is connected to the first initialization signal line VRE1 through the first type via K1, and the second electrode of the second transistor T2 is connected to the first electrode plate 11 of the first capacitor C1 through the fifth connecting line 115.

[0185] Specifically, the second electrode of the second transistor T2 is connected to one end of the fifth connection line 115 through the first type via K1, and the first electrode plate 11 of the first capacitor C1 is connected to the other end of the fifth connection line 115 through the second type via K2, thereby realizing the connection between the second transistor T2 and the first capacitor C1.

[0186] Optionally, the orthographic projection of the third active layer 33 on the substrate 10 overlaps with the orthographic projection of the first initialization signal line VRE1 on the substrate 10, and at the position where the first initialization signal line VRE1 crosses the third active layer 33 (i.e., the position where the projections of the two overlap), the first initialization signal line VRE1 is connected to the first electrode of the second transistor T2 through the first type via K1, without the need for connection through a crossover line. The first initialization signal line VRE1 is located in the fourth conductive layer and extends along the first direction X.

[0187] Continue to refer Fig.10The display panel further includes a first scan signal line S1, and the first scan signal line S1 is located in the fourth conductive layer. In this embodiment, since the gates of the first transistor T1 and the second transistor T2 are both connected to the first scan signal line S1, and the gates of the first transistor T1 and the second transistor T2 are both the second metal line 52, that is, the gates of the two transistors are connected as an integral structure, the first scan signal line S1 can be connected to the gates of the first transistor T1 and / or the second transistor T2.

[0188] Optionally, the first scanning signal line S1 can be connected to any one of the gates of the first transistor T1 and the second transistor T2 to reduce the number of openings, which is beneficial to improving the signal transmission quality. Fig.10 As shown, the first scan signal line S1 is connected to the gate of the second transistor T2 via the first type via K1. Optionally, the first scan signal line S1 and the gate of the second transistor T2 are arranged to intersect, and at the position where the first scan signal line S1 and the gate of the second transistor T2 intersect, the gate of the second transistor T2 is connected to the first scan signal line S1 via the first type via K1.

[0189] Of course, in other embodiments, the first scan signal line S1 may also be connected to the gate of the first transistor T1 via the first type via. For example, the first scan signal line S1 is arranged to intersect the gate of the first transistor T1 and the second transistor T2, respectively, and at the intersection of the first scan signal line S1 and the gate of the first transistor T1, the first scan signal line S1 is connected to the gate of the first transistor T1 via the first type via K1.

[0190] Optionally, continue to refer to Fig.11 and Fig.13 The first conductive layer also includes a first light-shielding layer 12. The first light-shielding layer 12 is in the same layer as the first electrode plate 11 of the first capacitor C1 and is not connected thereto. The orthographic projection of the first light-shielding layer 12 on the substrate 10 at least partially covers the orthographic projection of the channel region of the first transistor T1 and the channel region of the second transistor T2 on the substrate 10, so as to perform bottom light shielding on the first transistor T1 and the second transistor T2, so as to avoid changes in the electrical performance of the first transistor T1 and the second transistor T2 caused by light, which is beneficial to improving the reliability of the pixel circuit and thus improving the reliability of the screen.

[0191] Continue to refer Figure 7The pixel circuit provided in this embodiment further includes a second capacitor C2, a third transistor T3 and a fourth transistor T4, the display panel further includes a second initialization signal line VRE2 and a data line data, the first electrode of the third transistor T3 is connected to the second initialization signal line VRE2, the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 are connected to the third node N3, the first electrode of the fourth transistor T4 is connected to the data line data, and the second capacitor C2 is connected between the first node N1 and the third node N3. Among them, the third transistor T3 is used to transmit a fixed voltage to the third node N3, the fourth transistor T4 is used to transmit a data voltage to the third node N3, and the second capacitor C2 is used to couple the voltage change of the third node N3 to the first node N1, and transmit it to the first gate G1 of the driving transistor T0 through the first transistor T1, so that the voltage of the first gate G1 of the driving transistor T0 is associated with the data voltage.

[0192] Fig.14 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention, Fig.15 A schematic diagram of a planar structure of another display panel provided in an embodiment of the present invention, referring to Fig.14 and Fig.15 On the basis of the above embodiments, optionally, the active layer 30 further includes a fourth active layer 34, the fourth active layer 32 extends along the second direction, the fourth active layer 34, the third active layer 33, the second active layer 32 and the first active layer 31 are in the same layer and are not connected, and the channel region of the third transistor T3 is located in the fourth active layer 34.

[0193] Specifically, the channel region of the third transistor T3 is located at the positive projection position of the gate of the third transistor T3 on the fourth active layer 34, and the first electrode of the third transistor T3 is connected to the second initialization signal line VRE2 through the first type via K1. For example, the positive projection of the fourth active layer 34 on the substrate 10 overlaps with the positive projection of the second initialization signal line VRE2 on the substrate 10, and at the intersection of the fourth active layer 34 and the second initialization signal line VRE2, the first electrode of the third transistor T3 is connected to the second initialization signal line VRE2 through the first type via K1, without cross-line connection.

[0194] The fourth conductive layer further includes a sixth connecting line 116 and a seventh connecting line 117. The second electrode of the third transistor T3 is connected to the first electrode plate 13 of the second capacitor C2 via the sixth connecting line 116, and the second electrode plate 22 of the second capacitor C2 is connected to the second electrode of the driving transistor T0 via the seventh connecting line 117. The first electrode plate 13 of the second capacitor C2 is located in the first conductive layer, and the second electrode plate 22 of the second capacitor C2 is located in the second conductive layer.

[0195] Optionally, the display panel further includes a first light emitting control signal line EM1, which is located in the fourth conductive layer and connected to the gate of the third transistor T3 through the first type via K1. The fourth metal line 54 located in the third conductive layer serves as the gate of the third transistor T3.

[0196] Fig.16 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically: Fig.15 The cross-sectional structure of the display panel shown along the cutting line GG' is shown in FIG. Fig.17 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically: Fig.15 The cross-sectional structure of the display panel shown in FIG. 1 is obtained along the section line HH'. Fig.15 , Fig.16 and Fig.17 The second electrode of the third transistor T3 is connected to one end of the sixth connection line 116 via the first type via K1, the first electrode plate 13 of the second capacitor C2 is connected to the other end of the sixth connection line 116 via the second type via K2, the second electrode plate 22 of the second capacitor C2 is connected to one end of the seventh connection line 117 via the second type via K2, and the second electrode of the driving transistor T0 is connected to the other end of the seventh connection line 117 via the first type via K1.

[0197] Specifically, the orthographic projection of the fourth active layer 34 on the substrate 10 overlaps with the orthographic projection of the second initialization signal line VRE2 on the substrate 10, and at the intersection of the fourth active layer 34 and the second initialization signal line VRE2, the first electrode of the third transistor T3 is connected to the second initialization signal line VRE2 through the first type via K1. The first light-emitting control signal line EM1 and the gate of the third transistor T3 are arranged to intersect, and at the intersection of the first light-emitting control signal line EM1 and the gate of the third transistor T3, the first light-emitting control signal line EM1 is connected to the gate of the third transistor T3 through the first type via K1.

[0198] Optionally, the first light-emitting control signal line EM1 and the second initialization signal line VRE2 both extend along the first direction X and are both located in the fourth conductive layer. The first light-emitting control signal line EM1 is located on the side of the second initialization signal line VRE2 away from the first active layer 31 to facilitate wiring, thereby improving layout space utilization.

[0199] Fig.18 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention, Fig.19 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention, wherein: Fig.18 Only the structures of the fourth conductive layer and the fifth conductive layer are shown. Figure 15-19The channel region of the fourth transistor T4 is located at the positive projection position of the gate of the fourth transistor T4 on the fourth active layer 34, wherein the gate of the fourth transistor T4 is located in the third conductive layer, for example, the fourth metal line 54 located in the third conductive layer serves as the gate of the fourth transistor T4.

[0200] In this embodiment, the fourth transistor T4 further includes an eighth connection line 118, the first electrode of the fourth transistor T4 is connected to the data line data via the eighth connection line 118, and the second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3 via the fourth active layer 34. The display panel further includes a second scan signal line S2, the second scan signal line S2 is located in the fourth conductive layer, and the second scan signal line S2 is connected to the gate of the fourth transistor T4 through the first type via K1, that is, the second scan signal line S2 is connected to the fourth metal line 54 through the first type via K1. The second scan signal line S2 extends along the first direction X.

[0201] Specifically, continue to refer to Fig.16 , the first electrode and the second electrode of the fourth transistor T4 are both located in the fourth active layer 34, and are respectively located on both sides of the channel region of the fourth transistor T4. The first electrode of the fourth transistor T4 is connected to one end of the eighth connection line 118 through the first type via K1. Since the fourth transistor T4 and the third transistor T3 share the fourth active layer 34, the second electrode of the fourth transistor T4 is directly connected to the second electrode of the third transistor T3 through the fourth active layer 34. The second scanning signal line S2 is arranged to cross the gate of the fourth transistor T4. At the intersection of the second scanning signal line S2 and the gate of the fourth transistor T4, the second scanning signal line S2 is connected to the gate of the fourth transistor T4 through the first type via K2, and there is no need to set a crossover line, which is conducive to reducing the number of vias.

[0202] Optionally, the orthographic projection of the first light-emitting control signal line EM1 on the substrate 10 is located between the orthographic projection of the second initialization signal line VRE2 on the substrate 10 and the orthographic projection of the second scanning signal line S2 on the substrate 10; along the second direction Y, the first light-emitting control signal line EM1, the second scanning signal line S2 and the second initialization signal line VRE2 are located on the same side of the first active layer 31, and the first initialization signal line VRE1 and the first scanning signal line S1 are located on the other side of the first active layer 31. The purpose of this arrangement is to optimize the position of each transistor in the layout to reduce the layout space occupied, thereby improving the layout space utilization and improving the maximum PPI of the screen.

[0203] Fig. 20 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically: Fig.19 The cross-sectional structure of the display panel shown along the cutting line II' is shown in FIG. Fig.19 and Fig. 20Since the data line data extends along the second direction Y, the data line data and the second scanning signal line S2 are arranged in different layers to simplify the wiring. For example, the data line data can be located in the fifth conductive layer, the fifth conductive layer is located on the side of the fourth conductive layer away from the substrate 10, and a first planarization layer 150 is arranged between the fifth conductive layer and the fourth conductive layer. The first electrode of the fourth transistor T4 is connected to one end of the eighth connection line 118 through the first type via K1, and the data line data is connected to the other end of the eighth connection line 118 through the third type via K3, thereby realizing the connection between the fourth transistor and the data line data.

[0204] Optionally, the first plate 13 of the second capacitor C2 is located in the first conductive layer, the second plate 22 of the second capacitor C2 is located in the second conductive layer, and the overlapping position of the first plate 13 of the second capacitor C2 and the second plate 22 thereof constitutes an effective area of ​​the second capacitor C2. In this embodiment, due to the presence of the first type via K1 between the second initialization signal line VRE2 and the fourth active layer 34, the second plate 22 of the second capacitor C2 is arranged in an L shape. The orthographic projection of the second plate 22 of the second capacitor C2 on the substrate 10 at least partially overlaps with the orthographic projection of the second initialization signal line VRE2 on the substrate 10, so that the capacitance of the second capacitor C2 meets the requirements.

[0205] For example, in combination Fig.15 The second electrode 22 of the second capacitor C2 includes a main body 221 extending along the first direction X and a branch 222 extending along the second direction Y. The orthographic projection of the branch 222 on the substrate 10 overlaps with the orthographic projection of the second initialization signal line VRE2 on the substrate 10. The orthographic projection of the main body 221 on the substrate 10 is located between the orthographic projection of the second initialization signal line VRE2 on the substrate 10 and the orthographic projection of the first active layer 31 on the substrate 10. The main body 221 and the branch 222 are an integrated structure.

[0206] Continue to refer Fig.15 and Fig.19In this embodiment, the orthographic projection of the first electrode plate 13 of the second capacitor C2 on the substrate 10 at least partially covers the orthographic projection of the channel region of the third transistor T3 on the substrate 10. The first conductive layer further includes a second light shielding layer 14, which is in the same layer as the first light shielding layer 12 and the first electrode plate 11 of the first capacitor C1 and is not connected. The orthographic projection of the second light shielding layer 14 on the substrate 10 at least partially covers the orthographic projection of the channel region of the fourth transistor T4 on the substrate 10. Optionally, the orthographic projection of the first electrode plate 13 of the second capacitor C2 on the substrate 10 completely covers the orthographic projection of the channel region of the third transistor T3 on the substrate 10, and the orthographic projection of the second light shielding layer 14 on the substrate 10 completely covers the orthographic projection of the channel region of the fourth transistor T4 on the substrate 10, so as to achieve bottom shielding of the third transistor T3 and the fourth transistor T4, avoid changes in the electrical performance of the third transistor T3 and the fourth transistor T4 caused by light, which is conducive to improving the reliability of the pixel circuit, and thus improving the reliability of the screen.

[0207] Continue to refer Figure 7 , Fig.16 and Fig.19 On the basis of the above embodiments, optionally, the pixel circuit provided in this embodiment further includes a fifth transistor T5, the first electrode of the fifth transistor T5 is connected to the second electrode of the second transistor T2, the second electrode of the fifth transistor T5 is connected to the first electrode of the second transistor T2, and the fifth transistor T5 is used to initialize the light-emitting diode D1 within the holding frame to achieve low-frequency driving.

[0208] The active layer 30 further includes a fifth active layer 35, which is in the same layer as and not connected to the fourth active layer 34, the third active layer 34, the second active layer 32 and the first active layer 31, and the channel region of the fifth transistor T5 is located in the fifth active layer 35. The fifth active layer 35 and the fourth active layer 34 are located on the other side of the first active layer 31, and are located on a different side of the first active layer 31 from the third active layer 34 and the second active layer 32.

[0209] Specifically, the channel region of the fifth transistor T5 is located at the positive projection position of the gate of the fifth transistor T5 on the fifth active layer 35, and the fifth metal line located in the third conductive layer can serve as the gate of the fifth transistor T5. The second electrode of the fifth transistor T5 is connected to the first electrode of the second transistor through the ninth connecting line, the first electrode of the fifth transistor is connected to the second electrode of the second transistor through the tenth connecting line, and the gate of the fifth transistor is connected to the second scan signal line through the first type via. The second scan signal line is arranged to cross the gate of the fifth transistor, and at the intersection of the second scan signal line and the gate of the fifth transistor, the gate of the fifth transistor is connected to the second scan signal line through the first type via.

[0210] Specifically, the ninth connection line 119 and the tenth connection line 120 are both located in the fifth conductive layer. The fourth conductive layer also includes an eleventh connecting line 121, a twelfth connecting line 122, a thirteenth connecting line 123 and a fourteenth connecting line 124. The second electrode of the fifth transistor T5 is connected to one end of the eleventh connecting line 121 via the first type via K1, the other end of the eleventh connecting line 121 is connected to one end of the ninth connecting line 119 via the third type via K3, the other end of the ninth connecting line 119 is connected to one end of the twelfth connecting line 122 via the third type via K3, and the other end of the twelfth connecting line 122 is connected to the first electrode of the second transistor T2 via the first type via K1; the first electrode of the fifth transistor T5 is connected to one end of the thirteenth connecting line 123 via the first type via K1, the other end of the thirteenth connecting line 123 is connected to one end of the tenth connecting line 120 via the third type via K3, the other end of the tenth connecting line 120 is connected to one end of the fourteenth connecting line 124 via the third type via K3, and the other end of the fourteenth connecting line 124 is connected to the second electrode of the second transistor T2 via the first type via K2.

[0211] The connection between the fifth transistor T5 and the second transistor T2 is the same as the connection between the fourth transistor T4 and the data line data, both of which are switched through the fourth conductive layer and the fifth conductive layer, which will not be described in detail.

[0212] Optionally, the orthographic projection of the second light-shielding layer 14 on the substrate 10 at least partially covers the orthographic projection of the channel region of the fifth transistor T5 on the substrate 10. Optionally, the orthographic projection of the second light-shielding layer 14 on the substrate 10 completely covers the orthographic projection of the channel region of the fifth transistor T5 on the substrate 10, so as to shield the bottom of the fifth transistor T5, avoid changes in the electrical performance of the fifth transistor T5 caused by light, and help improve the reliability of the pixel circuit, thereby improving the reliability of the screen.

[0213] Optionally, since the second electrode of the second transistor T2, the first electrode of the fifth transistor T5 and the first electrode plate 11 of the first capacitor C1 are connected to the second node N2, the fourteenth connection line 124 and the fifth connection line 115 may be the same connection line.

[0214] Optionally, continue to refer to Fig.19In this embodiment, the first initialization signal line VRE1 includes a first sub-signal line VRE1-1 extending along the first direction X and a second sub-signal line VRE1-2 extending along the second direction Y, and the first sub-signal line VRE1-1 and the second sub-signal line VRE1-2 are connected at least at one intersection to form a mesh structure. The first sub-signal line VRE1-1 and the second sub-signal line VRE1-2 are arranged in different layers, for example, the first sub-signal line VRE1-1 is located in the fourth conductive layer, and the second sub-signal line VRE1-2 is located in the fifth conductive layer. Since the fifth transistor T5 and the second transistor T2 are both connected to the first initialization signal line VRE1, the second sub-signal line VRE1-2 can be reused as the ninth connection 119 at the position where the first electrode of the fifth transistor T5 is connected to the second electrode of the second transistor T2, which is beneficial to reduce the number of connection lines to improve PPI.

[0215] Optionally, the orthogonal projection of the first sub-signal line VRE1 - 1 on the substrate 10 is located on a side of the orthogonal projection of the first scanning signal line S1 on the substrate 10 away from the orthogonal projection of the first gate G1 of the driving transistor T0 on the substrate 10 .

[0216] The orthographic projection of the second sub-signal line VRE1-2 on the substrate 10 covers the orthographic projection of the channel region of some transistors on the substrate 10 to perform top shielding on these transistors. For example, the orthographic projection of the second sub-signal line VRE1-2 on the substrate 10 at least covers the orthographic projection of the channel region of the second transistor T2 on the substrate 10. Combined with the bottom shielding of the channel region of the second transistor T2 by the first shading layer 12, the influence of light on the second transistor T2 can be avoided.

[0217] In this embodiment, the orthographic projection of the first scanning signal line S1 on the substrate 10 is located between the orthographic projection of the first active layer 31 on the substrate 10 and the orthographic projection of the first sub-signal line VRE1-1 (the first initialization signal line VRE1 extending along the first direction X) on the substrate 10, so that the first scanning signal line S1 is arranged close to the first gate G1 of the driving transistor T0, thereby reducing the cross-line connected to the first sub-signal line VRE1-1, and further reducing the parasitic capacitance at the first gate G1 and the second gate G2 of the driving transistor T0, which is beneficial to reducing the display crosstalk problem and improving the brightness uniformity.

[0218] Continue to refer Fig.19The pixel circuit provided in this embodiment further includes a sixth transistor T6 and a seventh transistor T7, and the display panel further includes a power line VDD. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor T0, and the second electrode of the sixth transistor T0 is connected to the power line VDD. The first electrode of the seventh transistor T7 is connected to the second node N2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the driving transistor T0. The sixth transistor T6 and the seventh transistor T7 are used to control the power supply voltage on the power line VDD to be transmitted to the light-emitting diode D1.

[0219] Specifically, combined Fig.16 and Fig.19 , the fourth conductive layer further includes a fifteenth connection line 125, the second electrode of the sixth transistor T6 is connected to the power line VDD through the first type via K1, and the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T0 through the fourth connection line 114; the second electrode of the seventh transistor T7 is connected to the first electrode of the driving transistor T0 through the fifteenth connection line 125, and the first electrode of the seventh transistor T7 is connected to the thirteenth connection line 123;

[0220] Exemplarily, the first electrode of the sixth transistor T6 is connected to one end of the fourth connection line 114 via the first type via K1, and the second electrode of the driving transistor T0 is connected to the other end of the fourth connection line 114 via the first type via K1; the second electrode of the seventh transistor T7 is connected to one end of the fifteenth connection line 125 via the first type via K1, the first electrode of the driving transistor T0 is connected to the other end of the fifteenth connection line 125 via the first type via K1, and the first electrode of the seventh transistor T7 is connected to the thirteenth connection line 123 via the first type via K1.

[0221] Optionally, the power line VDD includes a third sub-signal line VDD1 extending along the first direction X and a fourth sub-signal line VDD2 extending along the second direction Y, the third sub-signal line VDD1 and the fourth sub-signal line VDD2 are located in different conductive layers, and the third sub-signal line VDD1 and the fourth sub-signal line VDD2 are connected to form a mesh structure at least at one intersection. For example, at the intersection of the third sub-signal line VDD1 and the fourth sub-signal line VDD2, the two are connected through a third type via K3 to form a mesh structure. The third sub-signal line VDD1 can be located in the fourth conductive layer, and the fourth sub-signal line VDD2 can be located in the fifth conductive layer.

[0222] The third sub-signal line VDD1 included in the power line VDD is arranged to cross the second active layer 32. At the intersection of the third sub-signal line VDD1 and the second active layer 32, the second electrode of the sixth transistor T6 is connected to the third sub-signal line VDD1 through the first type via K1, which is beneficial to reducing the number of cross-lines in the layout and reducing the parasitic capacitance of the sixth transistor T6.

[0223] The display panel further includes a second light-emitting control signal line extending along the first direction, the orthographic projection of the first light-emitting control signal line on the substrate and the orthographic projection of the second light-emitting control signal line on the substrate are respectively located on both sides of the orthographic projection of the first active layer on the substrate; the orthographic projection of the second light-emitting control signal line on the substrate is located on a side of the orthographic projection of the first initialization signal line on the substrate away from the orthographic projection of the first scanning signal line on the substrate;

[0224] Among them, the gate of the sixth transistor T6 is connected to the second light-emitting control signal line EM2 through the first type via K1, and the gate of the seventh transistor T7 is connected to the first light-emitting control signal line EM1 through the first type via K1. Exemplarily, the second light-emitting control signal line EM2 and the gate of the sixth transistor T6 are arranged to intersect, and at the intersection of the second light-emitting control signal line EM2 and the gate of the sixth transistor T6, the gate of the sixth transistor T6 is connected to the second light-emitting control signal line EM2 through the first type via K1; the first light-emitting control signal line EM1 and the gate of the seventh transistor T7 are arranged to intersect, and at the intersection of the first light-emitting control signal line EM1 and the gate of the seventh transistor T7, the gate of the seventh transistor T7 is connected to the first light-emitting control signal line EM1 through the first type via K1. Here, the connection method of the first light-emitting control signal line EM and the gate of the seventh transistor T7 is the same as the connection method of the first light-emitting control signal line EM and the gate of the third transistor T3, and has the same cross-sectional structure. For details, please refer to Fig.17 Similarly, the connection mode between the second light emitting control signal line EM2 and the gate of the sixth transistor T6 is the same as the connection mode between the first light emitting control signal line EM and the gate of the third transistor T3, which will not be described in detail.

[0225] Optionally, the orthographic projection of the third sub-signal line VDD1 on the substrate 10 is located on a side of the orthographic projection of the second light-emitting control signal line EM2 on the substrate 10 away from the orthographic projection of the first initialization signal line VRE1 on the substrate 10, specifically, on a side of the orthographic projection of the second light-emitting control signal line EM2 on the substrate 10 away from the orthographic projection of the first sub-signal line VRE1-1 on the substrate 10.

[0226] Optionally, in this embodiment, the orthographic projection of the first light shielding layer 12 on the substrate 10 at least partially covers the orthographic projection of the channel region of the sixth transistor T6 on the substrate 10; the orthographic projection of the first electrode plate 13 of the second capacitor C2 on the substrate 10 at least partially covers the orthographic projection of the channel region of the seventh transistor T7 on the substrate 10. At the same time, the orthographic projection of the fourth sub-signal line VDD2 on the substrate 10 covers the orthographic projection of the channel region of some transistors on the substrate 10, such as, the orthographic projection of the fourth sub-signal line VDD2 on the substrate 10 covers the orthographic projection of the channel region of the first transistor T1, the channel region of the third transistor T3, the channel region of the fourth transistor T4, the channel region of the driving transistor T0, and the channel region of the sixth transistor T6 on the substrate 10.

[0227] Optionally, since the fourth active layer 34 corresponding to the third transistor T3 and the fourth transistor T4 and the fifth active layer 35 corresponding to the fifth transistor T5 and the seventh transistor T7 are all located on the same side of the first active layer 31, the second shading layer 14 and the first electrode 13 of the second capacitor C2 can be connected as an integrated structure in the first conductive layer to jointly perform bottom shading on the transistors located on the same side of the first active layer 31, which is beneficial to saving layout area.

[0228] The technical solution provided in this embodiment shields the bottom of the transistor by the first conductive layer and shields the top of the transistor by the fifth conductive layer, which can avoid the influence of light on the transistor, thereby improving the reliability of the pixel circuit and further improving the stability of the screen.

[0229] Optionally, in the above embodiments, the first scanning signal line S1 crosses the gate of the first transistor T1 and the gate of the second transistor T2, the second scanning signal line S2 crosses the gate of the fourth transistor T4 and the gate of the fifth transistor T5, the first light-emitting control signal line EM1 crosses the gate of the third transistor T3 and the seventh transistor T7, and the second light-emitting control signal line EM2 crosses the gate of the sixth transistor T6. On the one hand, the number of cross-lines can be reduced. On the other hand, since each signal line is used to access a voltage signal, these signal lines can also shield the signal for the gate portion of the transistor they cover, so as to ensure the stability of the gate voltage of each transistor, which is beneficial to improving the uniformity of display brightness.

[0230] Fig.21 A schematic diagram of a planar structure of another display panel provided by an embodiment of the present invention, Fig. 22 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically: Fig.21 The cross-sectional structure of the display panel shown along the cutting line JJ' is shown in FIG. Fig.21 and Fig. 22On the basis of the above embodiments, optionally, the display panel further includes a light-emitting element, which may be a light-emitting diode D1, and includes a first electrode 70, a light-emitting functional layer, and a second electrode (not shown in the figure) which are stacked. The first electrode 70 is located on a side of the fifth conductive layer away from the substrate 10, and a second planarization layer 160 is arranged between the fifth conductive layer and the first electrode 70.

[0231] The first electrode 70 is connected to one end of the tenth connection line 120 through the fourth type via K4 to achieve the connection between the light emitting element and the first electrode of the seventh transistor T7. The fourth type via K4 is a via that penetrates the second planarization layer 160.

[0232] In this embodiment, the orthographic projection of the first electrode 70 on the substrate 10 at least covers the orthographic projection of the channel region of the remaining transistors on the substrate 10. The remaining transistors here refer to transistors that are not blocked by the fifth conductive layer, such as the fifth transistor T5 and the seventh transistor T7. The top of the remaining transistors is blocked by the first electrode 70, so that all transistors have a film layer with a light-shielding function at the top and bottom, so as to improve the stability of the screen.

[0233] The technical solution provided by the embodiment of the present invention, by setting the first conductive layer to act as the first plate 11 of the first capacitor C1 and the bottom light shielding layer of the transistor, the first conductive layer acts as the second plate 21 of the first capacitor C1 and the first gate G1 of the driving transistor T0, the fifth conductive layer is used for the fourth sub-signal line VDD2 in the power line VDD and also takes into account the top function of shielding part of the transistor, the first electrode 70 is used as the electrode of the light-emitting element and takes into account the top function of shielding the remaining part of the transistor, which can fully improve the layout space utilization rate while avoiding the influence of light on the transistor, which is beneficial to improving the stability and reliability of the screen. In addition, the technical solution provided by this embodiment can effectively reduce the connection cross-line of the first scanning signal line S1 by setting the first scanning signal line S1 close to the driving transistor T0, so as to reduce the parasitic capacitance of the gate of the driving transistor T0, and at the same time use the fourth metal layer to shield the gate of each transistor (all are top gates), which is beneficial to reduce the parasitic capacitance of the gate of each transistor, and is beneficial to reduce the display crosstalk problem, thereby improving the display uniformity.

[0234] Fig.23 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention, Fig.24 A schematic diagram of a planar structure of another display panel provided in an embodiment of the present invention, referring to Fig.23 and Fig.24In this embodiment, the driving transistor T0 is a single-gate transistor, that is, the driving transistor T0 has only the first gate G1, and the second plate 21 of the first capacitor C1 no longer serves as a gate of the driving transistor T0. Therefore, the orthographic projection of the second plate 21 of the first capacitor C1 on the substrate 10 does not overlap with the orthographic projection of the channel region of the driving transistor T0 on the substrate 10. The first gate G1 of the driving transistor T0 is located in the third conductive layer, relative to Fig.16 The driving transistor T0 shown is a dual-gate layout. When the driving transistor T0 is a single-gate transistor, the first connecting line 111 can be omitted, and the connection between the first gate G1 of the driving transistor T0 and the second plate 21 of the first capacitor C1 is achieved through the second connecting line 112.

[0235] Fig.25 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically: Fig.24 The cross-sectional structure of the display panel along the cutting line LL' is shown as follows: Fig.25 As shown, the first gate G1 of the driving transistor T0 is connected to one end of the second connection line 112 through the first type via K1, and the second plate 21 of the first capacitor C1 is connected to the other end of the second connection line 112 through the second type via K2.

[0236] Optionally, the second connection line 112 may be connected with the third connection line 113 to form an integrated structure, so as to reduce one second type via K2.

[0237] When the driving transistor T0 is a single-gate transistor, the layout structure of the other transistors is the same as or similar to the layout structure of the corresponding transistors when the driving transistor T0 is a double-gate transistor. For details, please refer to Figures 16 to 21 The structure shown has the same beneficial effects as described in any of the above embodiments, which will not be repeated here.

[0238] Optionally, the specific working principle of the pixel circuit provided in the above embodiments may refer to the description in the related art, which will not be repeated here.

[0239] Optionally, an embodiment of the present invention further provides a display device, which includes the display panel provided by any embodiment of the present invention. Therefore, the display device also has the beneficial effects described in any of the above embodiments. Fig.26 A structural schematic diagram of a display device provided in an embodiment of the present invention. In this embodiment, the display device 200 can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals and other products. The embodiment of the present invention does not make any special limitation on this.

[0240] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0241] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A plurality of conductive layers stacked on one side of the substrate; at least one pixel circuit, the pixel circuit comprising a driving transistor and a first capacitor; The multi-layer conductive layer comprises a first conductive layer and a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the substrate, the first electrode plate of the first capacitor is located on the first conductive layer, the second electrode plate of the first capacitor is located on the second conductive layer, and the second electrode plate of the first capacitor is connected to the first gate of the driving transistor; An active layer is located on a side of the second conductive layer away from the substrate.

2. The display panel according to claim 1, characterized in that: The first gate of the driving transistor is located in the second conductive layer, and the second plate of the first capacitor is reused as the first gate of the driving transistor; Preferably, the active layer comprises a first active layer, the first active layer extends along a first direction, the channel region of the driving transistor is located in the first active layer, and the orthographic projection of the second electrode plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, the orthographic projection of the first plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, an orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with an orthographic projection of the second plate of the first capacitor on the substrate.

3. The display panel according to claim 2, characterized in that: The first electrode plate of the first capacitor includes a hole area, and the overlapping position of the orthographic projection of the first electrode plate of the first capacitor on the substrate and the orthographic projection of the second electrode plate of the first capacitor on the substrate at least partially covers the orthographic projection of the hole area on the substrate.

4. The display panel according to claim 2, characterized in that: The multi-layer conductive layer further includes a third conductive layer, the third conductive layer is located on a side of the active layer away from the substrate, the second gate of the driving transistor is located on the third conductive layer, and the second gate of the driving transistor is connected to the first electrode of the driving transistor; Preferably, the multi-layer conductive layer further includes a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, the fourth conductive layer includes a first connecting line, and the second gate electrode of the driving transistor is connected to the first electrode of the driving transistor through the first connecting line; Preferably, the second gate of the driving transistor is connected to one end of the first connecting line through a first type via hole, and the first electrode of the driving transistor is connected to the other end of the first connecting line through the first type via hole; Preferably, the orthographic projection of the first connecting line on the substrate at least partially covers the orthographic projection of the second gate of the driving transistor on the substrate; Preferably, the orthographic projection of the second gate of the driving transistor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate.

5. The display panel according to claim 1, characterized in that: The multi-layer conductive layer further comprises a third conductive layer, the third conductive layer is located on a side of the active layer away from the substrate, and the first gate of the driving transistor is located on the third conductive layer; Preferably, the active layer comprises a first active layer, the first active layer extends along a first direction, the channel region of the driving transistor is located in the first active layer, and the orthographic projection of the first gate of the driving transistor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, an orthographic projection of the second plate of the first capacitor on the substrate does not overlap with an orthographic projection of the channel region of the driving transistor on the substrate.

6. The display panel according to claim 5, characterized in that: The multi-layer conductive layer further includes a fourth conductive layer, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, the fourth conductive layer includes a second connecting line, and the first gate of the driving transistor is connected to the second plate of the first capacitor through the second connecting line; Preferably, the first gate of the driving transistor is connected to one end of the second connecting line through a first type via hole, and the second plate of the first capacitor is connected to the other end of the second connecting line through a second type via hole; Preferably, the orthographic projection of the second plate of the first capacitor on the substrate does not overlap with the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, the orthographic projection of the first plate of the first capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, an orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with an orthographic projection of the second plate of the first capacitor on the substrate; Preferably, the orthographic projection of the first electrode plate of the first capacitor on the substrate covers the orthographic projection of the second electrode plate of the first capacitor on the substrate.

7. The display panel according to claim 4 or 6, characterized in that: The pixel circuit further includes a first transistor, a gate of the first transistor is located in the third conductive layer, the active layer further includes a second active layer, the second active layer extends along a second direction, the first direction intersects with the second direction, the second active layer is in the same layer as the first active layer and is not connected, and a channel region of the first transistor is located in the second active layer; Preferably, the first direction intersects the second direction perpendicularly; Preferably, the channel region of the first transistor is located at a positive projection position of the gate of the first transistor on the second active layer, the fourth conductive layer further comprises a third connecting line and a fourth connecting line, the first electrode of the first transistor is connected to the first gate of the driving transistor through the third connecting line, and the second electrode of the first transistor is connected to the second electrode of the driving transistor through the fourth connecting line; Preferably, the first electrode of the first transistor is connected to one end of the third connection line through a first type via hole, and the first gate of the driving transistor is connected to the other end of the third connection line through the first type via hole or the second type via hole; the second electrode of the first transistor is connected to one end of the fourth connection line through the first type via hole, and the second electrode of the driving transistor is connected to the other end of the fourth connection line through the first type via hole; Preferably, the first transistor is used to compensate for the threshold voltage of the driving transistor; Preferably, the display panel further comprises a first scanning signal line, the first scanning signal line is located in the fourth conductive layer, and the first scanning signal line is connected to the gate of the first transistor through the first type of via hole; Preferably, the first scanning signal line is arranged to intersect with the gate of the first transistor, and at the intersection of the first scanning signal line and the gate of the first transistor, the first scanning signal line is connected to the gate of the first transistor through the first type of via hole; Preferably, the first scanning signal line extends along a first direction; Preferably, the first conductive layer also includes a first shading layer, which is in the same layer as the first plate of the first capacitor and is not connected, and the orthographic projection of the first shading layer on the substrate at least partially covers the orthographic projection of the channel region of the first transistor on the substrate.

8. The display panel according to claim 7, characterized in that: The display panel further includes a first initialization signal line, the pixel circuit further includes a second transistor, a gate of the second transistor is located in the third conductive layer, the active layer further includes a third active layer, the third active layer extends along the second direction, the third active layer, the second active layer and the first active layer are in the same layer and are not connected, and a channel region of the second transistor is located in the third active layer; Preferably, the second active layer and the third active layer are located on one side of the first active layer; Preferably, the channel region of the second transistor is located at the positive projection position of the gate of the second transistor on the third active layer, the first electrode of the second transistor is connected to the first initialization signal line through the first type via hole, the fourth conductive layer further includes a fifth connecting line, the second electrode of the second transistor is connected to the first plate of the first capacitor through the fifth connecting line, and the gate of the second transistor is connected to the first scanning signal line through the first type via hole; Preferably, the second electrode of the second transistor is connected to one end of the fifth connection line through the first type via hole, and the first electrode plate of the first capacitor is connected to the other end of the fifth connection line through the second type via hole; Preferably, the orthographic projection of the third active layer on the substrate overlaps with the orthographic projection of the first initialization signal line on the substrate; Preferably, at a position where the first initialization signal line crosses the third active layer, the first initialization signal line is connected to the first electrode of the second transistor through the first type via hole; Preferably, the first scanning signal line is arranged to intersect with the gate of the second transistor, and at the position where the first scanning signal line intersects with the gate of the second transistor, the gate of the second transistor is connected to the first scanning signal line through the first type of via hole; Preferably, the first initialization signal line is located in the fourth conductive layer, and the first initialization signal line extends along the first direction; Preferably, the orthographic projection of the first light-shielding layer on the substrate at least partially covers the orthographic projection of the channel region of the second transistor on the substrate.

9. The display panel according to claim 8, characterized in that: The display panel further includes a second initialization signal line, the orthographic projection of the second initialization signal line on the substrate being located on a side of the orthographic projection of the first gate of the driving transistor on the substrate away from the orthographic projection of the first scanning signal line on the substrate; Preferably, the pixel circuit further includes a second capacitor and a third transistor, the gate of the third transistor is located in the third conductive layer, the active layer further includes a fourth active layer, the fourth active layer extends along the second direction, the fourth active layer is in the same layer as the third active layer, the second active layer and the first active layer and is not connected, and the channel region of the third transistor is located in the fourth active layer; Preferably, the channel region of the third transistor is located at the positive projection position of the gate of the third transistor on the fourth active layer, the first electrode of the third transistor is connected to the second initialization signal line through the first type of via hole, the fourth conductive layer further includes a sixth connecting line and a seventh connecting line, the second electrode of the third transistor is connected to the first electrode plate of the second capacitor through the sixth connecting line, and the second electrode plate of the second capacitor is connected to the second electrode of the driving transistor through the seventh connecting line; the third transistor is used to transmit a fixed voltage to the first electrode plate of the second capacitor; Preferably, the second electrode of the third transistor is connected to one end of the sixth connection line through the first type via hole, the first electrode plate of the second capacitor is connected to the other end of the sixth connection line through the second type via hole, the second electrode plate of the second capacitor is connected to one end of the seventh connection line through the second type via hole, and the second electrode of the driving transistor is connected to the other end of the seventh connection line through the first type via hole; Preferably, the orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially covers the orthographic projection of the channel region of the third transistor on the substrate; Preferably, an orthographic projection of the fourth active layer on the substrate overlaps with an orthographic projection of the second initialization signal line on the substrate; Preferably, at the intersection of the fourth active layer and the second initialization signal line, the first electrode of the third transistor is connected to the second initialization signal line through the first type via hole; Preferably, the display panel further comprises a first light-emitting control signal line, the first light-emitting control signal line is located in the fourth conductive layer, and the first light-emitting control signal line is connected to the gate of the third transistor through the first type via hole; Preferably, the first light-emitting control signal line is arranged to cross the gate of the third transistor, and at the crossing position of the first light-emitting control signal line and the gate of the third transistor, the first light-emitting control signal line is connected to the gate of the third transistor through the first type of via hole; Preferably, the first light emitting control signal line extends along the first direction, and the second initializing signal line extends along the first direction; Preferably, the second initialization signal line is located in the fourth conductive layer; Preferably, the first light emitting control signal line is located on a side of the second initializing signal line away from the first active layer.

10. The display panel according to claim 9, characterized in that: The display panel further includes a data line, the pixel circuit further includes a fourth transistor, a gate of the fourth transistor is located in the third conductive layer, and a channel region of the fourth transistor is located in the fourth active layer; Preferably, the channel region of the fourth transistor is located at the positive projection position of the gate of the fourth transistor on the fourth active layer, the fourth conductive layer further includes an eighth connecting line, the first electrode of the fourth transistor is connected to the data line via the eighth connecting line, and the second electrode of the fourth transistor is connected to the second electrode of the third transistor via the fourth active layer; the fourth transistor is used to transmit a data voltage to the first electrode plate of the second capacitor, and the second capacitor is used to write voltage information associated with the data voltage into the first gate of the driving transistor; Preferably, the first electrode of the fourth transistor is connected to one end of the eighth connection line through the first type via hole, and the data line is connected to the other end of the eighth connection line through the third type via hole; Preferably, the display panel further comprises a second scanning signal line, the second scanning signal line is located in the fourth conductive layer, and the second scanning signal line is connected to the gate of the fourth transistor through the first type via hole; Preferably, the second scan signal line is arranged to cross the gate of the fourth transistor, and at the intersection of the second scan signal line and the gate of the fourth transistor, the second scan signal line is connected to the gate of the fourth transistor through the first type of via hole; Preferably, the first conductive layer further includes a second light shielding layer, the second light shielding layer is in the same layer as the first light shielding layer and the first electrode plate of the first capacitor and is not connected, and the orthographic projection of the second light shielding layer on the substrate at least partially covers the orthographic projection of the channel region of the fourth transistor on the substrate; Preferably, the second light shielding layer and the first electrode plate of the second capacitor are in the same layer and connected to form an integrated structure; Preferably, the multi-layer conductive layer further comprises a fifth conductive layer, the fifth conductive layer is located on a side of the fourth conductive layer away from the substrate, and the data line is located in the fifth conductive layer; Preferably, the second scanning signal line extends along the first direction; Preferably, the orthographic projection of the first light emitting control signal line on the substrate is located between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate; Preferably, along the second direction, the first light emitting control signal line, the second scanning signal line and the second initialization signal line are located on the same side of the first active layer, and the first initialization signal line and the first scanning signal line are located on the other side of the first active layer.

11. The display panel according to claim 9, characterized in that: The first electrode plate of the second capacitor is located on the first conductive layer, and the second electrode plate of the second capacitor is located on the second conductive layer; Preferably, the second electrode plate of the second capacitor is L-shaped; Preferably, the orthographic projection of the second plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the second initialization signal line on the substrate; Preferably, the second electrode plate of the second capacitor comprises a main body extending along the first direction and a branch extending along the second direction, the orthographic projection of the branch on the substrate overlaps with the orthographic projection of the second initialization signal line on the substrate, and the orthographic projection of the main body on the substrate is located between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the first active layer on the substrate; Preferably, the branch portion and the main body portion are an integral structure.

12. The display panel according to claim 10, characterized in that: The pixel circuit further includes a fifth transistor, a gate of the fifth transistor is located in the third conductive layer, the active layer further includes a fifth active layer, the fifth active layer is in the same layer as the fourth active layer, the third active layer, the second active layer, and the first active layer and is not connected, and a channel region of the fifth transistor is located in the fifth active layer; Preferably, the channel region of the fifth transistor is located at the positive projection position of the gate of the fifth transistor on the fifth active layer, the second electrode of the fifth transistor is connected to the first electrode of the second transistor through a ninth connecting line, the first electrode of the fifth transistor is connected to the second electrode of the second transistor through a tenth connecting line, and the gate of the fifth transistor is connected to the second scanning signal line through the first type via hole; Preferably, the second scan signal line is arranged to intersect with the gate of the fifth transistor, and at the intersection of the second scan signal line and the gate of the fifth transistor, the gate of the fifth transistor is connected to the second scan signal line through the first type of via hole; Preferably, the orthographic projection of the second light-shielding layer on the substrate at least partially covers the orthographic projection of the channel region of the fifth transistor on the substrate.

13. The display panel according to claim 12, characterized in that: The fourth conductive layer further includes an eleventh connecting line, a twelfth connecting line, a thirteenth connecting line and a fourteenth connecting line, the second electrode of the fifth transistor is connected to one end of the eleventh connecting line through the first type via hole, the other end of the eleventh connecting line is connected to one end of the ninth connecting line through the third type via hole, the other end of the ninth connecting line is connected to one end of the twelfth connecting line through the third type via hole, and the other end of the twelfth connecting line is connected to the first electrode of the second transistor through the first type via hole; the first electrode of the fifth transistor is connected to one end of the thirteenth connecting line through the first type via hole, the other end of the thirteenth connecting line is connected to one end of the tenth connecting line through the third type via hole, the other end of the tenth connecting line is connected to one end of the fourteenth connecting line through the third type via hole, and the other end of the fourteenth connecting line is connected to the second electrode of the second transistor through the first type via hole; Preferably, the ninth connecting line and the tenth connecting line are both located in the fifth conductive layer; Preferably, the fifth transistor is used to transmit the first initialization voltage on the first initialization signal line to the light emitting element; The fifth active layer and the fourth active layer are located on the other side of the first active layer.

14. The display panel according to claim 13, characterized in that: The first initialization signal line includes a first sub-signal line extending along the first direction and a second sub-signal line extending along the second direction, and the first sub-signal line and the second sub-signal line are connected at least at one intersection to form a mesh structure; Preferably, the first sub-signal line and the second sub-signal line are arranged in different layers; Preferably, the first sub-signal line is located in the fourth conductive layer, and the second sub-signal line is located in the fifth conductive layer; Preferably, the orthogonal projection of the first sub-signal line on the substrate is located on a side where the orthogonal projection of the first scanning signal line on the substrate is away from the orthogonal projection of the first gate of the driving transistor on the substrate; Preferably, the orthographic projection of the second sub-signal line on the substrate covers the orthographic projection of the channel region of a part of the transistor on the substrate; Preferably, the second sub-signal line is multiplexed as the ninth connecting line.

15. The display panel according to claim 13, characterized in that: The pixel circuit further includes a sixth transistor and a seventh transistor, the gate of the sixth transistor and the gate of the seventh transistor are both located in the third conductive layer, the channel region of the sixth transistor is located in the second active layer, and the channel region of the seventh transistor is located in the fifth active layer; Preferably, the display panel further includes a power line, the fourth conductive layer further includes a fifteenth connecting line, the second electrode of the sixth transistor is connected to the power line through the first type via hole, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor through the fourth connecting line; the second electrode of the seventh transistor is connected to the first electrode of the driving transistor through the fifteenth connecting line, and the first electrode of the seventh transistor is connected to the thirteenth connecting line; Preferably, the power line is arranged to cross the second active layer, and at the crossing position of the power line and the second active layer, the second electrode of the sixth transistor is connected to the power line through the first type of via hole; Preferably, the first electrode of the sixth transistor is connected to one end of the fourth connection line through the first type via hole, and the second electrode of the driving transistor is connected to the other end of the fourth connection line through the first type via hole; the second electrode of the seventh transistor is connected to one end of the fifteenth connection line through the first type via hole, the first electrode of the driving transistor is connected to the other end of the fifteenth connection line through the first type via hole, and the first electrode of the seventh transistor is connected to the thirteenth connection line through the first type via hole; Preferably, the display panel further comprises a second light emitting control signal line extending along the first direction, and an orthographic projection of the first light emitting control signal line on the substrate and an orthographic projection of the second light emitting control signal line on the substrate are respectively located on both sides of an orthographic projection of the first active layer on the substrate; Preferably, the orthographic projection of the second light-emitting control signal line on the substrate is located on a side of the orthographic projection of the first initialization signal line on the substrate away from the orthographic projection of the first scanning signal line on the substrate; Preferably, the gate of the sixth transistor is connected to the second light-emitting control signal line through the first type via hole, and the gate of the seventh transistor is connected to the first light-emitting control signal line through the first type via hole; Preferably, the second light-emitting control signal line is arranged to cross the gate of the sixth transistor, and at the crossing position of the second light-emitting control signal line and the gate of the sixth transistor, the gate of the sixth transistor is connected to the second light-emitting control signal line through the first type via hole; Preferably, the first light-emitting control signal line is arranged to cross the gate of the seventh transistor, and at the intersection of the first light-emitting control signal line and the gate of the seventh transistor, the gate of the seventh transistor is connected to the first light-emitting control signal line through the first type of via hole; Preferably, the orthographic projection of the power line on the substrate is located on a side of the orthographic projection of the second light-emitting control signal line on the substrate away from the orthographic projection of the first initialization signal line on the substrate; Preferably, the orthographic projection of the first light shielding layer on the substrate at least partially covers the orthographic projection of the channel region of the sixth transistor on the substrate; Preferably, the orthographic projection of the first plate of the second capacitor on the substrate at least partially covers the orthographic projection of the channel region of the seventh transistor on the substrate.

16. The display panel according to claim 15, characterized in that: The power line includes a third sub-signal line extending along the first direction and a fourth sub-signal line extending along the second direction, the third sub-signal line and the fourth sub-signal line are located in different conductive layers, and the third sub-signal line and the fourth sub-signal line are connected to form a mesh structure at least at one intersection position; Preferably, the second electrode of the sixth transistor is connected to the third sub-signal line through the first type via hole; Preferably, the orthographic projection of the fourth sub-signal line on the substrate covers the orthographic projection of the channel region of a part of the transistor on the substrate; Preferably, the third sub-signal line is located in the fourth conductive layer, and the fourth sub-signal line is located in the fifth conductive layer.

17. The display panel according to claim 15, characterized in that: The display panel further includes a light-emitting element, the light-emitting element including a first electrode, a light-emitting functional layer, and a second electrode that are stacked, the first electrode being located on a side of the fifth conductive layer away from the substrate; The first electrode is connected to one end of the tenth connecting line through a fourth type via hole; Preferably, the orthographic projection of the first electrode on the substrate at least covers a portion of the orthographic projection of the channel region of the transistor on the substrate.

18. The display panel according to claim 17, characterized in that: The display panel further includes: a capacitor insulating layer, the capacitor insulating layer being located between the first conductive layer and the second conductive layer, and an orthographic projection of the capacitor insulating layer on the substrate covering an orthographic projection of the first conductive layer on the substrate; a first gate insulating layer, wherein the first gate insulating layer is located between the second conductive layer and the active layer, and an orthographic projection of the first gate insulating layer on the substrate covers an orthographic projection of the second conductive layer on the substrate; a second gate insulating layer, wherein the second gate insulating layer is located between the active layer and the third conductive layer, and an orthographic projection of the second gate insulating layer on the substrate covers an orthographic projection of the active layer on the substrate; an interlayer insulating layer, wherein the interlayer insulating layer is located between the third conductive layer and the fourth conductive layer, and an orthographic projection of the interlayer insulating layer on the substrate covers an orthographic projection of the third conductive layer on the substrate; a first planarization layer, wherein the first planarization layer is located between the fourth conductive layer and the fifth conductive layer, and an orthographic projection of the first planarization layer on the substrate covers an orthographic projection of the fourth conductive layer on the substrate; a second planarization layer, wherein the second planarization layer is located on a side of the fifth conductive layer away from the substrate, and an orthographic projection of the second planarization layer on the substrate covers an orthographic projection of the fifth conductive layer on the substrate; Preferably, the first type via hole penetrates the interlayer insulating layer, or the first type via hole penetrates the interlayer insulating layer and the second gate insulating layer; The second type via hole penetrates the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer and the capacitor insulating layer; The third type via hole penetrates the first planarization layer; The fourth type via hole penetrates the second planarization layer.

19. The display panel according to claim 1, characterized in that: The material of the active layer includes metal oxide.

20. A display device, characterized in that: A display panel comprising any one of claims 1-19.

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