Semiconductor device

Abstract

Provided is a semiconductor device in which inductance in a circuit in which a plurality of semiconductor packages are connected in series with each other is reduced. The first terminal is disposed on a first side of the first semiconductor package and is electrically connected to a first pole side of the first semiconductor chip. The first output terminal is disposed on the second side of the first semiconductor package and is electrically connected to the second pole side of the first semiconductor chip. The second output terminal is disposed on the third side of the second semiconductor package and is electrically connected to the first pole side of the second semiconductor chip. The second terminal is disposed on a third side of the second semiconductor package and is electrically connected to a second pole side of the second semiconductor chip. The first output terminal is connected to the second output terminal. The bus bar is connected to the second terminal and extends from the second terminal in the direction of the first surface on which the first terminal is provided.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The structure in which two semiconductor devices are connected in series is suitable for various control systems such as power control equipment. In the semiconductor component described in Patent Document 1, two semiconductor devices with a common design are connected in series. In each semiconductor device, a + polarity terminal is provided on one side, and a - polarity terminal is provided on the other side. The - polarity terminal of one semiconductor component connected in series is folded back on its side, passes over the two semiconductor devices, and extends in the direction of the + polarity terminal. Prior art literature Patent Literature

[0003] Patent Document 1: U.S. Patent No. 10304770 Summary of the invention Technical problem to be solved by the invention

[0004] In a structure in which a plurality of semiconductor packages each including a switching element is connected in series, the path of a bus bar for guiding one terminal toward another terminal becomes longer, and the inductance becomes larger.

[0005] In order to solve the above-mentioned problems, the present disclosure provides a semiconductor device which reduces the inductance of a circuit in which a plurality of semiconductor packages are connected in series with each other. Technical means for solving technical problems

[0006] The semiconductor device involved in the present disclosure includes a first semiconductor package, a first terminal, a first output terminal, a second semiconductor package, a second output terminal, a second terminal and a bus bar. The first semiconductor package includes a first semiconductor chip. The first terminal is arranged on the first surface of the first semiconductor package. The first terminal is electrically connected to the first polarity side of the first semiconductor chip. The first output terminal is arranged on the second surface of the first semiconductor package. The first output terminal is electrically connected to the second polarity side of the first semiconductor chip. The second semiconductor package includes a second semiconductor chip. The second output terminal is arranged on the third surface of the second semiconductor package. The second output terminal is electrically connected to the first polarity side of the second semiconductor chip. The second terminal is arranged on the third surface of the second semiconductor package. The second terminal is electrically connected to the second polarity side of the second semiconductor chip. The bus bar is connected to the second terminal. The first output terminal is connected to the second output terminal. The bus bar extends from the second terminal toward the first surface where the first terminal is arranged. Effects of the Invention

[0007] According to the semiconductor device of the present disclosure, the inductance of a circuit in which a plurality of semiconductor packages are connected in series with each other is reduced.

[0008] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 : is a circuit diagram showing an example of the structure of a three-phase inverter. Figure 2 It is a cross-sectional view showing the structure of a semiconductor package for an upper arm of the semiconductor device in the first embodiment. Figure 3 This is a diagram showing the internal structure of the upper arm semiconductor package. Figure 4 It is a diagram showing the structure of a semiconductor package for an upper arm. Figure 5 It is a diagram showing the internal structure of a semiconductor package for a lower arm. Figure 6 It is a diagram showing the structure of a semiconductor package for a lower arm. Figure 7 It is a diagram showing a connection structure between an upper arm semiconductor package and a lower arm semiconductor package. Figure 8 This is a diagram showing the structure of a semiconductor device in Embodiment 1. Fig. 9 This is a diagram showing the structure of a semiconductor device in the second embodiment. Fig.10 This is a diagram showing the structure of a semiconductor device in Embodiment 3. Fig.11 It is a diagram showing a connection structure between an upper arm semiconductor package and a lower arm semiconductor package. Fig.12 It is a diagram showing the structure of a semiconductor package for an upper arm. Fig.13 It is a diagram showing the structure of a semiconductor package for a lower arm. Fig.14 This is a diagram showing the internal structure of the upper arm semiconductor package. Fig.15 It is a diagram showing the internal structure of a semiconductor package for a lower arm. Fig.16 It is a plan view showing the internal structure of the upper arm semiconductor package. Fig.17 It is a plan view showing the internal structure of the semiconductor package for the lower arm. Fig.18 This is a diagram showing the structure of a semiconductor device in a fourth embodiment. Fig.19 This is a side view showing an example of a semiconductor chip holding structure in the fifth embodiment. Fig. 20This is a diagram showing an example of the structure of a semiconductor package and a bus bar for an upper arm in the sixth embodiment. Fig.21 This is a diagram showing an example of the structure of a semiconductor package and a bus bar for an upper arm. Fig. 22 It is a plan view showing the internal structure of the semiconductor package for an upper arm in the seventh embodiment. Fig.23 It is a plan view showing the internal structure of the semiconductor package for the lower arm. Fig.24 This is a diagram showing the structure of a semiconductor device in an eighth embodiment. Fig.25 It is a plan view showing the internal structure of the semiconductor package for an upper arm in the ninth embodiment. Fig.26 It is a plan view showing the internal structure of the semiconductor package for the lower arm. DETAILED DESCRIPTION

[0010] <Implementation method 1> Figure 1 1 is a circuit diagram showing an example of the structure of a three-phase inverter. The three-phase inverter includes three upper arm semiconductor packages 111 and three lower arm semiconductor packages 121. The upper arm semiconductor packages 111 and the lower arm semiconductor packages 121 each include a switching element 10. One upper arm semiconductor package 111 and one lower arm semiconductor package 121 are connected in series to form a branch.

[0011] Figure 2 1 is a cross-sectional view showing the structure of the upper arm semiconductor package 111 of the semiconductor device in the first embodiment. Figure 3 1 is a diagram showing the internal structure of the upper arm semiconductor package 111 . Figure 4 1 is a diagram showing the structure of the upper arm semiconductor package 111. Figure 2 In the figure, the height direction positional relationship and the depth direction positional relationship of the P terminal 13, the first AC terminal 14 and the control terminal 15 are briefly described. Figure 3 The original positional relationship in the first embodiment shown is different.

[0012] The upper arm semiconductor package 111 includes an insulating substrate 11 , a first semiconductor chip 12 , a P terminal 13 , a first AC terminal 14 , a control terminal 15 , and a sealing material 16 .

[0013] The insulating substrate 11 includes a metal pattern 17 on its surface. The insulating substrate 11 holds the first semiconductor chip 12 on the metal pattern 17 via a bonding material 18A. The insulating substrate 11 is formed of, for example, ceramics.

[0014] The first semiconductor chip 12 includes a switching element 10. The first semiconductor chip 12 is formed of a semiconductor such as Si, or a so-called wide-bandgap semiconductor such as SiC, GaN, or gallium oxide. The first semiconductor chip 12 is a so-called power semiconductor chip. In the first semiconductor chip 12, an IGBT (Insulated Gate Bipolar Transistor) is formed as the switching element 10. The switching element 10 may be an RC-IGBT (Reverse-Conducting IGBT) in which an IGBT and a return diode are formed in one semiconductor substrate. Alternatively, the switching element 10 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or the like.

[0015] The P terminal 13 is formed, for example, by a metal frame. The metal frame is formed by a metal flat plate or a sheet metal to which the metal flat plate has been subjected to shape processing. One end of the P terminal 13 is connected to the metal pattern 17 via a bonding material 18B. That is, the P terminal 13 is electrically connected to the first pole side of the first semiconductor chip 12 via the metal pattern 17. The first pole side is the collector side of the IGBT. The other end of the P terminal 13 protrudes from the first side surface A of the semiconductor package 111 for the upper arm. In other words, the P terminal 13 is provided on the first side surface A of the semiconductor package 111 for the upper arm. The P terminal 13 is a positive terminal.

[0016] The first AC terminal 14 is formed of, for example, a metal frame. One end of the first AC terminal 14 is connected to a surface electrode (not shown) of the first semiconductor chip 12 through a bonding material 18C. That is, the first AC terminal 14 is electrically connected to the second pole side of the first semiconductor chip 12. Its surface electrode is an emitter electrode, and the second pole side is the emitter side of the IGBT. The other end of the first AC terminal 14 protrudes from the second side surface B of the semiconductor package 111 for the upper arm. In other words, the first AC terminal 14 is arranged on a second side surface B that is different from the first side surface A on which the P terminal 13 is arranged. In embodiment 1, the sealing material 16 that forms the outer shape of the semiconductor package 111 for the upper arm has a rectangular shape when viewed from above. The first side surface A and the second side surface B are surfaces that are opposite to each other in its rectangle. The first AC terminal 14 is a negative terminal.

[0017] The control terminal 15 is a terminal for transmitting a control signal related to the control of the switch element 10 included in the first semiconductor chip 12. The control terminal 15 is connected to the first semiconductor chip 12 through, for example, a control wire 19. Figure 3In the figure, the control lead wire 19 is omitted. A plurality of control terminals 15 may be provided. A part of the control terminal 15 protrudes from the first side surface A of the semiconductor package 111 for the upper arm.

[0018] The sealing material 16 seals the metal pattern 17 of the insulating substrate 11, the first semiconductor chip 12, a part of the P terminal 13, a part of the first AC terminal 14, and a part of the control terminal 15. The sealing material 16 is, for example, a resin. The sealing material 16 is formed, for example, by molding. The sealing material 16 has a rectangular shape in a plan view.

[0019] Figure 5 1 is a diagram showing the internal structure of the semiconductor package 121 for the lower arm. Figure 6 1 is a diagram showing the structure of a semiconductor package 121 for a lower arm.

[0020] The semiconductor package 121 for the lower arm includes an insulating substrate 21, a second semiconductor chip 22, a second AC terminal 23, an N terminal 24, a control terminal 25, and a sealing material 26. Although the figure showing the cross-sectional structure of the semiconductor package 121 for the lower arm is omitted, the structures of the insulating substrate 21, the metal pattern 27, and the sealing material 26 are respectively the same as the structures of the insulating substrate 11, the metal pattern 17, and the sealing material 16 of the semiconductor package 111 for the upper arm.

[0021] The second semiconductor chip 22 includes the switching element 10. The structure of the second semiconductor chip 22 is, for example, the same as that of the first semiconductor chip 12. The second semiconductor chip 22 is held on the metal pattern 27 of the insulating substrate 21 via a bonding material 28A.

[0022] The second AC terminal 23 is formed of, for example, a metal frame. One end of the second AC terminal 23 is connected to the metal pattern 27 through the bonding material 28B. That is, the second AC terminal 23 is electrically connected to the first pole side of the second semiconductor chip 22 via its metal pattern 27. The first pole side is the collector side of the IGBT. The other end of the second AC terminal 23 protrudes from the third side surface C of the semiconductor package 121 for the lower arm. In other words, the second AC terminal 23 is provided on the third side surface C of the semiconductor package 121 for the lower arm. The second AC terminal 23 is a positive terminal.

[0023] The N terminal 24 is formed of, for example, a metal frame. One end of the N terminal 24 is connected to a surface electrode (not shown) of the second semiconductor chip 22 through a bonding material 28C. That is, the N terminal 24 is electrically connected to the second pole side of the second semiconductor chip 22. Its surface electrode is an emitter electrode, and the second pole side is the emitter side of the IGBT. The other end of the N terminal 24 protrudes from the third side surface C of the semiconductor package 121 for the lower arm. The N terminal 24 is provided on the same surface as the third side surface C on which the second AC terminal 23 is provided. The N terminal 24 is a negative terminal.

[0024] The control terminal 25 is a terminal for transmitting a control signal related to the control of the switching element 10 included in the second semiconductor chip 22. The control terminal 25 is connected to the second semiconductor chip 22 via a control wire (not shown), for example. A plurality of control terminals 25 may also be provided. A portion of the control terminal 25 protrudes from the fourth side surface D of the semiconductor package 121 for the lower arm. In the first embodiment, the sealing material 26 forming the outer shape of the semiconductor package 121 for the lower arm has a rectangular shape when viewed from above. The third side surface C and the fourth side surface D are surfaces facing each other in the rectangle.

[0025] The sealing material 26 seals the metal pattern 27 of the insulating substrate 21, the second semiconductor chip 22, a part of the second AC terminal 23, a part of the N terminal 24, and a part of the control terminal 25. The sealing material 26 is, for example, a resin. The sealing material 26 is formed, for example, by molding. The sealing material 26 has a rectangular shape in a plan view.

[0026] Figure 7 1 is a diagram showing a connection structure between the upper arm semiconductor package 111 and the lower arm semiconductor package 121 . Figure 8 This is a diagram showing the structure of a semiconductor device 101 in the first embodiment.

[0027] The upper arm semiconductor package 111 is arranged so that its second side surface B faces the third side surface C of the lower arm semiconductor package 121. The first AC terminal 14 is connected to the second AC terminal 23. Thus, the switching element 10 of the upper arm semiconductor package 111 and the switching element 10 of the lower arm semiconductor package 121 are connected in series with each other. When the semiconductor device 101 is assembled into an inverter circuit, AC wiring for supplying power to a load is connected to the first AC terminal 14 or the second AC terminal 23.

[0028] The bus bar 31 is connected to the N terminal 24 of the lower arm semiconductor package 121. The bus bar 31 extends from the N terminal 24 thereof in the direction of the first side surface A where the P terminal 13 is provided. The bus bar 31 in Embodiment 1 is arranged on the upper surface of the upper arm semiconductor package 111. In other words, the bus bar 31 extends from the N terminal 24 across the upper surface of the upper arm semiconductor package 111 in the direction of the first side surface A.

[0029] The bus bar 31 includes a bus bar terminal portion 31A on the first side surface A side of the upper arm semiconductor package 111. The bus bar terminal portion 31A is arranged in parallel with the P terminal 13 of the upper arm semiconductor package 111. The bus bar terminal portion 31A has the same potential as the N terminal 24 of the lower arm semiconductor package 121.

[0030] In summary, the semiconductor device 101 in Embodiment 1 includes an upper arm semiconductor package 111, a P terminal 13, a first AC terminal 14, a lower arm semiconductor package 121, a second AC terminal 23, an N terminal 24, and a bus bar 31. The upper arm semiconductor package 111 includes a first semiconductor chip 12. The P terminal 13 is provided on a first side surface A as an example of a first surface of the upper arm semiconductor package 111. The P terminal 13 is electrically connected to the first polarity side of the first semiconductor chip 12. The first AC terminal 14 is provided on a second side surface B as an example of a second surface of the upper arm semiconductor package 111. That is, the first AC terminal 14 is electrically connected to the second polarity side of the first semiconductor chip 12. The lower arm semiconductor package 121 includes a second semiconductor chip 22. The second AC terminal 23 is provided on a third side surface C as an example of a third surface of the lower arm semiconductor package 121. The second AC terminal 23 is electrically connected to the first polarity side of the second semiconductor chip 22. The N terminal 24 is provided on a third side surface C as an example of a third surface of the lower arm semiconductor package 121. The N terminal 24 is electrically connected to the second polarity side of the second semiconductor chip 22. The bus bar 31 is connected to the N terminal 24. The first AC terminal 14 is connected to the second AC terminal 23. The bus bar 31 extends from the N terminal 24 toward the first side surface A as an example of a first surface where the P terminal 13 is provided.

[0031] When the switch element 10 included in the first semiconductor chip 12 and the second semiconductor chip 22 is an IGBT, the first side is the collector side of the IGBT, and the second side is the emitter side. When the switch element 10 is a MOSFET, the first side is the drain side of the MOSFET, and the second side is the source side.

[0032] Such a semiconductor device 101 reduces the inductance in a circuit in which the upper arm semiconductor package 111 and the lower arm semiconductor package 121 are connected in series to each other.

[0033] In Embodiment 1, an example in which the semiconductor device 101 is applied to a three-phase inverter is shown. However, the device in which the semiconductor device 101 is assembled is not limited to the three-phase inverter. The semiconductor device 101 can be applied to a system in which a plurality of semiconductor packages such as other power control devices and signal processing devices are connected in series, and such a system has the same effect as described above. In addition, the first pole side can be the negative pole side, and the second pole side can be the positive pole side.

[0034] <Implementation method 2> Embodiment 2 is a subordinate concept of Embodiment 1. In Embodiment 2, the same reference numerals are given to the same components as those in Embodiment 1, and their detailed descriptions are omitted.

[0035] Fig. 91 is a diagram showing a structure of a semiconductor device 102 in Embodiment 2. The semiconductor device 102 includes a third AC terminal 29 in a lower arm semiconductor package 122. The upper arm semiconductor package 112 is the same as the upper arm semiconductor package 111 in Embodiment 1.

[0036] The third AC terminal 29 is formed of, for example, a metal frame. Although the internal structure of the semiconductor package 122 for the lower arm is omitted from illustration, one end of the third AC terminal 29 is connected to the metal pattern 27 through a bonding material. That is, the third AC terminal 29 is electrically connected to the first pole side of the second semiconductor chip 22 via its metal pattern 27. The first pole side is the collector side of the IGBT. The other end of the third AC terminal 29 protrudes from the fourth side surface D of the semiconductor package 122 for the lower arm. That is, the third AC terminal 29 is provided on the fourth side surface D which is an example of a fourth surface different from the third side surface C on which the second AC terminal 23 is provided. The potential of the third AC terminal 29 is the same as that of the second AC terminal 23.

[0037] In such a semiconductor device 102 , AC wiring for supplying power to a load can be connected between the first side face A and the third side face C or to the fourth side face D side, so the AC wiring can be easily taken out.

[0038] <Implementation method 3> Embodiment 3 is a subordinate concept of Embodiment 1. In Embodiment 3, the same reference numerals are given to the same components as those in Embodiment 1 or Embodiment 2, and their detailed descriptions are omitted.

[0039] Fig.10 This is a diagram showing the structure of a semiconductor device 103 in the third embodiment. Fig.11 1 is a diagram showing a connection structure between the upper arm semiconductor package 113 and the lower arm semiconductor package 123 . Fig.12 1 is a diagram showing the structure of the upper arm semiconductor package 113 . Fig.13 1 is a diagram showing the structure of the semiconductor package 123 for the lower arm. Fig.14 1 is a diagram showing the internal structure of the upper arm semiconductor package 113 . Fig.15 1 is a diagram showing the internal structure of the semiconductor package 123 for the lower arm. Fig.16 It is a plan view showing the internal structure of the upper arm semiconductor package 113 . Fig.17 It is a plan view showing the internal structure of the semiconductor package 123 for the lower arm.

[0040] The P terminal 13 includes two P terminal elements 13A. The two P terminal elements 13A are separate components, each formed by a metal frame. The P terminal element 13A is connected to the metal pattern 17 via a bonding material 18B. The two P terminal elements 13A protrude from two locations of the first side surface A of the upper arm semiconductor package 113. The two P terminal elements 13A are arranged on both sides of the control terminal 15.

[0041] The first AC terminal 14 is electrically connected to the second electrode side of the first semiconductor chip 12 via the bonding material 18C as in Embodiment 1. The first AC terminal 14 in Embodiment 3 includes two first AC terminal portions 14A branching from the upper arm semiconductor package 113 and protruding from two locations on the second side surface B.

[0042] The second AC terminal 23 includes two second AC terminal elements 23A. The two second AC terminal elements 23A are separate components, each of which is formed of a metal frame. The second AC terminal element 23A is connected to the metal pattern 27 via a bonding material 28B. The two second AC terminal elements 23A protrude from two locations of the third side surface C of the semiconductor package 123 for the lower arm, respectively. The two second AC terminal elements 23A are arranged on both sides of the N terminal 24. The second AC terminal element 23A is connected to the first AC terminal portion 14A.

[0043] The third AC terminal 29 includes two third AC terminal elements 29A. The two third AC terminal elements 29A are separate components, each formed of a metal frame. The third AC terminal element 29A is connected to the metal pattern 27 via a bonding material 28D. The two third AC terminal elements 29A protrude from two locations of the fourth side surface D of the semiconductor package 123 for the lower arm, respectively. The two third AC terminal elements 29A are arranged on both sides of the control terminal 25.

[0044] The bus bar 31 includes two bus bar terminal portions 31A on the first side surface A side of the upper arm semiconductor package 113 .

[0045] In such a semiconductor device 103, the number of terminals increases, so the number of current paths also increases. In addition, since the current paths intersect, the inductance decreases.

[0046] The P terminal 13 may include three or more P terminal elements 13A. The first AC terminal 14 may include three or more first AC terminal portions 14A. The second AC terminal 23 may include three or more second AC terminal elements 23A. The third AC terminal 29 may include three or more third AC terminal elements 29A. In any case, the same effect as described above is achieved.

[0047] <Implementation method 4> Embodiment 4 is a subordinate concept of Embodiment 1. In Embodiment 4, the same reference numerals are given to the same components as those in any one of Embodiments 1 to 3, and their detailed descriptions are omitted.

[0048] Fig.18 1 is a diagram showing a structure of a semiconductor device 104 in Embodiment 4. The semiconductor device 104 includes an upper arm semiconductor package 114 and a lower arm semiconductor package 124. The lower arm semiconductor package 124 is the same as the lower arm semiconductor package 122 in Embodiment 2.

[0049] The upper arm semiconductor package 114 is not provided with the control terminal 15. When control of a diode (not shown) or the like related to driving the switching element 10 is not necessary, the control terminal 15 is not necessarily required.

[0050] Such a semiconductor device 104 improves the degree of freedom in layout when constructing a power control device such as an inverter circuit.

[0051] The lower arm semiconductor package 124 is provided with a control terminal 25, but when control by a diode or the like is not required, the control terminal 25 may not be provided. Similarly, the control terminals 15 and 25 may not be provided on both the upper arm semiconductor package 114 and the lower arm semiconductor package 124. In either case, the same effect as described above is achieved.

[0052] <Implementation method 5> In the fifth embodiment, the same components as those in any one of the first to fourth embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0053] Fig.19 1 is a side view showing an example of a holding structure of a semiconductor chip 52 in Embodiment 5. The semiconductor chip 52 corresponds to the first semiconductor chip 12 or the second semiconductor chip 22 .

[0054] The semiconductor device in the fifth embodiment includes a metal plate 53 , an insulating material 54 , and a heat sink 55 instead of the insulating substrates 11 , 21 having the metal patterns 17 , 27 .

[0055] The insulating material 54 is provided on the surface of the metal plate 53. The heat sink 55 is provided on the insulating material 54. The heat sink 55 holds the semiconductor chip 52 via the bonding material 56.

[0056] The heat capacity of the heat sink 55 is larger than that of the insulating substrates 11 and 21 having the metal patterns 17 and 27. Therefore, such a semiconductor device has a reduced transient thermal resistance.

[0057] <Implementation method 6> Embodiment 6 is a subordinate concept of Embodiment 1. In Embodiment 6, the same reference numerals are given to the same components as those in any one of Embodiments 1 to 5, and their detailed descriptions are omitted.

[0058] Fig. 20 and Fig.21 1 is a diagram showing an example of the structure of the upper arm semiconductor package 116 and the bus bar 32 in the sixth embodiment.

[0059] The upper arm semiconductor package 116 includes two protrusions 16B on its upper surface. The protrusions 16B are formed as a part of the sealing material 16. The bus bar 32 includes two holes 32B corresponding to the two protrusions 16B. The holes 32B of the bus bar 32 fit into the protrusions 16B of the upper arm semiconductor package 116.

[0060] In the semiconductor device assembly process, the mounting position of the bus bar 32 relative to the upper arm semiconductor package 116 is determined by its fitting structure. The number of protrusions 16B and holes 32B is not limited to two, but may be one or three or more.

[0061] <Implementation method 7> Embodiment 7 is a subordinate concept of Embodiment 1. In Embodiment 7, the same reference numerals are given to the same components as those in any one of Embodiments 1 to 6, and their detailed descriptions are omitted.

[0062] Fig. 22 1 is a plan view showing the internal structure of the upper arm semiconductor package 117 in the seventh embodiment. Fig.23 It is a plan view showing the internal structure of the semiconductor package 127 for the lower arm.

[0063] The first semiconductor chip 12 and the second semiconductor chip 22 include SiC as a semiconductor material. With such a structure, the output of the semiconductor device is increased.

[0064] <Implementation method 8> In Embodiment 8, the same reference numerals are given to the same components as those in any one of Embodiments 1 to 7, and their detailed descriptions are omitted.

[0065] Fig.24 This is a diagram showing the structure of a semiconductor device 108 in the eighth embodiment.

[0066] The semiconductor device 108 includes two upper arm semiconductor packages 118 and two lower arm semiconductor packages 128. The two upper arm semiconductor packages 118 are arranged in parallel with each other. The two lower arm semiconductor packages 128 are arranged in parallel with each other. The upper arm semiconductor package 118 has the same structure as the upper arm semiconductor package 113 in Embodiment 3. The lower arm semiconductor package 128 has the same structure as the lower arm semiconductor package 123 in Embodiment 3.

[0067] The upper arm semiconductor package 118 is arranged so that its second side surface B faces the third side surface C of the lower arm semiconductor package 128. The first AC terminal portion 14A is connected to the second AC terminal element 23A. Thus, the switching element 10 of the upper arm semiconductor package 118 and the switching element 10 of the lower arm semiconductor package 128 are connected in series.

[0068] The bus bar 31 is a single component, and is connected to all the N terminals 24 of the two lower arm semiconductor packages 128 .

[0069] With such a structure, the area of ​​the current path in the bus bar 31 increases, thereby reducing the inductance.

[0070] Each of the two upper arm semiconductor packages 118 may have the same structure as the upper arm semiconductor package described in any one of Embodiments 1 to 7. Each of the two lower arm semiconductor packages 128 may have the same structure as the lower arm semiconductor package described in any one of Embodiments 1 to 7.

[0071] The number of the upper arm semiconductor package 118 and the number of the lower arm semiconductor package 128 may each be 3. Even in this case, the bus bar 31 is a single component and is connected to all the N terminals 24 .

[0072] <Implementation method 9> In Embodiment 9, the same reference numerals are given to the same components as those in any one of Embodiments 1 to 8, and their detailed descriptions are omitted.

[0073] Fig.25 1 is a plan view showing the internal structure of the upper arm semiconductor package 119 in the ninth embodiment. Fig.26 It is a plan view showing the internal structure of the semiconductor package 129 for the lower arm.

[0074] The upper arm semiconductor package 119 includes two first semiconductor chips 12. The first AC terminal 14 is collectively connected to the second polarity side of the two first semiconductor chips 12. The second polarity side is, for example, the emitter side of the IGBT.

[0075] The semiconductor package 129 for the lower arm includes two second semiconductor chips 22. The N terminals 24 are connected collectively to the second polarity sides of the two second semiconductor chips 22.

[0076] Since a plurality of first semiconductor chips 12 and a plurality of second semiconductors are mounted, the output of the semiconductor device increases.

[0077] In the ninth embodiment, the upper arm semiconductor package 119 may have the same structure as the upper arm semiconductor package described in any one of the first to seventh embodiments. The lower arm semiconductor package 129 may have the same structure as the lower arm semiconductor package described in any one of the first to seventh embodiments.

[0078] The number of the first semiconductor chips 12 and the number of the second semiconductor chips 22 may be three or more, respectively.

[0079] The present disclosure has been described in detail, but the above description is in all aspects illustrative and not restrictive, and it is understood that numerous modifications not shown are conceivable.

[0080] The present disclosure can freely combine the various embodiments, or appropriately modify or omit the various embodiments. Description of symbols

[0081] 10 switching element, 11 insulating substrate, 12 first semiconductor chip, 13 P terminal, 13A P terminal element, 14 first AC terminal, 14A first AC terminal portion, 15 control terminal, 16 sealing material, 16B protrusion, 17 metal pattern, 18A to 18C bonding materials, 19 control wire, 21 insulating substrate, 22 second semiconductor chip, 23 second AC terminal, 23A second AC terminal element, 24 N terminal, 25 control terminal, 26 sealing material, 27 metal pattern, 28A to 28D bonding materials, 29 third AC terminal, 29A third AC terminal element , 31 bus bar, 31A bus bar terminal portion, 32 bus bar, 32B hole, 52 semiconductor chip, 53 metal plate, 54 insulating material, 55 heat sink, 56 bonding material, 101~104 semiconductor device, 108 semiconductor device, 111~114 semiconductor package for upper arm, 116~119 semiconductor package for upper arm, 121~124 semiconductor package for lower arm, 127~129 semiconductor package for lower arm, A first side surface, B second side surface, C third side surface, D fourth side surface.

Claims

1. A semiconductor device, characterized in that: include: a first semiconductor package including a first semiconductor chip; A first terminal, which is disposed on a first surface of the first semiconductor package and is electrically connected to a first polar side of the first semiconductor chip; a first output terminal, the first output terminal being disposed on the second surface of the first semiconductor package and electrically connected to the second polar side of the first semiconductor chip; a second semiconductor package including a second semiconductor chip; a second output terminal, the second output terminal being disposed on the third surface of the second semiconductor package and electrically connected to the first electrode side of the second semiconductor chip; a second terminal, the second terminal being disposed on the third surface of the second semiconductor package and electrically connected to the second electrode side of the second semiconductor chip; as well as a bus bar connected to the second terminal, The first output terminal is connected to the second output terminal, The bus bar extends from the second terminal toward the first surface where the first terminal is provided.

2. The semiconductor device according to claim 1, wherein The first semiconductor package is arranged such that the second surface of the first semiconductor package is opposite to the third surface of the second semiconductor package, The bus bar includes at least one bus bar terminal portion on the first surface side of the first semiconductor package and is disposed on the upper surface of the first semiconductor package. The at least one bus bar terminal portion is arranged side by side with the first terminal on the first surface side of the first semiconductor package.

3. The semiconductor device according to claim 1 or 2, wherein: The device further includes a third output terminal, which is disposed on the fourth surface of the second semiconductor package and is electrically connected to the first polar side of the second semiconductor chip.

4. The semiconductor device according to claim 2, wherein: The first terminal includes a plurality of terminal elements protruding from a plurality of positions of the first surface of the first semiconductor package, respectively. The first output terminal includes a plurality of output terminal portions branching from the inside of the first semiconductor package and protruding from a plurality of positions of the second surface, respectively. The second output terminal includes a plurality of output terminal elements protruding from a plurality of positions of the third surface of the second semiconductor package, respectively. The at least one bus bar terminal portion is a plurality of bus bar terminal portions.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The semiconductor device further includes a control terminal for transmitting a control signal related to control of a switching element included in the first semiconductor chip or the second semiconductor chip.

6. The semiconductor device according to any one of claims 1 to 5, wherein: Also included is an insulating substrate including a metal pattern on a surface thereof, The insulating substrate holds the first semiconductor chip or the second semiconductor chip via the metal pattern.

7. The semiconductor device according to any one of claims 1 to 5, wherein: Also includes: Metal sheets; An insulating material disposed on a surface of the metal plate; as well as A heat sink is provided on the insulating material, The heat sink holds the first semiconductor chip or the second semiconductor chip.

8. The semiconductor device according to claim 2, wherein: The first semiconductor package comprises at least one protrusion on the upper surface, The bus bar comprises at least one hole, The at least one hole of the bus bar is engaged with the at least one protrusion of the first semiconductor package.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The first semiconductor chip or the second semiconductor chip contains SiC as a semiconductor material.

10. A semiconductor device, characterized in that: include: a plurality of first semiconductor packages, the plurality of first semiconductor packages are arranged in parallel with each other and each comprises a first semiconductor chip; A first terminal, the first terminal being disposed on a first surface of each of the plurality of first semiconductor packages and electrically connected to a first polar side of the first semiconductor chip; a first output terminal, the first output terminal being disposed on the second surface of each of the plurality of first semiconductor packages and electrically connected to the second polar side of the first semiconductor chip; a plurality of second semiconductor packages, the plurality of second semiconductor packages being arranged in parallel with each other and each comprising a second semiconductor chip; a second output terminal, the second output terminal being disposed on the third surface of each of the plurality of second semiconductor packages and electrically connected to the first electrode side of the second semiconductor chip; a second terminal, the second terminal being disposed on the third surface of each of the plurality of second semiconductor packages and electrically connected to the second electrode side of the second semiconductor chip; as well as a bus bar connected to the second terminal, The first output terminal is connected to the second output terminal, The bus bar extends from the second terminal toward the first surface where the first terminal is provided.

11. A semiconductor device, characterized in that: include: a first semiconductor package including a plurality of first semiconductor chips; A first terminal, which is disposed on a first surface of the first semiconductor package and is electrically connected to a first polar side of the plurality of first semiconductor chips; A first output terminal, which is disposed on the second surface of the first semiconductor package and is electrically connected to the second polar side of the plurality of first semiconductor chips; a second semiconductor package including a plurality of second semiconductor chips; a second output terminal, which is disposed on the third surface of the second semiconductor package and is electrically connected to the first polarity side of the plurality of second semiconductor chips; a second terminal, which is disposed on the third surface of the second semiconductor package and is electrically connected to the second electrode side of the plurality of second semiconductor chips; as well as a bus bar connected to the second terminal, The first output terminal is connected to the second output terminal, The bus bar extends from the second terminal toward the first surface where the first terminal is provided.

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