DC / DC converter

Abstract

The switching modulation circuit (11) generates a first control signal having a predetermined duty ratio. The delay circuit (16) delays the first control signal and generates a second control signal. The zero-crossing detector (12) detects whether or not the output current of the DC / DC converter (1) is less than the threshold value in the rectification section, and generates a third control signal. The monitoring circuit detects a reverse current possibility of the output current and generates a fourth control signal. The delay time of the delay circuit is set to be shorter than the delay time of the zero crossing detector (12). The drive circuit turns off both of the first and second switching elements (Q1, Q2) when the third control signal transitions to indicate that the output current is less than the threshold value without the possibility of reverse current. The drive circuit turns off both the first and second switching elements (Q1, Q2) when there is a possibility of reverse current and when the second control signal transitions from the ON state to the OFF state.

Description

Technical Field

[0001] The present disclosure relates to a DC / DC converter and a control circuit thereof. Background Art

[0002] In recent years, as portable devices have become more functional and smaller, a large number of hysteresis-controlled switching power supplies that can be highly efficient and small and operate at high frequencies have been used as power supply circuits. For example, Patent Document 1 discloses a switching regulator that operates in a synchronous mode in which two power transistors are turned on complementarily, and in an asynchronous mode in which a high-side power transistor is turned on / off while a low-side power transistor is turned off.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent No. 8836294 Summary of the invention

[0006] Problems to be solved by the invention

[0007] If a DC / DC converter performs synchronous rectification when a light load is applied, a reverse current may sometimes be generated in the output terminal, and its efficiency is significantly reduced. In order to prevent the reverse current, for example, a current detection circuit is sometimes used to monitor the output current of the DC / DC converter. However, generally, since the current detection circuit has an inherent delay time, even if a precursor to the generation of a reverse current is detected, such as the output current becoming less than a specified threshold, the switching element cannot be turned off in time. As a result, a reverse current is generated during the period when the switching element is turned on, and the efficiency is reduced. In addition, when the peak value of the output current is small, it is considered that there is a concern about the generation of a reverse current, and the switching element is sometimes turned off. However, when the switching element is turned off, the energy of the inductor is released, so that the current flows through the body diode of the switching element, resulting in a decrease in efficiency. Therefore, it is required to prevent or at least reduce the reverse current and make the DC / DC converter operate more efficiently than before.

[0008] The present disclosure aims to provide a control circuit for a DC / DC converter that can prevent or at least reduce a reverse current and operate the DC / DC converter more efficiently than before. Furthermore, the present disclosure aims to provide a DC / DC converter having such a control circuit.

[0009] Means for solving problems

[0010] According to a control circuit of a DC / DC converter according to one embodiment of the present disclosure,

[0011] In a control circuit for controlling a DC / DC converter including an inductor and first and second switching elements for storing and releasing energy in the inductor,

[0012] The control circuit comprises:

[0013] The switch modulation circuit generates a first control signal having a predetermined duty ratio including an on state and an off state;

[0014] A delay circuit delays the first control signal by a first delay time to generate a second control signal;

[0015] a zero crossing detector for detecting whether the output current of the DC / DC converter is less than a first threshold value when the energy of the inductor is released, and generating a third control signal indicating whether the output current is less than the first threshold value;

[0016] a monitoring circuit for detecting whether there is a possibility of a reverse flow of the output current, and generating a fourth control signal indicating whether there is a possibility of the reverse flow; and

[0017] a drive circuit that generates a drive signal for turning on / off the first and second switch elements based on the first to fourth control signals,

[0018] The zero-crossing detector has a second delay time inherent to the zero-crossing detector from the time when the output current is detected to be less than the first threshold value to the time when the state of the third control signal is changed.

[0019] The first delay time is set shorter than the second delay time.

[0020] When the fourth control signal is in a state indicating that there is no possibility of the backflow, the drive circuit turns off both the first and second switching elements when the energy of the inductor is released and the third control signal changes to indicate that the output current is less than the first threshold value.

[0021] When the fourth control signal is in a state indicating the possibility of the backflow, the drive circuit turns off both the first and second switching elements when the energy of the inductor is released and the second control signal changes from an on state to an off state.

[0022] Effects of the Invention

[0023] According to one aspect of the present disclosure, it is possible to prevent or at least reduce a reverse current and operate a DC / DC converter more efficiently than before. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a block diagram showing the configuration of a DC / DC converter 1 according to the first embodiment.

[0025] Figure 2 Yes means Figure 1 1 is a timing chart of a first operation example of the DC / DC converter 1.

[0026] Figure 3 Yes means Figure 1 1 is a timing chart of a second operation example of the DC / DC converter 1.

[0027] Figure 4 Yes means Figure 1 1 is a timing chart of a third operation example of the DC / DC converter 1.

[0028] Figure 5 Yes means Figure 1 A circuit diagram of the structure of the delay circuit 16 is shown in FIG.

[0029] Figure 6 : is a circuit diagram showing the configuration of a delay circuit 16A according to a first modification.

[0030] Figure 7 : is a circuit diagram showing the configuration of a delay circuit 16B according to a second modification.

[0031] Figure 8 : is a circuit diagram showing the configuration of a delay circuit 16C according to a third modification.

[0032] Fig. 9 : is a circuit diagram showing the structure of a delay circuit 16D according to a fourth modification.

[0033] Fig.10 It is a block diagram showing the configuration of a DC / DC converter 1A according to the second embodiment.

[0034] Fig.11 Yes means Fig.10 1 is a timing chart of a first operation example of the DC / DC converter 1A.

[0035] Fig.12 Yes means Fig.10 1A is a timing chart of a second operation example of the DC / DC converter 1A.

[0036] Fig.13 : is a circuit diagram showing the structure of a delay circuit 16E according to the fifth modification.

[0037] Fig.14 It is a block diagram showing the configuration of a DC / DC converter 1B according to the third embodiment.

[0038] Fig.15 It is a block diagram showing the configuration of a DC / DC converter 1C according to the first comparative example.

[0039] Fig.16 Yes means Fig.15 1 is a timing chart of a first operation example of the DC / DC converter 1C.

[0040] Fig.17 Yes means Fig.15 1C is a timing chart of a second operation example of the DC / DC converter 1C.

[0041] Fig.18 It is a block diagram showing the configuration of a DC / DC converter 1D according to a second comparative example.

[0042] Fig.19 Yes means Fig.18 1 is a timing chart of a first operation example of the DC / DC converter 1D.

[0043] Fig. 20 Yes means Fig.18 1 is a timing chart of a second operation example of the DC / DC converter 1D.

[0044] Fig.21 Yes means Fig.18 1 is a timing chart of a third operation example of the DC / DC converter 1D. DETAILED DESCRIPTION

[0045] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In each of the drawings, the same components are denoted by the same reference numerals.

[0046] Before describing the embodiment of the present disclosure in detail, the configuration and operation of a DC / DC converter according to a comparative example will be described.

[0047] [Comparative Example 1]

[0048] Fig.15 1 is a block diagram showing the structure of a DC / DC converter 1C according to the first comparative example. The DC / DC converter 1C receives an input voltage Vin from an input voltage source Vdd, generates an output voltage Vout at its output terminal Nout, and supplies the output voltage Vout to a load device 2. The DC / DC converter 1C is an example of a step-down converter that generates an output voltage Vout lower than the input voltage Vin.

[0049] The DC / DC converter 1C includes switching elements Q1 and Q2 , an inductor L1 , a capacitor C1 , a control circuit 10C, and a current sensor 21 .

[0050] The switch elements Q1 and Q2 are connected in series between the input voltage source Vdd and the ground. The switch elements Q1 and Q2 are respectively arranged on the high side and the low side. The switch element Q1 is, for example, a P-channel field effect transistor, and the switch element Q2 is, for example, an N-channel field effect transistor.

[0051] The inductor L1 is connected between a node between the switching elements Q1 and Q2 and an output terminal Nout of the DC / DC converter 1C. The capacitor C1 is connected between the output terminal Nout of the DC / DC converter 1C and the ground.

[0052] The current sensor 21 detects the value of the output current Iout of the DC / DC converter 1C. In the first comparative example, the value of the output current Iout flowing when the energy of the inductor L1 is released is used by the zero-crossing detector 12 (described later) of the control circuit 10C. Therefore, the current sensor 21 may be configured to detect the value of the output current Iout by monitoring the voltage across the switching element Q2, for example.

[0053] The control circuit 10C generates drive signals S1 and S2 for controlling the on / off of each switching element Q1 and Q2 based on the values ​​of the output voltage Vout and the output current Iout, and applies the drive signals S1 and S2 to the control electrodes (gates) of each switching element Q1 and Q2. Thus, the control circuit 10C controls the switching elements Q1 and Q2 to store and release energy in the inductor L1.

[0054] The control circuit 10C includes a switching modulation circuit 11 , a zero-crossing detector 12 , an inverter 61 , and a NOR circuit 62 .

[0055] The switching modulation circuit 11 generates a signal S0 having a predetermined duty ratio including an on state and an off state based on the value of the output voltage Vout. The switching modulation circuit 11 changes the duty ratio of the signal S0 so that the output voltage Vout matches the desired voltage of the load device 2 .

[0056] The zero-crossing detector 12 detects that the output current Iout of the DC / DC converter 1 is less than the threshold value Ith1 when the energy of the inductor L1 is released, and generates a signal Szc indicating whether the output current Iout is less than the threshold value Ith1. When the output current Iout is greater than the threshold value Ith1 when the energy of the inductor L1 is released, the signal Szc becomes a low level, and when the output current Iout is less than the threshold value Ith1 when the energy of the inductor L1 is released, the signal Szc becomes a high level. The zero-crossing detector 12 has a delay time d1 inherent to the zero-crossing detector 12 from the detection that the output current Iout is less than the threshold value Ith1 to the transition of the state of the signal Szc.

[0057] The inverter 61 inverts the signal S0 to generate a signal S1. The NOR circuit 62 performs a NOR operation on the signals S0 and Szc to generate a signal S2.

[0058] Fig.16 Yes means Fig.15 1 is a timing chart of a first operation example of the DC / DC converter 1C. Fig.17 Yes means Fig.15 1C is a timing chart of a second operation example of the DC / DC converter 1C. Fig.16 as well as Fig.17 express Fig.15 The output current Iout, signal Szc, and signals S0 to S1. The switching operation of the switching elements Q1 and Q2 includes a conduction interval, a rectification interval, and a cutoff interval in one cycle. The "conduction interval" represents the time interval during which energy is stored in the inductor. Fig.15 In the example of , it indicates the time interval during which the switch element Q1 is turned on and the switch element Q2 is turned off. The “rectification period” indicates the time interval during which the energy of the inductor is released. Fig.15 In the example of , the time interval in which the switching element Q1 is turned off and the switching element Q2 is turned on is indicated. The "off interval" indicates a time interval in which both the switching elements Q1 and Q2 are turned off.

[0059] Fig.16 Indicates a case where the peak value of the output current Iout is large enough. In this case, in the rectification interval, the zero-crossing detector 12 changes the signal Szc from a low level (L) to a high level (H) after a delay time d1 has passed since the output current Iout became less than the threshold value Ith1. As a result, both the switching elements Q1 and Q2 are turned off. Considering the delay time d1 of the zero-crossing detector 12, the threshold value Ith1 is set so that the output current Iout becomes zero at the moment the signal Szc rises. Fig.16 As shown, when the peak value of the output current Iout is large enough, even if the zero crossing detector 12 has a delay time d1, the signal Szc changes from a low level to a high level before the reverse current is generated. Thus, the reverse current can be prevented or at least reduced by using the zero crossing detector 12. In addition, the zero crossing detector 12 resets the signal Szc to a low level at the end of the cycle based on the signal S0.

[0060] on the other hand, Fig.17Indicates the case where the peak value of the output current Iout is less than the threshold value Ith1. In this case, the zero-crossing detector 12 detects that the output current Iout is less than the threshold value Ith1 at the moment of entering the rectification interval. However, due to the delay time d1, the zero-crossing detector 12 cannot immediately change the signal Szc from a low level to a high level. Therefore, at the moment when the output current Iout decreases to zero, the switching element Q2 is not turned off, and a reverse current is generated.

[0061] according to Fig.15 Even if the DC / DC converter 1C includes the zero-crossing detector 12, when the peak value of the output current Iout is small, there is a possibility that the reverse current cannot be prevented from occurring. Therefore, it is required to more reliably prevent or at least reduce the reverse current.

[0062] [Comparative Example 2]

[0063] Fig.18 1D is a block diagram showing the configuration of a DC / DC converter 1D according to a second comparative example. The DC / DC converter 1D includes a control circuit 10D in place of Fig.15 control circuit 10C.

[0064] The control circuit 10D includes a switching modulation circuit 11 , a zero-crossing detector 12 , a peak current detector 13 , an inverter 71 , an inverter 72 , and a NOR circuit 73 .

[0065] Fig.18 The switching modulation circuit 11 and the zero-crossing detector 12 are similarly configured as Fig.15 , and operate in the same manner.

[0066] The peak current detector 13 detects the possibility of reverse flow that generates a reverse flow of the output current Iout, and generates a signal Spc indicating whether there is a possibility of reverse flow. The peak current detector 13 detects the possibility of reverse flow when the output current Iout does not exceed the threshold value Ith2 when energy is accumulated in the inductor L1. When the output current Iout is less than the threshold value Ith2 when energy is accumulated in the inductor L1, the signal Spc becomes a low level, and when the output current Iout is greater than the threshold value Ith2 when energy is accumulated in the inductor L1, the signal Spc becomes a high level. The possibility of reverse flow is, for example, a precursor to the generation of a reverse flow current. The peak current detector 13 has a unique delay time d2 for the peak current detector 13 from the detection of the output current Iout being greater than the threshold value Ith2 to the transition of the state of the signal Spc.

[0067] The inverter 71 inverts the signal Spc. The inverter 72 inverts the signal S0 and generates a signal S1. The NOR circuit 73 performs a NOR operation on the signal S0, the inverted signal of the signal Spc, and the signal Szc, and generates a signal S2.

[0068] In the second comparative example, the value of the output current Iout flowing when the energy of the inductor L1 is released is used by the zero-crossing detector 12 of the control circuit 10D. Therefore, the current sensor 21 may be configured to detect the value of the output current Iout by, for example, monitoring the voltage across the switching element Q2 for the zero-crossing detector 12. In addition, in the second comparative example, the value of the output current Iout flowing when the energy is accumulated in the inductor L1 is used by the peak current detector 13 (described later) of the control circuit 10D. Therefore, the current sensor 21 may be configured to detect the value of the output current Iout by, for example, monitoring the voltage across the switching element Q1 for the peak current detector 13.

[0069] Fig.19 Yes means Fig.18 1 is a timing chart of a first operation example of the DC / DC converter 1D. Fig. 20 Yes means Fig.18 1 is a timing chart of a second operation example of the DC / DC converter 1D. Fig.21 Yes means Fig.18 1 is a timing chart of a third operation example of the DC / DC converter 1D. Figure 19 to Figure 21 In addition to expressing Figure 16-17 In addition to the various signals shown, a signal Spc is also shown.

[0070] Fig.19 Indicates that the peak value of the output current Iout is large enough, for example, greater than the threshold value Ith2. Fig.16 As described above, the threshold value Ith2 is set to a level at which the peak value of the output current Iout becomes large enough to cause the signal Szc to change from a low level to a high level before the reverse current is generated. Fig.19 As shown, the threshold value Ith2 may also be set to be greater than the threshold value Ith1. In this case, the peak current detector 13 changes the signal Spc from a low level to a high level after a delay time d2 has passed since the output current Iout has become greater than the threshold value Ith2 in the conduction interval. Thereafter, the zero-crossing detector 12 changes the signal Szc from a low level to a high level after a delay time d1 has passed since the output current Iout has become less than the threshold value Ith1 in the rectification interval. As a result, both the switching elements Q1 and Q2 are turned off. The peak current detector 13 resets the signal Spc to a low level at the end of the cycle based on the signal S0.

[0071] Fig. 20Indicates the case where the peak value of the output current Iout is greater than the threshold value Ith1 and less than the threshold value Ith2. In this case, the signal Spc remains at a low level, and the switch element Q2 does not conduct even when the conduction interval ends, and directly transfers to the cut-off interval. The switch element Q2 is not turned on, so no reverse current is generated. However, the energy of the inductor L1 is released by flowing through the body diode of the switch element Q2.

[0072] Fig.21 Indicates the case where the peak value of the output current Iout is less than the threshold value Ith1. In addition, this case is also similar to Fig. 20 Similarly, the signal Spc remains at a low level, and the switch element Q2 does not conduct even when the conduction period ends, and directly shifts to the off period. The energy of the inductor L1 is released by flowing through the body diode of the switch element Q2.

[0073] according to Fig.18 The DC / DC converter 1D can prevent the generation of reverse current by including the peak current detector 13, but the current flows through the body diode of the switching element Q2 in the off-time, so the efficiency is lowered compared with the case where the switching element Q2 is turned on. Therefore, it is required to prevent or at least reduce the reverse current and make the DC / DC converter operate more efficiently.

[0074] Hereinafter, a DC / DC converter according to an embodiment will be described which can prevent or at least reduce a reverse current and operate more efficiently than before.

[0075] [First embodiment]

[0076] Reference Figures 1 to 9 , a DC / DC converter according to a first embodiment is described.

[0077] [Structure of the first embodiment]

[0078] Figure 1 It is a block diagram showing the configuration of a DC / DC converter 1 according to the first embodiment.

[0079] The DC / DC converter 1 includes switching elements Q1 and Q2, an inductor L1, a capacitor C1, and a control circuit.

[0080] 10; and a current sensor 21.

[0081] Figure 1 The switching elements Q1, Q2, the inductor L1, the capacitor C1, and the current sensor 21 are connected to Fig.15 as well as Fig.18 The corresponding structural elements are constructed similarly and operate similarly.

[0082] The control circuit 10 includes a switching modulation circuit 11, a zero-crossing detector 12, a peak current detector 13, a NAND circuit 14, an inverter 15, a delay circuit 16, a NOR circuit 17, an inverter 18, and a NOR circuit 19. The control circuit 10 may be configured as an integrated circuit having terminals N0 to N4.

[0083] Figure 1 The switching modulation circuit 11, the zero crossing detector 12, and the peak current detector 13 are Fig.18 The corresponding structural elements are constructed similarly and operate similarly.

[0084] The NAND circuit 14 performs a NAND operation on the signals Szc and Spc. The inverter 15 inverts the output signal of the NAND circuit 14.

[0085] The delay circuit 16 delays the signal S0 by a predetermined delay time d10 to generate a signal S0d. The length of the delay time d10 is set shorter than the delay time d1 of the zero-crossing detector 12. The length of the delay time d10 may be a fixed value or may be changed according to the peak value of the output current Iout or the difference between the input voltage Vin and the output voltage Vout.

[0086] The NOR circuit 17 performs a NOR operation on the signal S0, the signal S0d, and the signal Spc. The inverter 18 inverts the signal S0 and generates a signal S1. The NOR circuit 19 performs a NOR operation on the signal S0, the output signal of the inverter 15, and the output signal of the NOR circuit 17 and generates a signal S2.

[0087] The peak current detector 13 is an example of a monitoring circuit that detects the possibility of reverse flow of the output current Iout and generates a control signal indicating whether there is a possibility of reverse flow. In addition, the NAND circuit 14, the inverter 15, the NOR circuit 17, the inverter 18, and the NOR circuit 19 are examples of a driving circuit that generates driving signals S1 and S2 for turning on / off the switching elements Q1 and Q2 based on the signals S0, S0d, Szc, and Spc.

[0088] [Operation of the First Embodiment]

[0089] Figure 2 Yes means Figure 1 1 is a timing chart of a first operation example of the DC / DC converter 1. Figure 3 Yes means Figure 1 1 is a timing chart of a second operation example of the DC / DC converter 1. Figure 4 Yes means Figure 1 1 is a timing chart of a third operation example of the DC / DC converter 1. Figure 2 to Figure 4 In addition to expressing Figure 19 to Figure 21In addition to the various signals shown, a signal S0d is also shown.

[0090] Figure 2 This indicates that the peak value of the output current Iout is large enough, that is, greater than the threshold value Ith2. In this case, the peak current detector 13 changes the signal Spc from a low level to a high level after a delay time d2 has passed since the output current Iout has exceeded the threshold value Ith2 in the conduction interval. Thereafter, the zero-crossing detector 12 changes the signal Szc from a low level to a high level after a delay time d1 has passed since the output current Iout has fallen below the threshold value Ith1 in the rectification interval. As a result, both the switching elements Q1 and Q2 are turned off.

[0091] Figure 3 Indicates the case where the peak value of the output current Iout is greater than the threshold value Ith1 and less than the threshold value Ith2. In this case, after the conduction interval, it is transferred to the rectification interval. After that, when the signal Sd0 changes from a high level to a low level, both the switching elements Q1 and Q2 are turned off. If the output current Iout does not decrease to zero in the rectification interval, the energy of the inductor L1 is released through the body diode of the switching element Q2 in the cut-off interval. However, due to Figure 3 The switching action includes the rectification period, so Fig. 20 Compared with the case of , the time for which the current flows through the body diode of the switching element Q2 becomes shorter, and the efficiency is improved.

[0092] Figure 4 Indicates the case where the peak value of the output current Iout is less than the threshold value Ith1. In addition, this case is also similar to Figure 3 The same is true for the case where the switching element Q1 and Q2 are turned off after the conduction interval. Figure 4 The action of includes the rectification interval, so it is the same as Fig.21 Compared with the case of , the time for which the current flows through the body diode of the switching element Q2 becomes shorter, and the efficiency is improved.

[0093] according to Figure 2 to Figure 4 In accordance with the signal Szc or the signal S0d, the switch elements Q1 and Q2 are turned off, thereby preventing or at least reducing the reverse current. In particular, by setting the length of the delay time d10 to be shorter than the delay time d1 of the zero crossing detector 12, as shown in FIG. Figure 4 As shown, when the output current Iout is small, the switch element Q2 can be turned off before the reverse current is generated, thereby preventing or at least reducing the reverse current. Figure 3-4Even when the output current Iout is less than the threshold value Ith2, the switching action includes the rectification period, so the time for the current to flow through the body diode of the switching element Q2 can be shortened, thereby improving efficiency. Figure 1 The DC / DC converter 1 can prevent or at least reduce the reverse current and operate more efficiently than before.

[0094] [Structure of delay circuit]

[0095] Figure 5 Yes means Figure 1 1 is a circuit diagram of a structure of a delay circuit 16. The delay circuit 16 may also include an even number of inverters 31 connected in series. The delay time d10 of the delay circuit 16 is the sum of the delay times of the inverters 31.

[0096] Figure 6 1 is a circuit diagram showing the configuration of a delay circuit 16A according to a first modification. The delay circuit 16A includes inverters 31-1 to 31-3, switching elements Q31 to Q32, a resistor E31, and a capacitor C31. The delay time d10 of the delay circuit 16A is determined by the time constants of the resistor R31 and the capacitor C31.

[0097] Figure 7 1 is a circuit diagram showing the configuration of a delay circuit 16B according to a second modification. The delay circuit 16B includes a constant current source 32 instead of Figure 6 The delay time d10 of the delay circuit 16B is determined by the current supplied by the constant current source 32 and the capacitance of the capacitor C31.

[0098] Figure 8 1 is a circuit diagram showing a configuration of a delay circuit 16C according to a third modification. The delay circuit 16C includes a variable current source 33 instead of Figure 6 The variable current source 33 may also include a resistor to which the voltage across the switching element Q1 is applied. In this case, the larger the current flowing through the switching element Q1, the larger the voltage across the switching element Q1, and the larger the current flowing through the resistor. By folding back the current of the resistor through the current mirror, a variable current source that changes according to the value of the output current Iout can be obtained. The delay time d10 of the delay circuit 16C changes according to the size of the peak value Ipeak of the output current Iout. By changing the delay time d10, the time for the current to flow through the body diode of the switching element Q2 can be further shortened.

[0099] Fig. 9 1 is a circuit diagram showing a configuration of a delay circuit 16D according to a fourth modification. The delay circuit 16D includes switch elements Q33 to Q36, resistors R32 to R33, and a constant current source 34 in place of Figure 6 resistor R31. Fig. 9 The circuit is a combination of a current mirror circuit that operates as a variable current source that changes according to the input voltage Vin, and a current mirror circuit that operates as a variable current source that changes according to the output voltage Vout. The delay time d10 of the delay circuit 16D changes according to the difference between the input voltage Vin and the output voltage Vout of the DC / DC converter 1. The lower the input voltage Vin and / or the higher the output voltage Vout, the shorter the delay time d10. By changing the delay time d10, the time for the current to flow through the body diode of the switching element Q2 can be further shortened.

[0100] Not limited to Figures 5 to 9 Examples of this invention may use any other delay circuit.

[0101] [Summary of the First Embodiment]

[0102] As described above, the DC / DC converter 1 according to the first embodiment can prevent or at least reduce the reverse current and can operate more efficiently than before.

[0103] [Second embodiment]

[0104] Reference Figure 10 to Figure 13 , a DC / DC converter according to a second embodiment is described.

[0105] [Structure of the Second Embodiment]

[0106] Fig.10 The DC / DC converter 1A according to the second embodiment is a block diagram showing a configuration of the DC / DC converter 1A. The DC / DC converter 1A includes a control circuit 10A instead of Figure 1 The control circuit 10.

[0107] The control circuit 10A includes an on-time detector 41 instead of Figure 1 The peak current detector 13. The on-time detector 41 detects the possibility of reverse flow of the output current Iout, and generates a signal Sont indicating whether there is a possibility of reverse flow. The on-time detector 41 detects the possibility of reverse flow when the length of time for which energy is accumulated in the inductor L1 does not exceed the threshold value Tth. When the time for which energy is accumulated in the inductor L1 is less than the threshold value Tth, the signal Sont becomes a low level. When the time for which energy is accumulated in the inductor L1 is longer than the threshold value Tth, the signal Sont becomes a high level. When the time for which energy is accumulated in the inductor L1 is short, it is considered that the peak value of the output current Iout also becomes smaller. As a result, as shown in reference Fig.17 As explained above, there is a concern that a reverse current may be generated. Figure 1The signal Spc and the signal Sont are input to the NAND circuit 14 and the NOR circuit 17.

[0108] The on-time detector 41 is an example of a monitoring circuit that detects the possibility of a reverse flow of the output current Iout and generates a control signal indicating whether there is a possibility of a reverse flow.

[0109] [Operation of the Second Embodiment]

[0110] Fig.11 Yes means Fig.10 1 is a timing chart of a first operation example of the DC / DC converter 1A. Fig.12 Yes means Fig.10 1A is a timing chart of a second operation example of the DC / DC converter 1A. Figure 11-12 Indicates that the signal Sont is used instead Figure 2 to Figure 4 The on-time detector 41 has a delay time d3 specific to the on-time detector 41 from the time when it detects that the length of time for which energy is accumulated in the inductor L1 is longer than the threshold value Tth to the time when the state of the signal Sont is changed.

[0111] Fig.11 This indicates that the conduction interval is long enough to estimate that no reverse current will be generated, that is, longer than the threshold value Tth. In this case, the conduction time detector 41 changes the signal Sont from a low level to a high level after a delay time d3 has passed since the length of the time for which energy is stored in the inductor L1 exceeds the threshold value Tth in the conduction interval. Thereafter, the zero-crossing detector 12 changes the signal Szc from a low level to a high level after a delay time d1 has passed since the output current Iout is less than the threshold value Ith1 in the rectification interval. As a result, both the switching elements Q1 and Q2 are turned off.

[0112] Fig.12 Indicates the case where the conduction time is shorter than the threshold value Tth. In this case, the signal Sont maintains a low level. After the conduction interval, it shifts to the rectification interval. Thereafter, when the signal Sd0 changes from a high level to a low level, both the switch elements Q1 and Q2 are turned off.

[0113] according to Figure 11-12 In particular, by setting the delay time d10 to be shorter than the delay time d1 of the zero crossing detector 12, the reverse current can be prevented or at least reduced by turning off both the switching elements Q1 and Q2 according to the signal Szc or the signal S0d. Fig.12 As shown, when the conduction interval is short, the reverse current can be prevented or at least reduced. In addition, since the switching action includes the rectification interval, the time for the current to flow through the body diode of the switching element Q2 can be shortened, thereby improving efficiency. Fig.10The DC / DC converter 1A can prevent or at least reduce reverse current and operate more efficiently than ever before.

[0114] [Structure of delay circuit]

[0115] Fig.10 The delay circuit 16 may also have Figure 5 The delay circuit 16 and Figure 6 to Figure 9 Any structure of the delay circuits 16A to 16D.

[0116] Fig.13 : is a circuit diagram showing the structure of a delay circuit 16E according to the fifth modification. Fig.10 The control circuit 10A may also include Fig.13 The delay circuit 16E is used instead Figure 5 The delay circuit 16E includes an inverter 35, a constant current source 36, switches SW31, SW32, and a capacitor C32 instead of Fig. 9 The delay time d10 of the delay circuit 16E varies according to the length of time that energy is stored in the inductor L1 (that is, the length of time that the signal S1 is at a high level). By varying the delay time d10, the time that the current flows through the body diode of the switching element Q2 can be further shortened.

[0117] Not limited to Figures 5 to 9 as well as Fig.13 Examples of this invention may use any other delay circuit.

[0118] [Summary of the Second Embodiment]

[0119] As described above, the DC / DC converter 1A according to the second embodiment can prevent or at least reduce the reverse current and can operate more efficiently than before.

[0120] [Third Embodiment]

[0121] Reference Fig.14 , a DC / DC converter according to a third embodiment is described.

[0122] Fig.14 The DC / DC converter 1B according to the third embodiment is a block diagram showing a configuration of the DC / DC converter 1B. The DC / DC converter 1B includes a control circuit 10B instead of Figure 1 The control circuit 10.

[0123] The control circuit 10B has Figure 1 In addition to the components of the control circuit 10, the control circuit 10B further includes an on-time detector 41, a NAND circuit 51, and an inverter 52. In other words, the control circuit 10B has a combination of Figure 1 The control circuit 10 and Fig.10 10A is a control circuit of the embodiment of the present invention.

[0124] The DC / DC converter 1B according to the third embodiment has a configuration that combines the first and second embodiments, and can more reliably prevent or at least reduce a reverse current, and can operate more efficiently, compared to the first and second embodiments.

[0125] [Other Modifications]

[0126] exist Figure 2 In the example of etc., the case where both the rising and falling of the signal S0 are delayed to generate the signal S0d is described. However, in the embodiment described, only the part of the signal S0 indicating the end of the conduction interval (in Figure 2 For the portion of signal S0 indicating the start of the conduction interval (in the Figure 2 As for the rising in the example of the above, it is possible to have no delay or to have a delay time different from the delay time d10.

[0127] exist Figure 1 In the examples of , etc., the switch elements Q1 and Q2 are provided outside the integrated circuit having the terminals N0 to N4 , but the switch elements Q1 and Q2 may be integrated inside the control circuit 10 .

[0128] Figure 1 , Fig.10 ,as well as Fig.14 An example of a DC / DC converter as a step-down converter is shown. On the other hand, the control of the DC / DC converter according to the embodiment can also be applied to a step-up converter or a step-up / step-down converter.

[0129] [Summary of implementation methods]

[0130] The control circuit 10 of the DC / DC converter 1 according to the first embodiment of the present disclosure controls the DC / DC converter 1 including an inductor L1 and first and second switching elements Q1 and Q2 for accumulating and releasing energy in the inductor L1. The control circuit 10 includes a switching modulation circuit 11, a delay circuit 16, a zero crossing detector 12, a monitoring circuit, and a driving circuit. The switching modulation circuit 11 generates a first control signal having a predetermined duty ratio including an on state and an off state. The delay circuit 16 delays the first control signal over a first delay time to generate a second control signal. The zero crossing detector 12 detects whether the output current of the DC / DC converter 1 is less than a first threshold value when releasing the energy of the inductor L1, and generates a third control signal indicating whether the output current is less than the first threshold value. The monitoring circuit detects the possibility of reverse flow of the output current, and generates a fourth control signal indicating whether there is a possibility of reverse flow. The driving circuit generates a driving signal for turning on / off the first and second switching elements Q1 and Q2 based on the first to fourth control signals. The zero-crossing detector 12 has a second delay time inherent to the zero-crossing detector 12 from the time when the output current is detected to be less than the first threshold value to the time when the state of the third control signal is changed. The first delay time is set to be shorter than the second delay time. When the fourth control signal is in a state indicating that there is no possibility of backflow, the drive circuit releases the energy of the inductor L1, and when the third control signal changes to indicate that the output current is less than the first threshold value, the first and second switching elements Q1 and Q2 are turned off. When the fourth control signal is in a state indicating that there is a possibility of backflow, the drive circuit releases the energy of the inductor L1, and when the second control signal changes from the on state to the off state, the first and second switching elements Q1 and Q2 are turned off.

[0131] According to the control circuit 10 of the DC / DC converter 1 according to the second aspect of the present disclosure, the control circuit according to the first aspect may be configured as follows: The monitoring circuit detects that the output current does not exceed the second threshold value when energy is stored in the inductor L1 as a possibility of backflow.

[0132] According to the control circuit 10 of the DC / DC converter 1 according to the third aspect of the present disclosure, the control circuit according to the second aspect may be configured as follows: The delay circuit 16C changes the length of the first delay time according to the magnitude of the peak value of the output current.

[0133] According to the control circuit 10 of the DC / DC converter 1 according to the fourth aspect of the present disclosure, the control circuit according to the second aspect may be configured as follows: The delay circuit 16D changes the length of the first delay time according to the difference between the input voltage and the output voltage of the DC / DC converter 1 .

[0134] According to the control circuit 10A of the DC / DC converter 1A according to the fifth aspect of the present disclosure, the control circuit according to the first aspect may be configured as follows: The monitoring circuit detects that the length of time for which energy is stored in the inductor L1 does not exceed the third threshold value as a possibility of backflow.

[0135] According to the control circuit 10A of the DC / DC converter 1A according to the sixth aspect of the present disclosure, the control circuit according to the fifth aspect may be configured as follows: The delay circuit 16C changes the length of the first delay time according to the magnitude of the peak value of the output current.

[0136] According to the control circuit 10A of the DC / DC converter 1A according to the seventh aspect of the present disclosure, the control circuit according to the fifth aspect may be configured as follows: The delay circuit 16D changes the length of the first delay time according to the difference between the input voltage and the output voltage of the DC / DC converter 1A.

[0137] According to the control circuit 10A of the DC / DC converter 1A according to the eighth aspect of the present disclosure, the control circuit according to the fifth aspect may be configured as follows: The delay circuit 16E changes the length of the first delay time according to the length of time for which energy is accumulated in the inductor L1 .

[0138] A DC / DC converter 1 according to a ninth aspect of the present disclosure includes an inductor L1 , first and second switching elements Q1 and Q2 for storing and releasing energy in the inductor L1 , and the DC / DC converter 1 , 1A, or 1B according to one of the first to eighth aspects.

[0139] Description of Reference Numerals

[0140] 1. 1A~1D DC / DC converter; 2 load device; 10, 10A~10D control circuit; 11 switch modulation circuit; 12 zero crossing detector; 13 peak current detector; 14 NAND circuit; 15 inverter; 16 delay circuit; 17 NOR circuit; 18 inverter; 19 NOR circuit; 21 current sensor; 31, 31-1~31-3 inverter; 32 constant current source; 33 variable current source; 34 constant current source; 35 inverter; 36 constant current source; 41 conduction time detector; 51 NAND circuit; 52 inverter; 61 inverter; 62 NOR circuit; 71 inverter; 72 inverter; 73 NOR circuit; C1, C31, C32 capacitors; L1 inductor; Q1, Q2, Q31~Q36 switching elements; R31~R33 resistors; SW31, SW32 switches.

Claims

1. A control circuit for a DC / DC converter, In a control circuit for controlling a DC / DC converter including an inductor and first and second switching elements for storing and releasing energy in the inductor, The control circuit comprises: The switch modulation circuit generates a first control signal having a predetermined duty ratio including an on state and an off state; A delay circuit delays the first control signal by a first delay time to generate a second control signal; a zero-crossing detector for detecting whether the output current of the DC / DC converter is less than a first threshold value when the energy of the inductor is released, and generating a third control signal indicating whether the output current is less than the first threshold value; a monitoring circuit for detecting whether there is a possibility of reverse flow of the output current, and generating a fourth control signal indicating whether there is a possibility of the reverse flow; as well as a drive circuit that generates a drive signal for turning on / off the first and second switch elements based on the first to fourth control signals, The zero-crossing detector has a second delay time inherent to the zero-crossing detector from the time when the output current is detected to be less than the first threshold value to the time when the state of the third control signal is changed. The first delay time is set shorter than the second delay time. When the fourth control signal is in a state indicating that there is no possibility of the backflow, the drive circuit turns off both the first and second switching elements when releasing the energy of the inductor and when the third control signal changes to indicate that the output current is less than the first threshold value, When the fourth control signal is in a state indicating the possibility of the backflow, the drive circuit turns off both the first and second switching elements when the energy of the inductor is released and when the second control signal changes from an on state to an off state.

2. The control circuit of the DC / DC converter according to claim 1, wherein: The monitoring circuit detects, as the possibility of the backflow, that the output current does not exceed the second threshold value when energy is stored in the inductor.

3. The control circuit of the DC / DC converter according to claim 2, wherein: The delay circuit changes the length of the first delay time according to the magnitude of the peak value of the output current.

4. The control circuit of the DC / DC converter according to claim 2, wherein: The delay circuit changes the length of the first delay time according to a difference between an input voltage and an output voltage of the DC / DC converter.

5. The control circuit of the DC / DC converter according to claim 1, wherein: The monitoring circuit detects, as the possibility of the backflow, that the length of time during which the energy is accumulated in the inductor does not exceed a third threshold value.

6. The control circuit of the DC / DC converter according to claim 5, wherein: The delay circuit changes the length of the first delay time according to the magnitude of the peak value of the output current.

7. The control circuit of the DC / DC converter according to claim 5, wherein: The delay circuit changes the length of the first delay time according to a difference between an input voltage and an output voltage of the DC / DC converter.

8. The control circuit of the DC / DC converter according to claim 5, wherein: The delay circuit changes the length of the first delay time according to the length of time during which energy is accumulated in the inductor.

9. A DC / DC converter comprising: Inductors; a first switching element and a second switching element for storing and releasing energy in the inductor; and A control circuit as claimed in any one of claims 1 to 8.

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