Integrated mems chip and method of manufacturing the same

Abstract

An integrated MEMS chip and a manufacturing method thereof, wherein the manufacturing method comprises: forming a first substrate, including a first structure layer and a first dielectric film on a surface of the first structure layer, the first structure layer having a first opening and a second opening independent of each other, and the first dielectric film being different from a material of the first structure layer; forming a MEMS structure layer on the first substrate, the MEMS structure layer having an auxiliary groove facing the first substrate opening, and a groove length of the auxiliary groove being greater than a groove depth; bonding a second substrate to the MEMS structure layer; after bonding the second substrate, etching the first substrate from a side opposite to the first dielectric film to form a conductive via, the conductive via and the first opening being respectively communicated with a micro air channel; drawing air or feeding air to a first cavity through the conductive via and the micro air channel; and forming a first electrical interconnection structure in the conductive via, the first electrical interconnection structure being connected with a groove bottom of the auxiliary groove. The manufacturing method can set respective air pressures for different sensors on the same MEMS chip.

Description

Technical Field

[0001] This invention relates to the technical field of manufacturing methods for integrated MEMS chips, and particularly to an integrated MEMS chip and its manufacturing method. Background Technology

[0002] Integrated MEMS chips refer to the integration of multiple sensors with different functions onto the same MEMS chip. This trend of integration can not only reduce the physical size of the system and reduce power consumption, but also improve the overall system reliability and performance.

[0003] Some sensor structures integrated on MEMS chips need to operate in a sealed cavity, which is typically achieved through wafer bonding to encapsulate the sensor within the sealed cavity. However, different sensors require different cavity pressures, and wafer bonding can only achieve a given cavity pressure, making it impossible to set the pressure separately for different sensor structures integrated on the same wafer. Summary of the Invention

[0004] The technical problem solved by this invention is to provide an integrated MEMS chip and its manufacturing method, which sets the air pressure for different sensors on the same MEMS chip.

[0005] To address the aforementioned technical problems, the present invention provides a method for manufacturing an integrated MEMS chip, comprising: forming a first substrate, the first substrate including a first structural layer and a first dielectric film located on the surface of the first structural layer, the first structural layer having mutually independent first opening and second opening, and the first dielectric film being made of a different material than the first structural layer; forming a MEMS structural layer on the first substrate, the MEMS structural layer having auxiliary trenches facing the openings of the first substrate, the length of the auxiliary trenches being greater than the depth of the trenches, the first dielectric film and the auxiliary trenches forming a micro-air channel; and bonding a second substrate to the MEMS structural layer to seal the first opening and... The second opening forms an independent first cavity and a second cavity. After bonding the second substrate, the first substrate is etched from the side opposite to the first dielectric film to form a conductive via independent of the first opening and the second opening within the first substrate. The conductive via and the first opening are respectively connected to the micro-air channel. Air is drawn into or drawn into the first cavity through the conductive via and the micro-air channel, so that the air pressure in the first cavity is different from that in the second cavity. A first electrical interconnect structure is formed in the micro-air channel between the bottom of the conductive via and the bottom of the auxiliary trench, and in the conductive via. The first electrical interconnect structure is connected to the bottom of the auxiliary trench.

[0006] Optionally, the method for forming a MEMS structure layer on the first substrate includes: providing a third substrate having opposing first and second sides; forming an auxiliary trench exposed on the first side within the third substrate; after forming the auxiliary trench, bonding the third substrate to the first substrate, with the first side facing the first substrate; after bonding the third substrate to the first substrate, thinning the third substrate from the second side to form a MEMS material layer; and patterning the MEMS material layer from the second side to form a second structure layer, the second structure layer including a first sensor structure corresponding to a first opening and a second sensor structure corresponding to a second opening.

[0007] Optionally, the method of forming a MEMS structure layer on the first substrate further includes: forming a second electrical interconnect layer on the surface of the MEMS material layer; the second substrate includes a second dielectric layer, a third electrical interconnect layer located within the second dielectric layer, and a fourth electrical interconnect layer located on the surface of the second dielectric layer, the fourth electrical interconnect layer corresponding to the second electrical interconnect layer, and the method of bonding the second substrate on the MEMS structure layer includes: aligning the fourth electrical interconnect layer toward the second side, and aligning and bonding the fourth electrical interconnect layer with the second electrical interconnect layer, wherein there is a gap between the second dielectric layer and the first sensor structure, and between the second dielectric layer and the second sensor structure.

[0008] Optionally, both the first structural layer and the second structural layer are made of silicon.

[0009] Optionally, the method for forming the first electrical interconnect structure includes: depositing a seed material film on the surface of the first substrate opposite to the first dielectric film, the inner wall surface of the conductive via, and the bottom surface of an auxiliary trench corresponding to the bottom of the conductive via; forming a conductive material filling layer on the surface of the seed material film, the conductive material filling layer filling at least part of the conductive via; grinding or etching the conductive material filling layer and the seed material film from the side of the first substrate opposite to the first dielectric film until the surface of the first substrate opposite to the first dielectric film is exposed, thereby forming the first electrical interconnect structure.

[0010] Optionally, before forming the conductive via, the air pressure in the first cavity and the air pressure in the second cavity are the same initial air pressure; during the deposition of the seed material film, the process air pressure of the deposition process is a target air pressure different from the initial air pressure, so that air is drawn or introduced into the first cavity through the conductive via and the micro-air channel, so that the air pressure in the first cavity is adjusted to the target air pressure.

[0011] Optionally, the target air pressure is lower than the initial air pressure.

[0012] Optionally, the thickness of the seed material film is more than three times the depth of the auxiliary groove.

[0013] Optionally, the conductive material layer fills the conductive via completely.

[0014] Optionally, the first opening has a first projection on the surface of the first substrate, the bottom of the conductive via has a second projection on the surface of the first substrate, and the auxiliary trench is divided into a first end region, a channel region, and a second end region along its length. The lengths of the first end region and the second end region are both less than the length of the channel region. The projection of the first end region on the surface of the first substrate is within the first projection range, and the projection of the second end region on the surface of the first substrate penetrates the second projection or is within the second projection range.

[0015] Optionally, the length of the auxiliary trench is more than 10 times the depth of the trench.

[0016] Optionally, the length of the auxiliary trench is more than 10 micrometers, and the depth of the auxiliary trench ranges from 0.1 micrometers to 1 micrometer.

[0017] Optionally, the number of auxiliary trenches may be multiple.

[0018] Optionally, the auxiliary trench includes one or more combinations of straight structures, bent structures, and circular tube structures.

[0019] Optionally, the method for forming the first substrate includes: providing an initial first substrate; patterning the initial first substrate to form the first structural layer; and forming the first dielectric film on the surface of the first structural layer, the inner wall surface of the first opening, and the inner wall surface of the second opening.

[0020] Optionally, the method for forming the first substrate includes: providing an initial first substrate; forming an initial first dielectric film on the surface of the initial first substrate; and patterning the initial first substrate and the initial first dielectric film to form the first structural layer and a first dielectric film located on the surface of the first structural layer.

[0021] Accordingly, the technical solution of the present invention also provides an integrated MEMS chip manufactured by the above-described manufacturing method, comprising: a first substrate, including a first structural layer and a first dielectric film located on the surface of the first structural layer, the first structural layer having mutually independent first and second openings, and the first dielectric film being made of a different material from the first structural layer; a MEMS structural layer, stacked on the first substrate, the MEMS structural layer having auxiliary trenches facing the openings of the first substrate, the trench length being greater than the trench depth, and the first dielectric film and the auxiliary trenches forming a micro-air channel; and a second substrate, bonded to the MEMS structural layer, and The second substrate is located on opposite sides of the MEMS structure layer, respectively, to seal the first opening and the second opening, forming an independent first cavity and a second cavity. The air pressure in the first cavity is different from that in the second cavity. A conductive via is located within the first substrate and is independent of the first opening and the second opening. The conductive via and the first opening are respectively connected to the micro-air channel. A first electrical interconnect structure is located within the micro-air channel between the bottom of the conductive via and the bottom of the auxiliary trench, and within the conductive via. The first electrical interconnect structure is connected to the bottom of the auxiliary trench.

[0022] Optionally, the MEMS structure layer includes: a second structure layer having a first side and a second side opposite to each other, the second structure layer being bonded to the first substrate, the first side facing the first substrate, the auxiliary trench being located within the second structure layer and exposed to the first side by the surface of the second structure layer, and the second structure layer further including a first sensor structure corresponding to the first opening and a second sensor structure corresponding to the second opening.

[0023] Optionally, the MEMS structure layer further includes: a second electrical interconnect layer located on the second side surface of the second structure layer; the second substrate includes a second dielectric layer, a third electrical interconnect layer located within the second dielectric layer, and a fourth electrical interconnect layer located on the surface of the second dielectric layer, the fourth electrical interconnect layer corresponding to the second electrical interconnect layer, the fourth electrical interconnect layer being aligned and bonded to the second electrical interconnect layer, and the second dielectric layer being spaced from the first sensor structure, as well as from the second sensor structure.

[0024] Optionally, the first electrical interconnect structure includes a seed layer and a filling conductive layer. The seed layer is located on the inner wall surface of the conductive via and extends to the bottom surface of an auxiliary trench corresponding to the bottom of the conductive via. The filling conductive layer is located on the surface of the seed layer and at least partially fills the conductive via.

[0025] Optionally, the thickness of the seed layer 511 is more than three times the depth of the auxiliary trench.

[0026] Optionally, the first opening has a first projection on the surface of the first substrate, the bottom of the conductive via has a second projection on the surface of the first substrate, and the auxiliary trench is divided into a first end region, a channel region, and a second end region along its length. The lengths of the first end region and the second end region are both less than the length of the channel region. The projection of the first end region on the surface of the first substrate is within the first projection range, and the projection of the second end region on the surface of the first substrate penetrates the second projection or is within the second projection range.

[0027] Optionally, the length of the auxiliary trench is more than 10 times the depth of the trench.

[0028] Optionally, the number of auxiliary trenches may be multiple.

[0029] Optionally, the first dielectric film is also located on the inner wall surfaces of the first opening and the second opening.

[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0031] The integrated MEMS chip and its manufacturing method provided by the present invention can set different internal air pressures for the first cavity 610 and the second cavity 620 on the same MEMS chip. Furthermore, it balances device reliability and conductivity. Attached Figure Description

[0032] Figures 1 to 14 This is a schematic diagram of the structure of each step in the manufacturing method of an integrated MEMS chip according to an embodiment of the present invention;

[0033] Figure 15 yes Figure 14 A schematic diagram of the projection of each structure onto the surface of the first substrate;

[0034] Figure 16 This is a schematic diagram of the projection of each structure in the integrated MEMS chip of another embodiment of the present invention on the first substrate surface;

[0035] Figure 17 yes Figure 16 Schematic diagram of the length of the auxiliary trench;

[0036] Figures 18 to 19 This is a schematic diagram of the steps in the method for forming the first substrate in another embodiment of the present invention.

[0037] Figure label:

[0038] 100 - First substrate; 11 - Initial first substrate; 110 - First structural layer; 111 - First opening; 112 - Second opening; 120, 121 - First dielectric film; 1211 - Initial first dielectric film; 130 - Conductive via;

[0039] 200 - Second substrate; 210 - Substrate structure layer; 220 - Second dielectric layer; 230 - Third electrical interconnect layer; 240 - Fourth electrical interconnect layer;

[0040] 300 - Third substrate; 301 - First side; 302 - Second side; 303 - MEMS material layer; 310 - Second structural layer; 311 - First sensor structure; 312 - Second sensor structure; 313 - Auxiliary trench; H - Trench depth; 320 - Second electrical interconnect layer;

[0041] 400-Micro air channel;

[0042] 500 - First electrical interconnect structure; 510 - Seed material layer; 511 - Seed layer; 520 - Filled conductive material layer; 521 - Filled conductive layer;

[0043] 610 - First cavity; 620 - Second cavity;

[0044] 601 - First projection; 602 - Second projection; 6031, 6032 - Auxiliary trench projections. Detailed Implementation

[0045] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Figures 1 to 14 This is a schematic diagram of the structure of each step in a method for manufacturing an integrated MEMS chip according to an embodiment of the present invention. Figure 15 yes Figure 14 The following is a detailed description of the projection of each structure onto the first substrate surface, in conjunction with the accompanying drawings.

[0047] First, the first substrate 100 is formed.

[0048] The first substrate 100 includes a first structural layer 110 and a first dielectric film 120.

[0049] Figures 1 to 3 This is a schematic diagram of the steps involved in forming the first substrate 100 in this embodiment. The following is in conjunction with... Figures 1 to 3 The method for forming the first substrate 100 is described in detail.

[0050] Please refer to Figure 1 Provides the initial first base 11.

[0051] In this embodiment, the initial first substrate 11 is made of silicon.

[0052] Please refer to Figure 2 The initial first base 11 is graphically visualized to form the first structural layer 110.

[0053] The first structural layer 110 has a first opening 111 and a second opening 112 that are independent of each other.

[0054] The first opening 111 is used to subsequently form the first cavity 610 (e.g., Figure 11 As shown), the second opening 112 is used to subsequently form the second cavity 620 (as shown). Figure 11 (As shown).

[0055] The first opening 111 has a first projection 601 on the first surface (e.g., ... Figure 15 (As shown).

[0056] In this embodiment, the material of the first structural layer 110 corresponds to that of the initial first substrate 11, that is, the material of the first structural layer 110 is silicon.

[0057] In some embodiments, the method of patterning an initial first substrate 11 includes: forming a first mask layer (not shown) on the surface of the initial first substrate 11, the first mask layer exposing a portion of the surface of the initial first substrate 11; using the first mask layer as a mask, etching the initial first substrate 11 until a first structural layer 110 having a first opening 111 and a second opening 112 is formed.

[0058] Furthermore, after forming the first structural layer 110, the first mask layer is removed.

[0059] Please refer to Figure 3 A first dielectric film 120 is formed on the surface of the first structural layer 110, the inner wall surface of the first opening 111, and the inner wall surface of the second opening 112.

[0060] The material of the first dielectric film 120 is different from the material of the first structural layer 110.

[0061] In this embodiment, the material of the first dielectric film 120 is silicon oxide.

[0062] In this embodiment, the first dielectric film 120 is preferably formed by oxidizing the first structural layer 110.

[0063] In some other embodiments, the first dielectric film can also be formed by a deposition process.

[0064] In yet another embodiment, please Figure 1 Based on reference Figure 18 and Figure 19The method for forming the first substrate includes: forming an initial first dielectric film 1211 (e.g., ...) on the surface of the initial first substrate 11. Figure 18 (As shown); patterning the initial first substrate 11 and the initial first dielectric film 1211 to form a first structural layer 110 and a first dielectric film 121 located on the surface of the first structural layer 110 (as shown); Figure 19 (As shown).

[0065] Next, a MEMS structure layer is formed on the first substrate 100.

[0066] The MEMS structural layer has auxiliary trenches 313 that open toward the first substrate 100 (e.g., Figure 4 As shown), and the first dielectric film 120 and the auxiliary trench 313 form a micro-air channel 400 (as shown). Figure 5 (As shown).

[0067] Figures 4 to 8 This is a schematic diagram of the steps involved in forming a MEMS structure layer on the first substrate 100 in this embodiment. The following is in conjunction with... Figures 4 to 8 The method for forming a MEMS structure layer on the first substrate 100 is described in detail.

[0068] Please refer to Figure 4 Provides a third base 300.

[0069] The third base 300 has a first side 301 and a second side 302 opposite to each other.

[0070] In this embodiment, the material of the third substrate 300 is silicon.

[0071] Continue to refer to Figure 4 An auxiliary trench 313 is formed within the third substrate 300, exposed on the first side 301.

[0072] The auxiliary trench 313 has an auxiliary trench projection 6031 on the surface of the first substrate 100 (e.g., Figure 15 (As shown).

[0073] The length L1 of the auxiliary trench 313 is greater than the depth H. The length L1 of the auxiliary trench 313 refers to the total length of its extension path.

[0074] In some embodiments, the length L1 of the auxiliary trench 313 is more than 10 times the depth H.

[0075] Furthermore, the length L1 of the auxiliary trench 313 is greater than 10 micrometers, and the depth H of the auxiliary trench 313 ranges from 0.1 micrometers to 1 micrometer.

[0076] In this embodiment, the number of auxiliary grooves 313 is one.

[0077] In some embodiments, the number of auxiliary grooves 313 is multiple, so that even if one micro-air channel 400 is blocked by environmental or process contaminants, other micro-air channels 400 can still ensure ventilation, while also better ensuring air intake or extraction efficiency.

[0078] In this embodiment, the auxiliary groove 313 is a straight structure.

[0079] In another embodiment, the auxiliary trench includes a plurality of straight structures and a plurality of bent structures, which are sequentially connected end-to-end. The auxiliary trench has an auxiliary trench projection 6032 on the surface of the first substrate (e.g., Figure 16 (As shown), please refer to Figure 17 The length of the auxiliary trench is L2 = a1 + a2 + (3 × a3) + b1 + b2 + b3 + b4 + b5 + b6.

[0080] In some other embodiments, the auxiliary groove may also be a disc tube structure, or the auxiliary groove may be a combination of at least one of a straight structure and a bent structure with a disc tube structure.

[0081] By adopting a bent structure or a disc structure, it is beneficial to increase the ratio of the length to the width of the auxiliary trench and increase the complexity of the extension path of the auxiliary trench. Therefore, in the subsequent material process of forming the first electrical interconnect structure, the risk of conductive material molecules entering the first cavity through the auxiliary trench is further reduced. Thus, while forming cavities with different gas pressures, the reliability of the device is improved.

[0082] In some embodiments, the method of forming the auxiliary trench 313 includes: forming a second mask layer (not shown) on the surface of a third substrate 300, the second mask layer exposing a portion of the surface of the third substrate 300; using the second mask layer as a mask, etching the third substrate 300 until the auxiliary trench 313 is formed.

[0083] Furthermore, the second mask layer is removed after the auxiliary trench 313 is formed.

[0084] It is necessary to understand that Figure 4 The steps shown are the same as Figures 1 to 3 There is no sequential order among the steps shown.

[0085] Please refer to Figure 5 After forming the auxiliary trench 313, the third substrate 300 is bonded to the first substrate 100, with the first side 301 facing the first substrate 100.

[0086] Specifically, the third substrate 300 is bonded to the surface of the first side 301 with the first dielectric film 120 to achieve bonding between the third substrate 300 and the first substrate 100, wherein the first dielectric film 120 is the bonding layer when the third substrate 300 and the first substrate 100 are bonded.

[0087] Thus, the auxiliary trench 313 opens toward the first substrate 100, and the first dielectric film 120 and the auxiliary trench 313 form a micro-air channel 400.

[0088] Among them, the micro-air channel 400 is connected to the first opening 111.

[0089] Please refer to Figure 6 After the third substrate 300 is bonded to the first substrate 100, the third substrate 300 is thinned from the second side 302 to form a MEMS material layer 303.

[0090] The process of forming the MEMS material layer 303 includes: grinding the third substrate 300 to thin it, and then performing chemical mechanical polishing (CMP) on the surface of the thinned third substrate 300 to planarize the surface of the thinned third substrate 300.

[0091] Please refer to Figure 7 A second electrical interconnect layer 320 is formed on the surface of the MEMS material layer 303.

[0092] In some embodiments, the material of the second electrical interconnect layer 320 is metal.

[0093] Furthermore, the material of the second electrical interconnect layer 320 is one or more of the following: Ti, TiW, Cr, Al, Ge, Cu, and Au.

[0094] In some embodiments, the method of forming the second electrical interconnect layer 320 includes: forming a second electrical interconnect material layer (not shown) on the surface of the MEMS material layer 303; forming a third mask layer (not shown) on the surface of the second electrical interconnect material layer, the third mask layer exposing a portion of the surface of the second electrical interconnect material layer; etching the second electrical interconnect material layer using the third mask layer as a mask until the MEMS material layer 303 is exposed, thereby forming a patterned second electrical interconnect layer 320.

[0095] Please refer to Figure 8 After forming the second electrical interconnect layer 320, the MEMS material layer 303 is patterned from the second side 302 to form the second structural layer 310.

[0096] The second structural layer 310 includes a first sensor structure 311 corresponding to the first opening 111 and a second sensor structure 312 corresponding to the second opening 112.

[0097] Large shear forces are generated during the grinding and planarization process. Since the second structural layer 310 is formed by patterning the MEMS material layer 303 from the second side 302 after the third substrate 300 is thinned from the second side 302, the shear forces during grinding and planarization are borne by the third substrate 300 with high structural strength, thus avoiding damage to the more fragile second structural layer 310 by the shear forces. As a result, the manufactured integrated MEMS chip has good reliability.

[0098] In this embodiment, the material of the second structural layer 310 corresponds to that of the third substrate 300, that is, the material of the second structural layer 310 is silicon.

[0099] In this embodiment, the etching process during the patterning of the MEMS material layer 303 can produce a large etching ratio for both the MEMS material layer 303 and the first dielectric film 120. Since the first dielectric film 120 is also located on the inner wall surface of the first opening 111 and the inner wall surface of the second opening 112, it can also act as a protective film during the etching process to protect the inner wall surfaces of the first opening 111 and the second opening 112, thereby better ensuring the pattern size and morphology of the first opening 111 and the second opening 112. Please refer to... Figure 9 Provide a second substrate 200.

[0100] The second substrate 200 includes: a substrate structure layer 210, a second dielectric layer 220, a third electrical interconnect layer 230, and a fourth electrical interconnect layer 240.

[0101] In some embodiments, the substrate structure layer 210 includes a control chip or a driver chip.

[0102] In some other embodiments, the substrate structure layer may not contain a chip.

[0103] The material of the substrate structure layer 210 includes silicon.

[0104] The second dielectric layer 220 is located on the surface of the substrate structure layer 210.

[0105] In some embodiments, the material of the second dielectric layer 220 is a stacked combination of one or all of silicon oxide and silicon nitride.

[0106] The third electrical interconnect layer 230 is located within the second dielectric layer 220.

[0107] In some embodiments, the material of the third electrical interconnect layer 230 is one or more of the following: Ti, TiW, TiN, Al, Cu, Au, and Cr.

[0108] The fourth electrical interconnect layer 240 is located on the surface of the second dielectric layer 220, and corresponds to the second electrical interconnect layer 320. The fourth electrical interconnect layer 240 is used for bonding with the second electrical interconnect layer 320.

[0109] In some embodiments, the material of the fourth electrical interconnect layer 240 is one or more of the following: Ti, TiW, Cr, Al, Ge, Cu, and Au.

[0110] Please refer to Figure 10 A second substrate 200 is bonded to the MEMS structure layer to seal the first opening 111 and the second opening 112, forming a first cavity 610 and a second cavity 620 that are independent of each other.

[0111] During the bonding of the second substrate 200 onto the MEMS structure layer, the process gas pressure of the bonding process is controlled to ensure that the first cavity 610 and the second cavity 620 have the same initial gas pressure.

[0112] In addition, since the micro-air channel 400 is connected to the first opening 111, the micro-air channel 400 is also connected to the first cavity 610, so as to be used for evacuating or inflating the first cavity 610 in the future.

[0113] Specifically, the method of bonding the second substrate 200 on the MEMS structure layer includes: aligning the fourth electrical interconnect layer 240 toward the second side 302, and aligning and bonding the fourth electrical interconnect layer 240 with the second electrical interconnect layer 320.

[0114] A first open space is formed by the fourth electrical interconnect layer 240 and the second electrical interconnect layer 320, and the second dielectric layer 220 and the first sensor structure 311. The first open space and the first opening 111 provide deformation space for the first sensor structure 311, so that the first sensor structure 311 can deform within the first cavity 610 formed by the first open space and the first opening 111.

[0115] Similarly, a second overhead space is formed by the fourth electrical interconnect layer 240 and the second electrical interconnect layer 320, and the second dielectric layer 220 and the second sensor structure 312. The second overhead space and the second opening 112 provide deformation space for the second sensor structure 312, so that the second sensor structure 312 can deform within the second cavity 620 formed by the second overhead space and the second opening 112.

[0116] Please refer to Figure 11 After bonding the second substrate 200, the first substrate 100 is etched from the side opposite to the first dielectric film 120 to form a conductive via 130 independent of the first opening 111 and the second opening 112 in the first substrate 100. The conductive via 130 is connected to the micro air channel 400.

[0117] On the one hand, the conductive via 130 reserves space for forming the first electrical interconnection structure. On the other hand, the conductive via 130 and the first opening 111 are respectively connected to the micro air channel 400. That is to say, the conductive via 130 and the first cavity 610 are respectively connected to the micro air channel 400. Therefore, air can be drawn or introduced into the first cavity 610 through the conductive via 130 and the micro air channel 400.

[0118] In this embodiment, the first dielectric film 120 is not only the bonding layer when the third substrate 300 is bonded to the first substrate 100, but also a protective film for the first opening 111 and the second opening 112. Since the first dielectric film 120 and the auxiliary trench 313 form a micro-channel 400, and after bonding the second substrate 200, the first substrate 100 is etched from the side opposite to the first dielectric film 120 to form a conductive via 130 independent of the first opening 111 and the second opening 112 and connected to the micro-channel 400, during the etching of the first structural layer 110 to form the conductive via 130, the first structural layer 110 and the auxiliary trench 313 have the first dielectric film 120 between them. Furthermore, the materials of the first structural layer 110 and the first dielectric film 120 are different; therefore, the etching... The etching process of the first structural layer 110 can produce a large etching ratio for the materials of the first structural layer 110 and the first dielectric film 120. Thus, the first dielectric film 120 can also serve as an etching stop layer in this process to protect the trench wall of the auxiliary trench 313 from being damaged. At the same time, the etching process of the first structural layer 110 has fewer influencing factors and higher process freedom, and can perform thorough etching and cleaning steps to form a smooth conductive via 130 hole wall and reduce the contaminants adhering to the conductive via 130 hole wall, thereby forming a conductive via 130 with low hole wall roughness and few adhering contaminants.

[0119] Furthermore, since the materials of the first dielectric film 120 (silicon oxide) and the second structural layer 310 (silicon) in the MEMS structural layer are also different, the etching process of etching the first dielectric film 120 to form the conductive via 130 has little effect on the second structural layer 310. Therefore, the process of etching the first dielectric film 120 is less likely to damage the auxiliary trench 313.

[0120] In this embodiment, the bottom of the conductive via 130 has a second projection 602 on the surface of the first substrate 100 (e.g., Figure 15 (As shown).

[0121] In some embodiments, the method for forming the conductive via 130 includes: performing a flipping operation after bonding the second substrate 200 so that the side of the first substrate 100 opposite to the first dielectric film 120 faces upward; forming a fourth mask layer on the surface of the first substrate 100 opposite to the first dielectric film 120, the fourth mask layer exposing a portion of the surface of the first substrate 100 opposite to the first dielectric film 120; using the fourth mask layer as a mask, etching the first structural layer 110 to form an initial conductive via (not shown), wherein the etching process of the first structural layer 110 includes an etching step and a cleaning step; after forming the initial conductive via, continuing to use the fourth mask layer as a mask to etch the first dielectric film 120 until the micro-gas channel 400 is exposed, thereby forming the conductive via 130.

[0122] In some embodiments, the fourth mask layer is removed after the conductive via 130 is formed.

[0123] Next, a first electrical interconnect structure 500 is formed within the micro-air channel 400 between the bottom of the conductive via 130 and the bottom of the auxiliary trench 313, and within the conductive via 130. Figure 14 As shown in the diagram, the first electrical interconnect structure 500 is connected to the bottom of the auxiliary trench 313.

[0124] In this embodiment, the conductive via 130 not only reserves space for forming the first electrical interconnect structure 500, but also allows air to be drawn into or drawn into the first cavity 610 through the conductive via 130 and the micro-air channel 400. At the same time, the first electrical interconnect structure 500 can not only serve as part of the circuit in the integrated MEMS chip, but also provides sealing for the micro-air channel 400. Therefore, the conductive via 130 and the first electrical interconnect structure 500 are not only used to achieve electrical interconnection, but also, through their combined use with the micro-air channel 400, achieve a difference in air pressure between the first cavity 610 and the second cavity 620.

[0125] Specifically, since the conductive via 130 and the first opening 111 are respectively connected to the micro-air channel 400, that is, the conductive via 130 and the first cavity 610 are respectively connected to the micro-air channel 400, by setting the process gas pressure for forming the first electrical interconnect structure 500 to a target gas pressure different from the initial gas pressure, air can be drawn or drawn into the first cavity 610 through the conductive via 130 and the micro-air channel 400 during the formation of the first electrical interconnect structure 500, so that the gas pressure in the first cavity 610 is adjusted to the target gas pressure. Based on this, since a first electrical interconnect structure 500 is formed in the micro-air channel 400 between the bottom of the conductive via 130 and the bottom of the auxiliary trench 313, and in the conductive via 130, the first electrical interconnect structure 500 not only blocks the conductive via 130, thereby sealing the micro-air channel 400 and maintaining the target air pressure in the first cavity 610, but also connects to the bottom of the auxiliary trench 313, so that the first electrical interconnect structure 500 can be used as part of the circuit in the integrated MEMS chip.

[0126] Based on this, since the length L1 of the auxiliary trench 313 is greater than the depth H, the MEMS structure layer has an auxiliary trench 313 that opens toward the first substrate 100. Furthermore, after bonding the second substrate 200, the first substrate 100 is etched from the side opposite to the first dielectric film 120 to form a conductive via 130. Therefore, not only is the amount of conductive material molecules entering the first cavity 610 through the micro-gas channel 400 effectively reduced, but the first electrical interconnect structure 500 also has good and stable electrical characteristics while providing good sealing for the micro-gas channel 400. Thus, while taking into account the electrical characteristics of the device, the reliability of the device is improved.

[0127] Specifically, when the length L1 of the auxiliary trench 313 is greater than the depth H, during the process of forming the first electrical interconnect structure 500 material, conductive material molecules are prone to collide with the wall of the auxiliary trench 313 corresponding to the bottom of the conductive via 130 (e.g., Figure 11 As shown in the middle region S), the conductive material molecules entering the first cavity 610 through the micro-air channel 400 can be effectively reduced.

[0128] Based on this, since the MEMS structure layer has an auxiliary trench 313 that opens toward the first substrate 100, and after the second substrate 200 is bonded, the first substrate 100 is etched from the side opposite to the first dielectric film 120 to form a conductive via 130, thus the trench wall of the auxiliary trench 313 is not damaged. At the same time, the hole wall roughness of the conductive via 130 is small and there are few contaminants attached (for related reasons, please refer to the above description).

[0129] To prevent damage to the walls of the auxiliary trench 313, not only is the risk of air leakage from the micro-air channel 400 reduced, but the risk of increased trench depth H is also reduced. This ensures that conductive material molecules can easily collide with the walls of the auxiliary trench 313 at the bottom of the conductive through hole 130.

[0130] The conductive via 130 has a small wall roughness (i.e., the wall of the conductive via 130 is smooth) and fewer contaminants adhere to it. This not only allows the first electrical interconnect structure 500 formed in the conductive via 130 to fully fit with the wall of the conductive via 130, thus reducing the risk of air leakage or air intake from the gap between the first electrical interconnect structure 500 and the wall of the conductive via 130, but also reduces the impact of contaminants on the conductivity of the first electrical interconnect structure 500.

[0131] In summary, the integrated MEMS chip manufacturing method of this embodiment not only achieves different air pressures in the first cavity 610 and the second cavity 620 within the same MEMS chip, but also takes into account both device reliability and conductivity.

[0132] Furthermore, when the length L1 of the auxiliary trench 313 is more than 10 times the depth H, it ensures that the length of the auxiliary trench 313 is much greater than the width. Therefore, during the material process of forming the first electrical interconnect structure 500, it can be ensured that the possibility of conductive material molecules entering the first cavity 610 through the micro-air channel 400 is small.

[0133] In some embodiments, please refer to Figure 15 The auxiliary trench 313 is divided into a first end region, a channel region and a second end region along the length of the trench. The length of the trench in the first end region and the length of the trench in the second end region are both less than the length of the trench in the channel region. Furthermore, the projection I of the first end region on the surface of the first base 100 is within the range of the first projection 601, and the projection III of the second end region on the surface of the first base 100 penetrates the second projection 602 or is within the range of the second projection 602.

[0134] Since the groove length of the first end region and the groove length of the second end region are both smaller than the groove length of the channel region, and the projection I of the first end region on the surface of the first substrate 100 is within the range of the first projection 601, and the projection III of the second end region on the surface of the first substrate 100 penetrates the second projection 602 or is within the range of the second projection 602, on the one hand, it ensures that there is a sufficiently long micro-air channel 400 between the first cavity 610 and the conductive via 130, so as to effectively reduce the conductive material molecules entering the first cavity 610 through the micro-air channel 400. On the other hand, the projection I realizes the connection between the first cavity 610 and the micro-air channel 400 within the range of the first projection 601, and the projection III realizes the connection between the conductive via 130 and the micro-air channel 400 by penetrating the second projection 602 or within the range of the second projection 602.

[0135] For ease of understanding and explanation, in Figure 15 The diagram schematically illustrates the projection I of the first terminal region onto the surface of the first substrate 100, the projection II of the channel region onto the surface of the first substrate 100, the projection III of the second terminal region onto the surface of the first substrate 100, the first projection 601, and the second projection 602. Figure 15 This refers to the case where projection III penetrates through the second projection 602.

[0136] Figures 12 to 14 This is a schematic diagram of the steps involved in forming the first electrical interconnect structure 500 in this embodiment. The following is in conjunction with... Figures 12 to 14 The steps for forming the first electrical interconnect structure 500 are described in detail.

[0137] Please refer to Figure 12 Seed material film 510 is deposited on the other side surface of the first substrate 100 opposite to the first dielectric film 120, the inner wall surface of the conductive through hole 130, and the bottom surface of the auxiliary trench 313 corresponding to the bottom of the conductive through hole 130.

[0138] Seed material membrane 510, on the one hand, is used to form a seed layer 511 with good sealing properties (such as... Figure 14 (As shown in the figure), on the other hand, it is used as a seed layer for subsequent electroplating processes to achieve the formation of the conductive material layer 520.

[0139] The deposition process for the seed material film 510 includes vapor deposition, PVD, or CVD.

[0140] The seed material film 510 is made of one or more of the following materials in a stacked combination: Ti / Cu, Ti, Cr, TiW, Cr / Cu, TiW / Cu, Ti / Al, and TiW / Al.

[0141] In this embodiment, during the deposition of the seed material film 510, the process gas pressure of the deposition process is a target gas pressure that is different from the initial gas pressure. Air is drawn or introduced into the first cavity 610 through the conductive through-hole 130 and the micro-air channel 400 to adjust the gas pressure in the first cavity 610 to the target gas pressure.

[0142] Preferably, the target gas pressure is lower than the initial gas pressure, so that air is drawn into the first cavity 610 through the conductive through-hole 130 and the micro-air channel 400. Compared with air intake, the air extraction method can further reduce the conductive material molecules and possible contaminants entering the first cavity 610, thereby improving the reliability of the device.

[0143] In some embodiments, the thickness of the seed material membrane 510 is more than three times the groove depth H to further ensure the sealing capability of the formed seed layer 511 to the micro-air channel 400.

[0144] Please refer to Figure 13 A conductive material layer 520 is formed on the surface of the seed material film 510, and the conductive material layer 520 at least partially fills the conductive via 130.

[0145] The conductive material layer 520 is used to form the conductive material layer 511 (e.g.) Figure 14 The material shown.

[0146] Furthermore, by forming a conductive material layer 520 on the surface of the seed material film 510, the blockage of the conductive through-hole 130 is further enhanced, and the sealing of the micro-air channel 400 is strengthened.

[0147] Preferably, the conductive material layer 520 fills the conductive through hole 130 to better enhance the blocking of the conductive through hole 130 and strengthen the sealing of the micro air channel 400.

[0148] In some embodiments, the process for forming the conductive material layer 520 is an electroplating process.

[0149] In some embodiments, the material filling the conductive material layer 520 is one or more of Cu, Ni, Ag and Al in a stacked combination.

[0150] Please refer to Figure 14 The conductive material layer 520 and the seed material film 510 are ground or etched from the other side of the first substrate 100 relative to the first dielectric film 120 until the other side surface of the first substrate 100 relative to the first dielectric film 120 is exposed, forming the first electrical interconnect structure 500.

[0151] In this embodiment, the first electrical interconnect structure 500 includes a seed layer 511 and a conductive filling layer 521. The seed layer 511 is located on the inner wall surface of the conductive via 130 and extends to the bottom surface of the auxiliary trench 313 corresponding to the bottom of the conductive via 130. The conductive filling layer 521 is located on the surface of the seed layer 511 and at least fills part of the conductive via.

[0152] The seed layer 511 and the conductive filling layer 521 form a double sealing layer, thereby effectively ensuring the sealing performance of the first electrical interconnect structure 500 to the micro-air channel 400.

[0153] The process of grinding or etching the conductive material layer 520 and the seed material film 510 includes chemical etching or CMP.

[0154] Preferably, the conductive filling layer 521 fills the conductive through hole 130 to better enhance the blocking of the conductive through hole 130 and strengthen the sealing of the micro air channel 400.

[0155] Accordingly, please continue to refer to Figure 14The present invention also provides an integrated MEMS chip manufactured by the above-described integrated MEMS chip manufacturing method, comprising: a first substrate 100, a MEMS structure layer, a second substrate 200, a conductive via 130, and a first electrical interconnect structure 500.

[0156] The first substrate 100 includes a first structural layer 110 and a first dielectric film 120 located on the surface of the first structural layer 110. The first structural layer 110 has a first opening 111 and a second opening 112 that are independent of each other. The first dielectric film 120 is made of a different material than the first structural layer 110.

[0157] In this embodiment, the first dielectric film 120 is also located on the inner wall surface of the first opening 111 and the second opening 112.

[0158] In another embodiment, the first dielectric film 121 is located only on the surface of the first structural layer 110.

[0159] MEMS structure layers are stacked on the first substrate 100. The MEMS structure layers have auxiliary trenches 313 that open toward the first substrate 100. The length of the auxiliary trenches 313 is greater than the depth. The first dielectric film 120 and the auxiliary trenches 313 form a micro air channel 400.

[0160] In some embodiments, the length L1 of the auxiliary trench 313 is more than 10 times the depth H.

[0161] Furthermore, the length L1 of the auxiliary trench 313 is greater than 10 micrometers, and the depth H of the auxiliary trench 313 ranges from 0.1 micrometers to 1 micrometer.

[0162] In this embodiment, the number of auxiliary grooves 313 is one.

[0163] In some embodiments, the number of auxiliary grooves 313 is multiple.

[0164] In this embodiment, the auxiliary groove 313 is a straight structure.

[0165] In another embodiment, the auxiliary trench includes a plurality of straight structures and a plurality of bent structures, which are sequentially connected end-to-end. The auxiliary trench has an auxiliary trench projection 6032 on the surface of the first substrate 100 (e.g., Figure 16 (As shown), please refer to Figure 17 The length of the auxiliary trench is L2 = a1 + a2 + (3 × a3) + b1 + b2 + b3 + b4 + b5 + b6.

[0166] In some other embodiments, the auxiliary groove 313 may also be a disc tube structure, or the auxiliary groove 313 may also be a combination of at least one of a straight structure and a bent structure with a disc tube structure.

[0167] The MEMS structural layer includes: the second structural layer 310.

[0168] The second structural layer 310 has a first side 301 and a second side 302 opposite to each other. The second structural layer 310 is bonded to the first substrate 100. The first side 301 faces the first substrate 100. An auxiliary trench 313 is located in the second structural layer 310 and is exposed to the first side 301 by the surface of the second structural layer 310. The second structural layer 310 also includes a first sensor structure 311 corresponding to the first opening 111 and a second sensor structure 312 corresponding to the second opening 112.

[0169] The MEMS structure layer also includes a second electrical interconnect layer 320 located on the surface of the second side 302 of the second structure layer 310.

[0170] The second substrate 200 is bonded to the MEMS structure layer and is located on opposite sides of the MEMS structure layer, respectively, as the first substrate 100. The second substrate 200 is used to seal the first opening 111 and the second opening 112 to form an independent first cavity 610 and a second cavity 620. The air pressure in the first cavity 610 is different from the air pressure in the second cavity 620.

[0171] The second substrate 200 includes a second dielectric layer 220, a third electrical interconnect layer 230 located within the second dielectric layer 220, and a fourth electrical interconnect layer 240 located on the surface of the second dielectric layer 220. The fourth electrical interconnect layer 240 corresponds to the second electrical interconnect layer 320 and is aligned and bonded to the second electrical interconnect layer 320. There is a gap between the second dielectric layer 220 and the first sensor structure 311, and between the second dielectric layer 220 and the second sensor structure 312.

[0172] The sensor formed by the MEMS structure consisting of the first sensor structure 311 and the first cavity 610, and the MEMS structure consisting of the second sensor structure 312 and the first cavity 610620, can be an accelerometer, a gyroscope, a pressure gauge, or a combination of these three.

[0173] The conductive via 130 is located within the first substrate 100 and is independent of the first opening 111 and the second opening 112. The conductive via 130 and the first opening 111 are respectively connected to the micro-air channel 400.

[0174] The first electrical interconnect structure 500 is located in the micro-air channel 400 between the bottom of the conductive via 130 and the bottom of the auxiliary trench 313, and in the conductive via 130. The first electrical interconnect structure 500 is connected to the bottom of the auxiliary trench 313.

[0175] The first electrical interconnect structure 500 includes a seed layer 511 and a filling conductive layer 521. The seed layer 511 is located on the inner wall surface of the conductive via 130 and extends to the bottom surface of the auxiliary trench 313 corresponding to the bottom of the conductive via 130. The filling conductive layer 521 is located on the surface of the seed layer 511 and fills the conductive via 130.

[0176] In some embodiments, the thickness of the seed layer 511 is more than three times the depth of the auxiliary trench 313.

[0177] Please refer to Figure 15 The first opening 111 has a first projection 601 on the surface of the first substrate 100, and the bottom of the conductive via 130 has a second projection 602 on the surface of the first substrate 100. The auxiliary trench 313 is divided into a first end region, a channel region and a second end region along the length of the trench. The trench lengths of the first end region and the second end region are both less than the trench length of the channel region. The projection of the first end region on the surface of the first substrate 100 is within the range of the first projection 601, and the projection of the second end region on the surface of the first substrate 100 penetrates the second projection 602 or is within the range of the second projection 602.

[0178] For detailed descriptions of the first substrate 100, MEMS structure layer, second substrate 200, vias, first electrical interconnect structure 500, and their respective features, please refer to the descriptions in the above manufacturing method embodiments; they will not be repeated here.

[0179] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing an integrated MEMS chip, characterized in that, include: A first substrate is formed, the first substrate including a first structural layer and a first dielectric film located on the surface of the first structural layer, the first structural layer having a first opening and a second opening that are independent of each other, and the first dielectric film being made of a different material from the first structural layer. A MEMS structure layer is formed on the first substrate, and the MEMS structure layer has an auxiliary trench that opens toward the first substrate. The length of the auxiliary trench is greater than the depth of the trench. The first dielectric film and the auxiliary trench form a micro-air channel. A second substrate is bonded to the MEMS structure layer to seal the first opening and the second opening, forming a first cavity and a second cavity that are independent of each other; After bonding the second substrate, the first substrate is etched from the side opposite to the first dielectric film to form a conductive via independent of the first opening and the second opening in the first substrate. The conductive via and the first opening are respectively connected to the micro-gas channel. Air is drawn into or drawn into the first cavity through the conductive through-hole and the micro-air channel, so that the air pressure in the first cavity is different from the air pressure in the second cavity; A first electrical interconnection structure is formed in the micro-air channel between the bottom of the conductive through hole and the bottom of the auxiliary trench, and in the conductive through hole. The first electrical interconnection structure is connected to the bottom of the auxiliary trench.

2. The manufacturing method as described in claim 1, characterized in that, The method for forming a MEMS structure layer on the first substrate includes: A third substrate is provided, the third substrate having opposing first and second sides; The auxiliary trench exposed on the first side is formed within the third substrate; After the auxiliary trench is formed, the third substrate is bonded to the first substrate, with the first side facing the first substrate; After bonding the third substrate to the first substrate, the third substrate is thinned from the second side to form a MEMS material layer. The MEMS material layer is patterned from the second side to form a second structural layer, the second structural layer including a first sensor structure corresponding to the first opening and a second sensor structure corresponding to the second opening.

3. The manufacturing method as described in claim 2, characterized in that, The method of forming a MEMS structure layer on the first substrate further includes: forming a second electrical interconnect layer on the surface of the MEMS material layer; The second substrate includes a second dielectric layer, a third electrical interconnect layer located within the second dielectric layer, and a fourth electrical interconnect layer located on the surface of the second dielectric layer, the fourth electrical interconnect layer corresponding to the second electrical interconnect layer. The method of bonding the second substrate to the MEMS structure layer includes: oriented the fourth electrical interconnect layer toward the second side, and aligning and bonding the fourth electrical interconnect layer with the second electrical interconnect layer, with the second dielectric layer and the first sensor structure being separated, as well as the second dielectric layer and the second sensor structure being separated.

4. The manufacturing method as described in claim 2, characterized in that, Both the first structural layer and the second structural layer are made of silicon.

5. The manufacturing method as described in claim 1, characterized in that, The method for forming the first electrical interconnect structure includes: Seed material film is deposited on the other side surface of the first substrate opposite to the first dielectric film, the inner wall surface of the conductive via, and the bottom surface of the auxiliary trench corresponding to the bottom of the conductive via; A conductive material filling layer is formed on the surface of the seed material film, wherein the conductive material filling layer at least fills a portion of the conductive vias; The conductive material layer and the seed material film are ground or etched from the side of the first substrate opposite to the first dielectric film until the surface of the first substrate opposite to the first dielectric film is exposed, forming the first electrical interconnect structure.

6. The manufacturing method as described in claim 5, characterized in that, Before the conductive via is formed, the air pressure in the first cavity and the air pressure in the second cavity are the same initial air pressure; During the deposition of seed material film, the process gas pressure of the deposition process is a target gas pressure that is different from the initial gas pressure, so that air is drawn or introduced into the first cavity through the conductive through-hole and the micro-air channel, so that the gas pressure in the first cavity is adjusted to the target gas pressure.

7. The manufacturing method as described in claim 6, characterized in that, The target air pressure is lower than the initial air pressure.

8. The manufacturing method as described in claim 5, characterized in that, The thickness of the seed material membrane is more than three times the depth of the auxiliary groove.

9. The manufacturing method as described in claim 5, characterized in that, The conductive material layer completely fills the conductive via.

10. The manufacturing method as described in claim 1, characterized in that, The first opening has a first projection on the surface of the first substrate, and the bottom of the conductive via has a second projection on the surface of the first substrate. The auxiliary trench is divided into a first end region, a channel region, and a second end region along its length. The lengths of the first end region and the second end region are both less than the length of the channel region. The projection of the first end region on the surface of the first substrate is within the first projection range, and the projection of the second end region on the surface of the first substrate penetrates the second projection or is within the second projection range.

11. The manufacturing method as described in claim 1 or 10, characterized in that, The length of the auxiliary trench is more than 10 times its depth.

12. The manufacturing method as described in claim 11, characterized in that, The auxiliary trench has a length of more than 10 micrometers and a depth ranging from 0.1 micrometers to 1 micrometer.

13. The manufacturing method as described in claim 1, characterized in that, The number of auxiliary trenches is multiple.

14. The manufacturing method as described in claim 1, characterized in that, The auxiliary trench includes one or more of the following: a straight structure, a bent structure, and a coiled tube structure.

15. The manufacturing method as described in claim 1, characterized in that, The method for forming the first substrate includes: Provide the initial first base; The initial first substrate is graphically represented to form the first structural layer; The first dielectric film is formed on the surface of the first structural layer, the inner wall surface of the first opening, and the inner wall surface of the second opening.

16. The manufacturing method as described in claim 1, characterized in that, The method for forming the first substrate includes: Provide the initial first base; An initial first dielectric film is formed on the surface of the initial first substrate; The initial first substrate and the initial first dielectric film are graphically represented to form the first structural layer and the first dielectric film located on the surface of the first structural layer.

17. An integrated MEMS chip, characterized in that, include: The first substrate includes a first structural layer and a first dielectric film located on the surface of the first structural layer. The first structural layer has a first opening and a second opening that are independent of each other. The first dielectric film is made of a different material than the first structural layer. A MEMS structure layer is stacked on the first substrate. The MEMS structure layer has an auxiliary trench that opens toward the first substrate. The length of the auxiliary trench is greater than its depth. The first dielectric film and the auxiliary trench form a micro-air channel. The second substrate is bonded to the MEMS structure layer and is located on opposite sides of the MEMS structure layer, respectively, as the first substrate. The second substrate is used to seal the first opening and the second opening to form an independent first cavity and a second cavity. The air pressure in the first cavity is different from the air pressure in the second cavity. A conductive via is located within the first substrate and is independent of the first opening and the second opening. The conductive via and the first opening are respectively connected to the micro-air channel. A first electrical interconnect structure is located within a micro-air channel between the bottom of the conductive via and the bottom of the auxiliary trench, and within the conductive via. The first electrical interconnect structure is connected to the bottom of the auxiliary trench.

18. The integrated MEMS chip as described in claim 17, characterized in that, The MEMS structure layer includes: a second structure layer having a first side and a second side opposite to each other, the second structure layer being bonded to the first substrate, the first side facing the first substrate, the auxiliary trench being located within the second structure layer and exposed to the first side by the surface of the second structure layer, and the second structure layer further including a first sensor structure corresponding to the first opening and a second sensor structure corresponding to the second opening.

19. The integrated MEMS chip as described in claim 18, characterized in that, The MEMS structure layer further includes: a second electrical interconnect layer located on the second side surface of the second structure layer; The second substrate includes a second dielectric layer, a third electrical interconnect layer located within the second dielectric layer, and a fourth electrical interconnect layer located on the surface of the second dielectric layer. The fourth electrical interconnect layer corresponds to the second electrical interconnect layer and is aligned and bonded to the second electrical interconnect layer. There is a gap between the second dielectric layer and the first sensor structure, and between the second dielectric layer and the second sensor structure.

20. The integrated MEMS chip as described in claim 19, characterized in that, The first electrical interconnect structure includes a seed layer and a filling conductive layer. The seed layer is located on the inner wall surface of the conductive via and extends to the bottom surface of an auxiliary trench corresponding to the bottom of the conductive via. The filling conductive layer is located on the surface of the seed layer and at least partially fills the conductive via.

21. The integrated MEMS chip as described in claim 20, characterized in that, The thickness of the seed layer (511) is more than three times the depth of the auxiliary trench.

22. The integrated MEMS chip as described in claim 17, characterized in that, The first opening has a first projection on the surface of the first substrate, and the bottom of the conductive via has a second projection on the surface of the first substrate. The auxiliary trench is divided into a first end region, a channel region, and a second end region along its length. The lengths of the first end region and the second end region are both less than the length of the channel region. The projection of the first end region on the surface of the first substrate is within the first projection range, and the projection of the second end region on the surface of the first substrate penetrates the second projection or is within the second projection range.

23. The integrated MEMS chip as described in claim 17 or 22, characterized in that, The length of the auxiliary trench is more than 10 times its depth.

24. The integrated MEMS chip as described in claim 23, characterized in that, The number of auxiliary trenches is multiple.

25. The integrated MEMS chip as described in claim 17, characterized in that, The first dielectric film is also located on the inner wall surfaces of the first opening and the second opening.

Images