Circuit device and physical quantity sensor

Abstract

The invention provides a circuit device and a physical quantity sensor, which can perform fault detection in the use of a detection circuit. A circuit device is provided with: a detection circuit that includes a first A / D conversion circuit that A / D converts a signal output from a sensor element and outputs a first digital signal, and that generates a detection signal on the basis of the first digital signal; a dummy detection circuit that includes a second A / D conversion circuit that performs A / D conversion on a signal output from the sensor element and outputs a second digital signal, and that generates a dummy detection signal on the basis of the second digital signal; and a failure detection circuit that detects a failure of the detection circuit on the basis of a comparison result obtained by comparing the value of the detection signal and the value of the dummy detection signal.

Description

Technical Field

[0001] The present invention relates to a circuit device and a physical quantity sensor. Background Art

[0002] A structure for detecting a fault of a circuit device is known. For example, Patent Document 1 discloses a structure for performing a diagnostic process after power is turned on and before a normal operation period. Through this diagnostic process, a diagnostic signal is input to a detection circuit that detects an output signal of a physical quantity transducer, and based on a response to the signal, it is diagnosed whether the detection circuit is operating normally.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2016-170136

[0004] A failure may occur during use of the detection circuit. Therefore, it is desirable to be able to detect a failure during use of the detection circuit, not just before the normal operation period. Summary of the invention

[0005] The circuit device comprises: a detection circuit, which includes a first A / D conversion circuit that performs A / D conversion on a signal output from a sensor element and outputs a first digital signal, and generates a detection signal based on the first digital signal; a virtual detection circuit, which includes a second A / D conversion circuit that performs A / D conversion on a signal output from the sensor element and outputs a second digital signal, and generates a virtual detection signal based on the second digital signal; and a fault detection circuit that detects a fault in the detection circuit based on a comparison result obtained by comparing the value of the detection signal with the value of the virtual detection signal.

[0006] The physical quantity sensor comprises: a sensor element; a detection circuit, which includes a first A / D conversion circuit that performs A / D conversion on a signal output from the sensor element and outputs a first digital signal, and generates a detection signal based on the first digital signal; a virtual detection circuit, which includes a second A / D conversion circuit that performs A / D conversion on a signal output from the sensor element and outputs a second digital signal, and generates a virtual detection signal based on the second digital signal; and a fault detection circuit that detects a fault in the detection circuit based on a comparison result obtained by comparing a value of the detection signal with a value of the virtual detection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram of a physical quantity sensor including the circuit device according to the first embodiment.

[0008] Figure 2 It is a diagram showing a configuration example of a driving circuit.

[0009] Figure 3It is a diagram showing a configuration example of a detection circuit and a dummy detection circuit.

[0010] Figure 4 It is a diagram showing an input and output example of a limit processing unit.

[0011] Figure 5 It is a diagram showing an input and output example of a limit processing unit.

[0012] Figure 6 It is a diagram showing a configuration example of a failure detection circuit.

[0013] Figure 7 It is a diagram showing a configuration example of a value determination unit.

[0014] Figure 8 It is a diagram showing a configuration example of a change rate determination unit.

[0015] Fig. 9 is a graph representing a sine wave.

[0016] Description of symbols

[0017] 1: physical quantity sensor; 10: sensor element; 20: drive circuit; 21: current-voltage converter; 22: gain control circuit; 23: comparator; 24: comparator; 30: amplifier circuit; 40: detection circuit; 42: first synchronous detection circuit; 43: first low-pass filter; 44: first A / D conversion circuit; 45: limit processing unit; 46: IIR filter; 50: virtual detection circuit; 52: second synchronous detection circuit; 53: second low-pass filter; 54: second A / D conversion circuit; 55: limit processing unit; 56: IIR filter; 60: fault detection circuit; 61: change rate determination unit; 61a: differentiator ;61a1: adder;61a2: delay unit;61b: differentiator;61b1: adder;61b2: delay unit;61c: sign comparison unit;61d: change determination unit;62: multiplication unit;63: addition unit;64: value determination unit;64a: selector;64b: addition unit;64c: absolute value output unit;64d: absolute value output unit;64e: multiplication unit;64f: addition unit;64g: comparison unit;65: fault determination unit;70: control unit;80: register unit;90: temperature sensor;PD1: connection disk;PD2: connection disk;PD3: connection disk;PD4: connection disk;SW1~SW4: switches. DETAILED DESCRIPTION

[0018] 1. First Implementation Method

[0019] Hereinafter, preferred embodiments of the present invention will be described in detail using the accompanying drawings. In addition, the embodiments described below do not unduly limit the contents of the present invention as described in the claims. In addition, not all structures described below are necessarily necessary constituent conditions of the present invention. Hereinafter, an embodiment will be described by taking a sensor element for detecting angular velocity, i.e., an angular velocity sensor, as an example.

[0020] Figure 1 : is a block diagram showing a configuration example of a physical quantity sensor 1 including a circuit device according to the present embodiment. Figure 1 The physical quantity sensor 1 shown includes a sensor element 10 , a drive circuit 20 , an amplifier circuit 30 , a detection circuit 40 , a dummy detection circuit 50 , a failure detection circuit 60 , a control unit 70 , a register unit 80 , and a temperature sensor 90 .

[0021] In this embodiment, the sensor element 10 is an angular velocity sensor. The angular velocity sensor can be implemented by various known structures. For example, the sensor element 10 can be formed by an element that outputs vibrations based on the Coriolis force acting on the vibration arm. Of course, the shape of the sensor is not limited, and sensors of various shapes such as double T-type, tuning fork type, and H-type can be used.

[0022] The sensor element 10 includes an input terminal for inputting a drive signal DQ from the drive circuit 20 and an output terminal for outputting a feedback signal DI to the drive circuit 20. In the present embodiment, the input terminal is electrically connected to the connection pad PD4. In addition, the output terminal is electrically connected to the connection pad PD3. The sensor element 10 includes two detection signal output terminals for outputting detection signals, and each detection signal output terminal is electrically connected to the connection pads PD1 and PD2.

[0023] The driving circuit 20 drives the sensor element 10. The driving circuit 20 is electrically connected to the sensor element 10 via the connection pads PD3 and PD4. The driving circuit 20 receives a feedback signal DI from the sensor element 10 via the connection pad PD3, and outputs a driving signal DQ corresponding to the feedback signal DI via the connection pad PD4, thereby driving the sensor element 10.

[0024] The driving circuit 20 can be realized by various well-known circuits. Figure 2 This is a configuration example of the drive circuit 20 . Figure 2 The driving circuit 20 shown can be realized by a configuration including a current-voltage converter (I / V converter) 21, a gain control circuit 22, a comparator 23, and a comparator 24. Each of these circuits can be realized by a known configuration.

[0025] exist Figure 2In the example shown, when the feedback signal DI is input from the sensor element 10 to the current-voltage converter 21 via the connection pad PD3, the current-voltage converter 21 converts it into an AC voltage signal having the same frequency as the vibration frequency of the feedback signal DI and outputs it.

[0026] The AC voltage signal output from the current-voltage converter 21 is input to the comparator 23 and the comparator 24. The comparator 23 converts the AC voltage signal of the current-voltage converter 21 into a rectangular wave and inputs it to the sensor element 10 as a drive signal DQ. As a result, the sensor element 10 is driven by the drive signal DQ. The gain control circuit 22 controls the reference voltage of the comparator 23 so that the amplitude of the input AC voltage signal is kept at a fixed value.

[0027] The comparator 24 uses the amplitude center of the AC voltage signal of the current-voltage converter 21 as a reference voltage, compares the AC voltage signal with the reference voltage signal, and outputs a square wave voltage signal whose output level changes in such a way that the former becomes a high level when the former is larger and becomes a low level when the latter is larger. The square wave voltage signal is a signal generated based on the drive signal DQ and is used for synchronous detection described later, so the square wave voltage signal is referred to as a synchronous detection signal SDET here. The synchronous detection signal SDET is input to the detection circuit 40 and the virtual detection circuit 50.

[0028] The sensor element driven by the driving circuit 20 outputs the first and second detection signals IQ1 and IQ2 from the detection signal output terminal. The first and second detection signals IQ1 and IQ2 are differential signals, which are input to the amplifier circuit 30 via the connection pads PD1 and PD2. The amplifier circuit 30 is a Q / V conversion circuit, which has a Q / V conversion circuit to which the first detection signal IQ1 is input and a Q / V conversion circuit to which the second detection signal IQ2 is input. The Q / V conversion circuit (charge amplifier) ​​is a circuit that converts the charge signal (small charge signal, small current signal) from the sensor element 10 into a voltage signal, and can also be considered as a type of I / V conversion circuit.

[0029] The first and second voltage signals outputted by converting the first and second detection signals 1IQ1 and IQ2 also become differential signals of opposite phases to each other, but Figure 1 In FIG. 1 , for simplicity, an arrow representing an output signal is shown by a single arrow. The first and second voltage signals output from the amplifier circuit 30 are input to the detection circuit 40 and the dummy detection circuit 50 .

[0030] The detection circuit 40 is a circuit that outputs a detection signal indicating the angular velocity detected by the sensor element 10 based on the first and second voltage signals output from the amplifier circuit 30. The detailed configuration of the detection circuit 40 will be described later.

[0031] The pseudo detection circuit 50 includes a circuit for virtually reproducing the operation of the detection circuit 40 based on the first and second voltage signals output from the amplifier circuit 30, and is a circuit for outputting a pseudo detection signal imitating the detection signal. The detailed structure of the pseudo detection circuit 50 will be described later.

[0032] The failure detection circuit 60 is a circuit that detects a failure of the detection circuit based on a comparison result of the value of the detection signal output from the detection circuit 40 and the value of the dummy detection signal output from the dummy detection circuit 50. The detailed structure of the failure detection circuit 60 will be described later.

[0033] The control unit 70 performs various control processes. For example, the control unit 70 performs control processes for the detection circuit 40, the dummy detection circuit 50, and the fault detection circuit 60. The control unit 70 can be implemented, for example, by a logic circuit generated by an automatic configuration and wiring method such as a gate array or a processor that operates based on firmware.

[0034] The register unit 80 has registers for storing various information. The register unit 80 can be implemented, for example, by a memory such as an SRAM, a flip-flop circuit, etc. In the present embodiment, the various information stored in the register unit 80 includes the gain (det_gain, Vth_gain), offset (det_offs, Vth_offs), the second threshold del_Vth, the filter coefficient, etc., which will be described later. This information is obtained by the control unit 70 and provided to each circuit.

[0035] The temperature sensor 90 is a sensor that outputs a signal (temperature signal) of a voltage level corresponding to the temperature of its surroundings. It can be a positive polarity sensor whose output voltage increases as the temperature increases, or a negative polarity sensor whose output voltage decreases as the temperature increases. The temperature sensor 90 can also be a circuit that outputs a voltage proportional to the absolute temperature (PTAT (Proportional To Absolute Temperature) voltage). The temperature signal output from the temperature sensor 90 is input to the virtual detection circuit 50.

[0036] 1.1 Structure of the detection circuit

[0037] Next, the configuration of the detection circuit 40 will be described in detail. Figure 3The following is a structural example of the detection circuit 40. In this example, the detection circuit 40 includes a PGA (Programmable Gain Amplifier) ​​41, a first synchronous detection circuit 42, a first low-pass filter (first LPF) 43, a first A / D conversion circuit (first ADC) 44, a limiter processing unit 45, an IIR (Infinite impulse response) filter 46, and a DSP (Digital Signal Processor) 47. The PGA 41, the first synchronous detection circuit 42, the first low-pass filter 43, and the first A / D conversion circuit 44 can be implemented by various known analog circuits. The limiter processing unit 45, the IIR filter 46, and the DSP 47 can be implemented by various known digital circuits. The digital circuit can be implemented by various integrated circuits such as a CPU, or by a programmable gate array, etc.

[0038] The PGA 41 is a circuit for amplifying the signal output from the amplifier circuit 30. The PGA 41 includes a differential amplifier circuit and an AC amplifier circuit, performs differential amplification based on the first and second voltage signals which are differential signals output from the amplifier circuit 30, and further amplifies the obtained signal.

[0039] The first synchronous detection circuit 42 is a multiplication circuit that performs synchronous detection by multiplying the signal output from the PGA 41 by the synchronous detection signal SDET output from the comparator 24. In addition, the first low-pass filter 43 is a circuit that smoothes the signal output from the first synchronous detection circuit 42. A signal having a voltage value corresponding to the angular velocity detected by the sensor element 10 is generated by the first synchronous detection circuit and the first low-pass filter 43, and is output from the first low-pass filter 43.

[0040] The first A / D conversion circuit 44 is a circuit that performs A / D conversion on the signal output from the first low-pass filter 43 and outputs it as the first digital signal Dt1. The DSP 47 performs various processes based on the first digital signal Dt1 to generate a detection signal output to the outside of the physical quantity sensor 1. The various processes can be well-known processes, and various filtering processes and temperature compensation processes can be cited. The filtering process can also be a process equivalent to the process of the IIR filter 46. The DSP 47 can output the generated detection signal to the outside via an interface not shown in the figure, or it can output it to the control unit 70. In this case, the control unit 70 can also save the detection signal in the register unit 80, etc., and output it to the outside according to a request from an external device, etc.

[0041] In the limit processing unit 45, when an instruction based on the signal clip_flg is given from the limit processing unit 55 described later, the size of the output signal output from the limit processing unit 45 is set to a fixed value. In addition, when no instruction based on the signal clip_flg is given from the limit processing unit 55, the limit processing unit 45 directly uses the input signal to the limit processing unit 45 as an output signal. That is, the limit processing unit 45 is a circuit that limits the size of the output signal to a fixed value or less, and when limited by the limit processing unit 45, the size of the detection signal output from the IIR filter 46 described later is a fixed value.

[0042] The IIR filter 46 is a filter having various functions such as removing a signal of a predetermined frequency band. In the present embodiment, the control unit 70 determines the filter coefficient of the IIR filter 46 based on the filter coefficient stored in the register unit 80. The IIR filter 46 applies a filter having a characteristic determined by the filter coefficient to the input signal, and outputs a detection signal Sr. The IIR filter 46 is used, for example, to remove a signal of a frequency band different from the angular velocity as the detection object detected by the sensor element 10. The detection signal Sr output from the IIR filter 46 is input to the fault detection circuit 60.

[0043] 1.2 Structure of virtual detection circuit

[0044] Next, the structure of the dummy detection circuit 50 will be described in detail. Figure 3 , a structural example of a virtual detection circuit 50 is shown. In this example, the virtual detection circuit 50 includes a PGA (Programmable Gain Amplifier) ​​51, a second synchronous detection circuit 52, a second low-pass filter (second LPF) 53, a second A / D conversion circuit (second ADC) 54, a limiting processing unit 55, and an IIR (Infinite impulse response) filter 56. The PGA 51, the second synchronous detection circuit 52, the second low-pass filter 53, and the second A / D conversion circuit 54 can be implemented by various well-known analog circuits. The limiting processing unit 55 and the IIR filter 56 can be implemented by various well-known digital circuits. Digital circuits can be implemented by various integrated circuits such as CPUs, or by programmable gate arrays, etc.

[0045] The second synchronous detection circuit 52 is a multiplication circuit that performs synchronous detection by multiplying the signal output from the amplifier circuit 30 by the synchronous detection signal SDET output from the comparator 24. In addition, the second low-pass filter 53 is a circuit that smoothes the signal output from the second synchronous detection circuit 52. According to the second synchronous detection circuit and the second low-pass filter 53, a signal of a voltage value corresponding to the angular velocity detected by the sensor element 10 is generated and output from the second low-pass filter 53.

[0046] The PGA 51 is a circuit that amplifies the signal output from the second low-pass filter 53. The PGA 51 includes a differential amplifier circuit and an AC amplifier circuit, and performs differential amplification based on each signal output from the second low-pass filter 53, and further amplifies the obtained signal. The second A / D conversion circuit 54 is a circuit that performs A / D conversion on the signal output from the PGA 51 and outputs it as a second digital signal Dt2.

[0047] In the amplitude limiting processing unit 55, when the size (absolute value) of the input signal exceeds the specified value, the size of the output signal is limited to a fixed value, and when the size of the input signal is below the specified value, the input signal is directly used as the output signal. The specified value is a predetermined size, which is a value smaller than the maximum value of the input range of the second A / D conversion circuit 54. That is, the amplitude limiting processing unit 55 is a circuit that limits the size of the output signal to below a fixed value. Under the limitation of the amplitude limiting processing unit 55, the size of the virtual detection signal output from the IIR filter 56 described later is a fixed value.

[0048] In addition, when the magnitude (absolute value) of the input signal exceeds a predetermined value, the clipping processing unit 55 outputs a signal clip_flg indicating the start of clipping to the clipping processing unit 45. Therefore, in the clipping processing unit 45, when an instruction based on the signal clip_flg is given from the clipping processing unit 55 described later, the magnitude of the output signal output from the clipping processing unit 45 is set to a fixed value. In addition, when no instruction based on the signal clip_flg is given from the clipping processing unit 55, the clipping processing unit 45 directly uses the input signal to the clipping processing unit 45 as an output signal. In addition, the clipping processing unit 55 also outputs the signal clip_flg to the value determination unit 64, and the validity and invalidation of the value determination are controlled by the signal clip_flg.

[0049] The IIR filter 56 is a filter having various functions such as removing a signal of a predetermined frequency band. In the present embodiment, the control unit 70 determines the filter coefficient of the IIR filter 56 based on the filter coefficient stored in the register unit 80. The IIR filter 56 applies a filter having a characteristic determined by the filter coefficient to the input signal, and outputs a virtual detection signal Sp. In the present embodiment, the filter coefficient of the IIR filter 56 is set to a value that outputs a signal having the same characteristic as the IIR filter 46, for example. The virtual detection signal Sp output from the IIR filter 56 is input to the fault detection circuit 60.

[0050] In this embodiment, the virtual detection circuit 50 includes switches SW1 to SW4. The switch SW1 is provided between the second low-pass filter 53 and the PGA 51, and the switch SW4 is provided between the second A / D conversion circuit 54 and the limit processing unit 55. The switch SW2 is provided between the temperature sensor 90 and the PGA 51, and the switch SW3 is provided between the second A / D conversion circuit 54 and the DSP 47.

[0051] Switches SW1 to SW4 are turned on and off by control signals SEL1 and SEL2 output from control unit 70. Control signals SEL1 and SEL2 are signals with opposite phases. When control signal SEL1 is turned on, control signal SEL2 is turned off. When control signal SEL1 is turned off, control signal SEL2 is turned on.

[0052] The switches SW1 and SW4 are controlled by the control signal SEL1, and the switches S2 and S3 are controlled by the control signal SEL2. Therefore, when the switches SW1 and SW4 are turned on by the control signal SEL1, the switches SW2 and SW3 are turned off by the control signal SEL2. In this state, the virtual detection circuit 50 is not electrically connected to the temperature sensor 90 and the DSP 47, and the virtual detection circuit 50 is in a state of outputting the virtual detection signal Sp based on the output signal from the amplifier circuit 30.

[0053] When the switches SW1 and SW4 are turned off by the control signal SEL1, the switches SW2 and SW3 are turned on by the control signal SEL2. In this state, the output signal of the second low-pass filter 53 of the virtual detection circuit 50 is not provided to the PGA 51, and the output signal of the second A / D conversion circuit 54 is not provided to the limit processing unit 55. Therefore, the virtual detection signal Sp is not output. In addition, in this state, the temperature sensor 90 is connected to the PGA 51, and the output signal of the second A / D conversion circuit 54 is input to the DSP 47. Therefore, the signal detected by the temperature sensor 90 is amplified in the PGA 51, and is set as a digital temperature detection signal by the second A / D conversion circuit 54, and is input to the DSP 47.

[0054] In addition, the transmission path of the output signal of the temperature sensor 90 is indicated by a single arrow, but the output signal of the temperature sensor 90 of the present embodiment is a differential signal, and two types of signals are input to the PGA 51. Therefore, in the PGA 51, the signal output by the temperature sensor 90 is differentially amplified in the same manner as the signal output by the second low-pass filter 53. The second A / D conversion circuit 54 converts the differentially amplified signal into a digital temperature detection signal, and outputs it to the DSP 47.

[0055] As a result, the DSP 47 can obtain the temperature detected by the temperature sensor 90. Based on the obtained temperature detection signal, the DSP 47 performs temperature compensation processing on the detection signal generated based on the signal output from the sensor element 10. That is, the DSP 47 performs a predetermined process based on the first digital signal Dt1 to obtain a detection signal indicating the detection result of the sensor element 10, and at this time, correction is performed to offset the characteristic change of the sensor element 10 caused by the temperature.

[0056] In the present embodiment, the control unit 70 switches the state of outputting the virtual detection signal Sp from the virtual detection circuit 50 and the state of performing temperature compensation processing based on the detection result of the temperature sensor 90 by controlling the switches SW1 to SW4. That is, the second A / D conversion circuit 54 performs A / D conversion for generating the virtual detection signal Sp and A / D conversion for generating the temperature detection signal in a time-division manner under the control of the control unit 70. According to the above structure, the virtual detection signal Sp and the temperature detection signal can be generated using a common circuit, and the physical quantity sensor 1 can be realized at a low cost.

[0057] In addition, in the present embodiment, in order to generate a temperature detection signal based on the detection result of the temperature sensor 90, the circuit is configured in the order of inputting the output signal of the PGA 51 to the second A / D conversion circuit 54. However, if the temperature compensation process based on the temperature detection signal is not performed, or the temperature compensation process is performed without sharing the circuit with the virtual detection circuit 50, the order of the circuit is not limited. Therefore, in this case, the circuit can also be configured to perform the process in the same order as the detection circuit 40, for example, the order of the PGA 51, the second synchronous detection circuit 52, the second low-pass filter 53, and the second A / D conversion circuit 54.

[0058] In addition, in the present embodiment, the second A / D conversion circuit 54 is used not only to generate the virtual detection signal Sp but also to generate the temperature detection signal, and therefore is composed of a circuit having sufficient performance required for generating the temperature detection signal. Therefore, it is not necessary to have sufficient performance required for detecting the physical quantity based on the sensor element 10, and it can be a simpler circuit than the first A / D conversion circuit 44 used in the detection circuit 40.

[0059] Therefore, in the present embodiment, the second A / D conversion circuit 54 is configured by a circuit having a resolution lower than that of the first A / D conversion circuit 44. Specifically, the resolution of the first A / D conversion circuit 44 is 16 bits, while the resolution of the second A / D conversion circuit 54 is 10 bits. According to the above configuration, the physical quantity sensor 1 can be realized at a low cost compared to the case where the second A / D conversion circuit 54 is configured by a circuit equivalent to the first A / D conversion circuit 44 used in the detection circuit 40.

[0060] Furthermore, in the present embodiment, the second A / D conversion circuit 54 is composed of a simpler circuit than the first A / D conversion circuit 44, and therefore, the input range of the second A / D conversion circuit 54 is smaller than the input range of the first A / D conversion circuit 44. For example, a configuration is adopted in which the input range of the second A / D conversion circuit 54 is 1.2V, but the input range of the first A / D conversion circuit 44 is 1.8V. In the case of this configuration, the second A / D conversion circuit 54 converts the analog voltage signal of -1.2V to 1.2V into the second digital signal Dt2. On the other hand, the first A / D conversion circuit 44 converts the analog voltage signal of -1.8V to 1.8V into the first digital signal Dt1.

[0061] In the present embodiment, the functions of each circuit of PGA 51, the second synchronous detection circuit 52, and the second low-pass filter 53 are the same as those of each circuit of PGA 41, the first synchronous detection circuit 42, and the first low-pass filter 43, and the characteristics of the transfer function are similar. However, the circuits are not completely identical, and the gains of PGA 41 and 51 may be different, so the functional form of the transfer characteristic (the degree of the variable, the variable represented by the denominator and numerator, and the form of addition, subtraction, multiplication and division of the variable) is the same. On the other hand, the coefficients included in the transfer function are values ​​close to each other, but not completely the same. Therefore, in the present embodiment, the size of the signal input to the first A / D conversion circuit 44 based on the signal from the sensor element 10 is designed to be roughly the same as the size of the signal input to the second A / D conversion circuit 54, and the change characteristics (such as the rate of change relative to time) are roughly the same.

[0062] Furthermore, in the present embodiment, the fault detection circuit 60 determines a fault based on whether the difference between the detection signal Sr generated based on the first digital signal Dt1 output by the first A / D conversion circuit 44 and the virtual detection signal Sp generated based on the second digital signal Dt2 output by the second A / D conversion circuit 54 is greater than a threshold value (details will be described later). Therefore, if the magnitude of the detection signal Sr and the magnitude of the virtual detection signal Sp are different from each other but are obviously normal, it is determined to be a fault. Such a situation may occur due to the difference in the input ranges of the first A / D conversion circuit 44 and the second A / D conversion circuit 54. For example, the following situation may occur: the output signal of the PGA 51 exceeds the input range of the second A / D conversion circuit 54, but the output signal of the first low-pass filter 43 does not exceed the input range of the first A / D conversion circuit 44. In this case, the second digital signal Dt2 output from the second A / D conversion circuit 54 is a saturated value (for example, a digital value corresponding to the input analog voltage 1.2V), but the first digital signal Dt1 output from the first A / D conversion circuit 44 is an unsaturated value (for example, a digital value corresponding to the input analog voltage 1.5V).

[0063] In this case, the difference between the detection signal Sr and the virtual detection signal Sp is greater than the threshold value, but this condition is not a fault. Therefore, in the present embodiment, when the size of the second digital signal Dt2 output from the second A / D conversion circuit 54 having a relatively small input range exceeds the specified value, the first digital signal Dt1 and the second digital signal Dt2 are respectively limited by the limit processing unit 45 and the limit processing unit 55, and the judgment based on the above-mentioned difference is not performed. That is, when the size of the second digital signal Dt2 output from the second A / D conversion circuit 54 and input to the limit processing unit 55 exceeds the specified value, it is considered that the size of the input signal to the second A / D conversion circuit 54 may be a value exceeding the input range, and the fault judgment is invalidated.

[0064] Figure 4 4 is a diagram showing an input signal In1 and an output signal Out1 of the clipping processing unit 45, an input signal In2 and an output signal Out2 of the clipping processing unit 55, and clip_flg output from the second A / D conversion circuit 54. Figure 4 In the figure, the horizontal axis is time and the vertical axis is signal level. Figure 4 As shown in FIG. 5 , when the magnitude (absolute value) of the input signal In2 to the limit processing unit 55 exceeds the specified value Thi, the output signal Out2 is limited and fixed to the specified value Thi. Figure 4 In the example shown, during the period from time t1 to t2 and from time t3 to t4, the magnitude (absolute value) of the input signal In2 exceeds the predetermined value Thi, and the output signal Out2 is limited.

[0065] When clipping is performed in the clipping processing unit 55, the clipping processing unit 55 outputs a signal clip_flg indicating the start of clipping to the clipping processing unit 45. Figure 4 The input signal In1 of the clipping processing unit 45 shown in the figure is clipped during the period between time t1 and t2 and time t3 and t4, and becomes the output signal Out1. The prescribed value for determining whether to perform the clipping process is a value smaller than the maximum value of the input range of the second A / D conversion circuit 54. Therefore, when the clipping is performed when the second digital signal Dt2 is greater than the prescribed value, the clipping is performed at least when the magnitude of the input signal to the second A / D conversion circuit 54 exceeds the maximum value of the input range. When the clipping is performed, the fault detection circuit 60 described later is invalidated. Therefore, the fault detection circuit 60 can be invalidated when the magnitude of the input signal to the second A / D conversion circuit 54 exceeds the maximum value of the input range and the second digital signal Dt2 cannot reflect the magnitude of the input signal to the second A / D conversion circuit 54. According to the above structure, it is possible to configure such that when the judgment is made based on the difference between the output results of the A / D conversion circuits with different input ranges, an erroneous judgment due to the difference in the input range will not occur.

[0066] On the other hand, when the detection circuit 40 fails, there is a case where the magnitude of the first digital signal Dt1 deviates from the magnitude of the second digital signal Dt2 although the magnitude of the second digital signal Dt2 does not exceed the specified value. Typically, a failure mode is considered in which the output from the first A / D conversion circuit 44, that is, the first digital signal Dt1, is saturated with a positive maximum value or a negative maximum value. In such a case, the output from the second A / D conversion circuit 54 does not exceed the specified value, so the amplitude limiting by the amplitude limiting processing unit 55, 45 is not performed.

[0067] exist Figure 5 , an example is shown in which, at time t0, for example, a failure occurs in the PGA 41, and the first digital signal Dt1 output from the first A / D conversion circuit 44, that is, the input signal In1 to the amplitude limiting processing unit 45 is saturated. In this example, at time t0, the second digital signal Dt2 output from the second A / D conversion circuit 54, that is, the input signal In2 to the amplitude limiting processing unit 55 is less than the specified value Thi, and therefore the amplitude limiting processing is not performed. Therefore, the fault detection circuit 60 is activated. In this situation, the output from the amplitude limiting processing unit 45 is also saturated, so the detection signal Sr output from the detection circuit 40 becomes larger. As a result, the difference between the detection signal Sr and the virtual detection signal Sp is greater than the threshold value, and the fault can be detected by the fault detection circuit 60.

[0068] In addition, in the present embodiment, whether to perform the limiting process is determined based on the size of the output signal of the second A / D conversion circuit 54. However, since the size of the input signal of the second A / D conversion circuit 54 corresponds to the size of the output signal, it is also possible to determine whether to perform the limiting process based on the size of the input signal of the second A / D conversion circuit 54.

[0069] 1.3 Structure of fault detection circuit

[0070] Next, the configuration of the failure detection circuit 60 will be described in detail. Figure 6 : is a diagram showing the structure of the fault detection circuit 60. The fault detection circuit 60 is a digital circuit that performs predetermined processing based on the detection signal Sr output from the IIR filter 46 provided in the detection circuit 40 and the virtual detection signal Sp output from the IIR filter 56 provided in the virtual detection circuit 50. The digital circuit can be implemented by various integrated circuits such as a CPU, or by a programmable gate array or the like. Figure 6 This diagram shows digital processing modularized by function.

[0071] The fault detection circuit 60 includes a change rate determination unit 61, a multiplication unit 62, an addition unit 63, a value determination unit 64, and a fault determination unit 65. The detection signal Sr and the virtual detection signal Sp are input to the fault detection circuit 60. However, in the present embodiment, the virtual detection signal Sp is multiplied by a gain (det_gain) by the multiplication unit 62, and an offset (det_offs) is added by the addition unit 63. In addition, the gain (det_gain) and the offset (det_offs) are predetermined and stored in the register unit 80. The control unit 70 obtains the gain (det_gain) and the offset (det_offs), and adjusts the multiplication unit 62 and the addition unit 63 so as to obtain the obtained gain (det_gain) and the offset (det_offs). The gain (det_gain) and the offset (det_offs) are set to cancel the difference in circuit characteristics between the detection circuit 40 and the dummy detection circuit 50 or the difference not considered in the design so that the detection signal Sr and the dummy detection signal Sp have substantially the same magnitude and characteristics.

[0072] The detection signal Sr and the virtual detection signal Sp corrected by the gain (det_gain) and the offset (det_offs) are input to the change rate determination unit 61. The change rate determination unit 61 calculates the flag ef_del for fault detection based on the change of the detection signal Sr and the change of the corrected virtual detection signal Sp. The calculation method of the flag ef_del will be described later. The flag ef_del is a flag that is turned off when the change of the detection signal Sr is consistent with the change of the corrected virtual detection signal Sp, and turned on when it is inconsistent.

[0073] The virtual detection circuit 50 is a replica of the detection circuit 40. Therefore, if the detection circuit 40 and the virtual detection circuit 50 operate normally, the detection signal Sr and the corrected virtual detection signal Sp should have qualitatively the same characteristics. Therefore, if the detection circuit 40 and the virtual detection circuit 50 operate normally, it is estimated that the change characteristics of the detection signal Sr and the virtual detection signal Sp are consistent. Therefore, in this embodiment, when the change of the detection signal Sr is inconsistent with the change of the corrected virtual detection signal Sp, the flag ef_del is set to on by the change rate determination unit 61, indicating that a failure may have occurred.

[0074] In addition, the detection signal Sr and the corrected virtual detection signal Sp are input to the value determination unit 64. The value determination unit 64 obtains the difference between the value of the detection signal Sr and the value of the corrected virtual detection signal Sp, and calculates a flag ef_val for fault detection based on the difference. The calculation method of the flag ef_val will be described later. The flag ef_val is a flag that obtains the difference between the value of the detection signal Sr and the value of the corrected virtual detection signal Sp, turns off when the difference is less than the threshold value, and turns on when the difference is greater than the threshold value.

[0075] In the present embodiment, the virtual detection signal Sp is corrected in such a way that the detection signal Sr and the virtual detection signal Sp have substantially the same magnitude and characteristics without assuming a state where the virtual detection circuit 50 fails. Therefore, if the detection circuit 40 does not fail, it is estimated that the value of the detection signal Sr is substantially consistent with the value of the virtual detection signal Sp. That is, when the value of the detection signal Sr is inconsistent with the value of the corrected virtual detection signal Sp, the flag ef_val is set to on by the value determination unit 64, indicating that there may be a failure.

[0076] The fault determination unit 65 determines whether the detection circuit 40 has a fault based on the flag ef_del set by the change rate determination unit 61 and the flag ef_val set by the value determination unit 64. Specifically, when both the flag ef_del and the flag ef_val are on (1), the fault detection circuit 60 determines that the detection circuit 40 has a fault. When at least one of the flag ef_del and the flag ef_val is off (0), the fault detection circuit 60 determines that the detection circuit 40 is normal. In this way, in the present embodiment, when both the flag ef_del and the flag ef_val indicating the possibility of a fault indicate that a fault may exist, it is detected that a fault exists. As a result, compared with a configuration in which only one of them is used to detect a fault, the possibility of erroneous determination that a fault exists can be reduced.

[0077] Figure 7 is a diagram showing a configuration example of the value determination unit 64. Figure 7 In the illustrated configuration example, the value determination unit 64 includes a selector 64a, an adding unit 64b, 64f, an absolute value output unit (ABS) 64c, 64d, a multiplication unit 64e, and a comparison unit 64g. The selector 64a receives the detection signal Sr and the corrected virtual detection signal Sp as inputs, and performs a process of switching between a state of outputting the input signal and a state of not outputting the input signal. Specifically, when the signal clip_flg input from the clipping processing unit 55 is valid (high level in this embodiment), that is, when the input signal to the clipping processing unit 55 exceeds a specified value, the selector 64a is set to a state of not outputting the input signal to the selector 64a. In this case, the fault detection of the fault detection circuit 60 is not performed. As a result, the value determination in the value determination unit 64 is invalidated.

[0078] On the other hand, when the signal clip_flg input from the clip processing unit 55 is inactive (low level in this embodiment), that is, when the input signal to the clip processing unit 55 does not exceed the specified value, the selector 64a is set to a state of outputting the input signal to the selector 64a. As a result, the value determination in the value determination unit 64 is enabled.

[0079] The adding unit 64b adds the detection signal Sr output from the selector 64a to the signal obtained by multiplying the corrected virtual detection signal Sp by a negative sign. That is, the adding unit 64b calculates the difference between the value of the detection signal Sr and the value of the corrected virtual detection signal Sp. The addition result output by the adding unit 64b is input to the absolute value output unit 64c, which outputs the absolute value of the addition result. That is, an error signal error indicating the magnitude of the difference between the value of the detection signal Sr and the value of the corrected virtual detection signal Sp is output.

[0080] The corrected virtual detection signal Sp output from the selector 64a is also input to the absolute value output unit 64d. The absolute value output unit 64d outputs a signal indicating the absolute value, i.e., the magnitude, of the corrected virtual detection signal Sp. The signal is multiplied by the gain (Vth_gain) by the multiplication unit 64e, and the offset (Vth_offs) is added by the addition unit 64f. In addition, the gain (Vth_gain) and the offset (Vth_offs) are predetermined and stored in the register unit 80. The control unit 70 obtains the gain (Vth_gain) and the offset (Vth_offs), and adjusts the multiplication unit 62 and the addition unit 63 to obtain the obtained gain (Vth_gain) and the offset (Vth_offs).

[0081] The value output from the adding unit 64f becomes the threshold value Vth to be compared with the error signal error. The threshold value Vth is a value for determining that the error signal error is substantially 0, that is, there is no difference between the detection signal Sr and the corrected virtual detection signal Sp. Even if the detection signal Sr and the corrected virtual detection signal Sp are substantially the same value, the difference may not be strictly 0 due to errors in circuit elements, etc., so the threshold value Vth is set to a value in a range in which the difference can be regarded as 0.

[0082] Furthermore, the larger the magnitude of each signal, the wider the range in which the difference between the detection signal Sr and the corrected virtual detection signal Sp can be regarded as substantially 0. This is because the larger the magnitude of each signal, the greater the noise. Therefore, in this embodiment, the magnitude of the threshold value is configured to change according to the magnitude of the signal output from the sensor element, that is, the magnitude of the virtual detection signal Sp.

[0083] In this embodiment, the threshold Vth is determined by a linear equation with the virtual detection signal Sp as a variable. Specifically, the threshold Vth is obtained by (absolute value of the virtual detection signal Sp) × (Vth_gain) + (Vth_offs). According to this structure, the larger the size of the virtual detection signal Sp is, the larger the threshold value can be set by simple processing. In addition, this structure is an example, and the structure that determines the threshold Vth based on an equation other than a linear equation may also be used.

[0084] The comparison unit 64g compares the error signal error with the threshold value Vth. When the error signal error is greater than the threshold value Vth, it is considered that the value of the detection signal Sr is inconsistent with the value of the corrected virtual detection signal Sp, and the flag ef_val is set to on. When it is not determined that the error signal error is greater than the threshold value Vth, the comparison unit 64g sets the flag ef_val to off. The flag set by the comparison unit 64g is input to the fault determination unit 65.

[0085] Figure 8is a diagram showing a configuration example of the change rate determination unit 61. Figure 8 In the illustrated configuration example, the change rate determination unit 61 includes differentiators 61a, 61b, a sign comparison unit 61c, and a change determination unit 61d. The differentiator 61a includes an adder 61a1 and a delay unit 61a2. The detection signal Sr is input to the differentiator 61a. In the differentiator 61a, the detection signal Sr and a signal obtained by adding a negative sign to a signal obtained by delaying the output of the adder 61a1 by the delay unit 61a2 are input to the adder 61a1. As a result, a signal obtained by time-differentiating the detection signal Sr, that is, a signal del1 indicating the change rate of the detection signal Sr is output.

[0086] The differentiator 61b includes an adder 61b1 and a delay unit 61b2. The configuration is the same as that of the differentiator 61a. The differentiator 61b receives the virtual detection signal Sp as an input and outputs a signal del2 which is a signal obtained by time-differentiating the virtual detection signal Sp, that is, indicating the rate of change of the virtual detection signal Sp.

[0087] The signals del1 and del2 are input to the sign comparison unit 61c. The sign comparison unit 61c compares the signs of the signal del1 and the signal del2. That is, the sign comparison unit 61c determines whether the signs of the signals del1 and del2 are positive or negative, and determines whether they are consistent. When the signs of the signal del1 and the signal del2 are inconsistent, the sign comparison unit 61c sets the flag ef_del to on. When the signs of the signals del1 and del2 are consistent, the sign comparison unit 61c sets the flag ef_del to off. The flag set by the sign comparison unit 61c is input to the fault determination unit 65.

[0088] When the signs of the signal del1 and the signal del2 are inconsistent, the change trends of the detection signal Sr and the corrected virtual detection signal Sp are opposite, so it can be considered that the detection signal Sr and the corrected virtual detection signal Sp have different characteristics. Therefore, in this embodiment, when the signs of the signal del1 and the signal del2 are inconsistent, it is considered that there may be a fault, and the flag ef_val is set to on.

[0089] Figure 6 The fault determination unit 65 shown in the figure determines that a fault occurs when both the flag ef_del set based on the difference in value and the flag ef_val set based on the rate of change are on (1). On the other hand, the fault determination unit 65 determines that the fault occurs when at least one of the flag ef_del and the flag ef_val is off (0). That is, when the difference between the value of the detection signal Sr and the value of the corrected virtual detection signal Sp is greater than the threshold value and the sign of the change of the detection signal Sr is different from the sign of the change of the corrected virtual detection signal Sp, a fault is determined.

[0090] When the difference between the value of the detection signal Sr and the value of the corrected virtual detection signal Sp is greater than a threshold value, the value of the detection signal Sr is substantially different from the value of the corrected virtual detection signal Sp, and therefore a fault may exist. Furthermore, when the sign of the change in the detection signal Sr is different from the sign of the change in the corrected virtual detection signal Sp, the change characteristic of the detection signal Sr is different from the change characteristic of the corrected virtual detection signal Sp, and therefore a fault may exist. In this embodiment, when both conditions for determining that a fault may exist are satisfied, it is determined that a fault exists. As a result, compared with a structure that uses only one condition to determine that a fault exists, the possibility of erroneously determining that a fault exists can be reduced.

[0091] In addition, in this embodiment, the sign of the signal change is not considered when the accuracy of the determination based on the sign of the signal change is relatively low and the accuracy of the determination based on the difference in value is relatively high. Fig. 9 The following is an example of a sine wave shape as shown in FIG. In such a signal, the sign of the signal changes like +, 0, and - near the maximum amplitude. Fig. 9 exemplified are times T1, T2, and T3 where the signs are +, 0, and -.

[0092] On the other hand, if the phase changes by 90° from near the maximum amplitude to near the zero-crossing point of the amplitude, the signal decreases monotonically and the sign does not change temporarily. Fig. 9 In the figure, the time T4, T5, and T6 near the zero crossing point are shown, and the sign is -. During the period from T1 to T3 near the maximum value of the amplitude, the change Δ1 of the signal value is small, but during the period from T4 to T6 near the zero crossing point of the amplitude, the change Δ2 of the signal value is relatively large. In this way, near the maximum value of the amplitude, the sign of the change of the signal changes greatly due to a small change in the signal, but in a phase domain different from the phase near the maximum value of the amplitude, even if the signal changes slightly, the sign of the change of the signal is difficult to change.

[0093] Therefore, near the maximum value of the amplitude, the fault detection accuracy based on the sign of the signal change becomes relatively low. In particular, the higher the frequency of the signal, the easier it is for the fault detection accuracy to decrease. On the other hand, when both the detection signal Sr and the corrected virtual detection signal Sp are near the maximum value of the amplitude, if the signal is normal, the difference in the signal value is small, and the possibility of the difference exceeding the threshold is low. Therefore, near the maximum value of the amplitude, even if the sign of the signal change is not used but the difference in value is used to determine whether a fault has occurred, the fault detection accuracy is unlikely to decrease. Such a situation is not limited to sine waves, and is the same in any signal.

[0094] Therefore, in the change rate determination unit 61, the signal del2 is input to the change determination unit 61d. The change determination unit 61d determines whether the change of the signal del2 is substantially 0. In the present embodiment, whether the change of the signal del2 is substantially 0 is determined based on the second threshold del_Vth. That is, the second threshold del_Vth represents the size at which the change of the signal del2 is regarded as 0, and is preset. In the present embodiment, the second threshold del_Vth is a predetermined fixed value, but it can also be variable according to the size of the signal del2, etc.

[0095] Moreover, when the magnitude of the change in the signal del2 is less than the second threshold del_Vth, the change in the signal del2 is deemed to be substantially 0. When the change in the signal del2 is substantially 0, the change determination unit 61d sets the flag ef_del to on. In this case, the determination in the sign comparison unit 61c is not reflected in the flag. In the present embodiment, the fault determination unit 65 is configured to determine that a fault exists when both the flag ef_del and the flag ef_val are on (1). Therefore, when the flag ef_del is set to on, regardless of the determination in the sign comparison unit 61c, it becomes a state to determine whether a fault has occurred based on whether the flag ef_val is on. According to the above structure, when the magnitude of the change in the corrected virtual detection signal Sp is less than the second threshold del_Vth, regardless of the change in the detection signal Sr and the change in the virtual detection signal Sp, fault detection is performed based on the comparison result of the value of the detection signal Sr and the value of the virtual detection signal Sp. According to the above structure, under the condition that the fault detection accuracy may be reduced, the determination based on the sign of the change in the signal is not performed. Therefore, it is possible to prevent the fault detection accuracy from being reduced.

[0096] 2. Other implementation methods, etc.

[0097] The above-mentioned embodiment is an example for implementing the present invention, and various embodiments can be adopted in addition. For example, in the above-mentioned embodiment, when the input signal to the limiting processing unit 55 exceeds the specified value, it is set to a state where the input signal to the selector 64a is not output from the selector 64a, so that the fault detection is invalidated. However, when the input signal to the limiting processing unit 55 exceeds the specified value, the input signal to the selector 64a can also be output from the selector 64a. In this case, although the detection signal Sr and the virtual detection signal Sp generated based on the limited signal are output from the selector 64a, these values ​​become fixed values ​​by limiting. Therefore, if these fixed values ​​are set to the same value as each other, the change of the virtual detection signal Sp is 0, and the value of the detection signal Sr is no different from the value of the virtual detection signal Sp, which becomes normal. Therefore, it becomes a state where no fault is detected, that is, the fault detection is invalid.

[0098] Furthermore, when the value determination is invalidated by the selector 64a, the configuration may be such that the data immediately after the switching by the selector 64a is not used for the value determination.

[0099] The detection circuit is a circuit that includes a first A / D conversion circuit that performs A / D conversion on a signal output from a sensor element and outputs a first digital signal, and generates a detection signal based on the first digital signal. That is, the detection circuit only needs to be able to perform analog / digital conversion on the detection result of the sensor element and generate a digital detection signal. Such a structure is not limited to the above-mentioned embodiment, and various alternative means can be used, and various functions can be omitted or added. For example, the number of bits of the first A / D conversion circuit is not limited to the above-mentioned structure, and the order of the circuit used for detection and the PGA can also be reversed. In addition, a downsampling filter can also be applied to the output of the first A / D conversion circuit, and gain adjustment and offset adjustment can also be implemented. Furthermore, various processing, such as gain adjustment and offset adjustment, can also be performed on the signal before it is input to the first A / D conversion circuit.

[0100] The sensor element can detect various detection objects such as physical quantities. For physical purposes, it is not limited to the angular velocity mentioned above. For example, acceleration, angular acceleration, speed, distance, temperature, pressure, sound pressure, magnetic quantity, etc. can also be used as detection objects. Of course, more than two of these physical quantities can also be detection objects. In addition, the structure of the detection circuit 40 and the virtual detection circuit 50 can also be changed according to the physical quantity of the detection object. For example, in the case of using a sensor element that outputs a signal that does not require differential amplification, a structure that does not include a differential amplifier circuit can also be used. In addition, the "signal output from the sensor element" can also include a signal after various processing has been performed on the output signal of the sensor element.

[0101] The detection signal may be generated based on the first digital signal as long as it is a signal representing the detection object of the sensor element. That is, the first digital signal is a signal representing the result obtained by the sensor element, and the detection signal may be a signal representing the detection result of the sensor element in a form used in other devices. The first digital signal and the detection signal may also be the same signal.

[0102] As long as the virtual detection circuit includes a second A / D conversion circuit that performs A / D conversion on the signal output from the sensor element and outputs a second digital signal, it can generate a virtual detection signal based on the second digital signal. That is, the virtual detection circuit can generate a digital virtual detection signal by performing analog / digital conversion on the detection result of the sensor element. Such a structure is not limited to the above-mentioned embodiment, and various alternative means can be used, and various functions can be omitted or added. For example, the number of bits of the second A / D conversion circuit is not limited to the above-mentioned structure, and the order of the circuit used for detection and the PGA can also be reversed. In addition, a downsampling filter can also be applied to the output of the second A / D conversion circuit, and gain adjustment and offset adjustment can also be implemented. Furthermore, various processing, such as gain adjustment and offset adjustment, can also be performed on the signal before it is input to the second A / D conversion circuit.

[0103] The virtual detection signal is a signal representing the detection object of the sensor element, and is a signal generated based on the second digital signal and virtually reproduces the detection signal. Since the virtual detection signal is a signal that virtually reproduces the detection signal, the virtual detection signal may not be used for the sensor element to detect physical quantities, etc. In addition, the circuit used to virtually reproduce the detection signal to generate the virtual detection signal may be the same as the detection circuit, or may be a circuit that is at least partially consistent, or may be a circuit with the same function but different specifications. Here, the same function of the circuit refers to a circuit with the same transfer function but different coefficients and constants. In any case, the virtual detection circuit is designed to reproduce the behavior of the detection signal through the virtual detection signal, so that a difference is generated between the virtual detection signal and the detection signal when a fault occurs in the detection circuit. The second digital signal and the virtual detection signal may be the same signal.

[0104] As long as the fault detection circuit can detect the fault of the detection circuit based on the comparison result of comparing the value of the detection signal with the value of the virtual detection signal. That is, as long as the fault detection circuit can compare the value of the detection signal generated by the detection circuit with the value of the virtual detection signal generated by the virtual detection circuit that imitates the detection circuit, it can determine whether the detection circuit is normal based on the difference. The difference between the value of the detection signal and the value of the virtual detection signal can be evaluated by various methods. For example, fault detection is performed based on the difference and change between the value of the above-mentioned detection signal and the value of the virtual detection signal, but fault detection can also be performed based on either the difference and the change. In addition, other factors can also be added to the evaluation factors of the difference. In addition, in order to determine the value of the detection signal and the value of the virtual detection signal, various processing other than limiting can also be performed.

[0105] The above-mentioned embodiment is an example and is not limited thereto. The present invention includes a structure substantially the same as the structure described in the embodiment (for example, a structure with the same function, method and result, or a structure with the same purpose and effect). In addition, the present invention includes a structure that replaces a non-essential part of the structure described in the embodiment. In addition, the present invention includes a structure that has the same effect as the structure described in the embodiment or a structure that can achieve the same purpose. In addition, the present invention includes a structure to which a known technology is added to the structure described in the embodiment.

Claims

1. A circuit device comprising: a detection circuit including a first A / D conversion circuit that performs A / D conversion on a signal output from the sensor element and outputs a first digital signal, and generates a detection signal based on the first digital signal; a dummy detection circuit including a second A / D conversion circuit that performs A / D conversion on a signal output from the sensor element and outputs a second digital signal, and generates a dummy detection signal based on the second digital signal; and A fault detection circuit detects a fault of the detection circuit based on a comparison result obtained by comparing the value of the detection signal with the value of the dummy detection signal.

2. The circuit arrangement according to claim 1, wherein: The fault detection circuit detects the fault based on whether the difference between the value of the detection signal and the value of the dummy detection signal is less than a threshold value. The threshold value varies according to a signal output from the sensor element.

3. The circuit arrangement according to claim 2, wherein: The threshold is determined by a linear equation with the virtual detection signal as a variable.

4. The circuit arrangement according to claim 1, wherein: The circuit device further includes a drive circuit that generates a drive signal for driving the sensor element. The detection circuit includes: a first synchronous detection circuit that performs synchronous detection on a signal output from the sensor element using a synchronous detection signal based on the drive signal; and a first low-pass filter that smoothes the signal output from the first synchronous detection circuit. The first A / D conversion circuit performs A / D conversion on the signal output from the first low-pass filter. The virtual detection circuit includes: a second synchronous detection circuit that performs synchronous detection on a signal output from the sensor element using the synchronous detection signal; and a second low-pass filter that smoothes the signal output from the second synchronous detection circuit. The second A / D conversion circuit performs A / D conversion on the signal output from the second low-pass filter.

5. The circuit arrangement according to claim 1, wherein: The resolution of the second A / D conversion circuit is lower than the resolution of the first A / D conversion circuit.

6. The circuit arrangement according to claim 1, wherein: The detection circuit performs temperature compensation processing on the detection signal based on the temperature detection signal, The second A / D conversion circuit performs A / D conversion for generating the dummy detection signal and A / D conversion for generating the temperature detection signal in a time-division manner.

7. The circuit arrangement according to claim 1, wherein: The input range of the second A / D conversion circuit is smaller than the input range of the first A / D conversion circuit. When the magnitude of the output signal from the second A / D conversion circuit exceeds a predetermined value, the detection signal and the dummy detection signal are set to fixed values.

8. The circuit arrangement according to claim 1, wherein: The fault detection circuit detects a fault based on the comparison result, the change of the detection signal, and the change of the virtual detection signal.

9. The circuit arrangement according to claim 8, wherein: The fault detection circuit determines that a fault has occurred when the comparison result indicates that the difference between the value of the detection signal and the value of the virtual detection signal is greater than a threshold and the sign of the change in the detection signal is different from the sign of the change in the virtual detection signal. When the change in the virtual detection signal is below the second threshold, the fault is detected based on the comparison result regardless of the change in the detection signal and the change in the virtual detection signal.

10. A physical quantity sensor comprising: Sensor elements; a detection circuit including a first A / D conversion circuit that performs A / D conversion on a signal output from the sensor element to output a first digital signal, and generates a detection signal based on the first digital signal; a dummy detection circuit including a second A / D conversion circuit that performs A / D conversion on a signal output from the sensor element and outputs a second digital signal, and generates a dummy detection signal based on the second digital signal; and A fault detection circuit detects a fault of the detection circuit based on a comparison result obtained by comparing the value of the detection signal with the value of the dummy detection signal.

11. The physical quantity sensor according to claim 10, wherein: The physical quantity sensor further includes a drive circuit that drives the sensor element. The signal output from the sensor element is a signal corresponding to the angular velocity detected by the sensor element.

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