Phase estimation method, signal processing channel and storage medium

Abstract

A phase estimation method, a signal processing channel and a storage medium are applied to the technical field of signal processing, and the phase estimation method comprises the following steps: obtaining an original input signal and an initial phase value interval; calculating a target Fibonacci sequence; determining an initial left test phase value and an initial right test phase value based on the target Fibonacci sequence, and calculating an amplitude estimation value; performing test phase value iteration based on the target Fibonacci sequence; if the length of the target Fibonacci sequence does not meet the preset length, subtracting 1 from the length and adding 1 to the number of iterations, and continuing to test the phase value iteration; if yes, the phase corresponding to the minimum amplitude estimation value is obtained based on the current iteration left test phase value and the iteration right test phase value. The phase estimation is performed by analyzing the amplitude estimation value of the signal to be tested, and then the phase search is performed based on the target Fibonacci sequence, so that the phase corresponding to the minimum amplitude estimation value can be obtained, and the phase estimation process is simplified.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a phase estimation method, a signal processing channel and a storage medium. Background Art

[0002] As an important device for converting digital signals into analog signals, the Digital-to-Analog Converter (DAC) is widely used in all walks of life. However, due to the influence of nonlinear factors such as mismatch of internal components of the DAC, the output of the DAC always contains other signals besides the main signal of the input signal, which in turn affects the spurious free dynamic range (SFDR) of the DAC. Among them, the harmonics and spurs corresponding to the main signal in the output signal of the DAC have a greater impact on SFDR.

[0003] In the current technical solution, other analytical instruments are mainly used to analyze the analog signal output by DAC to directly analyze the harmonic phase of harmonics or the spurious phase of spurious signals. However, this requires high accuracy of the analytical instrument, and the cost of high-precision analytical instruments is also relatively high. In addition, the direct analysis process is complicated and not suitable for large-scale applications. Therefore, a new technical solution is needed to obtain the phase of harmonics or spurious signals generated by DAC. Summary of the invention

[0004] The main technical problem solved by the present application is how to simplify the acquisition of the phase of harmonics or spurious generated by DAC.

[0005] According to the first aspect, an embodiment provides a phase estimation method, including:

[0006] Get the original input signal and the initial phase value interval [an^0, bn^0]; where an^0 is the initial left phase value and bn^0 is the initial right phase value;

[0007] Determine a target error value, and calculate a target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0]; wherein the length of the target Fibonacci sequence F(D) is D;

[0008] Determine an initial left test phase value xn^0 and an initial right test phase value yn^0 based on the sequence value in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], and perform amplitude estimation calculations on the initial left test phase value xn^0 and the initial right test phase value yn^0, respectively, to obtain amplitude estimation values ​​of corresponding test phase values, respectively;

[0009] Determine whether the length D of the target Fibonacci sequence F(D) meets a preset length;

[0010] If not satisfied, then based on the sequence value in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], as well as the initial left test phase value xn^0 and the initial right test phase value yn^0 and their corresponding amplitude estimation values, test phase value iteration is performed to obtain the iterative left test phase value xn^K and the iterative right test phase value yn^K, and based on the amplitude estimation value calculation, the amplitude estimation values ​​corresponding to the current iterative left test phase value xn^K and the iterative right test phase value yn^K are respectively obtained, wherein K is the number of iterations and its initial value is 1, and xn^K and yn^K are the iterative left test phase value and the iterative right test phase value corresponding to the Kth iteration, respectively; the length D of the target Fibonacci sequence F(D) is subtracted by 1 and the number of iterations K is increased by 1, and it is continued to be judged whether the preset length is satisfied;

[0011] If satisfied, the iteration of the test phase value is terminated, and the phase corresponding to the minimum amplitude estimation value is obtained based on the current iterative left test phase value xn^K and iterative right test phase value yn^K.

[0012] In some embodiments, the amplitude estimation value calculation includes: generating a cancellation signal based on the harmonic frequencies and harmonic amplitude values ​​of the harmonics of the original input signal or based on the spurious frequencies and spurious amplitude values ​​of the spurious of the original input signal, and the corresponding test phase value; superimposing the cancellation signal and the original input signal to obtain a digital signal to be tested; inputting the digital signal to be tested into a DAC for digital-to-analog conversion to obtain an analog signal to be tested, and performing spectrum analysis on the analog signal to be tested to obtain an amplitude estimation value of the corresponding test phase value.

[0013] In some embodiments, the calculating the target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0] comprises:

[0014] The target value of the target Fibonacci sequence F(D) is calculated based on the following formula:

[0015] δ=(bn^0-an^0) / ε;

[0016] Wherein, δ is the target value, ε is the target error value;

[0017] When the D-th sequence value in the Fibonacci sequence is greater than or equal to the target value, the acquisition length of the Fibonacci sequence is determined to be D to obtain the target Fibonacci sequence F(D).

[0018] In some embodiments, determining the initial left test phase value xn^0 and the initial right test phase value yn^0 based on the sequence value in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0] comprises:

[0019] The initial left test phase value xn^0 is calculated by the following formula:

[0020] xn^0=an^0+f(D-2) / f(D)*(bn^0-an^0);

[0021] Wherein, f(D-2) is the D-2th sequence value in the target Fibonacci sequence F(D), and F(D) is the Dth sequence value in the target Fibonacci sequence F(D);

[0022] The initial right test phase value yn^0 is calculated by the following formula:

[0023] yn^0=an^0+f(D-1) / f(D)*(bn^0-an^0);

[0024] Wherein, f(D-1) is the D-1th sequence value in the target Fibonacci sequence F(D).

[0025] In some embodiments, the test phase value iteration includes:

[0026] If the first iteration of the test phase value is performed, it is determined whether the amplitude estimation value corresponding to the initial left test phase value xn^0 is greater than the amplitude estimation value corresponding to the initial right test phase value yn^0;

[0027] If it is greater than, the first iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0] to obtain the iterative right-end phase value bn^1 and the iterative left-end phase value an^1; wherein bn^1=bn^0, an^1=xn^0; the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1 to obtain xn^1=yn^0, and the preset unimodal function search method calculates the iterative right test phase value yn^1 by the following formula:

[0028] yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1);

[0029] If it is less than, the second iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0] to obtain the iterative right phase value bn^1 and the iterative left phase value an^1; wherein an^1=an^0, bn^1=yn^0; the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1 to obtain yn^1=xn^0, and the preset unimodal function search method calculates the iterative left test phase value xn^1 by the following formula:

[0030] xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1);

[0031] If the test phase value iteration is performed for the K+1th time, it is determined whether the amplitude estimation value corresponding to the iterative left test phase value xn^K is greater than the amplitude estimation value corresponding to the iterative right test phase value yn^K;

[0032] If it is greater than, the first iteration of the phase value interval is performed on the initial phase value interval [an^K, bn^K] to obtain the iterative right-end phase value bn^(K+1) and the iterative left-end phase value an^(K+1); wherein bn^(K+1)=bn^K, an^(K+1)=xn^K; the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1) to obtain xn^(K+1)=yn^K, and the preset unimodal function search method calculates the iterative right test phase value yn^K by the following formula:

[0033] yn^(K+1)=an^(K+1)+f(D-1) / f(D)*(bn^(K+1)-an^(K+1));

[0034] If it is less than, the iterative phase value interval [an^K, bn^K] is subjected to a second iteration of the phase value interval to obtain an iterative right phase value bn^(K+1) and an iterative left phase value an^(K+1); wherein an^(K+1)=an^K, bn^(K+1)=yn^K; the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1) to obtain yn^(K+1)=xn^K, and the preset unimodal function search method calculates the iterative left test phase value xn^(K+1) by the following formula:

[0035] xn^(K+1)=an^(K+1)+f(D-2) / f(D)*(bn^(K+1)-an^(K+1)).

[0036] In some embodiments, the test phase value iteration includes:

[0037] If the first iteration of the test phase value is performed, it is determined whether the amplitude estimation value corresponding to the initial left test phase value xn^0 is greater than the amplitude estimation value corresponding to the initial right test phase value yn^0;

[0038] If it is greater than, the second iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0] to obtain the iterative right phase value bn^1 and the iterative left phase value an^1; wherein an^1=an^0, bn^1=yn^0; the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1 to obtain yn^1=xn^0, and the preset unimodal function search method calculates the iterative left test phase value xn^1 by the following formula:

[0039] xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1);

[0040] If it is less than, the first iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0] to obtain the iterative right-end phase value bn^1 and the iterative left-end phase value an^1; wherein bn^1=bn^0, an^1=xn^0; the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1 to obtain xn^1=yn^0, and the preset unimodal function search method calculates the iterative right test phase value yn^1 by the following formula:

[0041] yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1);

[0042] If the test phase value iteration is performed for the K+1th time, it is determined whether the amplitude estimation value corresponding to the iterative left test phase value xn^K is greater than the amplitude estimation value corresponding to the iterative right test phase value yn^K;

[0043] If it is greater than, the iterative phase value interval [an^K, bn^K] is subjected to a second iteration of the phase value interval to obtain an iterative right phase value bn^(K+1) and an iterative left phase value an^(K+1); wherein an^(K+1)=an^K, bn^(K+1)=yn^K; the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1) to obtain yn^(K+1)=xn^K, and the preset unimodal function search method calculates the iterative left test phase value xn^(K+1) by the following formula:

[0044] xn^(K+1)=an^(K+1)+f(D-2) / f(D)*(bn^(K+1)-an^(K+1));

[0045] If it is less than, the first iteration of the phase value interval is performed on the initial phase value interval [an^K, bn^K] to obtain the iterative right-end phase value bn^(K+1) and the iterative left-end phase value an^(K+1); wherein bn^(K+1)=bn^K, an^(K+1)=xn^K; the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1) to obtain xn^(K+1)=yn^K, and the preset unimodal function search method calculates the iterative right test phase value yn^K by the following formula:

[0046] yn^(K+1)=an^(K+1)+f(D-1) / f(D)*(bn^(K+1)-an^(K+1)).

[0047] In some embodiments, the calculating based on the amplitude estimation value to respectively obtain the amplitude estimation values ​​corresponding to the current iterative left test phase value xn^K and the iterative right test phase value yn^K includes:

[0048] If the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1, the amplitude estimation value corresponding to the initial right test phase value yn^0 is assigned to the amplitude estimation value corresponding to the iterative left test phase value xn^1, and the amplitude estimation value calculation is performed on the iterative right test phase value yn^1 to obtain the amplitude estimation value corresponding to the iterative right test phase value yn^1;

[0049] If the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1), then the amplitude estimation value corresponding to the iterative right test phase value yn^K is assigned to the amplitude estimation value corresponding to the iterative left test phase value xn^(K+1), and the amplitude estimation value calculation is performed on the iterative right test phase value yn^(K+1) to obtain the amplitude estimation value corresponding to the iterative right test phase value yn^(K+1);

[0050] If the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1, the amplitude estimation value corresponding to the initial left test phase value xn^0 is assigned to the amplitude estimation value corresponding to the iterative right test phase value yn^1, and the amplitude estimation value calculation is performed on the iterative left test phase value xn^1 to obtain the amplitude estimation value corresponding to the iterative left test phase value xn^1;

[0051] If the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1), the amplitude estimation value corresponding to the iterative left test phase value xn^K is assigned to the amplitude estimation value corresponding to the iterative right test phase value yn^(K+1), and the amplitude estimation value calculation is performed on the iterative left test phase value xn^(K+1) to obtain the amplitude estimation value corresponding to the iterative left test phase value xn^(K+1).

[0052] In some embodiments, obtaining the phase corresponding to the minimum amplitude estimation value based on the current iterative left test phase value xn^K and the iterative right test phase value yn^K includes:

[0053] The average phase value of the current iterative left test phase value xn^K and the iterative right test phase value yn^K is obtained as the phase corresponding to the minimum amplitude estimation value.

[0054] In some embodiments, obtaining the phase corresponding to the minimum amplitude estimation value based on the current iterative left test phase value xn^K and the iterative right test phase value yn^K includes:

[0055] The average phase value of the current iterative left test phase value xn^K and the iterative right test phase value yn^K is obtained, and the average phase value is shifted by a preset phase to obtain the phase corresponding to the amplitude estimation minimum value.

[0056] In some embodiments, if the average phase value is between [0, π), the preset phase of the translation is π;

[0057] If the average phase value is between [π, 2π), the preset phase of the translation is -π;

[0058] The phase after translation is the sum of the average phase value and the preset phase of translation.

[0059] In some embodiments, the initial phase value interval [an^0, bn^0] is generated by:

[0060] The phase value 0 is configured as the initial left phase value an^0, and the phase value 2π is configured as the initial right phase value bn^0, so as to obtain the initial phase value interval [an^0, bn^0];

[0061] or,

[0062] Obtain an estimated phase empirical value, and generate the initial phase value interval [an^0, bn^0] according to the estimated phase empirical value.

[0063] In some embodiments, obtaining the estimated phase empirical value includes:

[0064] Obtaining a phase estimation value corresponding to a harmonic frequency or a spurious frequency of a known input signal after the known input signal is input into the DAC;

[0065] Based on the frequency relationship between the known input signal and the original input signal, the estimated phase empirical value corresponding to the harmonic of the original input signal is obtained from the phase estimation value; or,

[0066] Based on the frequency relationship between the known input signal and the original input signal, and the frequency relationship between the spurious frequency of the known input signal and the spurious frequency of the original input signal, the estimated phase empirical value corresponding to the spur of the original input signal is obtained from the phase estimation value.

[0067] In some embodiments, the performing spectrum analysis on the simulated signal to be tested includes:

[0068] Inputting the simulated signal to be tested into a spectrum analyzer for spectrum analysis;

[0069] or,

[0070] The simulated signal to be tested is input into an analog-to-digital converter for analog-to-digital conversion and then subjected to Fourier transform processing for spectrum analysis.

[0071] In some embodiments, for harmonics, the corresponding frequency of the cancellation signal is the harmonic frequency of the harmonics of the original input signal; for spurious signals, the corresponding frequency of the cancellation signal is the spurious frequency of the spurious signals of the original input signal.

[0072] According to a second aspect, an embodiment provides a signal processing channel for implementing the phase estimation method as described in the first aspect, wherein the signal processing channel comprises at least two DDS phase accumulators, and the signal processing circuits where each of the DDS phase accumulators is located are connected in parallel, and the number of parallel connections is defined as an integer H greater than 1;

[0073] One of the signal processing circuits including a DDS phase accumulator generates the original input signal after phase-amplitude conversion processing and attenuation processing, and the remaining signal processing circuits including a DDS phase accumulator generate cancellation signals corresponding to harmonics or cancellation signals corresponding to spurious signals based on corresponding test phase values ​​through phase-amplitude conversion processing.

[0074] In some embodiments, the signal processing channel is used to process multiple harmonics, or multiple spurious signals, or at least one harmonic and at least one spurious signal. If the value of H is ≥3, the remaining other signal processing circuits including the DDS phase accumulator are used to generate cancellation signals corresponding to multiple harmonics, or cancellation signals corresponding to multiple spurious signals, or cancellation signals corresponding to at least one harmonic and at least one spurious signal respectively.

[0075] The maximum number of times the remaining signal processing circuits including the DDS phase accumulator are called is equal to the sum of the number of harmonics and the number of spurious signals.

[0076] In some embodiments, the signal processing channel also includes a phase counter and a memory, wherein the phase counter is used to accumulate and count the test phase value corresponding to the cancellation signal when the test phase value is iterated, and the memory is used to store the corresponding test phase values ​​and their corresponding amplitude estimation values.

[0077] In some embodiments, obtaining a total number L of harmonics and spurious signals to be processed;

[0078] Divide the total number L by H-1 and round up to get the number of times the signal processing channel is called;

[0079] According to the number of times the signal processing channel is called, the phase counter and the memory are reset to clear the amplitude estimation value and the corresponding test phase value stored in history.

[0080] According to the third aspect, an embodiment provides a computer-readable storage medium, on which a program is stored, and the program can be executed by a processor to implement the method as described in the first aspect.

[0081] According to the phase estimation method, signal processing channel and storage medium of the above embodiment, after the original input signal and the cancellation signal are superimposed, if the phase of the harmonic frequency or spurious frequency corresponding to the original input signal is in phase with the phase of the harmonic frequency or spurious frequency corresponding to the cancellation signal, the amplitude estimation value of the harmonic frequency or spurious frequency corresponding to the phase reaches the maximum value, otherwise if the phase is inverted, the amplitude estimation value of the harmonic frequency or spurious frequency corresponding to the phase reaches the minimum value, and the phase and amplitude estimation value of the cancellation signal are a one-dimensional single-peak function. Therefore, the target error value is first determined, and the target Fibonacci sequence is calculated based on the target error value and the initial phase value interval, the phase search is performed based on the target Fibonacci sequence and the initial phase value interval, and the test phase value iteration is performed based on the initial left test phase value and the initial right test phase value, and the corresponding cancellation signal is generated based on the searched test phase value, and then the cancellation signal and the original input signal are superimposed, and the DAC performs digital-to-analog conversion, and finally the analog signal output by the digital-to-analog converter is analyzed to obtain the amplitude estimation value corresponding to the harmonic frequency or spurious frequency. Finally, when the iteration of the test phase value ends, the phase corresponding to the minimum amplitude estimation value is obtained based on the current iteration left test phase value and the iteration right test phase value. Since the phase estimation process is simplified, the phase corresponding to the minimum amplitude estimation value can be obtained by superimposing the cancellation signal and the original input signal, analyzing the amplitude estimation value corresponding to the harmonic frequency or spurious frequency in the simulated signal to be tested, and then performing phase search based on the target Fibonacci sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] Figure 1 A schematic diagram of the structure of a signal processing channel according to an embodiment;

[0083] Figure 2 A schematic diagram of the structure of a signal processing channel in another embodiment;

[0084] Figure 3 A phase estimation flow chart of a signal processing channel of an embodiment;

[0085] Figure 4 A record diagram of test phase value iterations for one embodiment;

[0086] Figure 5 A record diagram of test phase value iterations of another embodiment;

[0087] Figure 6 A flow chart of a phase estimation method according to an embodiment. DETAILED DESCRIPTION

[0088] The present application is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments use associated similar element numbers. In the following embodiments, many detailed descriptions are intended to enable the present application to be better understood. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and the related operations can be fully understood according to the description in the specification and the general technical knowledge in the art.

[0089] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0090] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0091] In some embodiments of the present application, when two signals of the same frequency are superimposed, if the two signals are in phase, the superposition amplitude will increase, if the two signals are in anti-phase, the superposition amplitude will cancel, and the superposition amplitude is a one-dimensional single-peak function, that is, the amplitude estimation value of the superposition of the cancellation signal and the original input signal is a one-dimensional single-peak function. Therefore, a phase search is performed based on the target Fibonacci sequence and the initial phase value interval, and a test phase value iteration is performed based on the initial left test phase value and the initial right test phase value. When the test phase value iteration ends, a phase estimation value is obtained based on the current iterative left test phase value and the iterative right test phase value. Since the phase estimation process is mainly performed by superimposing the cancellation signal and the original input signal, and analyzing the amplitude estimation value corresponding to the harmonic frequency or the spurious frequency in the simulated signal to be tested, and then performing a phase search based on the target Fibonacci sequence, the phase corresponding to the minimum amplitude estimation value can be obtained, so that the phase estimation process is simplified.

[0092] Some embodiments provide a signal processing channel, please refer to Figure 1The signal processing channel includes at least two DDS phase accumulators 10, and the signal processing circuits where each DDS phase accumulator 10 is located are connected in parallel, and the number of parallel connections is defined as an integer H greater than 1.

[0093] The DDS phase accumulator 10 is used to complete the accumulation of phase values ​​according to the received frequency control word to obtain a phase accumulation value. Figure 2 In some embodiments, the components within the signal processing circuit where each DDS phase accumulator 10 is located are connected in series. For example, the DDS phase accumulator 10 includes a phase adder and a phase register connected in series. The phase register is used to output the current accumulated phase to the phase adder. The phase adder adds the frequency control word and the accumulated phase output by the phase register, and sends the result of the addition to the phase register for the next phase accumulation. In some embodiments, the frequency control word can be generated based on a processor, wherein the processor can also be used to adjust the initial phase of the phase register. In some embodiments, the processor can be implemented based on a device with data processing capabilities such as a CPU, an FPGA, and a single-chip microcomputer. Among them, the frequency control word is determined by the frequency of the input signal, the clock frequency, and the total number of bits of the DDS phase accumulator 10.

[0094] In some embodiments, the signal processing circuit where each DDS phase accumulator 10 is located can be configured with a phase amplitude mapping module 20, and the phase amplitude mapping module 20 is used to obtain the corresponding signal amplitude according to the phase accumulation value output by the corresponding DDS phase accumulator 10, and output the corresponding digital waveform signal. In some embodiments, the phase amplitude mapping module 20 can obtain the signal amplitude corresponding to the phase accumulation value based on a phase lookup table, for example, the phase lookup table can be a sine lookup table. In some embodiments, the phase amplitude mapping module 20 can also calculate the signal amplitude corresponding to the phase accumulation value in real time based on algorithms such as coordinate rotation.

[0095] In some embodiments, the signal processing circuits where the DDS phase accumulators 10 are located may also share a phase-amplitude mapping module 20 , for example, the phase-amplitude mapping module 20 is multiplexed between the DDS phase accumulators 10 .

[0096] In some embodiments, the digital waveform signal output by the phase amplitude mapping module 20 can be converted from digital to analog by the digital-to-analog conversion unit 30 to output an analog waveform signal. In some embodiments, the digital-to-analog conversion unit 30 can realize the digital-to-analog conversion of the signal based on an analog-to-digital converter. In some embodiments, the digital-to-analog conversion unit 30 can also include a signal adder, which is used to superimpose multiple digital waveform signals and then output them to the analog-to-digital converter to realize the digital-to-analog conversion of the superimposed signal.

[0097] In the above embodiment, each signal processing circuit including a DDS phase accumulator 10 is used to generate a digital waveform signal. Therefore, each time the signal processing circuit is adjusted, a digital waveform signal can be generated to correspond to a harmonic or spurious cancellation signal, and each time the signal processing channel is adjusted, a plurality of digital waveform signals corresponding to the number of DDS phase accumulators 10 can be generated to correspond to multiple harmonics, or multiple spurious signals, or spurious and harmonic cancellation signals.

[0098] The above is some description of the signal processing channel, please refer to Figure 3 ,The following describes the process of phase estimation based on the signal processing channel in detail.

[0099] The original input signal is obtained, wherein one of the signal processing channels includes a signal processing circuit of a DDS phase accumulator 10, and generates the original input signal after phase-amplitude conversion processing and attenuation processing.

[0100] In some embodiments, the signal processing circuit may further include an attenuator, so that attenuation processing of the signal is performed based on the attenuator.

[0101] In some embodiments, the harmonics of the original input signal may include one harmonic or multiple harmonics, for example, the second harmonic or the third harmonic, or multiple harmonics such as the second harmonic and the third harmonic, so the cancellation signal may be a signal corresponding to the second harmonic or the third harmonic, or a signal corresponding to multiple harmonics such as the second harmonic and the third harmonic. In some embodiments, the spurious of the original input signal may include one spurious or multiple spurious, so the cancellation signal may be a signal corresponding to one spurious, or a signal corresponding to multiple spurious. In this embodiment, the harmonics and spurious of the original input signal refer to the harmonics and spurious generated after the original input signal is input into the DAC.

[0102] Get the initial phase value interval [an^0, bn^0]. Where an^0 is the initial left phase value, and bn^0 is the initial right phase value. Where n is a positive integer greater than or equal to 1, which corresponds to a spurious wave or a harmonic. For example, when n=1, it corresponds to the second harmonic, when n=2, it corresponds to the third harmonic, and when n=3, it corresponds to the spurious wave.

[0103] In some embodiments, the phase value 0 is configured as the initial left phase value an^0, and the phase value 2π is configured as the initial right phase value bn^0 to obtain the initial phase value interval [an^0, bn^0]. In this embodiment, the required phase value is searched based on the full range of the phase. After the cancellation signal and the original input signal are superimposed, there is a maximum value and a minimum value in the full range of the phase for the amplitude estimation value, so the phase value corresponding to the maximum value can be searched, and the phase value corresponding to the minimum value can also be searched.

[0104] In some embodiments, an estimated phase empirical value is obtained, and an initial phase value interval [an^0, bn^0] is generated based on the estimated phase empirical value. In some embodiments, the initial phase value interval [an^0, bn^0] can be generated based on a preset range before and after the estimated phase empirical value, for example, the estimated phase empirical value is used as the center position, and a phase value that is larger than the estimated phase empirical value by a preset phase value is used as the initial right-end phase value bn^0, and a phase value that is smaller than the estimated phase empirical value by a preset phase value is used as the initial left-end phase value an^0. In some embodiments, for each original input signal without an estimated phase empirical value, the full range of the phase can be shared as the initial phase value interval [an^0, bn^0], and for each original input signal with an estimated phase empirical value, the initial phase value interval [an^0, bn^0] generated based on the estimated phase empirical value is used.

[0105] In some embodiments, after the known input signal is input into the DAC, the phase estimation value corresponding to the harmonic frequency or spurious frequency of the known input signal is obtained, wherein, since there is a certain relationship between the frequency of the signal and the phase of the signal, the phase corresponding to the harmonic frequency or spurious frequency of the original input signal can be estimated based on the frequency of the known input signal and the phase estimation value corresponding to the harmonic frequency or spurious frequency of the known input signal. For example, if the frequency between the known input signal and the original input signal is different, based on the frequency relationship between the known input signal and the original input signal, the estimated phase empirical value corresponding to the harmonic of the original input signal is obtained from the phase estimation value corresponding to the harmonic, or based on the frequency relationship between the known input signal and the original input signal, and the frequency relationship between the spurious frequency of the spurious of the known input signal and the spurious frequency of the spurious of the original input signal, the estimated phase empirical value corresponding to the spurious of the original input signal is obtained from the phase estimation value corresponding to the spurious. For example, if the frequency between the known input signal and the original input signal is the same, the phase estimation value corresponding to the harmonic is used as the estimated phase empirical value corresponding to the harmonic of the original input signal. For example, if the spurious frequency of the spurious input signal is known to be the same as the spurious frequency of the original input signal, the phase estimation value corresponding to the spurious frequency is used as the estimated phase empirical value corresponding to the spurious of the original input signal.

[0106] In the above embodiment, when signals of the same frequency are input to the same digital-to-analog converter, the phases corresponding to the generated harmonics are substantially consistent. Therefore, for a known input signal for which phase estimation has been completed, subsequent processing can be performed based on the acquired estimated phase without the need for repeated acquisition. In addition, for an original input signal for which phase estimation has not been completed, the phase of the harmonic corresponding to the original input signal can be predicted based on the phase of the harmonic of the known input signal, and then the phase of the original input signal can be estimated based on the predicted phase, thereby further simplifying the acquisition complexity and improving the accuracy of the phase estimation.

[0107] In some embodiments, when generating an initial phase value interval [an^0, bn^0] according to the estimated phase empirical value, the estimated phase empirical value is used as the center to determine the initial phase value interval [an^0, bn^0], where an^0=bc, bn^0=b+c, ​​where b is the estimated phase empirical value and c is the preset phase value. In this embodiment, since the estimated phase empirical value has been obtained, the initial phase value interval [an^0, bn^0] can be determined within a smaller phase range, thereby reducing the amount of data calculation and improving the calculation accuracy.

[0108] The target error value is determined, and the target Fibonacci sequence F(D) is calculated based on the target error value and the initial phase value interval [an^0, bn^0].

[0109] In some embodiments, the target value of the target Fibonacci sequence F(D) is calculated based on the following formula:

[0110] δ=(bn^0-an^0) / ε;

[0111] Among them, δ is the target value, ε is the target error value;

[0112] In some embodiments, when the Dth sequence value in the Fibonacci sequence is greater than or equal to the above target value, the length of the Fibonacci sequence is determined to be D to obtain the target Fibonacci sequence F(D). In this embodiment, the Fibonacci sequence is a sequence of infinite length, so it is necessary to first determine the target value of the target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0], and then determine the length D of the target Fibonacci sequence F(D) based on the target value.

[0113] In some embodiments, the smaller the target error value is and the longer the length of the target Fibonacci sequence F(D) is, the higher the accuracy of the phase estimation result obtained in the end is. Therefore, the target error value can be determined according to actual conditions.

[0114] The initial left test phase value xn^0 and the initial right test phase value yn^0 are determined based on the sequence values ​​in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0].

[0115] In some embodiments, when determining the initial left test phase value xn^0 and the initial right test phase value yn^0 based on the sequence value in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], the initial left test phase value xn^0 is calculated by the following formula:

[0116] xn^0=an^0+f(D-2) / f(D)*(bn^0-an^0);

[0117] Wherein, f(D-2) is the D-2th sequence value in the target Fibonacci sequence F(D), and F(D) is the Dth sequence value in the target Fibonacci sequence F(D).

[0118] The initial right test phase value yn^0 is calculated by the following formula:

[0119] yn^0=an^0+f(D-1) / f(D)*(bn^0-an^0);

[0120] Wherein, f(D-1) is the D-1th sequence value in the target Fibonacci sequence F(D).

[0121] Amplitude estimation values ​​are calculated for the initial left test phase value xn^0 and the initial right test phase value yn^0 respectively.

[0122] In some embodiments, when calculating the amplitude estimation value, a cancellation signal is first generated based on the harmonic frequency and harmonic amplitude value of the harmonics of the original input signal or based on the spurious frequency and spurious amplitude value of the spurious of the original input signal, and the corresponding test phase value. For example, when calculating the amplitude estimation value of the initial right test phase value yn^0, the corresponding test phase value is the initial right test phase value yn^0.

[0123] In some embodiments, when generating a cancellation signal, the remaining signal processing circuits in the signal processing channel including the DDS phase accumulator 10 are subjected to phase-amplitude conversion processing based on the phase value in the corresponding phase table to be measured to generate a cancellation signal corresponding to the harmonic or a cancellation signal corresponding to the spurious.

[0124] In some embodiments, before generating the cancellation signal, the original input signal may be input into a digital-to-analog converter for digital-to-analog conversion to obtain an analog input signal corresponding to the output of the digital-to-analog converter, and then the analog input signal may be subjected to spectrum analysis to obtain an estimated amplitude value of the harmonics of the original input signal. Alternatively, the spurious frequency and spurious amplitude value of the spurious of the original input signal may be obtained, for example, based on the spurious frequency and spurious amplitude value of the spurious of the original input signal known by other measuring equipment.

[0125] In some embodiments, the analog input signal may be converted into a digital signal based on an analog-to-digital converter to obtain a corresponding digital signal, and then the digital signal may be transformed from the time domain to the frequency domain based on a processor or an external data processing device, such as performing a fast Fourier transform (FFT) process, and then analyzing the transformed frequency domain signal to obtain an amplitude estimate of the harmonic of the original input signal. Since the frequency of the FFT may have a deviation, the obtained amplitude estimate may be selected as the amplitude corresponding to the harmonic frequency of the harmonic, or may be selected as the maximum amplitude within a frequency range around the harmonic frequency.

[0126] In some embodiments, when generating a cancellation signal, for harmonics, the frequency of the corresponding cancellation signal is the harmonic frequency of the harmonic of the original input signal, and for spurious, the frequency of the corresponding cancellation signal is the spurious frequency of the spurious of the original input signal.

[0127] In some embodiments, when the original input signal is obtained by attenuation, the amplitude of the digital signal to be measured after the original input signal is superimposed with the cancellation signal can be made to meet the maximum input range of the digital-to-analog converter or be less than the maximum input range. In some embodiments, when the amplitude of the digital signal to be measured meets the maximum input range of the digital-to-analog converter, the digital-to-analog converter can be fully utilized to improve the subsequent data processing accuracy. In some embodiments, the amplitude of the original input signal attenuation can be controlled by a processor or by an external data processing device.

[0128] In some embodiments, the remaining other signal processing circuits including the DDS phase accumulator 10 may generate a cancellation signal corresponding to a harmonic or a cancellation signal corresponding to a spurious signal. In some embodiments, the remaining other signal processing circuits including the DDS phase accumulator 10 may generate cancellation signals corresponding to multiple harmonics, or cancellation signals corresponding to multiple spurious signals, or cancellation signals corresponding to at least one harmonic and at least one spurious signal. The cancellation signals may be generated separately based on multiple signal processing circuits including the DDS phase accumulator 10, or may be generated by multiplexing based on one signal processing circuit including the DDS phase accumulator 10.

[0129] For example, if the value of H is ≥3, the remaining other paths including the signal processing circuit of the DDS phase accumulator 10 are used to generate cancellation signals corresponding to multiple harmonics, or cancellation signals corresponding to multiple spurious signals, or cancellation signals corresponding to at least one harmonic and at least one spurious signal. The maximum number of times the remaining other paths including the signal processing circuit of the DDS phase accumulator 10 are called is equal to the sum of the number of harmonics and the number of spurious signals, wherein each time the signal processing circuit is called, a cancellation signal corresponding to a harmonic or a cancellation signal corresponding to a spurious signal is generated.

[0130] Then, the cancellation signal and the original input signal are superimposed to obtain a digital test signal, which is input into the DAC for digital-to-analog conversion to obtain an analog test signal, and the analog test signal is subjected to spectrum analysis to obtain an amplitude estimation value of the harmonic frequency or spurious frequency corresponding to the corresponding test phase value.

[0131] In some embodiments, the analog signal to be tested can also be converted into digital form based on an analog-to-digital converter to obtain a corresponding digital signal, and then the processor or external data processing device transforms the digital signal from the time domain to the frequency domain, such as performing a fast Fourier transform (FFT) process, and then analyzing the transformed frequency domain signal to obtain an amplitude estimation value corresponding to the harmonic frequency or spurious frequency in the analog signal to be tested. In some embodiments, the analog signal to be tested can also be directly input into a spectrum analyzer for spectrum analysis.

[0132] After the amplitude estimation value is calculated, it is determined whether the length D of the target Fibonacci sequence F(D) meets the preset length.

[0133] If the length D does not meet the preset length, the test phase value iteration is performed based on the sequence value and the initial phase value interval [an^0, bn^0] in the target Fibonacci sequence F(D), as well as the initial left test phase value xn^0 and the initial right test phase value yn^0 and their corresponding amplitude estimation values, so as to obtain the iterative left test phase value xn^K and the iterative right test phase value yn^K, where K is the number of iterations and its initial value is 1. In some embodiments, when the test phase value iteration is performed based on the sequence value and the initial phase value interval [an^0, bn^0] in the target Fibonacci sequence F(D), as well as the initial left test phase value xn^0 and the initial right test phase value yn^0 and their corresponding amplitude estimation values, if the first test phase value iteration is performed, the iteration process is:

[0134] First, determine whether the amplitude estimation value corresponding to the initial left test phase value xn^0 is greater than the amplitude estimation value corresponding to the initial right test phase value yn^0.

[0135] If the amplitude estimation value corresponding to the initial left test phase value xn^0 is greater than the amplitude estimation value corresponding to the initial right test phase value yn^0, the first iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0], that is, the phase value interval is reduced to the right end, at which time the right end phase value remains unchanged, and the left test phase value is assigned to the iterative left end phase value to obtain the iterative right end phase value bn^1 and the iterative left end phase value an^1. Among them, bn^1=bn^0, an^1=xn^0. Among them, when performing the first iteration of the phase value interval, the flag sign=0 can be set.

[0136] At the same time, the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1, so that xn^1=yn^0 is obtained, and the iterative right test phase value yn^1 is calculated by the following formula:

[0137] yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1).

[0138] If the amplitude estimate corresponding to the initial left test phase value xn^0 is smaller than the amplitude estimate corresponding to the initial right test phase value yn^0, the second iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0], that is, the phase value interval is reduced to the left end. At this time, the left end phase value remains unchanged, and the right test phase value is assigned to the iterative right end phase value to obtain the iterative right phase value bn^1 and the iterative left phase value an^1; wherein, an^1=an^0, bn^1=yn^0; wherein, when performing the second iteration of the phase value interval, the flag sign=1 can be set.

[0139] At the same time, the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1, and yn^1=xn^0 is obtained, and the iterative left test phase value xn^1 is calculated by the following formula:

[0140] xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1).

[0141] The above-mentioned test phase value iteration is to search for the phase corresponding to the minimum value of the amplitude estimation value. In some embodiments, the phase corresponding to the maximum value of the amplitude estimation value can also be searched based on the test phase value iteration. The process is symmetrical and opposite to the above process, which is briefly described below.

[0142] In some embodiments, it is first determined whether the amplitude estimation value corresponding to the initial left test phase value xn^0 is greater than the amplitude estimation value corresponding to the initial right test phase value yn^0.

[0143] If it is greater than, the above second iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0] to obtain the iterative right end phase value bn^1 and the iterative left end phase value an^1. At the same time, the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1, and the iterative left test phase value xn^1 is calculated. The specific process is not repeated here.

[0144] If it is less than, the phase value interval [an^0, bn^0] is subjected to the above-mentioned first iteration of the phase value interval to obtain the iterative right end phase value bn^1 and the iterative left end phase value an^1. At the same time, the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1, and the iterative right test phase value yn^1 is calculated. The specific process is not repeated here.

[0145] In the above embodiment, when the test phase value iteration is performed based on the target Fibonacci sequence F(D), since the length of the target Fibonacci sequence F(D) is determined, the number of test phase value iterations can be determined. And in each test phase value iteration, the initial right test phase value yn^0 can be assigned to the iterated left test phase value xn^1, or the initial left test phase value xn^0 can be assigned to the iterated right test phase value yn^1, which is equivalent to each test phase value iteration, only needing to additionally calculate a new phase value interval endpoint and a new test phase value, thereby reducing the amount of data calculation.

[0146] The above is a description of the first test phase value iteration. If the K+1th test phase value iteration is performed, the iteration process is:

[0147] First, determine whether the amplitude estimation value corresponding to the iterative left test phase value xn^K is greater than the amplitude estimation value corresponding to the iterative right test phase value yn^K. Where K is the number of iterations and its initial value is 1, and xn^K and yn^K are the iterative left test phase value and iterative right test phase value corresponding to the Kth iteration, respectively.

[0148] If the amplitude estimation value corresponding to the iterative left test phase value xn^K is greater than the amplitude estimation value corresponding to the iterative right test phase value yn^K, the first iteration of the phase value interval is performed on the iterative phase value interval [an^K, bn^K], that is, the phase value interval is reduced to the right end, at which time the right end phase value remains unchanged, and the left test phase value is assigned to the iterative left end phase value to obtain the iterative right end phase value bn^(K+1) and the iterative left end phase value an^K. Among them, bn^(K+1)=bn^K, an^(K+1)=xn^K. Among them, when performing the first iteration of the phase value interval, the flag sign=0 can be set.

[0149] At the same time, the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1), and xn^(K+1)=yn^K is obtained, and the preset unimodal function search method calculates the iterative right test phase value yn^(K+1) by the following formula:

[0150] yn^(K+1)=an^(K+1)+f(D-1) / f(D)*(bn^(K+1)-an^(K+1)).

[0151] If the amplitude estimate corresponding to the iterative left test phase value xn^K is less than the amplitude estimate corresponding to the iterative right test phase value yn^K, then the iterative phase value interval [an^K, bn^K] is subjected to a second iteration of the phase value interval, that is, the phase value interval is reduced toward the left end. At this time, the left end phase value remains unchanged, and the right test phase value is assigned to the iterative right end phase value to obtain the iterative right phase value bn^(K+1) and the iterative left phase value an^(K+1); wherein, an^(K+1)=an^K, bn^(K+1)=yn^K; wherein, when performing the second iteration of the phase value interval, the flag sign=1 can be set.

[0152] At the same time, the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1), and yn^(K+1)=xn^K is obtained, and the preset unimodal function search method calculates the iterative left test phase value xn^(K+1) by the following formula:

[0153] xn^(K+1)=an^(K+1)+f(D-2) / f(D)*(bn^(K+1)-an^(K+1)).

[0154] The above-mentioned test phase value iteration is to search for the phase corresponding to the minimum value of the amplitude estimation value. In some embodiments, the phase corresponding to the maximum value of the amplitude estimation value can also be searched based on the test phase value iteration. The process is a symmetrical and opposite process to the above process. The specific process can refer to the process of the first test phase value iteration, which will not be repeated here. In the above embodiment, each test phase value iteration only requires additional calculation of a new phase value interval endpoint and a new test phase value, thereby reducing the amount of data calculation.

[0155] Then, based on the amplitude estimation value calculation, the amplitude estimation values ​​corresponding to the current iterative left test phase value xn^K and the iterative right test phase value yn^K are obtained respectively. For example, based on the amplitude estimation value calculation, the amplitude estimation values ​​corresponding to the current iterative left test phase value xn^1 and the iterative right test phase value yn^1 are obtained respectively, the length of the target Fibonacci sequence F(D) is reduced by 1 and the number of iterations is increased by 1, and it is continued to determine whether the preset length is met. For example, based on the amplitude estimation value calculation, the amplitude estimation values ​​corresponding to the current iterative left test phase value xn^(K+1) and the iterative right test phase value yn^(K+1) are obtained respectively, the length of the target Fibonacci sequence F(D) is reduced by 1 and the number of iterations is increased by 1, and it is continued to determine whether the preset length is met.

[0156] In some embodiments, if the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1, that is, the flag sign = 0, then the amplitude estimation value corresponding to the initial right test phase value yn^0 is assigned to the amplitude estimation value corresponding to the iterative left test phase value xn^1, and the amplitude estimation value of the iterative right test phase value yn^1 is calculated to obtain the amplitude estimation value corresponding to the iterative right test phase value yn^1.

[0157] In some embodiments, if the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1), that is, the flag sign=0, then the amplitude estimation value corresponding to the iterative right test phase value yn^K is assigned to the amplitude estimation value corresponding to the iterative left test phase value xn^(K+1), and the amplitude estimation value of the iterative right test phase value yn^(K+1) is calculated to obtain the amplitude estimation value corresponding to the iterative right test phase value yn^(K+1).

[0158] In some embodiments, if the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1, that is, the flag sign = 1, then the amplitude estimation value corresponding to the initial left test phase value xn^0 is assigned to the amplitude estimation value corresponding to the iterative right test phase value yn^1, and the amplitude estimation value of the iterative left test phase value xn^1 is calculated to obtain the amplitude estimation value corresponding to the iterative left test phase value xn^1.

[0159] In some embodiments, if the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1), that is, the flag s ign = 1, then the amplitude estimation value corresponding to the iterative left test phase value xn^K is assigned to the amplitude estimation value corresponding to the iterative right test phase value yn^(K+1), and the amplitude estimation value of the iterative left test phase value xn^(K+1) is calculated to obtain the amplitude estimation value corresponding to the iterative left test phase value xn^(K+1) if the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1.

[0160] If the above-mentioned length D meets the preset length, the test phase value iteration is terminated, and the current iterative left test phase value xn^K and iterative right test phase value yn^K are output. Based on the current iterative left test phase value xn^K and iterative right test phase value yn^K, the phase corresponding to the minimum amplitude estimation value is obtained.

[0161] In some embodiments, the average phase value of the current iterative left test phase value xn^K and the iterative right test phase value yn^K is obtained as the phase corresponding to the minimum value of the amplitude estimation. For example, based on the test phase value iteration, the phase corresponding to the minimum value of the amplitude estimation value is directly searched, and the average phase value of the current iterative left test phase value xn^K and the iterative right test phase value yn^K is directly used as the phase corresponding to the minimum value of the amplitude estimation.

[0162] In some embodiments, the average phase value of the current iterative left test phase value xn^K and the iterative right test phase value yn^K is obtained, and the average phase value is shifted by a preset phase to obtain the phase corresponding to the minimum value of the amplitude estimation. For example, the phase corresponding to the maximum value of the amplitude estimation value is directly searched based on the test phase value iteration. In this case, the average phase value needs to be inverted to obtain the phase corresponding to the minimum value of the amplitude estimation.

[0163] In some embodiments, if the average phase value is between [0, π), the preset phase of the translation is π; if the average phase value is between [π, 2π), the preset phase of the translation is -π, and the phase after translation is the sum of the average phase value and the preset phase of the translation. In this embodiment, based on the phase range in which the average phase value is located, different addition and subtraction operations are performed on the average phase value, so that the phase after translation is always a positive value, which is convenient for subsequent use and calculation.

[0164] In the above embodiment, since there is a fixed relationship between the left test phase value and the right test phase value and the right end phase value and the left end phase value, they can be converted to each other based on the fixed relationship. Therefore, in the above embodiment, the phase corresponding to the minimum amplitude estimation value can be obtained based on the left test phase value and the right test phase value, and the phase corresponding to the minimum amplitude estimation value can be obtained based on the right end phase value and the left end phase value.

[0165] In some embodiments, when performing the above-mentioned test phase value iteration, the signal processing channel may also include a phase counter and a memory, the phase counter is used to accumulate and count the test phase value corresponding to the cancellation signal during the test phase value iteration, and the memory is used to store the corresponding test phase values ​​and their corresponding amplitude estimation values.

[0166] In the above embodiments, although the phase of the final estimated output is called the estimated phase of the harmonic or the estimated phase of the spurious, it should be clear that it is the antiphase of the phase of the real harmonic, and there is a phase difference of π between it and the phase of the real harmonic. Therefore, the phase of the output can be directly used when generating the cancellation signal corresponding to the harmonic or spurious.

[0167] In the above embodiments, the signal processing channel can process at least one harmonic or spurious wave, or can process harmonics and spurious waves. In some embodiments, the total number L of harmonics and spurious waves to be processed is obtained, the total number L is divided by H-1 and rounded up to obtain the number of times the signal processing channel is called, and the phase counter and the memory are reset according to the number of times the signal processing channel is called to clear the amplitude estimation value and its corresponding phase value stored in history. Each time the signal processing channel is adjusted, H-1 harmonics or spurious waves can be processed.

[0168] In some embodiments, a reset operation is required when calling a signal processing channel to avoid mutual interference. For example, if it is detected that the signal processing channel has been cleared before being called, no reset is required; if it is detected that the signal processing channel has not been cleared before being called, a reset and clearing operation is required. Therefore, when resetting the phase counter and the memory according to the number of times the signal processing channel is called, the number of times the signal processing channel is called can be the same as the number of resets. For example, a reset and clearing operation is performed before each call to the signal processing channel. When it is detected that the signal processing channel has been cleared, the number of times the signal processing channel is called can be less than the number of resets.

[0169] The following is an illustration through specific embodiments.

[0170] Assume that the input frequency f_in of the original input signal is 30MHz, then calculate the frequency control word based on the input frequency f_in, and then calculate the phase sequence output by the DDS phase accumulator 10, address the sine lookup table according to the output phase sequence, obtain the full-scale signal, and then multiply the full-scale signal by the attenuation coefficient α=0.95 and input it to the DAC. Assuming that the harmonics to be estimated are the second harmonic and the third harmonic, their frequencies are f_2=2*f_in=60MHz and f_3=3*f_in=90MHz respectively.

[0171] Assume that the initial phase value interval is [an^0, bn^0] = [0, 1], and the corresponding phase value is [0, 2π], that is, the initial left end phase value an^0 is 0, and the initial right end phase value bn^0 is 2π. Set the target error value to ε = 0.01, then the target value of the target Fibonacci sequence F(D) δ = (bn^0-an^0) / ε = 100, so the target Fibonacci sequence can be calculated as:

[0172] F(D)=[1,1,2,3,5,8,13,21,34,55,89,144];

[0173] That is, the sequence length D is equal to 12.

[0174] The calculated left test phase value is xn^0=an^0+(55 / 144)*(bn^0-an^0)=0.382, that is, the phase value is 0.382*2π, and the initial right test phase value is yn^0=an^0+(59 / 144)*(bn^0-an^0)=0.618, that is, the phase value is 0.618*2π.

[0175] In some embodiments, an estimated phase empirical value can also be obtained, and the phase value interval [an^0, bn^0] = [0.4, 0.5] is determined based on the estimated phase empirical value. Assuming the target error value is ε = 0.005, the target value of the target Fibonacci sequence F(D) is δ = (bn^0-an^0) / ε = 0, so the target Fibonacci sequence can be calculated to be F(D) = [1, 1, 2, 3, 5, 8, 13, 21], that is, the sequence length D is equal to 8.

[0176] Calculate the initial left test phase value xn^0=an^0+(8 / 21)*(bn^0-an^0)=0.4381, that is, the phase value is 0.4381*2π, and the initial right test phase value yn^0=an^0+(13 / 21)*(bn^0-an^0)=0.4619, that is, the phase value is 0.4619*2π.

[0177] According to the frequency f_n of the second harmonic and the third harmonic, the amplitude estimation value of the second harmonic and the third harmonic of the original input signal, and the phase value corresponding to xn^0=0.382 and yn^0=0.618, the cancellation signal corresponding to the second and third harmonics is generated, and the cancellation signal is superimposed with the original input signal and input to the DAC. The output signal of the DAC is analyzed by a spectrum analyzer, and the amplitude estimation value corresponding to xn^0 and the amplitude estimation value corresponding to yn^0 are recorded.

[0178] Determine whether the sequence length D is greater than 2.

[0179] If the length D is greater than 2, the test phase value is iterated and the minimum value of the amplitude estimate is searched. For the iteration results, please refer to Figure 4 and Figure 5 That is, it is determined whether the amplitude estimation value corresponding to xn^0 of the second harmonic and the third harmonic is greater than the amplitude estimation value corresponding to yn^0.

[0180] If so, the phase value interval is reduced to the right end. At this time, the right end phase value remains unchanged, and the left test phase value is assigned to the iterative left end phase value, that is, bn^1=bn^0, an^1=xn^0. At the same time, the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1, that is, xn^1=yn^0, and the right test phase value is recalculated:

[0181] yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1);

[0182] And determine that the flag s ign_n=0, and the number of iterations K is 1 at this time.

[0183] If not, the phase value interval is reduced to the left end. At this time, the left end phase value remains unchanged, and the right test phase value is assigned to the iterative right end phase value, that is, an^1=an^0, bn^1=yn^0. At the same time, the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1, that is, yn^1=xn^0, and the left test phase value is recalculated:

[0184] xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1),

[0185] And determine that the flag s ign_n=1, and the number of iterations K is 1 at this time.

[0186] If the flag s ign_n=0, the amplitude estimation value corresponding to the initial right test phase value yn^0 is assigned to the amplitude estimation value corresponding to the iterative left test phase value xn^1, and the amplitude estimation value of the iterative right test phase value yn^1 is calculated to obtain the amplitude estimation value corresponding to the iterative right test phase value yn^1.

[0187] If the flag s ign_n=1, the amplitude estimation value corresponding to the initial left test phase value xn^0 is assigned to the amplitude estimation value corresponding to the iterative right test phase value yn^1, and the amplitude estimation value of the iterative left test phase value xn^1 is calculated to obtain the amplitude estimation value corresponding to the iterative left test phase value xn^1.

[0188] The length D of the target Fibonacci sequence F(D) is reduced by 1 and the number of iterations K is increased by 1 and the above length determination is continued.

[0189] If the length D is less than or equal to 2, then based on the current number of iterations K, the output is:

[0190] φn=(xn^K+yn^K) / 2.

[0191] The above is the description of the signal processing channel.

[0192] Some embodiments provide a phase estimation method, which can be applied to the above-mentioned signal processing channel. Figure 6 , the harmonic phase acquisition method includes the following steps:

[0193] Step 100: Obtain the original input signal and the initial phase value interval, determine the target error value and calculate the target Fibonacci sequence based on the target error value and the initial phase value interval. Wherein, an^0 is the initial left end phase value, and bn^0 is the initial right end phase value. Wherein, the length of the target Fibonacci sequence F(D) is D.

[0194] Step 110: Determine the initial left test phase value and the initial right test phase value based on the target Fibonacci sequence and the initial phase value interval, and perform amplitude estimation calculation. Determine the initial left test phase value xn^0 and the initial right test phase value yn^0 based on the sequence value in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], and perform amplitude estimation calculations on the initial left test phase value xn^0 and the initial right test phase value yn^0 respectively: generate a cancellation signal based on the harmonic frequency and harmonic amplitude value of the harmonics of the original input signal or based on the spurious frequency and spurious amplitude value of the spurious of the original input signal, and the corresponding test phase value; superimpose the cancellation signal and the original input signal to obtain a digital signal to be tested; input the digital signal to be tested into a DAC for digital-to-analog conversion to obtain an analog signal to be tested, perform spectrum analysis on the analog signal to be tested, and obtain an amplitude estimation value of the harmonic frequency or spurious frequency corresponding to the corresponding test phase value.

[0195] Step 120: Determine whether the length of the target Fibonacci sequence meets a preset length.

[0196] Step 130: If satisfied, then the phase corresponding to the minimum amplitude estimation value is obtained based on the current iterative left test phase value and the iterative right test phase value. The test phase value iteration is terminated, and the current iterative left test phase value xn^K and the iterative right test phase value yn^K are output, and the phase corresponding to the minimum amplitude estimation value is obtained based on the current iterative left test phase value xn^K and the iterative right test phase value yn^K. Wherein, K is the number of iterations and its initial value is 1, and xn^K and yn^K are the iterative left test phase value and the iterative right test phase value corresponding to the Kth iteration, respectively.

[0197] Step 140: If not satisfied, then perform test phase value iteration, and reduce the length of the target Fibonacci sequence by 1. Perform test phase value iteration based on the sequence value and initial phase value interval [an^0, bn^0] in the target Fibonacci sequence F(D), as well as the initial left test phase value xn^0 and the initial right test phase value yn^0 and their corresponding amplitude estimation values, to obtain the iterative left test phase value xn^K and the iterative right test phase value yn^K, and obtain the amplitude estimation values ​​corresponding to the current iterative left test phase value xn^K and the iterative right test phase value yn^K respectively based on the amplitude estimation value calculation; reduce the length D of the target Fibonacci sequence F(D) by 1 and increase the number of iterations K by 1, and continue to determine whether the preset length is satisfied.

[0198] Some embodiments provide a computer-readable storage medium having a program stored thereon, which can be executed by a processor to implement the above-mentioned phase estimation method.

[0199] Those skilled in the art will appreciate that all or part of the functions of the various methods in the above-mentioned embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above-mentioned embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, and the storage medium can include: a read-only memory, a random access memory, a disk, an optical disk, a hard disk, etc., and the program is executed by a computer to implement the above-mentioned functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor 30, all or part of the above-mentioned functions can be implemented. In addition, when all or part of the functions in the above-mentioned embodiments are implemented by computer programs, the program can also be stored in a storage medium such as a server, another computer, a disk, an optical disk, a flash disk or a mobile hard disk, and can be downloaded or copied and saved in the memory of the local device, or the system of the local device is updated, and when the program in the memory is executed by the processor 30, all or part of the functions in the above-mentioned embodiments can be implemented.

[0200] The above specific examples are used to illustrate the present application, which is only used to help understand the present application and is not intended to limit the present application. For technicians in the technical field to which the present application belongs, they can also make some simple deductions, deformations or substitutions based on the ideas of the present application.

Claims

1. A phase estimation method, characterized in that: include: Get the original input signal and the initial phase value interval [an^0, bn^0]; where an^0 is the initial left phase value and bn^0 is the initial right phase value; Determine a target error value, and calculate a target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0]; wherein the length of the target Fibonacci sequence F(D) is D; Determine an initial left test phase value xn^0 and an initial right test phase value yn^0 based on the sequence value in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], and perform amplitude estimation calculations on the initial left test phase value xn^0 and the initial right test phase value yn^0, respectively, to obtain amplitude estimation values ​​of corresponding test phase values, respectively; Determine whether the length D of the target Fibonacci sequence F(D) meets a preset length; If not satisfied, then based on the sequence value in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0], as well as the initial left test phase value xn^0 and the initial right test phase value yn^0 and their corresponding amplitude estimation values, test phase value iteration is performed to obtain the iterative left test phase value xn^K and the iterative right test phase value yn^K, and based on the amplitude estimation value calculation, the amplitude estimation values ​​corresponding to the current iterative left test phase value xn^K and the iterative right test phase value yn^K are respectively obtained, wherein K is the number of iterations and its initial value is 1, and xn^K and yn^K are the iterative left test phase value and the iterative right test phase value corresponding to the Kth iteration, respectively; the length D of the target Fibonacci sequence F(D) is subtracted by 1 and the number of iterations K is increased by 1, and it is continued to be judged whether the preset length is satisfied; If satisfied, the iteration of the test phase value is terminated, and the phase corresponding to the minimum amplitude estimation value is obtained based on the current iterative left test phase value xn^K and iterative right test phase value yn^K.

2. The phase estimation method according to claim 1, characterized in that: The amplitude estimation value calculation includes: generating a cancellation signal based on the harmonic frequency and harmonic amplitude value of the harmonics of the original input signal or based on the spurious frequency and spurious amplitude value of the spurious of the original input signal, and the corresponding test phase value; superimposing the cancellation signal and the original input signal to obtain a digital signal to be tested; inputting the digital signal to be tested into a DAC for digital-to-analog conversion to obtain an analog signal to be tested, and performing spectrum analysis on the analog signal to be tested to obtain an amplitude estimation value of the corresponding test phase value.

3. The phase estimation method according to claim 1, characterized in that: The calculating of the target Fibonacci sequence F(D) based on the target error value and the initial phase value interval [an^0, bn^0] comprises: The target value of the target Fibonacci sequence F(D) is calculated based on the following formula: δ=(bn^0-an^0) / ε; Wherein, δ is the target value, ε is the target error value; When the D-th sequence value in the Fibonacci sequence is greater than or equal to the target value, the acquisition length of the Fibonacci sequence is determined to be D to obtain the target Fibonacci sequence F(D).

4. The phase estimation method according to claim 1, characterized in that: The determining of the initial left test phase value xn^0 and the initial right test phase value yn^0 based on the sequence value in the target Fibonacci sequence F(D) and the initial phase value interval [an^0, bn^0] comprises: The initial left test phase value xn^0 is calculated by the following formula: xn^0=an^0+f(D-2) / f(D)*(bn^0-an^0); Wherein, f(D-2) is the D-2th sequence value in the target Fibonacci sequence F(D), and F(D) is the Dth sequence value in the target Fibonacci sequence F(D); The initial right test phase value yn^0 is calculated by the following formula: yn^0=an^0+f(D-1) / f(D)*(bn^0-an^0); Wherein, f(D-1) is the D-1th sequence value in the target Fibonacci sequence F(D).

5. The phase estimation method according to claim 4, characterized in that: The test phase value iteration comprises: If the first iteration of the test phase value is performed, it is determined whether the amplitude estimation value corresponding to the initial left test phase value xn^0 is greater than the amplitude estimation value corresponding to the initial right test phase value yn^0; If it is greater than, the first iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0] to obtain the iterative right-end phase value bn^1 and the iterative left-end phase value an^1; wherein bn^1=bn^0, an^1=xn^0; the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1 to obtain xn^1=yn^0, and the preset unimodal function search method calculates the iterative right test phase value yn^1 by the following formula: yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1); If it is less than, the second iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0] to obtain the iterative right phase value bn^1 and the iterative left phase value an^1; wherein an^1=an^0, bn^1=yn^0; the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1 to obtain yn^1=xn^0, and the preset unimodal function search method calculates the iterative left test phase value xn^1 by the following formula: xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1); If the test phase value iteration is performed for the K+1th time, it is determined whether the amplitude estimation value corresponding to the iterative left test phase value xn^K is greater than the amplitude estimation value corresponding to the iterative right test phase value yn^K; If it is greater than, the first iteration of the phase value interval is performed on the initial phase value interval [an^K, bn^K] to obtain the iterative right-end phase value bn^(K+1) and the iterative left-end phase value an^(K+1); wherein bn^(K+1)=bn^K, an^(K+1)=xn^K; the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1) to obtain xn^(K+1)=yn^K, and the preset unimodal function search method calculates the iterative right test phase value yn^K by the following formula: yn^(K+1)=an^(K+1)+f(D-1) / f(D)*(bn^(K+1)-an^(K+1)); If it is less than, the iterative phase value interval [an^K, bn^K] is subjected to a second iteration of the phase value interval to obtain an iterative right phase value bn^(K+1) and an iterative left phase value an^(K+1); wherein an^(K+1)=an^K, bn^(K+1)=yn^K; the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1) to obtain yn^(K+1)=xn^K, and the preset unimodal function search method calculates the iterative left test phase value xn^(K+1) by the following formula: xn^(K+1)=an^(K+1)+f(D-2) / f(D)*(bn^(K+1)-an^(K+1)).

6. The phase estimation method according to claim 4, characterized in that: The test phase value iteration comprises: If the first iteration of the test phase value is performed, it is determined whether the amplitude estimation value corresponding to the initial left test phase value xn^0 is greater than the amplitude estimation value corresponding to the initial right test phase value yn^0; If it is greater than, the second iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0] to obtain the iterative right phase value bn^1 and the iterative left phase value an^1; wherein an^1=an^0, bn^1=yn^0; the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1 to obtain yn^1=xn^0, and the preset unimodal function search method calculates the iterative left test phase value xn^1 by the following formula: xn^1=an^1+f(D-2) / f(D)*(bn^1-an^1); If it is less than, the first iteration of the phase value interval is performed on the initial phase value interval [an^0, bn^0] to obtain the iterative right-end phase value bn^1 and the iterative left-end phase value an^1; wherein bn^1=bn^0, an^1=xn^0; the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1 to obtain xn^1=yn^0, and the preset unimodal function search method calculates the iterative right test phase value yn^1 by the following formula: yn^1=an^1+f(D-1) / f(D)*(bn^1-an^1); If the test phase value iteration is performed for the K+1th time, it is determined whether the amplitude estimation value corresponding to the iterative left test phase value xn^K is greater than the amplitude estimation value corresponding to the iterative right test phase value yn^K; If it is greater than, the iterative phase value interval [an^K, bn^K] is subjected to a second iteration of the phase value interval to obtain an iterative right phase value bn^(K+1) and an iterative left phase value an^(K+1); wherein an^(K+1)=an^K, bn^(K+1)=yn^K; the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1) to obtain yn^(K+1)=xn^K, and the preset unimodal function search method calculates the iterative left test phase value xn^(K+1) by the following formula: xn^(K+1)=an^(K+1)+f(D-2) / f(D)*(bn^(K+1)-an^(K+1)); If it is less than, the first iteration of the phase value interval is performed on the initial phase value interval [an^K, bn^K] to obtain the iterative right-end phase value bn^(K+1) and the iterative left-end phase value an^(K+1); wherein bn^(K+1)=bn^K, an^(K+1)=xn^K; the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1) to obtain xn^(K+1)=yn^K, and the preset unimodal function search method calculates the iterative right test phase value yn^K by the following formula: yn^(K+1)=an^(K+1)+f(D-1) / f(D)*(bn^(K+1)-an^(K+1)).

7. The phase estimation method according to claim 5 or 6, characterized in that: The step of respectively obtaining the amplitude estimation values ​​corresponding to the current iterative left test phase value xn^K and the iterative right test phase value yn^K based on the amplitude estimation value calculation includes: If the initial right test phase value yn^0 is assigned to the iterative left test phase value xn^1, the amplitude estimation value corresponding to the initial right test phase value yn^0 is assigned to the amplitude estimation value corresponding to the iterative left test phase value xn^1, and the amplitude estimation value calculation is performed on the iterative right test phase value yn^1 to obtain the amplitude estimation value corresponding to the iterative right test phase value yn^1; If the iterative right test phase value yn^K is assigned to the iterative left test phase value xn^(K+1), then the amplitude estimation value corresponding to the iterative right test phase value yn^K is assigned to the amplitude estimation value corresponding to the iterative left test phase value xn^(K+1), and the amplitude estimation value calculation is performed on the iterative right test phase value yn^(K+1) to obtain the amplitude estimation value corresponding to the iterative right test phase value yn^(K+1); If the initial left test phase value xn^0 is assigned to the iterative right test phase value yn^1, the amplitude estimation value corresponding to the initial left test phase value xn^0 is assigned to the amplitude estimation value corresponding to the iterative right test phase value yn^1, and the amplitude estimation value calculation is performed on the iterative left test phase value xn^1 to obtain the amplitude estimation value corresponding to the iterative left test phase value xn^1; If the iterative left test phase value xn^K is assigned to the iterative right test phase value yn^(K+1), the amplitude estimation value corresponding to the iterative left test phase value xn^K is assigned to the amplitude estimation value corresponding to the iterative right test phase value yn^(K+1), and the amplitude estimation value calculation is performed on the iterative left test phase value xn^(K+1) to obtain the amplitude estimation value corresponding to the iterative left test phase value xn^(K+1).

8. The phase estimation method according to claim 5, characterized in that: The obtaining the phase corresponding to the minimum amplitude estimation value based on the current iterative left test phase value xn^K and the iterative right test phase value yn^K includes: The average phase value of the current iterative left test phase value xn^K and the iterative right test phase value yn^K is obtained as the phase corresponding to the minimum amplitude estimation value.

9. The phase estimation method according to claim 6, characterized in that: The obtaining the phase corresponding to the minimum amplitude estimation value based on the current iterative left test phase value xn^K and the iterative right test phase value yn^K includes: The average phase value of the current iterative left test phase value xn^K and the iterative right test phase value yn^K is obtained, and the average phase value is shifted by a preset phase to obtain the phase corresponding to the amplitude estimation minimum value.

10. The phase estimation method according to claim 9, characterized in that: If the average phase value is between [0, π), the preset phase of the translation is π; If the average phase value is between [π, 2π), the preset phase of the translation is -π; The phase after translation is the sum of the average phase value and the preset phase of translation.

11. The phase estimation method according to claim 1, characterized in that: The initial phase value interval [an^0, bn^0] is generated in the following way: The phase value 0 is configured as the initial left phase value an^0, and the phase value 2π is configured as the initial right phase value bn^0, so as to obtain the initial phase value interval [an^0, bn^0]; or, Obtain an estimated phase empirical value, and generate the initial phase value interval [an^0, bn^0] according to the estimated phase empirical value.

12. The phase estimation method according to claim 11, characterized in that: The obtaining of the estimated phase empirical value comprises: Obtaining a phase estimation value corresponding to a harmonic frequency or a spurious frequency of a known input signal after the known input signal is input into the DAC; Based on the frequency relationship between the known input signal and the original input signal, the estimated phase empirical value corresponding to the harmonic of the original input signal is obtained from the phase estimation value; or, Based on the frequency relationship between the known input signal and the original input signal, and the frequency relationship between the spurious frequency of the known input signal and the spurious frequency of the original input signal, the estimated phase empirical value corresponding to the spur of the original input signal is obtained from the phase estimation value.

13. The phase estimation method according to claim 1, characterized in that: The performing spectrum analysis on the simulated signal to be tested comprises: Inputting the simulated signal to be tested into a spectrum analyzer for spectrum analysis; or, The simulated signal to be tested is input into an analog-to-digital converter for analog-to-digital conversion and then subjected to Fourier transform processing for spectrum analysis.

14. The phase estimation method according to claim 1, characterized in that: For harmonics, the corresponding frequency of the cancellation signal is the harmonic frequency of the harmonics of the original input signal; for spurious signals, the corresponding frequency of the cancellation signal is the spurious frequency of the spurious signals of the original input signal.

15. A signal processing channel, characterized in that: Used to implement the phase estimation method according to any one of claims 1 to 14, the signal processing channel comprises at least two DDS phase accumulators, and the signal processing circuits where each of the DDS phase accumulators is located are connected in parallel, and the number of parallel connections is defined as an integer H greater than 1; One of the signal processing circuits including a DDS phase accumulator generates the original input signal after phase-amplitude conversion processing and attenuation processing, and the remaining signal processing circuits including a DDS phase accumulator generate cancellation signals corresponding to harmonics or cancellation signals corresponding to spurious signals based on corresponding test phase values ​​through phase-amplitude conversion processing.

16. The signal processing channel according to claim 15, characterized in that The signal processing channel is used to process multiple harmonics, or multiple spurious signals, or at least one harmonic and at least one spurious signal. If the value of H is ≥3, the remaining signal processing circuits including the DDS phase accumulator are used to generate cancellation signals corresponding to multiple harmonics, or cancellation signals corresponding to multiple spurious signals, or cancellation signals corresponding to at least one harmonic and at least one spurious signal respectively. The maximum number of times the remaining signal processing circuits including the DDS phase accumulator are called is equal to the sum of the number of harmonics and the number of spurious signals.

17. The signal processing channel of claim 16, wherein: The signal processing channel also includes a phase counter and a memory. The phase counter is used to accumulate and count the test phase value corresponding to the cancellation signal when the test phase value is iterated, and the memory is used to store the corresponding test phase values ​​and their corresponding amplitude estimation values.

18. The signal processing channel of claim 17, wherein: Obtain the total number L of harmonics and spurious signals to be processed; Divide the total number L by H-1 and round up to get the number of times the signal processing channel is called; According to the number of times the signal processing channel is called, the phase counter and the memory are reset to clear the amplitude estimation value and the corresponding test phase value stored in history.

19. A computer-readable storage medium, characterized in that: The medium stores a program, which can be executed by a processor to implement the method according to any one of claims 1 to 14.

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