Bus capacitor capacitance value monitoring method and device, terminal and storage medium

Abstract

The invention discloses a bus capacitor capacitance value monitoring method and device, a terminal and a storage medium. The method comprises the following steps: acquiring a positive bus capacitor voltage and a negative bus capacitor voltage of a static var generator; obtaining a three-phase bridge arm output current of the static var generator; acquiring the duty ratio of a positive three-phase switch tube and the duty ratio of a negative three-phase switch tube of a three-phase bridge arm of the static var generator; calculating a positive bus capacitive current according to the three-phase bridge arm output current and the duty ratio of a positive three-phase switch tube; calculating a cathode bus capacitance current according to the three-phase bridge arm output current and a cathode three-phase switch tube duty ratio; calculating positive bus capacitance according to the positive bus capacitance voltage and the positive bus capacitance current; and calculating the cathode bus capacitance according to the cathode bus capacitance voltage and the cathode bus capacitance current. According to the method, a current sensor of the bus capacitor is not additionally arranged, so that the capacitance value of the bus capacitor is monitored, additional cost is not needed, and the risk of the system is not increased.

Description

Technical Field

[0001] The present invention relates to the technical field of static VAR generators, and in particular to a method, a device, a terminal and a storage medium for monitoring the capacitance of a busbar capacitor. Background Art

[0002] In the current low-voltage electrical system, the three-level inverter circuit is the mainstream choice for the static VAR generator circuit topology. However, it is worth noting that most static VAR generators do not have the bus capacitance monitoring function. Monitoring the bus capacitance is crucial for evaluating the attenuation of the capacitor and determining whether it is in a normal state. Since it is difficult to directly measure the capacitance of the capacitor in operation, the existing technology usually relies on adding sensors to measure the capacitor current and combining the fluctuation data of the capacitor voltage to calculate the capacitance of the bus capacitor.

[0003] There are some problems with the current solution of using sensors to measure bus capacitor current. First, this solution requires additional cost investment. Especially for three-level circuits, due to the difference between positive and negative bus currents, two sensors need to be installed, which undoubtedly further increases the cost. Secondly, these additional sensors need to be connected in series in the circuit, which not only increases the loop length between the power device and the bus capacitor, but also may bring additional impedance. This increase in impedance may cause the voltage stress of the power device to increase, or cause resonance between the bus capacitor and the parasitic capacitor of the power device, thereby increasing the risk of the system. Summary of the invention

[0004] The technical problem to be solved by the present invention is that, in monitoring the bus capacitor value, the current solution of using a sensor to measure the bus capacitor current is costly and increases the risk of the system.

[0005] In order to solve the above technical problems, the first aspect of the present invention discloses a method for monitoring the capacitance of a busbar capacitor, the method comprising:

[0006] Obtaining a positive bus capacitor voltage and a negative bus capacitor voltage of a static VAR generator;

[0007] Obtain the three-phase bridge arm output current of the static VAR generator;

[0008] Obtaining the positive three-phase switch tube duty ratio and the negative three-phase switch tube duty ratio of the three-phase bridge arm of the static VAR generator;

[0009] Calculate the positive bus capacitor current according to the three-phase bridge arm output current and the positive three-phase switch duty cycle;

[0010] Calculate the negative bus capacitor current according to the three-phase bridge arm output current and the negative three-phase switch duty cycle;

[0011] Calculating the positive bus capacitance according to the positive bus capacitance voltage and the positive bus capacitance current;

[0012] The negative bus capacitance is calculated according to the negative bus capacitance voltage and the negative bus capacitance current.

[0013] As an optional implementation manner, in the first aspect of the present invention, the calculation of the positive bus capacitor current according to the three-phase bridge arm output current and the positive three-phase switch duty cycle includes:

[0014] The positive bus capacitor current is calculated using the following formula:

[0015] Ic1=Ia*D1a+Ib*D1b+Ic*D1c

[0016] Among them, Ic1 is the positive bus capacitor current, Ia is the output current of the A-phase inverter circuit, Ib is the output current of the B-phase inverter circuit, Ic is the output current of the C-phase inverter circuit, D1a is the duty cycle of the A-phase positive switch tube, D1b is the duty cycle of the B-phase positive switch tube, and D1c is the duty cycle of the C-phase positive switch tube.

[0017] As an optional implementation manner, in the first aspect of the present invention, the calculation of the negative bus capacitor current according to the three-phase bridge arm output current and the negative three-phase switch duty cycle includes:

[0018] The negative bus capacitor current is calculated using the following formula:

[0019] Ic2=Ia*D4a+Ib*D4b+Ic*D4c

[0020] Among them, Ic2 is the negative bus capacitor current, Ia is the output current of the A-phase inverter circuit, Ib is the output current of the B-phase inverter circuit, Ic is the output current of the C-phase inverter circuit, D4a is the duty cycle of the A-phase negative switch tube, D4b is the duty cycle of the B-phase negative switch tube, and D4c is the duty cycle of the C-phase negative switch tube.

[0021] As an optional implementation manner, in the first aspect of the present invention, the calculating the positive bus capacitance according to the positive bus capacitance voltage and the positive bus capacitance current includes:

[0022] The positive bus capacitance is calculated using the following formula:

[0023] C1=Ic1 / Uc1ac*2πf

[0024] Wherein, C1 is the positive bus capacitor, Ic1 is the positive bus capacitor current, Uc1ac is the effective value of the voltage AC component calculated based on the positive bus capacitor voltage, and f is the bus voltage fluctuation.

[0025] As an optional implementation manner, in the first aspect of the present invention, the calculating the negative bus capacitance according to the negative bus capacitance voltage and the negative bus capacitance current comprises:

[0026] The negative bus capacitance is calculated using the following formula:

[0027] C2=Ic2 / Uc2ac*2πf

[0028] Wherein, C2 is the negative bus capacitor, Ic2 is the negative bus capacitor current, Uc2ac is the effective value of the voltage AC component calculated based on the negative bus capacitor voltage, and f is the bus voltage fluctuation.

[0029] As an optional implementation manner, in the first aspect of the present invention, the circuit of the static VAR generator includes:

[0030] Positive bus capacitor, negative bus capacitor, A-phase inverter circuit, B-phase inverter circuit, C-phase inverter circuit, bus voltage detector, inverter bridge arm current detector, among which,

[0031] The positive busbar of the DC system is connected to the first end of the positive busbar capacitor and the first end of the A-phase inverter circuit, the negative busbar of the DC system is connected to the first end of the negative busbar capacitor and the first end of the C-phase inverter circuit, and the neutral busbar of the DC system is connected to the first end of the B-phase inverter circuit;

[0032] The second end of the positive bus capacitor is connected to the second end of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and the second end of the negative bus capacitor is connected to the third end of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit;

[0033] The bus voltage detector is connected to the positive bus and the negative bus of the DC system to detect the voltage of the positive bus and the negative bus;

[0034] The inverter bridge arm current detector is connected to the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and is used to detect the output current of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit.

[0035] As an optional implementation, in the first aspect of the present invention, the A-phase inverter circuit includes:

[0036] A first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode;

[0037] The second end of the positive bus capacitor is connected to the first end of the first switch tube and the first diode, the second ends of the first switch tube and the first diode are connected to the second diode, the fifth diode, and the first end of the second switch tube, the second end of the fifth diode is connected to the positive bus capacitor, the negative bus capacitor, and the first end of the sixth diode, the second end of the fifth diode and the second switch tube is connected to the first end of the third switch tube and the third diode as a current output end, the second ends of the sixth diode, the third switch tube, and the third diode are connected to the first end of the fourth switch tube and the fourth diode, and the second ends of the fourth switch tube and the fourth diode are connected to the second end of the negative bus capacitor.

[0038] A second aspect of the present invention discloses a device for monitoring the capacitance of a busbar, the device comprising:

[0039] An acquisition module, used for acquiring a positive bus capacitor voltage and a negative bus capacitor voltage of a static VAR generator;

[0040] The acquisition module is also used to acquire the three-phase bridge arm output current of the static VAR generator;

[0041] The acquisition module is also used to acquire the positive three-phase switch tube duty ratio and the negative three-phase switch tube duty ratio of the three-phase bridge arm of the static VAR generator;

[0042] A calculation module, used for calculating the positive bus capacitor current according to the three-phase bridge arm output current and the positive three-phase switch duty cycle;

[0043] The calculation module is further used to calculate the negative bus capacitor current according to the three-phase bridge arm output current and the negative three-phase switch duty cycle;

[0044] The calculation module is further used to calculate the positive bus capacitance according to the positive bus capacitance voltage and the positive bus capacitance current;

[0045] The calculation module is further used to calculate the negative bus capacitance according to the negative bus capacitance voltage and the negative bus capacitance current.

[0046] A third aspect of the present invention discloses a monitoring terminal for busbar capacitance, the terminal comprising:

[0047] A memory storing executable program code;

[0048] a processor coupled to the memory;

[0049] The processor calls the executable program code stored in the memory to execute part or all of the steps in the bus capacitor capacitance monitoring method disclosed in the first aspect of the present invention.

[0050] The fourth aspect of the present invention discloses a computer storage medium, which stores computer instructions. When the computer instructions are called, they are used to execute some or all of the steps in the bus capacitor capacitance monitoring method disclosed in the first aspect of the present invention.

[0051] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0052] In the embodiment of the present invention, by setting a bus voltage detector and an inverter bridge arm current detector in the static VAR generator circuit, the positive bus capacitor voltage, the negative bus capacitor voltage and the output current of the three-phase inverter bridge arm are measured, and the capacitance of the bus capacitor can be calculated based on this, so as to realize the monitoring of the bus capacitor capacitance. Since the three-level static VAR generator generally needs to measure the positive bus capacitor voltage, the negative bus capacitor voltage and the output current of the three-phase inverter bridge arm to ensure its normal operation, even if the bus capacitor capacitance does not need to be monitored, therefore, the bus capacitor capacitance monitoring method disclosed in the present invention does not add an additional bus capacitor current sensor, and while realizing the monitoring of the bus capacitor capacitance, it does not need to increase additional costs and will not increase the risk of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 It is a flow chart of a method for monitoring the capacitance of a busbar capacitor disclosed in an embodiment of the present invention;

[0055] Figure 2 It is an overall structural diagram of a static VAR generator circuit disclosed in an embodiment of the present invention;

[0056] Figure 3 It is a first example of an inverter circuit in a static VAR generator circuit disclosed in an embodiment of the present invention;

[0057] Figure 4 It is a second example of an inverter circuit in a static VAR generator circuit disclosed in an embodiment of the present invention;

[0058] Figure 5 It is a third example of an inverter circuit in a static VAR generator circuit disclosed in an embodiment of the present invention;

[0059] Figure 6It is a structural schematic diagram of a busbar capacitance monitoring device disclosed in an embodiment of the present invention;

[0060] Figure 7 It is a structural schematic diagram of a busbar capacitance monitoring terminal disclosed in an embodiment of the present invention;

[0061] Figure 8 It is a structural schematic diagram of a computer storage medium disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0062] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, device, product or end including a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to these processes, methods, products or ends.

[0064] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0065] The present invention discloses a bus capacitor capacitance monitoring method, device, terminal and storage medium. By setting a bus voltage detector and an inverter bridge arm current detector in a static VAR generator circuit, the positive bus capacitor voltage, the negative bus capacitor voltage and the output current of the three-phase inverter bridge arm can be measured, and the bus capacitor capacitance can be calculated based on the bus capacitor capacitance, so as to realize the monitoring of the bus capacitor capacitance. Since the three-level static VAR generator generally needs to measure the positive bus capacitor voltage, the negative bus capacitor voltage and the output current of the three-phase inverter bridge arm to ensure its normal operation, even if the bus capacitor capacitance does not need to be monitored, therefore, the bus capacitor capacitance monitoring method disclosed in the present invention does not add an additional bus capacitor current sensor, and while realizing the monitoring of the bus capacitor capacitance, it does not need to increase additional costs and will not increase the risk of the system. The following are detailed descriptions.

[0066] Embodiment 1

[0067] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for monitoring the capacitance of a busbar capacitor disclosed in an embodiment of the present invention. Figure 1 As shown, the busbar capacitance monitoring method may include the following operations:

[0068] 101. Obtain a positive bus capacitor voltage and a negative bus capacitor voltage of a static VAR generator;

[0069] 102. Obtain the three-phase bridge arm output current of the static VAR generator;

[0070] 103. Obtain a positive three-phase switch tube duty ratio and a negative three-phase switch tube duty ratio of a three-phase bridge arm of a static VAR generator;

[0071] 104. Calculate the positive bus capacitor current according to the three-phase bridge arm output current and the positive three-phase switch duty cycle;

[0072] 105. Calculate the negative bus capacitor current according to the three-phase bridge arm output current and the negative three-phase switch duty cycle;

[0073] 106. Calculate the positive bus capacitance according to the positive bus capacitance voltage and the positive bus capacitance current;

[0074] 107. Calculate the negative bus capacitance according to the negative bus capacitance voltage and the negative bus capacitance current.

[0075] In an optional embodiment, the calculating the positive bus capacitor current according to the three-phase bridge arm output current and the positive three-phase switch duty cycle includes:

[0076] The positive bus capacitor current is calculated using the following formula:

[0077] Ic1=Ia*D1a+Ib*D1b+Ic*D1c

[0078] Among them, Ic1 is the positive bus capacitor current, Ia is the output current of the A-phase inverter circuit, Ib is the output current of the B-phase inverter circuit, Ic is the output current of the C-phase inverter circuit, D1a is the duty cycle of the A-phase positive switch tube, D1b is the duty cycle of the B-phase positive switch tube, and D1c is the duty cycle of the C-phase positive switch tube.

[0079] In an optional embodiment, the calculating the negative bus capacitor current according to the three-phase bridge arm output current and the negative three-phase switch duty cycle includes:

[0080] The negative bus capacitor current is calculated using the following formula:

[0081] Ic2=Ia*D4a+Ib*D4b+Ic*D4c

[0082] Among them, Ic2 is the negative bus capacitor current, Ia is the output current of the A-phase inverter circuit, Ib is the output current of the B-phase inverter circuit, Ic is the output current of the C-phase inverter circuit, D4a is the duty cycle of the A-phase negative switch tube, D4b is the duty cycle of the B-phase negative switch tube, and D4c is the duty cycle of the C-phase negative switch tube.

[0083] In an optional embodiment, the calculating the positive bus capacitance according to the positive bus capacitance voltage and the positive bus capacitance current includes:

[0084] The positive bus capacitance is calculated using the following formula:

[0085] C1=Ic1 / Uc1ac*2πf

[0086] Wherein, C1 is the positive bus capacitor, Ic1 is the positive bus capacitor current, Uc1ac is the effective value of the voltage AC component calculated based on the positive bus capacitor voltage, and f is the bus voltage fluctuation.

[0087] In an optional embodiment, the calculating the negative bus capacitance according to the negative bus capacitance voltage and the negative bus capacitance current includes:

[0088] The negative bus capacitance is calculated using the following formula:

[0089] C2=Ic2 / Uc2ac*2πf

[0090] Wherein, C2 is the negative bus capacitor, Ic2 is the negative bus capacitor current, Uc2ac is the effective value of the voltage AC component calculated based on the negative bus capacitor voltage, and f is the bus voltage fluctuation.

[0091] In an optional embodiment, the circuit of the static VAR generator includes:

[0092] Positive bus capacitor, negative bus capacitor, A-phase inverter circuit, B-phase inverter circuit, C-phase inverter circuit, bus voltage detector, inverter bridge arm current detector, among which,

[0093] The positive busbar of the DC system is connected to the first end of the positive busbar capacitor and the first end of the A-phase inverter circuit, the negative busbar of the DC system is connected to the first end of the negative busbar capacitor and the first end of the C-phase inverter circuit, and the neutral busbar of the DC system is connected to the first end of the B-phase inverter circuit;

[0094] The second end of the positive bus capacitor is connected to the second end of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and the second end of the negative bus capacitor is connected to the third end of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit;

[0095] The bus voltage detector is connected to the positive bus and the negative bus of the DC system to detect the voltage of the positive bus and the negative bus;

[0096] The inverter bridge arm current detector is connected to the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and is used to detect the output current of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit.

[0097] In an optional embodiment, the A-phase inverter circuit includes:

[0098] A first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode;

[0099] The second end of the positive bus capacitor is connected to the first end of the first switch tube and the first diode, the second ends of the first switch tube and the first diode are connected to the second diode, the fifth diode, and the first end of the second switch tube, the second end of the fifth diode is connected to the positive bus capacitor, the negative bus capacitor, and the first end of the sixth diode, the second end of the fifth diode and the second switch tube is connected to the first end of the third switch tube and the third diode as a current output end, the second ends of the sixth diode, the third switch tube, and the third diode are connected to the first end of the fourth switch tube and the fourth diode, and the second ends of the fourth switch tube and the fourth diode are connected to the second end of the negative bus capacitor.

[0100] It can be seen that implementation Figure 1The bus capacitor capacitance monitoring method described can achieve the measurement of the positive bus capacitor voltage, the negative bus capacitor voltage and the output current of the three-phase inverter bridge arm by setting a bus voltage detector and an inverter bridge arm current detector in the static VAR generator circuit, and can calculate the bus capacitor capacitance value based on this, so as to achieve the monitoring of the bus capacitor capacitance value. Since the three-level static VAR generator generally needs to measure the positive bus capacitor voltage, the negative bus capacitor voltage and the output current of the three-phase inverter bridge arm to ensure its normal operation, even if the bus capacitor capacitance value does not need to be monitored, therefore, the bus capacitor capacitance monitoring method disclosed in the present invention does not add an additional bus capacitor current sensor, and while achieving the monitoring of the bus capacitor capacitance value, it does not need to increase additional costs and will not increase the risk of the system.

[0101] Embodiment 2

[0102] See also Figure 2 , Figure 2 1 is an overall structural diagram of a static VAR generator circuit disclosed in an embodiment of the present invention. Figure 2 As shown, the static VAR generator circuit includes:

[0103] Positive bus capacitor C1, negative bus capacitor C2, A phase inverter circuit, B phase inverter circuit, C phase inverter circuit, bus voltage detector (not shown), inverter bridge arm current detector (not shown), where:

[0104] The positive bus of the DC system is connected to the first end of the positive bus capacitor C1 and the first end of the A-phase inverter circuit, the negative bus of the DC system is connected to the first end of the negative bus capacitor C2 and the first end of the C-phase inverter circuit, and the neutral bus of the DC system is connected to the first end of the B-phase inverter circuit;

[0105] The second end of the positive bus capacitor C1 is connected to the second ends of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and the second end of the negative bus capacitor C2 is connected to the third ends of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit;

[0106] The bus voltage detector is connected to the positive bus and the negative bus of the DC system to detect the voltage of the positive bus and the negative bus;

[0107] The inverter bridge arm current detector is connected to the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and is used to detect the output current of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit.

[0108] Figure 3 This is the first example of an inverter circuit in a static VAR generator circuit disclosed in an embodiment of the present invention.

[0109] like Figure 3 As shown, the inverter circuit in the static VAR generator circuit may include:

[0110] A first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, and a sixth diode D6;

[0111] The second end of the positive bus capacitor C1 is connected to the first end of the first switch tube Q1 and the first diode D1, the second ends of the first switch tube Q1 and the first diode D1 are connected to the first end of the second diode D2, the fifth diode D5 and the second switch tube Q2, the second end of the fifth diode D5 is connected to the first end of the positive bus capacitor C1, the negative bus capacitor C2 and the sixth diode D6, the second ends of the fifth diode D5 and the second switch tube Q2 are connected to the first ends of the third switch tube Q3 and the third diode D3 as the current output end, the second ends of the sixth diode D6, the third switch tube Q3 and the third diode D3 are connected to the first ends of the fourth switch tube Q4 and the fourth diode D4, and the second ends of the fourth switch tube Q4 and the fourth diode D4 are connected to the second end of the negative bus capacitor C2.

[0112] Figure 4 This is a second example of an inverter circuit in a static VAR generator circuit disclosed in an embodiment of the present invention.

[0113] like Figure 4 As shown, the inverter circuit in the static VAR generator circuit may include:

[0114] A first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4;

[0115] The second end of the positive bus capacitor C1 is connected to the first end of the first switch tube Q1 and the first diode D1, the second ends of the first switch tube Q1 and the first diode D1 are connected to the first ends of the second switch tube Q2, the second diode D2, the fourth switch tube Q4 and the fourth diode D4 as a current output end, the second ends of the fourth switch tube Q4 and the fourth diode D4 are connected to the second end of the negative bus capacitor C2, the second ends of the second switch tube Q2 and the second diode D2 are connected to the first ends of the third switch tube Q3 and the third diode D3, and the second ends of the third switch tube Q3 and the third diode D3 are connected to the first ends of the positive bus capacitor C1 and the negative bus capacitor C2.

[0116] Figure 5 This is a third example of an inverter circuit in a static VAR generator circuit disclosed in an embodiment of the present invention.

[0117] like Figure 5 As shown, the inverter circuit in the static VAR generator circuit may include:

[0118] A first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a fifth switch tube Q5, a sixth switch tube Q6, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, and a sixth diode D6;

[0119] The second end of the positive bus capacitor C1 is connected to the first end of the first switch tube Q1 and the first diode D1, the second ends of the first switch tube Q1 and the first diode D1 are connected to the first ends of the second switch tube Q2, the second diode D2, the fifth switch tube Q5 and the fifth diode D5, the second ends of the second switch tube Q2 and the second diode D2 are connected to the first ends of the third switch tube Q3 and the third diode D3 as the current output end, the second ends of the fifth switch tube Q5 and the fifth diode D5 are connected to the first ends of the sixth switch tube Q6 and the sixth diode D6, the positive bus capacitor C1 and the first end of the negative bus capacitor C2, the second ends of the third switch tube Q3, the third diode D3, the sixth switch tube Q6 and the sixth diode D6 are connected to the first ends of the fourth switch tube Q4 and the fourth diode D4, and the second ends of the fourth switch tube Q4 and the fourth diode D4 are connected to the second end of the negative bus capacitor C2.

[0120] In an optional embodiment, the circuit further includes:

[0121] The filter circuit is connected to the fourth ends of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit.

[0122] The output currents of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit are filtered by the filter circuit before being output.

[0123] The following is an explanation of the calculation principle of busbar capacitance:

[0124] No matter which of the above three inverter circuits is used, there are corresponding three-level external tubes, namely the first switch tube Q1 and the fourth switch tube Q4. Among them, the duty ratios of the three-phase first switch tube Q1 are D1a, D1b, and D1c respectively, and the duty ratios of the three-phase fourth switch tube Q4 are D4a, D4b, and D4c respectively.

[0125] The output currents of the three-phase bridge arms are multiplied by the duty cycle of the first switch tube Q1 to obtain the currents flowing from the positive bus capacitor C1 to the inverter bridge arm, which are Ia*D1a, Ib*D1b, and Ic*D1c, respectively. The sum of them is the current value of the positive bus capacitor C1, Ic1=Ia*D1a+Ib*D1b+Ic*D1c.

[0126] Similarly, the current of the negative bus capacitor C2 can be obtained, Ic2 = Ia*D4a+Ib*D4b+Ic*D4c.

[0127] Since the positive bus capacitor voltage Uc1 is always measured, the effective value of the AC component of the voltage Uc1ac can be calculated using the Uc1 sampling value.

[0128] The capacitance of the positive bus capacitor C1 can be calculated by C1=Ic1 / Uc1ac*2πf. For a three-phase inverter circuit, the bus voltage fluctuation is mainly three times the power frequency. Therefore, for a 50Hz inverter output, f is 150Hz here.

[0129] Similarly, the capacitance of the negative bus capacitor C2 can be calculated by C2=Ic2 / Uc2ac*2πf.

[0130] Through the above calculation method, the static VAR generator circuit disclosed in the embodiment of the present invention does not need to increase additional costs, and does not need to increase the line impedance of the bus and power devices. The bus capacitance value can be calculated using the existing sampling data to determine whether the bus capacitance is still at a normal level.

[0131] Embodiment 3

[0132] See also Figure 6 , Figure 6 Schematic diagram of a busbar capacitance monitoring device disclosed in an embodiment of the present invention. Figure 6 As shown, the busbar capacitance monitoring device may include:

[0133] An acquisition module 601 is used to acquire a positive bus capacitor voltage and a negative bus capacitor voltage of a static VAR generator;

[0134] The acquisition module 601 is also used to acquire the three-phase bridge arm output current of the static VAR generator;

[0135] The acquisition module 601 is further used to acquire the positive three-phase switch duty ratio and the negative three-phase switch duty ratio of the three-phase bridge arm of the static VAR generator;

[0136] A calculation module 602 is used to calculate the positive bus capacitor current according to the three-phase bridge arm output current and the positive three-phase switch duty cycle;

[0137] The calculation module 602 is further used to calculate the negative bus capacitor current according to the three-phase bridge arm output current and the negative three-phase switch duty cycle;

[0138] The calculation module 602 is further used to calculate the positive bus capacitance according to the positive bus capacitance voltage and the positive bus capacitance current;

[0139] The calculation module 602 is further used to calculate the negative bus capacitance according to the negative bus capacitance voltage and the negative bus capacitance current.

[0140] For the specific description of the above-mentioned busbar capacitor capacitance monitoring device, reference can be made to the specific description of the above-mentioned busbar capacitor capacitance monitoring method, which will not be repeated here.

[0141] Embodiment 4

[0142] See also Figure 7 , Figure 7 Schematic diagram of a busbar capacitance monitoring terminal disclosed in an embodiment of the present invention. Figure 7 As shown, the monitoring terminal of the busbar capacitance value may include:

[0143] A memory 701 storing executable program codes;

[0144] a processor 702 coupled to the memory 701;

[0145] The processor 702 calls the executable program code stored in the memory 701 to execute the steps in the bus capacitor capacitance monitoring method disclosed in the first embodiment of the present invention.

[0146] Embodiment 5

[0147] An embodiment of the present invention discloses a computer storage medium, which stores computer instructions. When the computer instructions are called, they are used to execute the steps in the bus capacitor capacitance monitoring method disclosed in the first embodiment of the present invention.

[0148] The device embodiments described above are only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, i.e., they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative work.

[0149] Through the specific description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solution can be essentially or partly contributed to the prior art in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, and the storage medium includes a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable rewritable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0150] Finally, it should be noted that the bus capacitor capacitance monitoring method, device, terminal and storage medium disclosed in the embodiments of the present invention are only preferred embodiments of the present invention, which are only used to illustrate the technical solution of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for monitoring the capacitance of a busbar, characterized in that: The method comprises: Obtaining a positive bus capacitor voltage and a negative bus capacitor voltage of a static VAR generator; Obtain the three-phase bridge arm output current of the static VAR generator; Obtaining the positive three-phase switch tube duty ratio and the negative three-phase switch tube duty ratio of the three-phase bridge arm of the static VAR generator; Calculate the positive bus capacitor current according to the three-phase bridge arm output current and the positive three-phase switch duty cycle; Calculate the negative bus capacitor current according to the three-phase bridge arm output current and the negative three-phase switch duty cycle; Calculating the positive bus capacitance according to the positive bus capacitance voltage and the positive bus capacitance current; The negative bus capacitance is calculated according to the negative bus capacitance voltage and the negative bus capacitance current.

2. The method for monitoring the busbar capacitance according to claim 1, characterized in that: The calculating the positive bus capacitor current according to the three-phase bridge arm output current and the positive three-phase switch duty cycle includes: The positive bus capacitor current is calculated using the following formula: Ic1=Ia*D1a+Ib*D1b+Ic*D1c Among them, Ic1 is the positive bus capacitor current, Ia is the output current of the A-phase inverter circuit, Ib is the output current of the B-phase inverter circuit, Ic is the output current of the C-phase inverter circuit, D1a is the duty cycle of the A-phase positive switch tube, D1b is the duty cycle of the B-phase positive switch tube, and D1c is the duty cycle of the C-phase positive switch tube.

3. The method for monitoring the busbar capacitance value according to claim 2, characterized in that: The calculating the negative bus capacitor current according to the three-phase bridge arm output current and the negative three-phase switch duty cycle comprises: The negative bus capacitor current is calculated using the following formula: Ic2=Ia*D4a+Ib*D4b+Ic*D4c Among them, Ic2 is the negative bus capacitor current, Ia is the output current of the A-phase inverter circuit, Ib is the output current of the B-phase inverter circuit, Ic is the output current of the C-phase inverter circuit, D4a is the duty cycle of the A-phase negative switch tube, D4b is the duty cycle of the B-phase negative switch tube, and D4c is the duty cycle of the C-phase negative switch tube.

4. The method for monitoring the busbar capacitance value according to claim 3, characterized in that: The calculating the positive bus capacitance according to the positive bus capacitance voltage and the positive bus capacitance current comprises: The positive bus capacitance is calculated using the following formula: C1=Ic1 / Uc1ac*2πf Wherein, C1 is the positive bus capacitor, Ic1 is the positive bus capacitor current, Uc1ac is the effective value of the voltage AC component calculated based on the positive bus capacitor voltage, and f is the bus voltage fluctuation.

5. The method for monitoring the busbar capacitance value according to claim 4, characterized in that: The calculating the negative bus capacitance according to the negative bus capacitance voltage and the negative bus capacitance current comprises: The negative bus capacitance is calculated using the following formula: C2=Ic2 / Uc2ac*2πf Wherein, C2 is the negative bus capacitor, Ic2 is the negative bus capacitor current, Uc2ac is the effective value of the voltage AC component calculated based on the negative bus capacitor voltage, and f is the bus voltage fluctuation.

6. The method for monitoring the busbar capacitance according to any one of claims 1 to 5, characterized in that: The circuit of the static VAR generator comprises: Positive bus capacitor, negative bus capacitor, A-phase inverter circuit, B-phase inverter circuit, C-phase inverter circuit, bus voltage detector, inverter bridge arm current detector, among which, The positive busbar of the DC system is connected to the first end of the positive busbar capacitor and the first end of the A-phase inverter circuit, the negative busbar of the DC system is connected to the first end of the negative busbar capacitor and the first end of the C-phase inverter circuit, and the neutral busbar of the DC system is connected to the first end of the B-phase inverter circuit; The second end of the positive bus capacitor is connected to the second end of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and the second end of the negative bus capacitor is connected to the third end of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit; The bus voltage detector is connected to the positive bus and the negative bus of the DC system to detect the voltage of the positive bus and the negative bus; The inverter bridge arm current detector is connected to the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit, and is used to detect the output current of the A-phase inverter circuit, the B-phase inverter circuit, and the C-phase inverter circuit.

7. The method for monitoring the busbar capacitance value according to claim 6, characterized in that: A-phase inverter circuit, comprising: A first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode; The second end of the positive bus capacitor is connected to the first end of the first switch tube and the first diode, the second ends of the first switch tube and the first diode are connected to the second diode, the fifth diode, and the first end of the second switch tube, the second end of the fifth diode is connected to the positive bus capacitor, the negative bus capacitor, and the first end of the sixth diode, the second end of the fifth diode and the second switch tube is connected to the first end of the third switch tube and the third diode as a current output end, the second ends of the sixth diode, the third switch tube, and the third diode are connected to the first end of the fourth switch tube and the fourth diode, and the second ends of the fourth switch tube and the fourth diode are connected to the second end of the negative bus capacitor.

8. A busbar capacitance monitoring device, characterized in that: The device comprises: An acquisition module, used for acquiring a positive bus capacitor voltage and a negative bus capacitor voltage of a static VAR generator; The acquisition module is also used to acquire the three-phase bridge arm output current of the static VAR generator; The acquisition module is also used to acquire the positive three-phase switch tube duty ratio and the negative three-phase switch tube duty ratio of the three-phase bridge arm of the static VAR generator; A calculation module, used for calculating the positive bus capacitor current according to the three-phase bridge arm output current and the positive three-phase switch duty cycle; The calculation module is further used to calculate the negative bus capacitor current according to the three-phase bridge arm output current and the negative three-phase switch duty cycle; The calculation module is further used to calculate the positive bus capacitance according to the positive bus capacitance voltage and the positive bus capacitance current; The calculation module is further used to calculate the negative bus capacitance according to the negative bus capacitance voltage and the negative bus capacitance current.

9. A monitoring terminal for busbar capacitance, characterized in that: The terminal comprises: A memory storing executable program code; a processor coupled to the memory; The processor calls the executable program code stored in the memory to execute the bus capacitor capacitance monitoring method as described in any one of claims 1-7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for monitoring the bus capacitance value as described in any one of claims 1 to 7 is implemented.

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