BTI test circuit, BTI test method and equipment for MOS tube in wafer

Abstract

The present invention belongs to the field of integrated circuit testing, and specifically relates to a BTI test circuit, a BTI test method and a device for MOS tubes in a wafer. The BTI test circuit includes an inverter chain consisting of more than three groups of NMOS tubes and PMOS tubes, and an enable circuit consisting of two PMOS tubes and two NMOS tubes. The enable circuit adopts the architecture of a NOR gate circuit or a NAND gate circuit; the enable circuit is used to output a control signal to the inverter chain, thereby making the MOS tubes on all even bits or all odd bits on the inverter chain in the same bias state, so as to support parallel testing of the BTI effects of each MOS tube with synchronized state. The BTI test circuit can also be built using transistors in the circuit under test to further reduce the hardware cost and reusability of the test solution. The solution solves the problems of low efficiency and high cost of existing transistor BTI testing and chip reliability evaluation.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit testing, and specifically relates to a BTI testing circuit, a BTI testing method for a MOS tube in a wafer, and an IC testing device. Background Art

[0002] With the continuous advancement of chip manufacturing technology, the integration of chips is also increasing. The advancement of high integration means that the process size of integrated circuits has shrunk sharply, and the requirements for chip manufacturing are getting higher and higher. When the size of transistors enters the nanometer level, they will face the physical limits of devices, which will significantly increase the failure rate of devices and cause problems with the reliability of integrated circuits.

[0003] For example, as the size of the device decreases, the thickness of the gate oxide layer of the PMOS tube decreases, and the operating voltage of the circuit cannot meet the corresponding reduction, which causes the negative bias temperature instability (NBTI) effect to intensify. The aging effect that has the greatest impact on the circuit is the NBTI effect. These negative aging mechanisms gradually reduce the reliability and performance of the circuit and have a serious impact on the service life of the circuit chip. Therefore, the testing and monitoring of the NBTI effect is particularly important. In addition to the NBTI effect of the PMOS tube, the positive bias temperature instability (PBTI) effect of the NMOS tube will also affect the service life of the circuit.

[0004] Rapidly testing the BTI (bias temperature instability) effect of MOS tubes in circuits and evaluating the service life of circuits is an important task in circuit testing. In the prior art, the BTI effect of each transistor in a wafer needs to be measured in sequence by a specific test tool. This traditional measurement method is inefficient. For highly integrated large-scale ICs, the test time is relatively long and leads to reduced chip test efficiency. Therefore, how to improve the efficiency of circuit reliability evaluation is becoming a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0005] In order to solve the problem of low efficiency of transistor BTI testing and chip reliability evaluation in the prior art, the present invention provides a BTI testing circuit, a BTI testing method for MOS transistors in a wafer, and an IC testing device.

[0006] The technical solution provided by the present invention is:

[0007] A BTI test circuit includes an inverter chain (RO) composed of NMOS tubes and PMOS tubes in more than three groups of circuits to be tested, and an enable circuit composed of two PMOS tubes and two PMOS tubes. The enable circuit adopts the architecture of a NOR gate circuit or a NAND gate circuit; the enable circuit is used to output a control signal to the inverter chain, thereby making the MOS tubes on all even bits or all odd bits on the inverter chain in the same bias state, so as to support parallel testing of the BTI effects of various MOS tubes with synchronized states.

[0008] In one of the BTI test circuit design schemes provided by the present invention, each group of NMOS tubes and PMOS tubes in the inverter chain constitutes an inverter, and each inverter is cascaded in sequence, and each inverter input terminal and the output terminal of the last inverter are respectively recorded as potential points Pad1~Padn. The sources of all PMOS tubes are connected and recorded as potential point PadA. The enabling circuit includes P6, P7, N6, and N7, and the gates of P6 and N6 are connected to the output terminal of the inverter chain; the drains of P6, P7, and N6 are connected and connected to the input terminal of the inverter chain. The source of N6 is connected to the drain of N7; the source of N7 is connected to the source of all NMOS tubes in the inverter chain and recorded as potential point PadB. The gates of N7 and P7 are connected and recorded as potential point PadC.

[0009] As a further improvement of the present invention, the first BTI test circuit is used to perform parallel measurement on the NBTI effects of each PMOS tube on the even-numbered bits in the inverter chain; the process includes:

[0010] First, make Pad1~Padn float and connect PadA to V high , PadB and PadC are connected to 0V; then each PMOS tube in the even-numbered inverters in the inverter chain is in a negative bias state.

[0011] Then connect Pad1~Padn to -Vdd, connect PadA and PadB to 0V, and leave PadC floating. Then, each PMOS tube in the inverters of even-numbered bits in the inverter chain is in the test state.

[0012] In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each PMOS tube in the inverter of the even bit V th and saturation drain current I dsat , and then analyze the NBTI effect of the corresponding PMOS tube.

[0013] As a further improvement of the present invention, the first BTI test circuit is also used to perform parallel measurement on the PBTI effects of the NMOS transistors on the odd bits in the inverter chain, and the process includes:

[0014] First, make Pad1~Padn float and connect PadA to V high , PadB and PadC are connected to 0V; then each NMOS tube in the odd-numbered inverters in the inverter chain is in a positive bias state.

[0015] Then connect Pad1~Padn to +Vdd, connect PadA and PadB to 0V, and leave PadC floating. Then, each NMOS tube in the odd-numbered inverters in the inverter chain is in the test state.

[0016] In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each NMOS tube in the odd-bit inverter V th and saturation drain current I dsat , and then analyze the PBTI characteristics of the corresponding NMOS tube.

[0017] In another design scheme of the BTI test circuit provided by the present invention, each group of NMOS tubes and PMOS tubes in the inverter chain constitutes an inverter, and each inverter is cascaded in sequence, and each inverter input terminal and the output terminal of the last inverter are respectively recorded as potential points Pad1~Padn. The enabling circuit includes P6, P7, N6, and N7, and the source of P7 is connected to the source of each PMOS tube in the inverter chain and is recorded as potential point PadA. The drain of P7 is connected to the source of P6; the gates of P6 and N6 are connected to the output terminal of the inverter chain; the drains of P6, N6, and N7 are connected to the input terminal of the inverter chain. The sources of N6 and N7 are connected to the sources of all NMOS tubes in the inverter chain and are recorded as potential point PadB. The gates of P7 and N7 are connected and recorded as potential point PadC.

[0018] As a further improvement of the present invention, the second BTI test circuit is used to perform parallel measurement on the NBTI effects of the PMOS transistors on the odd bits in the inverter chain, and the process includes:

[0019] First, make Pad1~Padn float and connect PadA to V high , PadB is connected to 0V, and PadC is connected to Vdd; then each PMOS tube in the odd-numbered inverters in the inverter chain is in a negative bias state.

[0020] Then connect Pad1~Padn to -Vdd, connect PadA and PadB to 0V, and leave PadC floating. Then, each PMOS tube in the odd-numbered inverters in the inverter chain is in the test state.

[0021] In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each PMOS tube in the odd-bit inverter V th and saturation drain currentI dsat , and then analyze the NBTI effect of the corresponding PMOS tube.

[0022] As a further improvement of the present invention, the second BTI test circuit is also used to perform parallel measurement on the PBTI effects of each NMOS transistor on the even-numbered bits in the inverter chain, and the process includes:

[0023] First, make Pad1~Padn float and connect PadA to V high , PadB is connected to 0V, and PadC is connected to Vdd; then each NMOS tube in the inverter of the even-numbered bits in the inverter chain is in a positive bias state.

[0024] Then connect Pad1~Padn to +Vdd, connect PadA and PadB to 0V, and leave PadC floating. Then, each NMOS tube in the inverters of even-numbered bits in the inverter chain is in the test state.

[0025] In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each NMOS tube in the inverter of the even bit V th and saturation drain current I dsat , and then analyze the PBTI characteristics of the corresponding NMOS tube.

[0026] As a further improvement of the present invention, the number of inverters in the inverter chain does not exceed 11.

[0027] The present invention also includes a BTI test method for a MOS tube in a wafer, which comprises:

[0028] S1: Select several NMOS tubes and PMOS tubes to be tested as basic units of the inverter chain, and the remaining two PMOS tubes and two NMOS tubes as basic units of the enabling circuit, and connect each NMOS tube and PMOS tube through a test key to form any of the aforementioned BTI test circuits.

[0029] S2: Using the strategy in the aforementioned BTI test circuit to output or collect signals to each potential point, thereby achieving parallel measurement of the NBTI effects of multiple PMOS tubes at specified positions in the inverter chain.

[0030] At the same time, the strategy in the aforementioned BTI test circuit can be used to output or collect signals to each potential point as needed, thereby realizing parallel measurement of the PBTI effects of multiple NMOS transistors at designated positions in the inverter chain.

[0031] S3: adjusting the position of each MOS tube to be tested or each MOS tube in the inverter chain, repeating steps S1-S2, and thus completing the BTI test task of all MOS tubes in the wafer.

[0032] The present invention also includes an IC testing device, which uses the aforementioned BTI testing method for MOS tubes in a wafer to test the BTI effect of each MOS tube. The IC testing device includes: a test key, a voltage source, a signal acquisition module and a data analysis module.

[0033] The test key is used to construct any of the aforementioned BTI test circuits using the NMOS transistors and PMOS transistors to be tested in the IC.

[0034] The voltage source is used to input the required test signal to the corresponding potential point in the constructed BTI test circuit during the test process. The signal acquisition module is used to collect the electrical signal representing the test result at the specified potential point in the constructed BTI test circuit during the test process.

[0035] The data analysis module is used to analyze the BTI effect of each MOS tube according to the electrical signal collected by the signal acquisition module, and further infer the service life of the IC.

[0036] The technical solution provided by the present invention has the following beneficial effects:

[0037] The present invention designs a BTI test circuit consisting of an inverter chain and an enabling circuit. The circuit utilizes the synchronization of device states in inverters of different stages in the inverter chain to achieve parallel measurement of the BTI effects of multiple MOS tubes, thereby significantly improving the measurement efficiency of similar circuits and shortening the measurement time.

[0038] In addition, since the BTI test circuit provided by the present invention is only composed of NMOS tubes and PMOS tubes, it can be implemented by using the circuit to be tested in practical applications without designing additional hardware circuits, and the scale of the BTI circuit can be expanded in an IC containing a large number of PMOS tubes and NMOS tubes, further improving the measurement efficiency and reducing the measurement cost, and thus has very outstanding practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a basic principle diagram of the BTI test circuit provided in Example 1 of the present invention.

[0040] Figure 2 It is a circuit diagram of a BTI test circuit using a five-stage inverter chain and a NAND gate type enabling circuit provided in Embodiment 1 of the present invention.

[0041] Figure 3It is a circuit diagram of a BTI test circuit using a five-stage inverter chain and a NOR gate type enabling circuit provided in Embodiment 1 of the present invention.

[0042] Figure 4 This is a flow chart of the BTI testing method for MOS transistors in a wafer provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0044] Example 1

[0045] This embodiment provides a BTI test circuit, such as Figure 1 As shown, it includes an inverter chain composed of NMOS tubes and PMOS tubes in more than three groups of circuits to be tested, and an enabling circuit composed of two PMOS tubes P6, P7 and two NMOS tubes N6, N7. In the inverter chain of the BTI test circuit provided in this embodiment, each group of NMOS tubes and PMOS tubes constitutes an inverter, and each inverter is cascaded in sequence. Since the wiring method of the NMOS tubes and PMOS tubes in each stage of the inverter is the same; therefore, under the drive of the external input control signal, the output of each inverter is inverted step by step, so that the PMOS tubes and NMOS tubes in each stage of the inverter can be in the same state as the corresponding PMOS tubes and NMOS tubes in another inverter one level apart.

[0046] In view of the above characteristics of the inverter chain, the enabling circuit in the BTI test circuit designed in this embodiment is used to output a control signal to the inverter chain, thereby making the MOS tubes on all even bits or all odd bits on the inverter chain in the same bias state, so as to support parallel testing of the BTI effects of various MOS tubes with synchronized states. In relation to the existing test circuit, the circuit provided in this embodiment that can implement parallel testing of the BTI effects of multiple PMOS tubes or NMOS tubes can greatly improve the BTI test efficiency of large-scale transistors in integrated circuits and significantly shorten the test time.

[0047] It should be noted that the BTI test circuit designed in this embodiment is completely composed of two types of transistors, NMOS and PMOS, which happen to be the two corresponding test objects in the BTI test task. Therefore, in the actual application of the BTI test circuit, the technician can use external devices and some of the transistors of the test object to build a corresponding BTI test circuit to test the BTI effect of the transistors in the circuit to be tested, or completely use the transistors in the circuit to be tested to build a corresponding BTI test circuit and measure the BTI effect of the specified transistors in the circuit to be tested.

[0048] In actual circuit products, this embodiment provides two different BTI test circuits. The main difference between the two BTI test circuits is the different circuit connection relationship of the enabling circuit, where the four transistors in one enabling circuit adopt the architecture of a NOR gate circuit, and the four transistors in the other enabling circuit adopt the architecture of an NAND gate circuit.

[0049] Specifically, Figure 2 A BTI test circuit using a five-stage inverter chain and a NAND gate type enable circuit is shown. In each inverter, the gate of the PMOS tube is connected to the gate of the NMOS tube, and the drain of the PMOS tube is connected to the drain of the NMOS tube, forming the basic structure of the inverter. The output of the previous stage inverter is connected to the input of the next stage inverter, and the input of each inverter and the output of the last stage inverter are respectively recorded as potential points Pad1~Padn. The sources of all PMOS tubes are connected and recorded as potential point PadA. The gates of P6 and N6 are connected to the output of the inverter chain; the drains of P6, P7, and N6 are connected and connected to the input of the inverter chain. The source of N6 is connected to the drain of N7; the source of N7 is connected to the source of all NMOS tubes in the inverter chain and recorded as potential point PadB. The gates of N7 and P7 are connected and recorded as potential point PadC.

[0050] In addition, in the BTI test circuit of this embodiment, all PMOS transistors and NMOS transistors are connected in a manner of connecting the source end and the substrate in common.

[0051] The test process of the BTI test circuit provided in this embodiment includes two stages, and the test principle is: in the first stage, the voltage V highIt is applied to the circuit, so that the PMOS tube to be tested in the inverter chain is in a higher negative bias state, or the NMOS tube to be tested in the inverter chain is in a positive bias state, and then the corresponding voltage acceleration module is used to simulate a longer working state in a shorter time. In the second stage, the input and output ports of the inverter are connected to -Vdd or +Vdd, and then the working parameters of the MOS are obtained according to the peripheral test instrument. By measuring the potential of the input node and output node in the inverter chain, the threshold voltage of each MOS tube to be tested is determined. V th and saturation drain current I dsat Then, the corresponding NBTI or PBTI effect is analyzed based on the above two electrical parameters of the MOS tube.

[0052] In practical applications, the voltage V applied to the circuit in the first stage high is a value related to the device parameters in the circuit. The -Vdd applied to the circuit in the second stage is also a value related to the device parameters in the circuit. high The value is 1.5Vdd.

[0053] Based on the above circuit principle, we can know that: Figure 2 The BTI test circuit shown can be used to measure the NBTI effect of each PMOS tube on the even-numbered bits in the inverter chain in parallel; the process includes:

[0054] 1. Bias stage

[0055] First make Pad1~Padn=Floating, and connect PadA to V high , PadB and PadC are connected to 0V; then each PMOS tube in the inverters of even-numbered positions in the inverter chain is in a negative bias state. At this time, the gate-source voltage of P2 and P4 = -Vdd, and they are subject to NBTI stress.

[0056] 2. Testing Phase

[0057] Then connect Pad1~Padn to -Vdd, PadA and PadB to 0V, and PadC = Floating, then each PMOS tube in the inverter of the even-numbered bits in the inverter chain is in the test state.

[0058] In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each PMOS tube in the inverter of the even bit V th and saturation drain current I dsat , and then analyze the NBTI effect of the corresponding PMOS tube. Among them, according to the threshold voltage of the MOS tube V thand saturation drain current I dsat The process of analyzing the NBTI and PBTI effects belongs to the mature existing technology and is not an improvement point of the solution of this embodiment, so it is not described in detail in this embodiment.

[0059] Correspondingly, Figure 2 The BTI test circuit shown can also be used to perform parallel measurement of the PBTI effects of each NMOS tube on the odd-numbered bits in the inverter chain. The process includes:

[0060] 1. Bias stage

[0061] First, connect Pad1~Padn to Floating and PadA to V high , PadB and PadC are connected to 0V; then each NMOS transistor in the odd-numbered inverters in the inverter chain is in a positive bias state. P1, P3 and P5 are subjected to PBTI stress.

[0062] 2. Testing Phase

[0063] Then connect Pad1~Padn to +Vdd, PadA and PadB to 0V, and PadC = Floating, then each NMOS tube in the odd-numbered inverters in the inverter chain is in the test state.

[0064] In the test state, measure PAD1~PAD n The potential of the inverter is calculated to find the threshold voltage of each NMOS tube in the odd-numbered inverter. V th and saturation drain current I dsat , and then analyze the PBTI characteristics of the corresponding NMOS tube.

[0065] In this embodiment, Figure 3 A BTI test circuit using a five-stage inverter chain and a NAND gate type enable circuit is shown. The circuit connection relationship of the circuit is as follows:

[0066] Each group of NMOS tubes and PMOS tubes in the inverter chain constitutes an inverter, and each inverter is cascaded in sequence. The input end of each inverter and the output end of the last inverter are respectively recorded as potential points Pad1~Padn. The source of P7 is connected to the source of each PMOS tube in the inverter chain and is recorded as potential point PadA. The drain of P7 is connected to the source of P6; the gates of P6 and N6 are connected to the output end of the inverter chain; the drains of P6, N6, and N7 are connected to the input end of the inverter chain. The sources of N6 and N7 are connected to the sources of all NMOS tubes in the inverter chain and are recorded as potential point PadB. The gates of P7 and N7 are connected and recorded as potential point PadC.

[0067] For the BTI test circuit of the NAND gate type enable circuit and the enable circuit in the BTI test circuit of the NOR gate type enable circuit, there is a difference in the encoding logic of the control signal output to the corresponding positions (PadA, PadB and PadC) in the inverter chain. Therefore, the process of testing the BTI effect of different MOS is also different.

[0068] Specifically, Figure 3 The process of the BTI test circuit shown in the figure to measure the NBTI effect of each PMOS tube on the odd bit in the inverter chain in parallel includes the following steps:

[0069] 1. Bias stage

[0070] First, connect Pad1~Padn to Floating and PadA to V high , PadB is connected to 0V, and PadC is connected to Vdd; then each PMOS tube in the odd-numbered inverters in the inverter chain is in a negative bias state; P1, P3 and P5 are subject to NBTI stress.

[0071] 2. Testing Phase

[0072] Then connect Pad1~Padn to -Vdd, PadA and PadB to 0V, and PadC = Floating, then each PMOS tube in the odd-numbered inverters in the inverter chain is in the test state.

[0073] In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each PMOS tube in the odd-bit inverter V th and saturation drain current I dsat , and then analyze the NBTI effect of the corresponding PMOS tube.

[0074] Correspondingly, Figure 3 The process of the BTI test circuit shown in the figure to perform parallel measurement of the PBTI effect of each NMOS tube on the even-numbered bit in the inverter chain includes the following steps:

[0075] 1. Bias stage

[0076] First, connect Pad1~Padn to Floating and PadA to V high , PadB is connected to 0V, and PadC is connected to Vdd; then each NMOS tube in the inverter of the even-numbered position in the inverter chain is in a positive bias state. P2 and P4 are subjected to PBTI stress.

[0077] 2. Testing Phase

[0078] Then connect Pad1~Padn to +Vdd, connect PadA and PadB to 0V, and leave PadC floating. Then, each NMOS tube in the inverters of even-numbered bits in the inverter chain is in the test state.

[0079] In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each NMOS tube in the inverter of the even bit V th and saturation drain current I dsat , and then analyze the PBTI characteristics of the corresponding NMOS tube.

[0080] Combined with the above introduction to the working principle and operation logic of the BTI test circuit designed in this invention, it can be found that by increasing the inverter technology in the inverter chain, the BTI effect of more PMOS tubes or NMOS tubes can be measured in parallel in one test task. However, in practical applications, due to the influence of metal wiring, the cascade scale of the inverter cannot be expanded infinitely. Under the premise of not affecting the circuit measurement accuracy, the number of inverters in the inverter chain should not exceed 11.

[0081] Example 2

[0082] On the basis of the scheme in Example 1, this embodiment further provides a BTI test method for MOS tubes in a wafer. The main technical idea of ​​this method is to continuously select different PMOS tubes and NMOS tubes in the circuit to be tested, and build them into any one of the BTI test circuits in Example 1, and then test the NBTI effect of several specified PMOS tubes and the PBTI effect of several specified NMOS tubes based on this BTI test circuit. After each measurement, different PMOS tubes and NMOS tubes are reselected to continue to build the BTI test circuit and perform the corresponding test task; until the test task of the BTI effect of all MOS tubes in the circuit to be tested is completed.

[0083] Specifically, Figure 4 As shown, the BTI test method for MOS transistors in a wafer provided in this embodiment includes the following process:

[0084] S1: Select several NMOS tubes and PMOS tubes to be tested as basic units of an inverter chain, and the remaining two PMOS tubes and two NMOS tubes as basic units of an enabling circuit, and connect each NMOS tube and PMOS tube through a test key to form any BTI test circuit as in Example 1.

[0085] S2: Adopting the NBTI or PBTI test strategy as in Example 1, outputting or collecting signals to each potential point, thereby achieving parallel measurement of the NBTI effects of multiple PMOS tubes at designated positions in the inverter chain.

[0086] At the same time, the strategy in the aforementioned BTI test circuit can be used to output or collect signals to each potential point as needed, thereby realizing parallel measurement of the PBTI effects of multiple NMOS transistors at designated positions in the inverter chain.

[0087] S3: adjusting the position of each MOS tube to be tested or each MOS tube in the inverter chain, repeating steps S1-S2, and thus completing the BTI test task of all MOS tubes in the wafer.

[0088] Example 3

[0089] On the basis of the above-mentioned embodiment, this embodiment further provides an IC test device, which uses the BTI test method of the MOS tube in the wafer as in embodiment 2 to test the BTI effect of each MOS tube. The IC test device includes: a test key, a voltage source, a signal acquisition module and a data analysis module.

[0090] The test key is used to construct any of the aforementioned BTI test circuits using the NMOS and PMOS transistors to be tested in the IC. The voltage source is used to input the required test signal to the corresponding potential point in the constructed BTI test circuit during the test process. The signal acquisition module is used to collect the electrical signal representing the test result at the specified potential point in the constructed BTI test circuit during the test process.

[0091] The data analysis module is used to analyze the BTI effect of each MOS tube according to the electrical signal collected by the signal acquisition module, and further infer the service life of the IC.

[0092] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A BTI test circuit, characterized in that: It includes an inverter chain composed of more than three groups of NMOS tubes and PMOS tubes in the circuit to be tested, and an enabling circuit composed of two PMOS tubes and two NMOS tubes; each group of NMOS tubes and PMOS tubes in the inverter chain constitutes an inverter, each inverter is cascaded in sequence, and the input end of each inverter and the output end of the last inverter are respectively recorded as potential points Pad1~Padn; the source electrodes of all PMOS tubes are connected and recorded as potential point PadA; the enabling circuit includes P6, P7, N6, and N7, the gate plates of P6 and N6 are connected to the output end of the inverter chain; the drain electrodes of P6, P7, and N6 are connected and connected to the input end of the inverter chain; the source electrode of N6 is connected to the drain electrode of N7; the source electrode of N7 is connected to the source electrodes of all NMOS tubes in the inverter chain and recorded as potential point PadB; the gate electrodes of N7 and P7 are connected and recorded as potential point PadC; The process of measuring the NBTI effect of each PMOS tube on the even-numbered position in the inverter chain includes: First, make Pad1~Padn float and connect PadA to V high , PadB and PadC are connected to 0V; then each PMOS tube in the inverters of even-numbered positions in the inverter chain is in a negative bias state; Then connect Pad1~Padn to -Vdd, connect PadA and PadB to 0V, and leave PadC floating. Then, each PMOS tube in the inverters of even-numbered bits in the inverter chain is in the test state. In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each PMOS tube in the inverter of the even bit V th and saturation drain current I dsat , and then analyze the NBTI effect of the corresponding PMOS tube.

2. The BTI test circuit according to claim 1, wherein: It is also used to perform parallel measurement on the PBTI effect of each NMOS tube on the odd bit in the inverter chain, and the process includes: First, make Pad1~Padn float and connect PadA to V high , PadB and PadC are connected to 0V; then each NMOS tube in the inverter of odd bits in the inverter chain is in a positive bias state; Then connect Pad1~Padn to +Vdd, connect PadA and PadB to 0V, and leave PadC floating. Then, each NMOS tube in the odd-numbered inverters in the inverter chain is in the test state. In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each NMOS tube in the odd-bit inverter V th and saturation drain current I dsat , and then analyze the PBTI characteristics of the corresponding NMOS tube.

3. A BTI test circuit, characterized in that: It comprises an inverter chain composed of more than three groups of NMOS tubes and PMOS tubes in the circuit to be tested, and an enabling circuit composed of two PMOS tubes and two NMOS tubes; each group of NMOS tubes and PMOS tubes in the inverter chain constitutes an inverter, each inverter is cascaded in sequence, and each inverter input end and the output end of the last inverter are respectively recorded as potential points Pad1~Padn; the enabling circuit comprises P6, P7, N6, and N7, the source of P7 is connected to the source of each PMOS tube in the inverter chain and is recorded as potential point PadA; the drain of P7 is connected to the source of P6; the gates of P6 and N6 are connected to the output end of the inverter chain; the drains of P6, N6, and N7 are connected to the input end of the inverter chain; the sources of N6 and N7 are connected to the sources of all NMOS tubes in the inverter chain and are recorded as potential point PadB; the gates of P7 and N7 are connected and are recorded as potential point PadC; The process of measuring the NBTI effect of each PMOS tube on the odd bit in the inverter chain includes: First, make Pad1~Padn float and connect PadA to V high , PadB is connected to 0V, and PadC is connected to Vdd; then each PMOS tube in the inverter of odd bits in the inverter chain is in a negative bias state; Then connect Pad1~Padn to -Vdd, connect PadA and PadB to 0V, and leave PadC floating. Then, each PMOS tube in the odd-numbered inverters in the inverter chain is in the test state. In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each PMOS tube in the odd-bit inverter V th and saturation drain current I dsat , and then analyze the NBTI effect of the corresponding PMOS tube.

4. The BTI test circuit according to claim 3, wherein: It is also used to perform parallel measurement on the PBTI effect of each NMOS tube on the even-numbered position in the inverter chain, and the process includes: First, make Pad1~Padn float and connect PadA to V high , PadB is connected to 0V, and PadC is connected to Vdd; then each NMOS tube in the inverter of the even-numbered position in the inverter chain is in a positive bias state; Then connect Pad1~Padn to +Vdd, connect PadA and PadB to 0V, and leave PadC floating. Then each NMOS tube in the inverters of even-numbered bits in the inverter chain is in the test state. In the test state, measure the potential of Pad1~Padn and calculate the threshold voltage of each NMOS tube in the inverter of the even bit V th and saturation drain current I dsat , and then analyze the PBTI characteristics of the corresponding NMOS tube.

5. The BTI test circuit according to claim 3, wherein: The number of inverters in the inverter chain does not exceed 11.

6. A BTI test method for MOS tubes in a wafer, comprising: S1: using a selected number of NMOS tubes and PMOS tubes to be tested as basic units constituting an inverter chain, and the remaining two PMOS tubes and two NMOS tubes as basic units of an enabling circuit, and connecting each NMOS tube and PMOS tube to form a BTI test circuit as claimed in claim 1 or 3 through a test key; S2: using the strategy in the BTI test circuit as described in claim 1 or 3 to output or collect signals to each potential point, thereby realizing parallel measurement of the NBTI effect of the PMOS tube at a specified position in the inverter chain; and / or Adopting the strategy in the BTI test circuit as described in claim 2 or 4 to output or collect signals to each potential point, thereby realizing parallel measurement of the PBTI effect of the NMOS tube at a specified position in the inverter chain; S3: adjusting the position of each MOS tube to be tested or each MOS tube in the inverter chain, and repeating steps S1-S2, thereby completing the BTI test task of all MOS tubes in the wafer.

7. An IC testing device, characterized in that: The BTI test method of the MOS tube in the wafer as claimed in claim 6 is used to test the BTI of each MOS tube; the IC test equipment comprises: A test key, which is used to construct the BTI test circuit using each NMOS tube and PMOS tube to be tested in the IC; A voltage source, which is used to input a required test signal to a corresponding potential point in the BTI test circuit during the test process; A signal acquisition module, which is used to collect electrical signals representing test results at designated potential points in the BTI test circuit during the test process; The data analysis module is used to analyze the BTI effect of each MOS tube according to the electrical signal collected by the signal collection module, and further infer the service life of the IC.

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