Lifetime Prediction Method, Device, and Computer Equipment

Abstract

The present application relates to a lifespan prediction method, apparatus, and computer device. The method includes testing the integrated current under preset test conditions to obtain the electrical stress parameters of multiple target devices in the integrated circuit during the test process. Then, based on the condition parameters of the test conditions and the electrical stress parameters of each target device, the degradation parameters of each target device are determined respectively to identify the weak device of the integrated circuit from multiple target devices. Finally, based on the short board effect, the lifespan of the integrated circuit is determined according to the lifespan of the weak device. The weak device is the most easily damaged device in the integrated circuit. Therefore, the lifespan of the weak device can truly and effectively reflect the actual lifespan of the integrated circuit. The present application finds the weak device of the integrated circuit based on the actual operating parameters of each target device during the operation of the integrated circuit, and determines the lifespan of the integrated circuit according to the lifespan of the weak device, so as to accurately predict the lifespan of the integrated circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a method, device, and computer equipment for predicting the lifespan. Background Art

[0002] With the development of science and technology, more and more integrated circuit devices are applied to the control systems, data transmission systems, and telemetry systems of aerospace devices such as Beidou-3, Shenzhou series spacecraft, and space stations. Integrated circuit devices play a crucial role in aerospace devices, and the lifespan of aerospace devices is closely related to the lifespan of the integrated circuit devices therein.

[0003] Currently, there is a lack of a method that can accurately predict the lifespan of integrated circuit devices. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a lifespan prediction method, device, and computer equipment that can accurately predict the lifespan of integrated circuit devices.

[0005] In a first aspect, this application provides a lifespan prediction method, and the method includes:

[0006] Obtain the electrical stress parameters of multiple target devices in an integrated circuit during the test under preset test conditions;

[0007] According to the condition parameters of the test conditions and the electrical stress parameters of each target device, respectively determine the degradation parameters of each target device;

[0008] Determine the weak devices among the multiple target devices according to the degradation parameters of each target device; wherein, the degradation parameters of the weak devices are greater than the degradation parameters of the remaining devices among the multiple target devices;

[0009] Determine the lifespan of the integrated circuit according to the weak devices.

[0010] In one of the embodiments, the condition parameters of the test conditions include temperature parameters, frequency parameters, and timing parameters. The step of respectively determining the degradation parameters of each target device according to the condition parameters of the test conditions and the electrical stress parameters of each target device includes:

[0011] According to the temperature parameters and the electrical stress parameters of each target device, respectively determine the lifespan of each target device under the failure mechanism;

[0012] According to the frequency parameters, the timing parameters, and the lifespan of each target device, respectively determine the degradation parameters of each target device corresponding to the failure mechanism.

[0013] In one embodiment, the electrical stress parameters include drain current, substrate current, and gate voltage, the failure mechanisms include at least one of hot carrier injection mechanism, bias temperature instability mechanism, and time-dependent dielectric breakdown mechanism, and the lifetime of the target device includes at least one of a first sub-lifetime, a second sub-lifetime, and a third sub-lifetime;

[0014] Correspondingly determining the lifetime of each of the target devices under the failure mechanism according to the temperature parameter and the electrical stress parameters of each of the target devices includes:

[0015] Respectively determining the first sub-lifetime of each of the target devices under the hot carrier injection mechanism according to the drain current and the substrate current; and / or,

[0016] Respectively determining the second sub-lifetime of each of the target devices under the bias temperature instability mechanism according to the gate voltage and the test temperature; and / or,

[0017] Respectively determining the third sub-lifetime of each of the target devices under the time-dependent dielectric breakdown mechanism according to the gate voltage and the test temperature.

[0018] In one embodiment, the test process includes a plurality of test sub-processes; correspondingly determining the lifetime of each of the target devices under the failure mechanism according to the temperature parameter and the electrical stress parameters of each of the target devices includes:

[0019] Respectively determining the lifetime of each of the devices corresponding to each of the test sub-processes under the failure mechanism according to the temperature parameter and the electrical stress parameters of each of the target devices.

[0020] In one embodiment, the test process includes a plurality of test sub-processes, and the degradation parameters include at least one of a first degradation parameter, a second degradation parameter, and a third degradation parameter; respectively determining the degradation parameter of each of the target devices corresponding to the failure mechanism according to the frequency parameter, the timing parameter, and the lifetime of each of the target devices includes:

[0021] Determining the number of the test sub-processes according to the timing parameter;

[0022] Determining the time of the test sub-processes according to the frequency parameter;

[0023] Respectively determining the first degradation parameter of each of the target devices corresponding to the hot carrier injection mechanism according to the number of the test sub-processes, the time of the test sub-processes, and the first sub-lifetime of each of the target devices; and / or,

[0024] Determine the second degradation parameter corresponding to the bias temperature instability mechanism for each of the target devices according to the number of the test sub - processes, the time of the test sub - processes, and the second sub - lifetimes of the respective target devices; and / or,

[0025] Determine the third degradation parameter corresponding to the time - dependent dielectric breakdown mechanism for each of the target devices according to the number of the test sub - processes, the time of the test sub - processes, and the third sub - lifetimes of the respective target devices.

[0026] In one embodiment, the determining the weak devices among the multiple target devices according to the degradation parameters of the respective target devices includes:

[0027] Determine the sum of the degradation parameters for each of the target devices according to the first degradation parameter and / or the second degradation parameter and / or the third degradation parameter of the respective target devices;

[0028] Determine the maximum value among the sums of the degradation parameters as the target degradation parameter;

[0029] Determine the target device corresponding to the target degradation parameter as the weak device.

[0030] In one embodiment, the determining the lifetime of the integrated circuit according to the weak device includes:

[0031] Determine the minimum value among the first sub - lifetime, the second sub - lifetime, and the third sub - lifetime of the weak device under the failure mechanism as the target lifetime of the weak device;

[0032] Determine the target lifetime of the weak device as the lifetime of the integrated circuit.

[0033] In one embodiment, the obtaining the electrical stress parameters of multiple target devices in an integrated circuit during a test under preset test conditions includes:

[0034] Obtain the preset test conditions, where the preset test conditions include a test temperature, a test frequency, and a test timing;

[0035] Under the test temperature, test the integrated circuit according to the test frequency and the test timing;

[0036] Obtain the electrical stress parameters of the target devices in the integrated circuit during the test.

[0037] In a second aspect, the present application provides a lifetime prediction device, and the device includes:

[0038] An information acquisition module, configured to acquire the electrical stress parameters of multiple devices in an integrated circuit during a test under preset test conditions;

[0039] A first determination module, configured to obtain electro - stress parameters of multiple target devices in an integrated circuit during a test under preset test conditions;

[0040] A second determination module, configured to determine a weak device among the multiple target devices according to the degradation parameters of each of the target devices; wherein, the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices;

[0041] A third determination module, configured to determine the lifetime of the integrated circuit according to the weak device.

[0042] In a third aspect, the present application provides a computer device, including a memory and a processor, where the memory stores a computer program, and is characterized in that when the processor executes the computer program, the steps of the method described in any one of the above - mentioned embodiments are implemented.

[0043] For the above - mentioned lifetime prediction method, device and computer device, first, the integrated current is tested under preset test conditions to obtain the electro - stress parameters of multiple target devices in the integrated circuit during the test. Then, according to the condition parameters of the test conditions and the electro - stress parameters of each target device, the degradation parameters of each target device are respectively determined to determine the weak device of the integrated circuit from the multiple target devices. Finally, based on the short - board effect, the lifetime of the integrated circuit is determined according to the lifetime of the weak device. The weak device is the most easily damaged device in the integrated circuit. Therefore, the lifetime of the weak device can truly and effectively reflect the actual lifetime of the integrated circuit. The present application finds the weak device of the integrated circuit based on the actual operation parameters of each target device during the operation of the integrated circuit, and determines the lifetime of the integrated circuit according to the lifetime of the weak device, which can accurately predict the lifetime of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for describing the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can be obtained based on these drawings.

[0045] Figure 1 It is a schematic flowchart of a lifetime prediction method in an embodiment;

[0046] Figure 2 It is a schematic flowchart of step S101 in an embodiment;

[0047] Figure 3 It is a schematic flowchart of step S102 in an embodiment;

[0048] Figure 4 It is a schematic flowchart of S302 in an embodiment;

[0049] Figure 5 It is a schematic flowchart of S103 in an embodiment;

[0050] Figure 6 It is a schematic flowchart of S104 in an embodiment;

[0051] Figure 7 It is a structural block diagram of a life prediction device in an embodiment;

[0052] Figure 8 It is an internal structure diagram of a computer device in an embodiment. Detailed implementation manners

[0053] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] Integrated circuit devices generally include ADC (Analog to Digital Converter) chips, DAC (Digital to Analog Converter) chips, SRAM (Static Random Access Memory), etc. In related technologies, the life of integrated circuit devices is generally predicted by methods based on reliability prediction models of mathematical statistics or methods of reliability block diagrams (RBD). The method based on the reliability prediction model of mathematical statistics uses the failure rate of the statistical industry average level as an evaluation index, and the predicted result has a large gap from the actual engineering situation; if a reliability model reflecting the functional logic relationship of integrated circuit devices is established using a reliability block diagram, since an integrated circuit device is composed of at least millions of single-transistor MOS devices, the stress received by each single transistor is different due to its different working states. If it is simply considered that the reliability model of the integrated circuit device is a series model of millions of single transistors, the working state of the single transistor cannot be accurately described. Even if the working state of each single transistor can be obtained through simulation, the workload of its simulation analysis is huge, resulting in a huge deviation between the reliability prediction result of the integrated circuit device and the actual situation.

[0055] Based on the above technical problems, the present application proposes a life prediction method that can accurately predict the life of integrated circuit devices and make the life prediction result of integrated circuit devices closer to the actual situation. In an exemplary embodiment, please refer to Figure 1, this application provides a life prediction method. Taking the integrated circuit as an SRAM memory in the following text as an example, this method includes steps S101 to S104. It can be understood that only the SRAM memory is taken as an example in this application. In applications, the life prediction method of this application is also applicable to other integrated circuit devices such as ADC chips and DAC chips.

[0056] S101: Obtain the electrical stress parameters of multiple target devices in the integrated circuit during the test under preset test conditions.

[0057] In applications, the SRAM memory usually consists of parts such as a storage array circuit, a sense amplifier circuit, a decoder circuit, a control circuit, and an input / output circuit. Among them, the storage array circuit is the core of the SRAM memory, and the transistors in it account for more than 80% of the total number of transistors in the SRAM memory. The sense amplifier circuit mainly realizes the amplification of the storage cell signal and is the key circuit for SRAM data reading. Therefore, when predicting the life of the SRAM memory, the storage array circuit and the sense amplifier circuit of the SRAM memory can be used as the target detection objects. Specifically, there are multiple transistors in the storage array circuit and the sense amplifier circuit. Therefore, each transistor in the storage array circuit and the sense amplifier circuit can be marked as a target device. After that, the SRAM memory can be controlled for reading and writing according to the preset test conditions, and the electrical stress parameters of each target device during the reading and writing control process, that is, during the test process, can be obtained.

[0058] S102: Determine the degradation parameters of each target device according to the condition parameters of the test conditions and the electrical stress parameters of each target device.

[0059] After obtaining the electrical stress parameters of each target device, the life of each target device can be calculated according to the electrical stress situation of each target device during the test process and the condition parameters of the test conditions, and then the degradation parameters of each target device can be calculated. The degradation parameter of a target device is negatively correlated with the life of the target device.

[0060] S103: Determine the weak devices among the multiple target devices according to the degradation parameters of each target device; among them, the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices.

[0061] It can be understood that the degradation parameter represents the degradation degree of the device during the test. The larger the degradation parameter of a device, the shorter the life of the device. Therefore, the target device with the shortest life, that is, the weak device, can be determined from each target device according to the degradation parameters of each target device.

[0062] S104: Determine the life of the integrated circuit according to the weak device.

[0063] Due to the existence of the short - board effect, the lifespan of the weakest circuit in the SRAM memory can determine the lifespan of the SRAM memory, and the lifespan of the weakest transistor in the circuit can determine the lifespan of the circuit. Therefore, after determining the weak device in the SRAM memory, the lifespan of the SRAM memory can be determined based on this weak device.

[0064] The above - mentioned lifespan prediction method first tests the integrated current under preset test conditions to obtain the electrical stress parameters of multiple target devices in the integrated circuit during the test process. Then, based on the condition parameters of the test conditions and the electrical stress parameters of each target device, the degradation parameters of each target device are determined respectively to identify the weak device of the integrated circuit from multiple target devices. Finally, based on the short - board effect, the lifespan of the integrated circuit can be determined according to the lifespan of the weak device. The weak device is the most easily damaged device in the integrated circuit. Therefore, the lifespan of the weak device can truly and effectively reflect the actual lifespan of the integrated circuit. This application finds the weak device of the integrated circuit based on the actual operating parameters of each target device during the operation of the integrated circuit and determines the lifespan of the integrated circuit according to the lifespan of the weak device, which can accurately predict the lifespan of the integrated circuit.

[0065] In an exemplary embodiment, refer to Figure 2 , step S101, obtaining the electrical stress parameters of multiple target devices in the integrated circuit during the test process under preset test conditions, including steps S201 to S203.

[0066] S201: Obtain the preset test conditions, where the preset test conditions include test temperature, test frequency, and test timing.

[0067] Before predicting the lifespan of the SRAM memory, the test conditions of the SRAM memory can be determined first, such as test temperature, test frequency, and test timing. In one example, the most commonly used timing of the SRAM memory can be set as the test timing of the SRAM memory. For example, "write 0, read 0, write 1, read 1" can be used as the test timing. The test temperature of the SRAM memory can be set to room temperature, such as 25°C, and the most commonly used operating frequency of the SRAM memory can be set as the test frequency.

[0068] S202: Under the test temperature, test the integrated circuit according to the test frequency and test timing.

[0069] After obtaining the test conditions, the read - write control of the SRAM memory can be performed according to the test conditions.

[0070] S203: Obtain the electrical stress parameters of the target device in the integrated circuit during the test process.

[0071] The testing process may include multiple test sub - processes. During the process of controlling the read - write operations of the SRAM memory, the electro - stress parameters of each target device in the SRAM memory during each test sub - process can be obtained, so as to predict the life of each target device based on the obtained electro - stress parameters in the subsequent process.

[0072] In an exemplary embodiment, please refer to Figure 3 , step S102, determine the degradation parameters of each target device respectively according to the condition parameters of the test conditions and the electro - stress parameters of each target device, including step S301 and step S302.

[0073] S301: Correspondingly determine the life of each target device under the failure mechanism according to the temperature parameter and the electro - stress parameters of each target device.

[0074] In this embodiment, the preset test conditions may include the ambient temperature of the SRAM memory to be tested, the operating frequency of the SRAM memory to be tested, and the test timing for testing the SRAM memory to be tested. That is, the condition parameters of the test conditions include temperature parameters, frequency parameters, and timing parameters. First, the failure mechanism of the SRAM memory can be determined, and then the life of each target device under the corresponding failure mechanism can be determined according to the temperature parameter and the electro - stress parameters of each target device.

[0075] S302: Determine the degradation parameters of each target device corresponding to the failure mechanism respectively according to the frequency parameter, the timing parameter, and the life of each target device.

[0076] After determining the life of each target device, since the degradation parameter of the target device is inversely related to the life of the target device, the degradation parameters of each target device corresponding to the failure mechanism can be calculated respectively according to the life of each target device, combined with the tested frequency parameter and timing parameter.

[0077] In an exemplary embodiment, the electro - stress parameters include drain current, substrate current, and gate voltage, the failure mechanisms include at least one of hot - carrier injection mechanism, bias - temperature instability mechanism, and time - dependent dielectric breakdown mechanism, and the life of the target device includes at least one of the first sub - life, the second sub - life, and the third sub - life.

[0078] Step S301, correspondingly determine the life of each target device under the failure mechanism according to the temperature parameter and the electro - stress parameters of each target device, including the step of determining the first sub - life of each target device under the hot - carrier injection mechanism according to the drain current and the substrate current respectively, and / or determining the second sub - life of each target device under the bias - temperature instability mechanism according to the gate voltage and the test temperature respectively, and / or determining the third sub - life of each target device under the time - dependent dielectric breakdown mechanism according to the gate voltage and the test temperature respectively.

[0079] In one example, the failure mechanisms include the hot carrier injection mechanism, the bias temperature instability mechanism, and the time-dependent dielectric breakdown mechanism.

[0080] Under the hot carrier injection mechanism, the first sub-life τ of the target device can be determined according to the drain current I D of the target device, the substrate current I sub and the first failure model. The first failure model is: HCI where ρ1 is the first constant coefficient and m is the second constant coefficient.

[0081] Under the bias temperature instability mechanism, the second sub-life τ of the target device can be determined according to the gate voltage V g of the target device, the test temperature T, and the second failure model. The second failure model is: TDDB where n is the third constant coefficient, Ea is the activation energy, and k is the Boltzmann constant.

[0082] Under the time-dependent dielectric breakdown mechanism, the third sub-life τ of the target device can be determined according to the gate voltage V g of the target device, the test temperature T, and the third failure model. The third failure model is: BTI where ρ2 is the fourth constant coefficient.

[0083] In an exemplary embodiment, step S301 of determining the life of each target device under the failure mechanism according to the temperature parameter and the electrical stress parameter of each target device further includes: determining the life of each device corresponding to each test sub-process under the failure mechanism according to the temperature parameter and the electrical stress parameter of each target device.

[0084] In an application, the test process may include multiple test sub-processes, and the number of test sub-processes is related to the test timing. Taking the test timing of "write 0, read 0, write 1, read 1" as an example, the test process includes four test sub-processes: "write 0", "read 0", "write 1", and "read 1". Obtaining the electrical stress parameters of multiple target devices in the integrated circuit during the test process under preset test conditions includes obtaining the electrical stress parameters of each target device in each test sub-process. Furthermore, for each target device, its life in each test sub-process can be calculated.

[0085] In an exemplary embodiment, the test process includes multiple test sub-processes, and the degradation parameters include at least one of the first degradation parameter, the second degradation parameter, and the third degradation parameter. Please refer to Figure 4, step S302, determine the degradation parameters corresponding to the failure mechanisms of each target device according to the frequency parameter, timing parameter, and the lifetime of each target device, including steps S401 to S405.

[0086] S401: Determine the number of test subprocesses according to the timing parameter.

[0087] It can be understood that the number of test subprocesses is related to the test timing. Assuming the test timing is "write 0, read 0, write 1, read 1" as an example, then the number of test subprocesses is four: "write 0", "read 0", "write 1", and "read 1".

[0088] S402: Determine the time of the test subprocess according to the frequency parameter.

[0089] Taking the frequency parameter f as 100 MHz, the time of the test subprocess is 1 / f = 10 ns.

[0090] S403: Determine the first degradation parameter corresponding to the hot carrier injection mechanism of each target device according to the number of test subprocesses, the time of the test subprocess, and the first sub-lifetime of each target device.

[0091] In application, the first degradation parameter of the target device in the hot carrier injection mechanism can be determined according to the number of test subprocesses, the time of the test subprocess, the first sub-lifetime of the target device, and the first formula. The first formula is where D HCI is the first degradation parameter, n is the number of test subprocesses, t c is the time of the test subprocess, and τ HCIi is the first sub-lifetime of the target device in the i-th subprocess.

[0092] S404: Determine the second degradation parameter corresponding to the bias temperature instability mechanism of each target device according to the number of test subprocesses, the time of the test subprocess, and the second sub-lifetime of each target device.

[0093] Similarly, the second degradation parameter of the target device in the hot carrier injection mechanism can be determined according to the number of test subprocesses, the time of the test subprocess, the second sub-lifetime of the target device, and the second formula. The second formula is where D TDDB is the second degradation parameter, n is the number of test subprocesses, t c is the time of the test subprocess, and τ TDDBi is the second sub-lifetime of the target device in the i-th subprocess.

[0094] S405: Determine the third degradation parameter corresponding to the time-dependent dielectric breakdown mechanism of each target device according to the number of test subprocesses, the time of the test subprocess, and the third sub-lifetime of each target device.

[0095] Similarly, the third degradation parameter of the target device under the hot carrier injection mechanism can be determined according to the number of test subprocesses, the time of the test subprocess, the third sub-life of the target device, and the third formula. The second formula is where D BTI is the third degradation parameter, n is the number of test subprocesses, t c is the time of the test subprocess, and τ BTIi is the third sub-life of the target device in the i-th subprocess.

[0096] In an exemplary embodiment, please refer to Figure 5 , step S103, determining the weak device among the multiple target devices according to the degradation parameters of each target device, including step S501 and step S502.

[0097] S501: Determine the sum of the degradation parameters of each target device according to the first degradation parameter and / or the second degradation parameter and / or the third degradation parameter of each target device respectively.

[0098] Assume that the failure mechanisms include the hot carrier injection mechanism, the bias temperature instability mechanism, and the time-dependent dielectric breakdown mechanism. After calculating the first degradation parameter, the second degradation parameter, and the third degradation parameter of each target device, the total degradation parameter of each target device, that is, the sum of the degradation parameters of each target device, can be further calculated.

[0099] S502: Determine the maximum value among the sums of the degradation parameters as the target degradation parameter, and determine the target device corresponding to the target degradation parameter as the weak device.

[0100] It can be understood that the higher the total degradation parameter of the target device, the more serious the degradation degree of the target device and the shorter the life. Therefore, the sums of the degradation parameters of each calculated target device can be sorted, and the maximum value among the sums of the degradation parameters is determined as the target degradation parameter, and the target device corresponding to the target degradation parameter is determined as the weak device.

[0101] In an exemplary embodiment, please refer to Figure 6 , step S104, determining the life of the integrated circuit according to the weak device, including step S601 and step S602.

[0102] S601: Determine the minimum value among the first sub-life, the second sub-life, and the third sub-life of the weak device under the failure mechanism as the target life of the weak device.

[0103] After determining the weak device, the first sub-lives, the second sub-lives, and the third sub-lives calculated for the weak device during the test can be sorted, and the minimum value is selected as the target life of the weak device.

[0104] S602: Determine the target lifetime of the weak device as the lifetime of the integrated circuit.

[0105] Due to the existence of the short - board effect, the lifetime of the weakest circuit in the SRAM memory can determine the lifetime of the SRAM memory, and the lifetime of the weakest transistor in the circuit can determine the lifetime of the circuit. Therefore, after determining the weak device in the SRAM memory, the target lifetime of the weak device is determined as the lifetime of the SRAM memory.

[0106] In a detailed embodiment, taking the test timing as "write 0, read 0, write 1, read 1", the temperature parameter as 25 °C, and the frequency parameter as 100 MHz as an example, Table 1 below shows the electrical stress parameters endured by some target devices in the SRAM memory during the test. It can be seen that the electrical stress parameters of these target devices B1 - B12 in the four test sub - processes are recorded in the following table. Among them, Vgd represents the gate - drain voltage of the target device, Vg represents the gate voltage of the target device, Igate represents the gate current of the target device, Id represents the drain current of the target device, and Isub represents the substrate current of the target device.

[0107] Based on the electrical stress parameters of each target device in each test sub - process, combined with the temperature parameter, frequency parameter, the above - mentioned first failure model, second failure model, and third failure model, the first sub - lifetimes τ HCI of each target device in each test sub - process can be calculated. TDDB And the second sub - lifetimes τ BTI and the third sub - lifetimes τ HCI of each target device in each test sub - process can be calculated. TDDB And the third sub - lifetimes τ BTI After that, based on the first sub - lifetimes τ

[0108] Table 1 Electrical Stress Parameter Table of Some Target Devices in SRAM Memory

[0109]

[0110] To sum up, the life prediction method of the present application can perform targeted tests on the key circuit parts of the SRAM memory, and analyze and determine the weak devices from the key circuit parts of the SRAM memory, and finally determine the life of the SRAM memory according to the life of the weak devices. Through the life prediction method of the present application, the weak parts of the SRAM memory can be analyzed in detail, and the life of the SRAM memory can be predicted more realistically.

[0111] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0112] Based on the same inventive concept, the embodiment of the present application also provides a life prediction device for implementing the life prediction method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more life prediction device embodiments provided below can refer to the limitations of the life prediction method above, and will not be repeated here.

[0113] In one embodiment, see Figure 7 The present application provides a life prediction device, which includes an information acquisition module 701, a first determination module 702, a second determination module 703 and a third determination module 704.

[0114] The information acquisition module 701 is used to acquire electrical stress parameters of multiple devices in an integrated circuit during a test process under preset test conditions.

[0115] The first determination module 702 is used to determine the degradation parameters of each of the target devices according to the condition parameters of the test conditions and the electrical stress parameters of each of the target devices.

[0116] The second determination module 703 is used to determine a weak device among the multiple target devices according to the degradation parameters of each of the target devices; wherein the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices.

[0117] The third determination module 704 is used to determine the life of the integrated circuit according to the weak components.

[0118] In one embodiment, the conditional parameters of the test conditions include a temperature parameter, a frequency parameter, and a timing parameter. The first determination module 702 includes a first determination sub-module and a second determination sub-module.

[0119] The first determination sub-module is configured to respectively determine the lifetimes of the target devices under the failure mechanism according to the temperature parameter and the electrical stress parameters of the target devices.

[0120] The second determination sub-module is configured to respectively determine the degradation parameters of the target devices corresponding to the failure mechanism according to the frequency parameter, the timing parameter, and the lifetimes of the target devices.

[0121] In one embodiment, the electrical stress parameters include a drain current, a substrate current, and a gate voltage. The failure mechanism includes at least one of a hot carrier injection mechanism, a bias temperature instability mechanism, and a time-dependent dielectric breakdown mechanism. The lifetime of the target device includes at least one of a first sub-lifetime, a second sub-lifetime, and a third sub-lifetime. The first determination sub-module includes a first determination unit.

[0122] The first determination unit is configured to respectively determine the first sub-lifetime of each target device under the hot carrier injection mechanism according to the drain current and the substrate current, and / or determine the second sub-lifetime of each target device under the bias temperature instability mechanism according to the gate voltage and the test temperature, and / or determine the third sub-lifetime of each target device under the time-dependent dielectric breakdown mechanism according to the gate voltage and the test temperature.

[0123] In one of the embodiments, the test process includes a plurality of test sub-processes. The first determination sub-module further includes: a second determination unit, and the second determination unit is configured to respectively determine the lifetimes of the devices corresponding to each test sub-process under the failure mechanism according to the temperature parameter and the electrical stress parameters of the target devices.

[0124] In one embodiment, the test process includes a plurality of test sub-processes, and the degradation parameters include at least one of a first degradation parameter, a second degradation parameter, and a third degradation parameter. The second determination sub-module includes: a third determination unit, a fourth determination unit, and a fifth determination unit.

[0125] The third determination unit is configured to determine the number of test sub-processes according to the timing parameter.

[0126] The fourth determination unit is configured to determine the time of the test sub-process according to the frequency parameter.

[0127] The fifth determination unit is configured to respectively determine a first degradation parameter corresponding to the hot carrier injection mechanism of each target device according to the number of test sub - processes, the time of the test sub - processes, and the first sub - lifetime of each target device, and / or determine a second degradation parameter corresponding to the bias temperature instability mechanism of each target device according to the number of test sub - processes, the time of the test sub - processes, and the second sub - lifetime of each target device, and / or determine a third degradation parameter corresponding to the time - dependent dielectric breakdown mechanism of each target device according to the number of test sub - processes, the time of the test sub - processes, and the third sub - lifetime of each target device.

[0128] In one embodiment, the second determination module 703 includes a third determination sub - module, a fourth determination sub - module, and a fifth determination sub - module.

[0129] The third determination sub - module is configured to respectively determine the sum of the degradation parameters of each target device according to the first degradation parameter and / or the second degradation parameter and / or the third degradation parameter of each target device.

[0130] The fourth determination sub - module is configured to determine the maximum value among the sums of the degradation parameters as the target degradation parameter.

[0131] The fifth determination sub - module is configured to determine the target device corresponding to the target degradation parameter as the weak device.

[0132] In one embodiment, the third determination module 704 includes a sixth determination sub - module and a seventh determination sub - module.

[0133] The sixth determination sub - module is configured to determine the minimum value among the first sub - lifetime, the second sub - lifetime, and the third sub - lifetime of the weak device under the failure mechanism as the target lifetime of the weak device.

[0134] The seventh determination sub - module is configured to determine the target lifetime of the weak device as the lifetime of the integrated circuit.

[0135] In one embodiment, the information acquisition module 701 includes a first acquisition sub - module, a test sub - module, and a second acquisition sub - module.

[0136] The first acquisition sub - module is configured to acquire preset test conditions, where the preset test conditions include a test temperature, a test frequency, and a test timing sequence.

[0137] The test sub - module is configured to test the integrated circuit according to the test frequency and the test timing sequence at the test temperature.

[0138] The second acquisition sub - module is configured to acquire the electrical stress parameters of the target devices in the integrated circuit during the test process.

[0139] Each module in the above life prediction device can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules can be embedded in the processor of the computer device in hardware form or independent thereof, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0140] In an exemplary embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps of the method in any of the above embodiments are implemented.

[0141] The computer device may be a terminal, and its internal structure diagram may be as Figure 8 shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used for exchanging information between the processor and external devices. The communication interface of the computer device is used for communicating with external terminals in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC), or other technologies. When the computer program is executed by the processor, a life prediction method is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covered on the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, a touchpad, or a mouse, etc.

[0142] In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in any of the above embodiments are implemented.

[0143] In an embodiment, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the steps of the method described in any of the above embodiments are implemented.

[0144] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data that have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0145] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., and are not limited thereto. The processors involved in the embodiments provided in this application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., and are not limited thereto.

[0146] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0147] The above-described embodiments merely represent several implementation manners of this application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application shall be subject to the appended claims.

Claims

1. A method for predicting lifespan, characterized in that, The method includes: Obtaining the electrical stress parameters of multiple target devices in an integrated circuit during a test under preset test conditions; Respectively determining the degradation parameters of each of the target devices according to the condition parameters of the test conditions and the electrical stress parameters of each of the target devices; the condition parameters of the test conditions include temperature parameters, frequency parameters, and timing parameters; Determining the weak devices among the multiple target devices according to the degradation parameters of each of the target devices; wherein, the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices; Determining the lifetime of the integrated circuit according to the weak device; The step of respectively determining the degradation parameters of each of the target devices according to the condition parameters of the test conditions and the electrical stress parameters of each of the target devices includes: Correspondingly determining the lifetime of each of the target devices under the failure mechanism according to the temperature parameter and the electrical stress parameters of each of the target devices; Respectively determining the degradation parameters of each of the target devices corresponding to the failure mechanism according to the frequency parameter, the timing parameter, and the lifetime of each of the target devices.

2. The life prediction method according to claim 1, wherein, The electrical stress parameters include drain current, substrate current, and gate voltage, the failure mechanism includes at least one of the hot carrier injection mechanism, the bias temperature instability mechanism, and the time-dependent dielectric breakdown mechanism, and the lifetime of the target device includes at least one of a first sub-lifetime, a second sub-lifetime, and a third sub-lifetime; The step of correspondingly determining the lifetime of each of the target devices under the failure mechanism according to the temperature parameter and the electrical stress parameters of each of the target devices includes: Respectively determining the first sub-lifetime of each of the target devices under the hot carrier injection mechanism according to the drain current and the substrate current; and / or Respectively determining the second sub-lifetime of each of the target devices under the bias temperature instability mechanism according to the gate voltage and the test temperature; and / or Respectively determining the third sub-lifetime of each of the target devices under the time-dependent dielectric breakdown mechanism according to the gate voltage and the test temperature.

3. The life prediction method according to claim 1, wherein The test process includes multiple test sub-processes; The step of correspondingly determining the lifetime of each of the target devices under the failure mechanism according to the temperature parameter and the electrical stress parameters of each of the target devices includes: Respectively determining the lifetime of each of the devices corresponding to each of the test sub-processes under the failure mechanism according to the temperature parameter and the electrical stress parameters of each of the target devices.

4. The life prediction method according to claim 2, wherein The test process includes multiple test sub-processes, and the degradation parameter includes at least one of a first degradation parameter, a second degradation parameter, and a third degradation parameter; the step of respectively determining the degradation parameters of each of the target devices corresponding to the failure mechanism according to the frequency parameter, the timing parameter, and the lifetime of each of the target devices includes: Determining the number of the test sub-processes according to the timing parameter; Determining the time of the test sub-process according to the frequency parameter; Respectively determining the first degradation parameter of each of the target devices corresponding to the hot carrier injection mechanism according to the number of the test sub-processes, the time of the test sub-process, and the first sub-lifetime of each of the target devices; and / or Determine the second degradation parameter corresponding to the bias temperature instability mechanism for each of the target devices respectively according to the number of the test subprocesses, the time of the test subprocesses, and the second sub-lifetimes of the target devices; and / or, Determine the third degradation parameter corresponding to the time-dependent dielectric breakdown mechanism for each of the target devices respectively according to the number of the test subprocesses, the time of the test subprocesses, and the third sub-lifetimes of the target devices.

5. The life prediction method according to claim 4, wherein The determining the weak devices among the multiple target devices according to the degradation parameters of the target devices includes: Determine the sum of the degradation parameters of each of the target devices respectively according to the first degradation parameter and / or the second degradation parameter and / or the third degradation parameter of each of the target devices; Determine the maximum value among the sums of the degradation parameters as the target degradation parameter; Determine the target device corresponding to the target degradation parameter as the weak device.

6. The life prediction method according to claim 2, wherein The determining the lifetime of the integrated circuit according to the weak device includes: Determine the minimum value among the first sub-lifetime, the second sub-lifetime, and the third sub-lifetime of the weak device under the failure mechanism as the target lifetime of the weak device; Determine the target lifetime of the weak device as the lifetime of the integrated circuit.

7. The life prediction method according to any one of claims 1-6, characterized in that The obtaining the electro-stress parameters of multiple target devices in an integrated circuit during a test under preset test conditions includes: Obtain the preset test conditions, where the preset test conditions include a test temperature, a test frequency, and a test timing sequence; Under the test temperature, test the integrated circuit according to the test frequency and the test timing sequence; Obtain the electro-stress parameters of the target devices in the integrated circuit during the test.

8. A device for predicting lifespan, characterized in that, The apparatus includes: An information acquisition module, configured to obtain the electro-stress parameters of multiple target devices in an integrated circuit during a test under preset test conditions; A first determination module, configured to determine the degradation parameters of each of the target devices respectively according to the condition parameters of the test conditions and the electro-stress parameters of the target devices; the condition parameters of the test conditions include a temperature parameter, a frequency parameter, and a timing parameter; A second determination module, configured to determine the weak devices among the multiple target devices according to the degradation parameters of the target devices; wherein, the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices; A third determination module, configured to determine the lifetime of the integrated circuit according to the weak device; The first determination module includes a first determination sub-module and a second determination sub-module; The first determination sub-module is configured to determine the lifetime of each of the target devices under the failure mechanism respectively according to the temperature parameter and the electro-stress parameters of the target devices; The second determination sub-module is configured to determine the degradation parameters of each of the target devices corresponding to the failure mechanism respectively according to the frequency parameter, the timing parameter, and the lifetimes of the target devices.

9. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

Images