Signal processing method, corresponding circuit, device, radar system and vehicle

Abstract

The embodiment of the invention relates to a signal processing method, a corresponding circuit, equipment, a radar system and a vehicle. A first signal processing is applied to a first input signal oscillating at an input frequency and the first set of control signals to generate a first output signal oscillating at a multiple of the input frequency, the first output signal having an amplitude controlled by a control signal of the first set of control signals. A second signal processing is applied to a second input signal that oscillates orthogonally at the input frequency and the second set of control signals to generate a second output signal that oscillates at a multiple of the input frequency, the second output signal having an amplitude controlled by a control signal of the second set of control signals. Other output signals generated in response to the first output signal and the second output signal oscillate at a multiple of the input frequency, the other output signals having a phase shift controlled by a ratio of a control signal amplitude of the first set of control signals to a control signal amplitude of the second set of control signals.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000016764, filed on August 4, 2023, the contents of which are hereby incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The description relates to circuits and systems for providing radio frequency (RF) signals, such as, for example, frequency multiplier circuit arrangements.

[0004] One or more embodiments may be applied, for example, in automotive radar applications. Background Art

[0005] The increasing demand for higher driving safety standards has led to the widespread adoption of advanced driver assistance systems (ADAS) in the automotive sector.

[0006] ADAS implements a control system that may employ several sensors (eg, radar sensors) to provide functions such as, for example, adaptive cruise control, collision avoidance, parking assistance.

[0007] Vehicles may include multiple radar sensors to detect the position and speed of nearby objects. For example, a radar sensor may operate by transmitting a signal and receiving an echo signal reflected by a nearby object. The signal is, for example, a millimeter wave (1 millimeter = 1 mm = 10 -3 meters) signal (according to ETSI standard, it is 77GHz, where 1GHz = 1GigaHertz = 10 9 Hz).

[0008] In radars operating in the millimeter-wave range, a resonator-based approach (ie, LC tank) helps reduce the power consumption in generating the signal to be transmitted.

[0009] At the same time, for example, for a radar system configured to be equipped onboard an autonomous vehicle, the beam scanning resolution is a figure of merit of the radar system.

[0010] To provide high beam scanning resolution, the phase shift accuracy of the phase shifter becomes relevant in the signal processing chain of the radar system.

[0011] Phase shifters are mainly classified into active phase shifters and passive phase shifters.

[0012] Passive phase shifters employ variable physical delays based on switchable filters or tunable transmission lines.

[0013] Reference is made to the following documents (all of which are incorporated by reference):

[0014] (1) M. Jung, et al., “A Compact Ka-Band 4-bit Phase Shifter With Low Group Delay Deviation,” IEEE Microwave and Wireless Components Letters, vol. 30, no. 4, pp. 414-416, April 2020, doi: 10.1109 / LMWC.2020.2975108, which discusses a compact Ka-band 4-bit switching phase shifter with low group delay deviation (GDD) using 28 nm CMOS technology, in which a magnetically coupled all-pass network (APN) configuration is adopted to achieve both equal group delay characteristics and flat group delay characteristics with respect to frequency in each phase state;

[0015] (2) W. H. Woods, et al., “CMOS millimeter wave phase shifter based on tunable transmission lines,” Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, 2013, pp. 1-4, doi: 10.1109 / CICC.2013.6658442, which discusses a tunable transmission line (T-line) structure characterized by independent control of the line inductance and capacitance. The T-line uses direct digital control with FET switches to provide variable delay while maintaining a relatively constant characteristic impedance, wherein a 50 GHz RF phase shifter for phased array applications is implemented in a 32 nm SOI process, achieving state-of-the-art performance; and

[0016] (3) S. Kishimoto, et al., “A 79 GHz 13.5 dBm P sat at 150 °C transmitter with compact local phase shifter in 40 nm CMOS for automotive radar,” Proc. IEEE 20th Topical Meeting Silicon Monolithic Integr. Circuits RF Syst. (SiRF), pp. 66-69, 2020, which discusses passive phase shifters in which the output phase can be changed by adjusting the impedance of the reflective load.

[0017] The active phase shifter includes a vector modulator configured to provide a variable output phase by performing (eg, weighting) a sum of quadrature I / Q signals, wherein the phase of the output signal can be changed by adjusting the gain of a variable gain amplifier in the processing chain.

[0018] Reference is made to the following documents (all of which are incorporated by reference):

[0019] (4) Shimura, Toshihiro et al. “A 76–81GHz active phase shifter for phased array automotive radar in 65nm CMOS,” 2013 European Microwave Integrated Circuit Conference (2013): 252-255. This paper discusses a 65nm CMOS active phase shifter for phased array radar systems, covering dual radar bands of 76GHz and 79GHzd, using a vector combination method to achieve 360-degree phase change. The 4-phase orthogonal signals are generated using a coupled linear 90-degree hybrid circuit and two single differential amplifiers, which are designed using a neutralization technique and achieve stability and gain enhancement over a wide frequency range.

[0020] (5) F.Akbar, et al., “A frequency tunable 350° analog CMOS phase shifter with an adjustable amplitude,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 12, pp. 1427-1431, Dec. 2017, doi: 10.1109 / TCSII.2017.2766662, which discusses a vector sum phase shifter topology using a current-mode RC polyphase filter together with several current-steering variable gain amplifiers, where the phase shifter can generate a signal with adjustable phase and amplitude in a phased array, thereby providing better control of beamwidth and sidelobe levels; and

[0021] (6) B. Dou, et al., “A 4–10 GHz Programmable CMOS Vector-Sum Phase Shifter for a Two-Channel Transmitter,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 9, pp. 3699-3703, Sept. 2022, doi: 10.1109 / TCSII.2022.3173042, which discusses a 6-bit full-span programmable vector sum phase shifter in which a transformer-based matching network is used to match a PPF-based I / Q generator with a variable gain amplifier-based vector modulator (VGA-based VM), eliminating the performance degradation due to impedance mismatch, and in which the proposed phase shifter is integrated in a two-channel transmitter implemented in a 180 nm CMOS process.

[0022] Conventional phase shifters suffer from one or more of the following disadvantages: limited ability to reduce phase error when operating in the millimeter wave range; limited robustness of active phase shifters to PVT variations; passive phase shifters occupy increased area on the chip; and both passive and active phase shifters exhibit non-negligible power consumption.

[0023] There is a need in the art for contributions that overcome one or more limitations of the current technology. Summary of the invention

[0024] One or more embodiments may be directed to a method.

[0025] One or more embodiments may be directed to corresponding circuits.

[0026] One or more embodiments may be directed to a corresponding apparatus.

[0027] One or more embodiments may be directed to a corresponding system.

[0028] For example, a radar system equipped on a vehicle may be an example of such a system.

[0029] One or more embodiments contemplate a phase shifter that includes an embedded frequency doubler functionality.

[0030] One or more embodiments help reduce both silicon area usage and power consumption.

[0031] In one or more embodiments, the phase locked loop and / or other circuit elements operate at a fraction of the frequency to counteract the frequency pulling from the power amplifier. This can also relax circuit design constraints and power consumption.

[0032] One or more embodiments provide a phase shifter capable of performing phase shifting and frequency doubling operations simultaneously.

[0033] For example, the proposed phase shifter provides the Nth harmonic of the input signal as an output signal while applying a variable phase shift (eg, from 0° to 360°) to the output signal via a bias current control.

[0034] In one or more embodiments, the phase shift operation is independent of input voltage amplitude and / or supply voltage, thereby extending circuit robustness over process-voltage-temperature (PVT) variations. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0036] Figure 1 is a graphic illustration of the method;

[0037] Figure 2 is a diagrammatic illustration of a circuit;

[0038] Figure 3A , Figure 3B and Figure 3C is a diagrammatic illustration of a frequency multiplication principle associated with one or more embodiments;

[0039] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a graphical illustration of a phase shifting principle associated with one or more embodiments;

[0040] Figure 5 is a diagrammatic illustration of a circuit;

[0041] Figure 6 and Figure 7 is a graphical illustration of the phase and amplitude of a signal in one or more embodiments; and

[0042] Figure 8 is a diagram illustrating a radar system that is equipped on a vehicle. DETAILED DESCRIPTION

[0043] Corresponding reference numerals in the different figures generally refer to corresponding parts unless otherwise indicated.

[0044] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0045] The edges of features drawn in the figures do not necessarily indicate the end of the feature's extent.

[0046] In the following description, one or more specific details are illustrated to provide a deeper understanding of the described embodiment examples. The embodiments can be obtained without one or more specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that some aspects of such embodiments are not obscured.

[0047] Reference to "embodiment" or "one embodiment" in the framework of this description is intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" may appear in one or more points of this description and do not necessarily refer to the same embodiment.

[0048] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0049] The reference signs used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0050] For simplicity, in the following detailed description, the same reference numerals are used to indicate both a node / line in a circuit and a signal that may appear on that node or line.

[0051] like Figure 1 As illustrated, the device 10 according to the present disclosure includes: a radio frequency RF signal generator, the radio frequency RF signal generator is configured to generate a first radio frequency signal V1 having a first signal frequency f0; and an orthogonal generator 11, the orthogonal generator 11 is configured to provide a second radio frequency signal V2 as a preamble of the first radio frequency signal V1. In other words, the second input signal V2 is in orthogonality with the first input signal V1 (i.e., offset by 90°).

[0052] For example, the first input signal V1 and the second input signal V2 can be expressed as:

[0053] V1=A·sin(2πf0)

[0054] V2=A·cos(2πf0)

[0055] like Figure 1As illustrated, the device 10 also includes a signal processing circuit device 20, 50, the signal processing circuit device 20, 50 includes a first frequency converter circuit 121, the first frequency converter circuit 121 includes a first input node IN1 coupled to the RF signal generator and is configured to receive a first input signal V1 from the RF signal generator, the first frequency converter circuit 121 also includes a first control node PC1 and a first output node O1, the first control node PC1 is configured to receive a first group of control signals B1 (for example, a first bias current signal), and the first output node O1 is configured to provide an output signal, the output signal frequency and phase of which are based on the first input signal V1 and the amplitude / intensity of the first group of control signals B1, as discussed below. The first frequency converter circuit 121 also includes a second frequency converter circuit 122, the second frequency converter circuit 122 includes a second input node IN2, the second input node IN2 is coupled to the RF signal generator and is configured to receive the second input signal V2 from the RF signal generator, the second frequency converter circuit 122 also includes a second control node PC2 and a second output node O2, the second control node PC2 is configured to receive the second set of control signals B2 (e.g., the second bias current signal), and the second output node O2 is configured to provide an output signal, the output signal frequency and phase of the output signal are based on the second input signal V2 and the amplitude / intensity of the second set of control signals B2, as discussed below. The output circuit block 14 (e.g., such as a resonant circuit LC tuned at a harmonic of the input signal frequency f0) is coupled to the first frequency converter circuit 121 and the second frequency converter circuit 122 to receive the first output signal O1 and the second output cycle O2 (e.g., the output current signal I O1 ,I O2 ), and the output circuit block 14 is configured to apply signal combination (eg, superposition or subtraction) to the first output signal O1 and the second output signal O2 to provide a frequency-multiplied and phase-shifted signal OUT to the user circuit.

[0056] For example, the first and second sets of control signals B1 have different (eg, signal strength) values.For example, the phase shift introduced by the device 10 on the output signal OUT varies (eg, varies linearly) according to the ratio of the control signals B1, B2.

[0057] For example, the first output signal O1 generated by the first frequency converter circuit 121 and the second output signal O2 generated by the second frequency converter circuit 122 may be expressed as:

[0058] O1=B1·sin(2πNf0)

[0059] O2=B2·cos(2πNf0)

[0060] Where N is the frequency multiplication factor.

[0061] For example, the other output signal OUT generated by the output circuit block 14 by combining (eg, adding or subtracting) the output signals O1, O2 can be expressed as:

[0062] OUT=B·sin(2πNf0+θ)

[0063] Where B is the RMS value of control signals B1 and B2 (i.e., ), and Θ is the phase shift of the output signal.

[0064] For simplicity, one or more embodiments are discussed herein primarily with reference to switches comprising n-channel MOSFET switches, otherwise it is to be understood that such types of switches are merely illustrative and non-limiting. One or more embodiments may employ p-channel MOSFETs or BJTs or virtually any other type of transistor switches known per se.

[0065] The method illustrated herein comprises: receiving a first input signal V1 at IN1 oscillating at an input frequency f0; receiving a first group of control signals B1 at PC1; receiving a second input signal V2 at IN2, the second input signal V2 oscillating at the input frequency and being orthogonal to the first input signal; receiving a second group of control signals B2 at PC2; applying a first signal processing 121, 521 to the first input signal and a control signal in the first group of control signals, thereby providing a first output signal O1 as a result, the first output signal oscillating at an output frequency and having an output signal amplitude, the output frequency being based on the input frequency, the output signal amplitude being based on the amplitude of at least one first control signal IB1 in the first group of control signals; applying a second signal processing 121, 521 to the first input signal and a control signal in the first group of control signals 2, 522 is applied to the second input signal and the control signal in the second group of control signals, thereby providing a second output signal O2 as a result, the second output signal oscillating at a second output frequency equal to the first output frequency and having an output signal amplitude, which output signal amplitude is based on the amplitude of at least one second control signal IB2 in the second group of control signals; and based on the first output signal and the second output signal, providing 14 other output signal OUT, the other output signal OUT oscillating at an output signal frequency equal to the first output frequency and having a phase shift, which phase shift is based on the ratio of the signal amplitude of at least one control signal in the first group of control signals to the signal amplitude of at least one control signal in the second group of control signals.

[0066] As illustrated herein, the control signals in the first group of control signals B1 and the second group of control signals B2 include a bias current signal I B1 ,I B2And the other output signal OUT has a phase shift θ, which is based on the ratio of the current strength of at least one bias current signal in the first set of control signals to the current strength of at least one bias current signal in the second set of control signals.

[0067] The circuit 20, 50 illustrated herein includes: a first set of input nodes IN 11 , IN 21 ;IN 23 , IN 14 , the first set of input nodes is configured to receive a first input signal V1 oscillating at an input frequency f0; a first set of control nodes PC1; PC 12 、PC 34 , the first group of control nodes is configured to receive the first group of control signals B1; the second group of input nodes IN 12 , IN 22 ;IN 32 , IN 41 , the second set of input nodes is configured to receive a second input signal V2, the second input signal V2 oscillating at the input frequency and being orthogonal to the first input signal; a second set of control nodes PC2; PC 21 、PC 34 , the second group of control nodes is configured to receive a second group of control signals B2; and a signal processing circuit device 121, 122; 521, 522, which is coupled to the first group of input nodes, the first group of control nodes, the second group of input nodes and the second group of control nodes, and has other output circuit blocks 14; wherein the signal processing circuit device is configured to provide other output signals OUT at the other output nodes according to the method illustrated in this document, and the other output signals oscillate at an output signal frequency equal to the first output frequency and have a phase shift, which is based on the ratio of the signal amplitude of at least one first control signal in the first group of control signals to the signal amplitude of at least one second control signal in the second group of control signals.

[0068] The circuit 20; 50 illustrated herein may be included in a device 10 further comprising a frequency synthesizer LO, 11 coupled to the circuit and configured to provide an input signal oscillating at an input frequency to the circuit.

[0069] For example, the frequency synthesizer LO, 11 is configured to provide said input signal oscillating at an input frequency such that the output frequency of the other signal lies in the millimeter wavelength range.

[0070] The system illustrated herein includes: a device 10 according to the present disclosure; a power amplifier 180, which is coupled to the circuit and configured to receive other output signals from the circuit, the power amplifier is configured to amplify the other output signals and provide an amplified output signal TX as a result; and a transmitter antenna 20, which is coupled to the power amplifier and configured to transmit the amplified output signal. For example, the system includes a vehicle-mounted radar system.

[0071] As illustrated herein, a vehicle V may be equipped with an onboard radar system comprising: a receiver antenna 22 configured to receive an echo signal based on a transmitted amplified output signal; and a mixer stage 28 coupled to a circuit according to the present disclosure, the mixer stage 28 configured to apply frequency mixing to other output signals and the echo signal, thereby producing a mixed signal as a result.

[0072] exist Figure 2 In the first exemplary scenario shown, the signal processing circuit device 20 according to the present disclosure includes a first (eg, fully) differential pair M of switches. 11 、M 21 , the first differential pair of switches includes a first (eg, n-channel MOSFET) switch M 11 and a second (eg, n-channel MOSFET) switch M 21 , the first differential pair of switches is configured to have a voltage applied to the switch control node IN 11 , IN 21 and is coupled to a first bias (eg, current) signal generator 1210 referenced to ground GND to receive a first bias (eg, current) signal I from the first bias signal generator 1210. B1 , the first differential pair of switches M 11 、M 21 is configured to provide a differential output signal between the differential output nodes O1 and O2; for example, the first switch M 11 A first control node IN 11 , a first output node O1 and a first source node PC1, the first source node PC1 is coupled to the second switch M 21 The second source node of the second switch M 21 With a corresponding second control node IN 21 and a second output node O2. The signal processing circuit arrangement 20 also includes a second (eg, fully) differential pair M of switches. 12 、M 22 , the second differential pair of switches includes a third (eg, n-channel MOSFET) switch M 12and a fourth (eg, n-channel MOSFET) switch M 22 , the second (eg, full) differential pair of switches is configured to have a voltage applied to the switch control node IN 12 , IN 22 and is coupled to a second bias (eg, current) signal generator 1220 referenced to ground GND to receive a second bias (eg, current) signal I from the second bias signal generator 1220. B2 , the second differential pair of switches M 12 、M 22 is configured to provide a differential output signal between the differential output nodes O1 and O2; for example, the third switch M 12 A third control node IN 12 , a third output node and a third source node PC2, the third source node PC2 is coupled to the fourth switch M 22 The fourth source node of the fourth switch M 22 With a corresponding fourth control node IN 22 and a fourth output node.

[0073] like Figure 2 As shown, the first differential pair M 11 、M 21 The first output node O1 is coupled to the second differential pair M 12 、M 22 The third output node of the first differential pair M 11 、M 21 The second output node O2 is coupled to the second differential pair M 12 、M 22 The fourth output node of .

[0074] like Figure 2 As illustrated, the first frequency converter circuit 121 and the second frequency converter circuit 122 are coupled to a load circuit set Z1, Z2, the load circuit set including: a first load circuit Z1, the first load circuit Z1 including a first RLC network, for example, including a first resistance element R1 connected in parallel with a first capacitance element C1 and a first inductance element L1; and a second load circuit Z2, the second load circuit Z2 including a second RLC network, for example, including a second resistance element R2 connected in parallel with a second capacitance element C2 and a second inductance element L2.

[0075] like Figure 2 As illustrated, the load circuits Z1, Z2 are coupled to a bias node VDD configured to provide a supply voltage VDD, and have circuit output nodes O1, O2, which are configured to provide an output signal OUT as a differential output signal I provided by the frequency converter circuits 121, 122.O1 ,I O2 By combining (eg, superposing) the output signal OUT has a frequency based on (eg, a multiple of) the input frequency f0 of the input signals V1 and V2.

[0076] To this end, based on the relationship between resonant frequency and capacitance / inductance (which can be expressed as ω=1 / √LC), the passive electrical components L1, C1 in the first load circuit Z1 and the passive electrical components L2, C2 in the second load circuit Z2 are tuned at the desired Nth harmonic of the input signal frequency f0.

[0077] like Figure 2 As shown, the intensity I of the current generated by the current generators 1210 and 1220 is O1 ,I O2 Can be changed by the user depending on the application. For example, for current I O1 ,I O2 Setting different strength values ​​introduces a phase difference between the signals output from the first frequency converter circuit 121 and the second frequency converter circuit 122, as discussed below.

[0078] For example, the phase shift is a result of the combination (eg, addition or difference) of the output current signals generated by each differential circuit 121 , 122 at the output circuit block 14 (eg, via the resonant loads Z1 , Z2 ).

[0079] The method of driving the circuit 20 according to the present disclosure includes: 11 、M 21 The control node IN 11 , IN 21 A first input signal V1 is applied to drive the first differential pair M 11 、M 21 , alternatively, through the first switch M 11 The current flow path is conductive, and at the same time, the second switch M 21 The current flow path is non-conductive; and by 12 、M 22 The control node IN 12 , IN 22 A second input signal V2 (orthogonal to the first input signal V1) is applied to drive the second differential pair M 12 、M 22 , alternatively, through the fourth switch M 22 The current flow path is conductive, and at the same time, the third switch M 12 The current flow path is not conductive.

[0080] As a result, the first bias current signal I generated by the first current generator 1210 isB1 and the second bias current signal I generated by the second current generator 1220 B2 Each is multiplied by a square wave of unit amplitude.

[0081] Therefore, the first output current signal I O1 A square wave output is included, which includes odd harmonics of the first input signal V1.

[0082]

[0083] Among them I B1 is the bias current provided by the first current generator 1210 .

[0084] Similarly, the second output current signal I O2 The square wave output includes odd harmonics of the second input signal V2, and the second output current signal I O2 can be expressed as:

[0085]

[0086] like Figure 2 As illustrated, the LC resonant loads Z1, Z2 filter the unwanted (odd order) harmonics.

[0087] like Figure 1 and Figure 2 As illustrated, by tuning the LC resonant loads Z1, Z2 at the (2N+1)th harmonic of the input signal V1, a frequency multiplier circuit 10, 50 having an odd multiplication factor of (2N+1) can be obtained. The (2N+1)th harmonic of the input signal V1 can be expressed as:

[0088]

[0089] Figure 3A-3C is a graphical illustration of the spectral content of the frequency-multiplied signal at different multiples of the input signal frequency f0.

[0090] For example, by tuning the LC resonator at the third harmonic of the input signal Vi, a frequency multiplier circuit 10, 20 with a multiplication factor of 3 can be obtained. In such an exemplary case, the i-th differential output signal I Oi can be expressed as:

[0091]

[0092] For example, if the input signal Vi has an input signal frequency f0 of about 26 GHz, the multiplier circuit 20 with a multiplication factor of 3 can provide an output signal OUT having an output signal frequency f0 of about 78 GHz.OUT .

[0093] Figure 3A is a graphical illustration of the spectral content of the frequency multiplied signal at frequency multiples of 3 times the input signal frequency f0.

[0094] In another exemplary scenario, the 5-frequency multiplier is obtained by tuning the LC resonator at the 5th harmonic of the input signal Vi. In such an exemplary case, the i-th differential output signal I Oi can be expressed as:

[0095]

[0096] Figure 3B is a graphical illustration of the spectral content of the frequency multiplied signal at 5 frequency multiples of the input signal frequency f0.

[0097] like Figure 4A-4B As shown, the differential output current of the two circuit units receiving the orthogonal input signals V1 and V2 includes two orthogonal vectors I O1 ,I O2 The strength of the sum can be adjusted by changing the bias current I provided by the corresponding bias current generators 1210 and 1220. B1 ,I B2 To modulate.

[0098] For example, the output signal I O1 ,I O2 The current intensity can be expressed as:

[0099]

[0100]

[0101] Output current signal I O The current intensity can be expressed as the output current signal I O1 ,I O2 The sum, such as:

[0102]

[0103] like Figure 1 and Figure 2 As shown, the output voltage signal OUT is equal to the differential voltage at nodes O1 and O2. Figure 2 As illustrated, the output voltage can be expressed as OUT=Io×R, where Io is the output current, and R can be expressed as R=R1+R2, where the resonant networks L1C1 and L2C2 resonate at a frequency f, and the frequency f is an odd multiple of the input frequency f0, that is, f=(2N+1)*f o .

[0104] As illustrated herein, the method of operating the circuits 10, 20 includes: based on the differential output signal I output by the corresponding circuit units 121, 122 O1 ,I O2 to perform phase shift. For example, and the current I O (which can be expressed as I O =I O1 +I O2 ) Based on two vectors I O1 ,I O2 The sum of two vectors I O1 ,I O2 orthogonal and have different amplitudes / strengths, thereby changing the sum signal OUT I O phase shift.

[0105] For example, performing phase shifting includes converting the bias current I generated by the bias generators 1211 and 1221 to B1 ,I B2 The ratio of the intensities is set to have a ratio equal to the tangent of the phase shift angle θ, so that based on the differential output signal I O1 ,I O2 Provides and signal OUT I O A linear phase shift is the result.

[0106] like Figure 4A As illustrated, if the introduced phase shift θ falls within the range of 0° to 90°, the ratio of the bias current intensities can be expressed as:

[0107]

[0108] In other words, the phase shift θ of the output signal OUT caused by the differential voltage signal based on the first output signal O1 and the second output signal O2 is based on the ratio of the signal amplitudes of the control signal (for example, equal to the current intensity in the case of the bias current signal), which can be expressed as:

[0109]

[0110] Where arctan is the inverse function of the trigonometric tangent function.

[0111] In such an exemplary scenario, the first intensity I of the bias current generated by the first bias current generator 1211 is B1 can be expressed as:

[0112] I B1 =I B ·cosθ

[0113] Still in the exemplary scenario under consideration, the second intensity I of the bias current generated by the second bias current generator 1211 is B2 can be expressed as:

[0114] I B2 =I B sinθ

[0115] Therefore, the output current signal has an output current intensity I O , output current intensity I O can be expressed as:

[0116]

[0117] Using triangular equivalence, the output current intensity I of the output signal OUT O can be expressed as:

[0118]

[0119] Since the bias current is used to vary the phase shift, the illustrated circuits and methods help to improve robustness to PVT variations.

[0120] like Figure 2 The illustrated arrangement facilitates varying the phase shift θ of the output signal OUT within at least one quadrant of the rotation angle.

[0121] For example, by changing the bias current I B1 ,I B2 The sign and magnitude of the phase shift can also be changed within the entire rotation angle (i.e., within the linear phase shift angle value range of 0° to 360°).

[0122] FIG. 4B to FIG. 4D This is an example of the total current I O Represented as a graph of a vector, the orientation of the vector in the complex plane is the first output signal I O1 and the second output signal I O2 The first output signal I O1 and the second output signal I O2 The relative orientation of the bias current I B1 ,I B2 And changes.

[0123] exist Figure 5 In the alternative scenario illustrated in FIG. 1 , an alternative circuit 50 for use in device 10 includes: Figure 2The first frequency converter circuit 121 and the second frequency converter circuit 122 in the circuit 20 illustrated in FIG. 1 are: a first alternative (e.g., double-balanced) frequency converter circuit 521, the first alternative (e.g., double-balanced) frequency converter circuit 521 including a Gilbert cell-like arrangement including a switch (e.g., an n-channel MOSFET) Q 11 , Q 12 , Q 13 , Q 14 Two differential pairs (two pairs) of Figure 2 The first differential pair M shown in 11 、M 21 Each differential pair of the arrangement preserves the manner in which the control nodes of the switches are driven, as discussed below; and a second alternative (e.g., double-balanced) frequency converter circuit 522, the second alternative (e.g., double-balanced) frequency converter circuit 522 including other Gilbert cell-like arrangements including switches (e.g., n-channel MOSFETs) Q 21 , Q 22 , Q 23 , Q 24 The two other differential pairs (two other pairs) of Figure 2 The second differential pair M shown in 12 、M 22 Each other differential pair of the arrangement preserves the manner in which the control nodes of the switches are driven, as discussed below.

[0124] like Figure 5 As shown, the first alternative frequency converter circuit 521 includes: a first differential pair of switches Q 11 , Q 12 , the first differential pair of switches includes a first switch Q 11 , the first switch Q 11 With the fourth switch Q 14 The corresponding control node is coupled to the control node IN 14 And the second switch Q 12 The corresponding bias node is coupled to the first bias node PC 12 , the second switch Q 12 With the third switch Q 13 The corresponding control node is coupled to the control node IN 23 ; and the second differential pair of switches Q 13 , Q 14 , the second differential pair of switches includes a third switch Q 13 , the third switch Q 13 With the first differential pair Q 11 , Q 12The second switch Q 12 The control node is coupled to the control node IN 23 And the fourth switch Q 14 The bias node is coupled to the second bias node PC 34 , the fourth switch Q 14 With the first differential pair Q 11 , Q 12 The first switch Q 11 The corresponding control node is coupled to the control node IN 14 The first bias current generator 5211 is coupled to the first differential pair Q 11 , Q 12 The first bias node PC 12 , to the first bias node PC 12 Provide a first bias current I B11 , and the second bias current generator 5212 is coupled to the second differential pair Q 13 , Q 14 The second bias node PC 34 , to the second bias node PC 34 Provides a second bias current I B22 .

[0125] like Figure 5 As shown, the second alternative frequency converter circuit 522 includes: a third differential pair of switches Q 21 , Q 22 , the third differential pair of switches includes a fifth switch Q 21 , the fifth switch Q 21 With the eighth switch Q 24 The corresponding control node is coupled to the control node IN 41 and the sixth switch Q 22 The corresponding bias node is coupled to the third bias node PC 21 , the sixth switch Q 22 With the seventh switch Q 23 The corresponding control node IN 32 Coupling control node IN 32 ; and the fourth differential pair Q of the switch 23 , Q 24 , the fourth differential pair of switches includes a seventh switch Q 23 , the seventh switch Q 23 With the third differential pair Q 21 , Q 22 The sixth switch Q 22 The corresponding control node IN 32 Coupling control node IN 32 And the eighth switch Q 24The bias node is coupled to the fourth bias node PC 34 , the eighth switch Q 24 With the third differential pair Q 21 , Q 22 The fifth switch Q 21 The corresponding control node IN 41 Coupling control node IN 41 The third bias current generator 5221 is coupled to the third differential pair Q 21 , Q 22 The third bias node PC 21 , to the third bias node PC 21 Provides a third bias current I B21 , and the fourth bias current generator 5222 is coupled to the fourth differential pair Q 23 , Q 24 The fourth bias node PC 34 , to the fourth bias node PC 34 Providing a fourth bias current I B22 .

[0126] like Figure 5 As illustrated, the method of operating the circuit 50 includes: at a control node IN of the first alternative frequency converter circuit 521 23 , IN 14 A first input signal V1 is applied between the control node IN of the second alternative frequency converter circuit 522; 32 , IN 41 A second input signal V2 (orthogonal to the first input signal V1) is applied between the first bias current generator 5211, the second bias current generator 5212, the third bias current generator 5221 and the fourth bias current generator 5222; and a current intensity value I B11 ,I B12 ,I B21 ,I B22 , to produce a phase shift in the output signal.

[0127] Relative to Figure 2 The circuit 20 illustrated in Figure 5 The alternative circuit 50 illustrated in FIG. 5 helps to further improve the robustness against PVT variations by deactivating some current generators as the phase shift can be changed within a linear phase shift angle value range of 0° to 360°.

[0128] For example, for the phase shift value Different ranges of current intensity I B11 ,I B12 ,I B21 ,I B22 can be expressed as:

[0129]

[0130]

[0131]

[0132]

[0133] In other words, according to at least one other control signal I B11 ,I B12 ,I B21 ,I B22 The intensity value and at least one control signal I B1 ,I B2 Based on the bias phase shift value θ, input voltages V1, V2 with alternating phases may be alternately applied to the differential input nodes IN1, IN2 of the circuits 20, 50. Without being limited to a particular theoretical model, this may be the result of setting at least two control signals to zero strength / amplitude, thereby alternately turning transistors in a differential pair of transistors on and off.

[0134] In a variant embodiment, the two parameters β1 and β2 can be used to determine the relative magnitude of the sum of the two parameters. B To change the four current intensity values ​​I B11 ,I B12 ,I B21 ,I B22 .

[0135] For example, in such an alternative scenario, the bias current intensity value I B11 ,I B12 ,I B21 ,I B22 can be expressed as:

[0136] I B11 =I B -β1;I B12 =I B +β1;I B21 =I B -β2;I B22 =I B +β2

[0137] Among them reference Figure 4A-4D The considerations expressed in the above aspects can likewise be applied to determine the values ​​of the parameters β1 , β2 .

[0138] In the variant embodiment considered, in order to extend the range of applicable phase shifts θ to at least two quadrants of the rotation angle, the values ​​of the current intensity parameters β1, β2 can be expressed as:

[0139]

[0140]

[0141]

[0142]

[0143] Where α is a user-settable parameter whose value is greater than unity or 1.

[0144] The circuits 20 , 50 exemplified herein may be integrated circuits, for example integrated in 28 nm FD-SOI CMOS technology (known per se).

[0145] Figure 6 A graph showing the phase of the output signal OUT provided by the circuit 10, 20, 50 as a function of the phase shift θ is shown, the graph indicating a linear type relationship between the two parameters.

[0146] Figure 7 A graph of the amplitude of an output signal OUT provided by a device 10 including circuit 20 or 50 as a function of a phase shift θ is shown, indicating that the amplitude of the signal remains substantially constant during variations in the phase shift.

[0147] In the method illustrated herein, providing 14 other output signal OUT includes: providing at least one resonant network stage R1, L1, C1; R2, C2, L2, and tuning at least one (resonant) network stage to resonate at odd integer multiples of the input frequency f0 of the first input signal V1 and the second input signal V2, respectively; and applying resonant filtering Z1, Z2 to the signal based on the amplified first difference signal O1 and the amplified second difference signal O2, thereby generating other output (e.g., voltage) signal OUT as a result.

[0148] exist Figure 2 In the first exemplary scenario illustrated in FIG. 5 , applying the first signal processing 121; 521 and the second signal processing 122; 522 includes: providing a first signal amplification processing stage M 11 、M 21 ;Q 11 , Q 12 , Q 13 , Q 14 and the second signal amplification processing stage M 12 、M 22 ;Q 21 , Q 22 , Q 23 , Q 24, the first signal amplification processing stage and the second signal amplification processing stage respectively include at least one differential pair of transistors, the at least one differential pair of transistors has a current flow path passing through the at least one differential pair of transistors, the current flow path is configured to become selectively conductive and non-conductive based on the first input signal and the second input signal, respectively, and the current flow path has a common bias node between the at least one differential pair of transistors; a first group of current generators 1210; 5211, 5212 are coupled to the first signal amplification processing stage, the first group of current generators are configured to provide a first group of control signals; and a second group of current generators 1220; 5221, 5222 are coupled to the second signal amplification processing stage, the second group of current generators are configured to provide a second group of control signals.

[0149] As illustrated herein, the method includes: coupling at least one resonant network stage to a first signal amplification processing stage and a second signal amplification processing stage; tuning at least one resonant network stage to resonate at odd integer multiples of input frequencies of a first input signal and a second input signal, respectively; and applying resonant filtering to the difference between an amplified first difference signal and an amplified second difference signal, thereby producing other output signals as a result; wherein the other output signals include voltage signals.

[0150] For example, the method comprises varying the phase shift Θ over at least one quarter of the rotation angle.

[0151] As illustrated herein: the first set of control signals B1 includes a first plurality of bias current signals I B11 ,I B12 The second group of control signals B2 includes a second plurality of bias current signals I B21 ,I B22 ; and at least one bias current signal in the first plurality of bias current signals and at least one bias current signal in the second plurality of bias current signals are equal to zero.

[0152] As illustrated in this article: the first group of control signals B1 includes a first bias current signal I B11 and the second bias current signal I B12 ; and the second group of control signals B2 includes a third bias current signal I B21 and the fourth bias current signal I B22 .

[0153] For example, the first bias current signal has a first bias strength, and the first bias strength is equal to the common bias strength I B Add the first bias coefficient β1; the second bias current signal has a second bias strength, and the second bias strength is equal to the common bias strength I B Subtract the first bias coefficient β1; the third bias current signal has a third bias strength, and the third bias strength is equal to the common bias strength IB plus the second bias coefficient β2; the fourth bias current signal has a fourth bias strength, and the fourth bias strength is equal to the common bias strength I B A second bias coefficient β2 is subtracted; and the phase shift θ is equal to the arc tangent of the ratio of the first bias coefficient β1 to the second bias coefficient β2.

[0154] As illustrated herein, the first bias coefficient β1 and the second bias coefficient β2 are based on the common current intensity I B The ratio of α to an integer value greater than 1.

[0155] like Figure 8 As illustrated, a vehicle V may be equipped with a radar system 80 comprising a device 10 according to the present disclosure and antennas 21 , 22 in order to detect objects O, such as obstacles along a travel path of the vehicle V.

[0156] The distance R (and speed) of the object O can be detected by measuring the time delay d between the transmitted signal (whose wavefront is shown as a solid line) and the received echo signal (whose wavefront is shown as a dashed line), wherein the transmitted signal has a carrier signal frequency f0 and the received echo signal has a spectral content f0±f distributed on the carrier RF signal with frequency f0. d .

[0157] like Figure 8 As illustrated, the radar transceiver system 80 includes: a transmitter chain 18, which is configured to provide an RF signal to a transmit antenna (e.g., an array) 21; a receiver chain 24, which is configured to detect an echo signal reflected from an obstacle O via a receiver antenna (e.g., an array) 22; and a processing system 30, which is configured to drive the transmission of signals from the transmitter chain 18 and process signals detected by the receiver chain 24.

[0158] like Figure 8As illustrated, the transmitter chain 18 includes: a frequency synthesizer LO, such as a phase-locked loop (PLL), the frequency synthesizer LO being configured to generate a first input signal V1, the first input signal V1 being configured to provide a subharmonic of the operating frequency, for example, to cancel the frequency pulling from the power amplifier; an orthogonal generator 11, the orthogonal generator 11 being coupled to the frequency synthesizer LO to provide a second input signal V2 as an inverted or orthogonal version of the first input signal V1; a circuit (e.g., implemented in a single topology 20 or a double-balanced topology 50), the circuit being coupled to the frequency synthesizer LO and a phase shifter to receive the first input signal V1 and the second input signal V2 therefrom, the circuits 20, 50 being configured to perform frequency multiplication and apply a linear phase shift θ to the input signals V1, V2, providing an output signal OUT as a result, the output signal OUT comprising odd harmonics of the RF signal and having a phase shift θ, the phase shift θ being a function of user-settable parameters B1, B2; and a (transmitter) amplifier 180, e.g. a variable gain amplifier (VGA) or a power amplifier (PA), the amplifier 180 being coupled to the circuit 20, 50 to receive the (odd) harmonics OUT of the radio frequency signal V1 therefrom, the amplifier 180 being configured to amplify the harmonics of the RF signal generated via the circuit 20, 50 and to operate / drive a transmit (TX) antenna (array) 21 therewith.

[0159] like Figure 8 As illustrated, a corresponding incoming (echo) signal received at a receive (RX) antenna 22 is fed to a receiver chain 24 comprising: a low noise amplifier (LNA) 26 coupled to the receiver antenna (e.g., array) 22 to receive the echo signal from the receiver antenna; and a frequency converter stage 28 coupled to the LNA 26 to receive the detected echo signal from the LNA 26, and coupled to the PLL to receive a local oscillator signal LO from the PLL, the frequency converter stage 28 being configured to generate a down-converted frequency signal IF based on the echo signal and the LO signal in a manner known per se.

[0160] In one or more embodiments, the radar system 80 may be a system on chip integrated in a semiconductor device. For example, the proposed system may be integrated in a 28nm FD-SOI CMOS technology device, which is assembled on the transmitter stage of a millimeter wave 77GHz CMOS radar system.

[0161] It will be understood in other ways that the various individual implementation options illustrated in the accompanying drawings of this specification are not necessarily intended to adopt the same combination illustrated in the drawings. One or more embodiments may therefore adopt these (otherwise non-mandatory) options individually and / or in a different combination relative to the combinations illustrated in the drawings.

[0162] The claims are an integral part of the technical teaching provided herein with respect to the exemplary embodiments.

[0163] Without prejudice to the underlying principle, the details and embodiments may vary even significantly with respect to what has been described merely as an example, without departing from the scope of protection. The scope of protection is defined by the appended claims.

Claims

1. A method comprising: receiving a first input signal, the first input signal oscillating at an input frequency; receiving a first set of control signals; receiving a second input signal, the second input signal oscillating at the input frequency and being orthogonal to the first input signal; receiving a second set of control signals; applying a first signal process to the first input signal and to a control signal in the first set of control signals to provide a first output signal, the first output signal oscillating at a first output frequency and having an output signal amplitude based on an amplitude of at least one first control signal in the first set of control signals, the first output frequency being based on the input frequency; applying a second signal processing to the second input signal and to a control signal in the second set of control signals to provide a second output signal, the second output signal oscillating at a second output frequency and having an output signal amplitude based on an amplitude of at least one second control signal in the second set of control signals, the second output frequency being equal to the first output frequency; Based on the first output signal and the second output signal, a further output signal is generated, the further output signal oscillating at an output signal frequency equal to the first output frequency and having a phase shift, the output signal frequency being controlled by a ratio of a signal amplitude of at least one control signal of the first set of control signals to a signal amplitude of at least one control signal of the second set of control signals.

2. The method according to claim 1, wherein: The control signals in the first set of control signals and the control signals in the second set of control signals include bias current signals; and The other output signal has a phase shift based on a ratio of a current strength of the bias current signal in the first set of control signals to a current strength of the bias current signal in the second set of control signals.

3. The method of claim 1 , wherein generating the other output signal comprises: tuning at least one resonant network stage to resonate at odd integer multiples of the input frequencies of the first input signal and the second input signal; as well as Resonant filtering is applied to a signal based on the first output signal and the second output signal to generate the output voltage signal.

4. The method of claim 1 , wherein applying the first signal processing and the second signal processing comprises: providing a first signal amplification processing stage and a second signal amplification processing stage, each of the first signal amplification processing stage and the second signal amplification processing stage including at least one differential pair of transistors, the at least one differential pair of transistors having a current flow path through the at least one differential pair of transistors, the current flow path being configured to become selectively conductive and non-conductive based on the first input signal and the second input signal, respectively, and the current flow path having a common bias node between the at least one differential pair of transistors; coupling a first set of current generators to the first signal amplification processing stage, the first set of current generators being configured to provide the first set of control signals; A second set of current generators is coupled to the second signal amplification processing stage, the second set of current generators being configured to provide the second set of control signals.

5. The method according to claim 4, comprising: coupling at least one resonant network stage to the first signal amplification processing stage and the second signal amplification processing stage; tuning the at least one resonant network stage to resonate at odd integer multiples of the input frequencies of the first input signal and the second input signal; as well as applying resonant filtering to a difference between the first output signal and the second output signal to produce the output signal; The other output signals include voltage signals.

6. The method according to claim 1, further comprising: The phase shift is varied over at least one quarter of the rotation angle.

7. The method according to claim 1, wherein: The first set of control signals includes a first plurality of bias current signals; the second set of control signals comprising a second plurality of bias current signals; and At least one bias current signal of the first plurality of bias current signals and at least one bias current signal of the second plurality of bias current signals are equal to zero.

8. The method according to claim 1, wherein: The first set of control signals includes a first bias current signal and a second bias current signal; The second group of control signals includes a third bias current signal and a fourth bias current signal; in: The first bias current signal has a first bias strength, and the first bias strength is equal to the common bias strength plus a first bias coefficient; The second bias current signal has a second bias strength, and the second bias strength is equal to the common bias strength minus the first bias coefficient; The third bias current signal has a third bias strength, and the third bias strength is equal to the common bias strength plus a second bias coefficient; The fourth bias current signal has a fourth bias strength, and the fourth bias strength is equal to the common bias strength minus the second bias coefficient; The phase shift is equal to the inverse tangent of the ratio of the first bias coefficient to the second bias coefficient. 9 . The method of claim 8 , wherein the first bias coefficient and the second bias coefficient are based on a ratio of the common current strength to an integer value greater than 1. 10 .

10. A circuit comprising: a first set of input nodes configured to receive a first input signal oscillating at an input frequency; a first set of control nodes, the first set of control nodes being configured to receive a first set of control signals; a second set of input nodes configured to receive a second input signal oscillating at the input frequency and in quadrature with the first input signal; a second set of control nodes, the second set of control nodes being configured to receive a second set of control signals; as well as signal processing circuitry coupled to the first set of input nodes, the first set of control nodes, the second set of input nodes, and the second set of control nodes; The signal processing circuit arrangement is configured to provide a further output signal which oscillates at the output signal frequency and has a phase shift which is based on a ratio of a signal amplitude of at least one first control signal in the first set of control signals to a signal amplitude of at least one second control signal in the second set of control signals.

11. The circuit of claim 10, wherein: The control signals in the first set of control signals and the control signals in the second set of control signals include bias current signals; and The other output signal has a phase shift based on a ratio of a current strength of the bias current signal in the first set of control signals to a current strength of the bias current signal in the second set of control signals.

12. The circuit of claim 10, wherein the signal processing circuit means comprises: a first circuit configured to generate a first output signal based on the first input signal and the first set of control signals; a second circuit configured to generate a second output signal based on the second input signal and the second set of control signals; at least one resonant network stage tuned to resonate at odd integer multiples of the input frequencies of the first input signal and the second input signal; and Wherein the at least one resonant network stage applies resonant filtering based on the first output signal and the second output signal to generate the output voltage signal.

13. The circuit of claim 11, wherein: The first circuit includes a first signal amplification processing stage, and the second circuit includes a second signal amplification processing stage; each of the first signal amplification processing stage and the second signal amplification processing stage includes at least one differential pair of transistors, the at least one differential pair of transistors having a current flow path through the at least one differential pair of transistors, the current flow path being configured to become selectively conductive and non-conductive based on the first input signal and the second input signal, respectively, and the current flow path having a common bias node between the at least one differential pair of transistors; A first set of current generators is coupled to the first signal amplification processing stage, the first set of current generators being configured to provide the first set of control signals; and A second set of current generators is coupled to the second signal amplification processing stage, the second set of current generators being configured to provide the second set of control signals.

14. The method according to claim 13, wherein: The at least one resonant network stage is coupled to the first signal amplification processing stage and the second signal amplification processing stage; and The at least one resonant network stage is tuned to resonate at odd integer multiples of the input frequencies of the first input signal and the second input signal.

15. A device comprising: The circuit according to claim 10; as well as A frequency synthesizer is coupled to the circuit and configured to provide the input signal to the circuit, the input signal oscillating at the input frequency.

16. The apparatus of claim 15, wherein the frequency synthesizer is configured to provide the input signal oscillating at the input frequency such that the output frequency of the further output signal lies within the millimeter wavelength range.

17. A system comprising: The apparatus according to claim 15; a power amplifier coupled to the circuit and configured to receive the further output signal from the circuit, the power amplifier being configured to amplify the further output signal and provide an amplified output signal as a result, and A transmitter antenna is coupled to the power amplifier and configured to transmit the amplified output signal.

18. The system of claim 17, comprising a vehicle-mounted radar system, the vehicle-mounted radar system comprising: a receiver antenna configured to receive an echo signal based on the transmitted amplified output signal; A mixer stage is coupled to the circuit, the mixer stage being configured to apply frequency mixing to the other output signal and the echo signal, producing a mixed signal as a result.

19. A vehicle equipped with the vehicle-mounted radar system according to claim 18.

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