A low voltage bandgap reference circuit without operational amplifier

Abstract

The application discloses a low-voltage band gap reference voltage source circuit without an operational amplifier, and belongs to the field of electronic circuits.The application comprises a positive temperature coefficient current generating module, a positive temperature coefficient voltage generating module and a reference voltage synthesizing module; the positive temperature coefficient current generating module generates a positive temperature coefficient current; the positive temperature coefficient voltage generating module generates a first temperature-proportional voltage; the reference voltage synthesizing module generates a second temperature-proportional voltage, and adds the second temperature-proportional voltage with a negative temperature coefficient voltage to obtain a zero-temperature-coefficient band gap reference voltage.Through the structure, the application effectively reduces the temperature coefficient; the common-source common-gate current mirror is adopted to improve the power supply rejection ratio of the circuit.Compared with the prior art, the application does not adopt an operational amplifier, and thus reduces noise and power supply complexity.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a low-voltage bandgap reference voltage source circuit without operational amplifiers. Background Technology

[0002] Bandgap voltage references, as a type of bias voltage source, are widely used in analog and mixed-signal chips. To provide low temperature coefficients and high power supply rejection ratios, bandgap references often use operational amplifiers (op-amps), but this increases circuit power consumption and complexity, and introduces greater noise. However, op-amp-less bandgap references generally have higher temperature coefficients.

[0003] Since silicon has a bandgap voltage of approximately 1.205V, most bandgap voltage references are sized around 1.205V. However, many applications require low-voltage references, which conventional bandgap voltage references often cannot meet.

[0004] Therefore, there is an urgent need for a mature op-amp-free low-voltage bandgap reference voltage source to obtain a low-temperature coefficient, low-noise, and high power supply rejection ratio low-voltage bandgap reference without increasing power consumption and circuit complexity. Summary of the Invention

[0005] The purpose of this invention is to provide a low-voltage bandgap reference voltage source circuit without operational amplifiers to solve the problems in the prior art.

[0006] To solve the above-mentioned technical problems, the present invention provides a low-voltage bandgap reference voltage source circuit without operational amplifiers, comprising:

[0007] The positive temperature coefficient current generation module generates a stable, temperature-proportional current required in a bandgap reference source.

[0008] Positive temperature coefficient voltage generation module, utilizing V under different current densities BE The difference is proportional to the absolute temperature, resulting in the first positive temperature coefficient voltage;

[0009] The reference voltage synthesis module utilizes V under different current densities. BE The difference is proportional to the absolute temperature, generating a second positive temperature coefficient voltage. The second positive temperature coefficient voltage is superimposed on the first positive temperature coefficient voltage to form a third temperature coefficient voltage; where V BE It is the voltage between the base and emitter of the transistor, which determines the transistor's Ve. BE After voltage division by resistors, a negative temperature coefficient voltage is obtained; the third positive temperature coefficient voltage is added to the negative temperature coefficient voltage to obtain a reference voltage source with a near-zero temperature coefficient.

[0010] In one embodiment, the positive temperature coefficient current generating module includes PMOS transistors P1 to P4, NMOS transistor N1, transistor Q1, transistor Q2, resistors R1 to R3, and capacitor C1.

[0011] The positive temperature coefficient voltage generation module includes PMOS transistors P5-P6, PMOS transistors P13-P17, NMOS transistors N2, NMOS transistors N6-N8, transistor Q5, transistor Q6, and capacitor C3.

[0012] The reference voltage synthesis module includes PMOS transistors P7 to P12, NMOS transistor N4, transistors Q3 to Q4, resistors R3 to R4, and capacitor C2.

[0013] The sources of PMOS transistors P1, P2, P5, P7, P8, P9, P11, P12, P16, and P17, the drain of NMOS transistor N1, and the upper plate of capacitor C1 are all connected to the power supply. The drain of PMOS transistor P1 is connected to the source of PMOS transistor P2. The drain of PMOS transistor P2 is connected to the gates of PMOS transistors P1, P3, P5, P9, P11, and P13, and capacitor C1. The lower plate of transistor Q1 is connected to the first terminal of resistor R1. The second terminal of resistor R1 is connected to the gates of PMOS transistors P2, P4, P6, P10, P12, and P18, the gate of NMOS transistor N1, and the collector of transistor Q1. The emitter of transistor Q1 is connected to the first terminal of resistor R2. The base of transistor Q1 is connected to the first terminal of resistor R3. The drain of PMOS transistor P3 is connected to the source of PMOS transistor P4. The drain of PMOS transistor P4 is connected to the collector and base of transistor Q2, the source of NMOS transistor N1, and the second terminal of resistor R3. The drain of PMOS transistor P5 is connected to the source of PMOS transistor P6. The drain of PMOS transistor P6 is connected to the source and gate of NMOS transistor N2, the gate of NMOS transistor N4, and the gate of NMOS transistor N7; the gate of PMOS transistor P7 is connected to the drain of PMOS transistor P7 and the drain of NMOS transistor N3, and the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4; the drain of PMOS transistor P8 is connected to the base of transistor Q3, the base of transistor Q4, and the first terminal of resistor R4; the second terminal of resistor R4 is connected to the first terminal of resistor R5 and the output terminal VREF; the second terminal of resistor R5 is connected to the emitter of transistor Q4, the drain of NMOS transistor N5, and the upper plate of capacitor C2; the drain of PMOS transistor P9 is connected to the source of PMOS transistor P10. The drain of MOSFET P10 is connected to the collector of transistor Q3. The emitter of transistor Q3 is connected to the source of NMOS transistor N5, the emitter of transistor Q6, the upper plate of capacitor C3, and the drain of NMOS transistor N8. The drain of PMOS transistor P11 is connected to the source of PMOS transistor P12. The drain of PMOS transistor P12 is connected to the collector of transistor Q4. The drain of PMOS transistor P13 is connected to the source of PMOS transistor P14. The drain of PMOS transistor P14 is connected to the gate of NMOS transistor N6 and the collector of transistor Q5. The drain of PMOS transistor P15 is connected to the gate of PMOS transistor P15 and the drain of NMOS transistor N6. The source of NMOS transistor N6 is connected to the drain of NMOS transistor N7.The drain of PMOS transistor P16 is connected to the base of transistors Q5 and Q6; the drain of PMOS transistor P17 is connected to the source of PMOS transistor P18; the drain of PMOS transistor P18 is connected to the collector of transistor Q6, the lower plate of capacitor C3, and the gate of NMOS transistor N8; the second terminal of resistor R2, the emitter of transistor Q2, the emitter of transistor Q5, the source of NMOS transistor N2, the source of NMOS transistor N4, the source of NMOS transistor N7, and the source of NMOS transistor N8 are grounded.

[0014] In one embodiment, the ratio of the number of transistors Q1 to Q2 is n1:1, the ratio of the number of transistors Q4 to Q3 is n2:1, the ratio of the number of transistors Q6 to Q5 is n3:1, the ratio of the common-source cascode current mirrors P1 to P3 and P2 to P4 is 1:1, the ratio of the common-source cascode current mirrors P9 to P11 and P10 to P12 is m1:1, and the ratio of the common-source cascode current mirrors P13 to P17 and P14 to P18 is m2:1; where m1, m2, n1, n2, and n3 are positive integers.

[0015] In one embodiment, transistors Q1, Q2, Q3, Q4, Q5, and Q6 are vertical bipolar transistors.

[0016] In one embodiment, NMOS transistors N3 and N6 are inverted ratio transistors; wherein the gate length of the inverted ratio transistor is greater than its gate width.

[0017] This invention provides an operational amplifier-free low-voltage bandgap reference voltage source circuit. The bandgap reference circuit is designed by combining a positive temperature coefficient current generation module, a positive temperature coefficient voltage generation module, and a reference voltage synthesis module. Based on the positive temperature coefficient current generation module, first and second positive temperature coefficient voltages are generated. These two are superimposed to generate a third positive temperature coefficient voltage. This third positive temperature coefficient voltage is then superimposed with a negative temperature coefficient voltage to obtain the low-voltage bandgap reference voltage source. This structure effectively reduces the temperature coefficient. The use of a common-source, common-gate current mirror improves the circuit's power supply rejection ratio. Compared with existing technologies, the absence of operational amplifiers reduces noise and power supply complexity. Attached Figure Description

[0018] Figure 1 This is a circuit diagram of the low-voltage bandgap reference source in this invention.

[0019] Figure 2 This is the circuit diagram for a positive temperature coefficient current generation module.

[0020] Figure 3 This is an explanatory diagram for the synthesis of a low-voltage bandgap reference voltage source. Detailed Implementation

[0021] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the operational amplifier-free low-voltage bandgap reference voltage source circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0022] This invention provides a low-voltage bandgap reference voltage source circuit without operational amplifiers, including a positive temperature coefficient current generation module, a positive temperature coefficient voltage generation module, and a reference voltage synthesis module; the positive temperature coefficient current generation module is used to generate a stable, temperature-proportional current (i.e., positive temperature coefficient current) required in the bandgap reference source; the positive temperature coefficient voltage generation module utilizes V under different current densities BE The difference is proportional to the absolute temperature, generating a first positive temperature coefficient voltage; the reference voltage synthesis module utilizes V under different current densities. BE The difference is proportional to the absolute temperature, generating a second positive temperature coefficient voltage. The second positive temperature coefficient voltage is superimposed on the first positive temperature coefficient voltage to form a third temperature coefficient voltage. Where V... BE It is the voltage between the base and emitter of the transistor, which determines the transistor's Ve. BE After voltage division by resistors, a negative temperature coefficient voltage is obtained; the third positive temperature coefficient voltage is added to the negative temperature coefficient voltage to obtain a reference voltage source of 510mV with a temperature coefficient close to zero.

[0023] like Figure 1 As shown, the positive temperature coefficient current generating module includes PMOS transistors P1 to P4, NMOS transistor N1, transistor Q1, transistor Q2, resistors R1 to R3, and capacitor C1.

[0024] The positive temperature coefficient voltage generation module includes PMOS transistors P5-P6, PMOS transistors P13-P17, NMOS transistors N2, NMOS transistors N6-N8, transistor Q5, transistor Q6, and capacitor C3.

[0025] The reference voltage synthesis module includes PMOS transistors P7 to P12, NMOS transistor N4, transistors Q3 to Q4, resistors R3 to R4, and capacitor C2.

[0026] The sources of PMOS transistors P1, P2, P5, P7, P8, P9, P11, P12, P16, and P17, the drain of NMOS transistor N1, and the upper plate of capacitor C1 are all connected to the power supply. The drain of PMOS transistor P1 is connected to the source of PMOS transistor P2. The drain of PMOS transistor P2 is connected to the gates of PMOS transistors P1, P3, P5, P9, P11, and P13, and capacitor C1. The lower plate of transistor Q1 is connected to the first terminal of resistor R1. The second terminal of resistor R1 is connected to the gates of PMOS transistors P2, P4, P6, P10, P12, and P18, the gate of NMOS transistor N1, and the collector of transistor Q1. The emitter of transistor Q1 is connected to the first terminal of resistor R2. The base of transistor Q1 is connected to the first terminal of resistor R3. The drain of PMOS transistor P3 is connected to the source of PMOS transistor P4. The drain of PMOS transistor P4 is connected to the collector and base of transistor Q2, the source of NMOS transistor N1, and the second terminal of resistor R3. The drain of PMOS transistor P5 is connected to the source of PMOS transistor P6. The drain of PMOS transistor P6 is connected to the source and gate of NMOS transistor N2, the gate of NMOS transistor N4, and the gate of NMOS transistor N7; the gate of PMOS transistor P7 is connected to the drain of PMOS transistor P7 and the drain of NMOS transistor N3, and the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4; the drain of PMOS transistor P8 is connected to the base of transistor Q3, the base of transistor Q4, and the first terminal of resistor R4; the second terminal of resistor R4 is connected to the first terminal of resistor R5 and the output terminal VREF; the second terminal of resistor R5 is connected to the emitter of transistor Q4, the drain of NMOS transistor N5, and the upper plate of capacitor C2; the drain of PMOS transistor P9 is connected to the source of PMOS transistor P10. The drain of MOSFET P10 is connected to the collector of transistor Q3. The emitter of transistor Q3 is connected to the source of NMOS transistor N5, the emitter of transistor Q6, the upper plate of capacitor C3, and the drain of NMOS transistor N8. The drain of PMOS transistor P11 is connected to the source of PMOS transistor P12. The drain of PMOS transistor P12 is connected to the collector of transistor Q4. The drain of PMOS transistor P13 is connected to the source of PMOS transistor P14. The drain of PMOS transistor P14 is connected to the gate of NMOS transistor N6 and the collector of transistor Q5. The drain of PMOS transistor P15 is connected to the gate of PMOS transistor P15 and the drain of NMOS transistor N6. The source of NMOS transistor N6 is connected to the drain of NMOS transistor N7.The drain of PMOS transistor P16 is connected to the base of transistors Q5 and Q6; the drain of PMOS transistor P17 is connected to the source of PMOS transistor P18; the drain of PMOS transistor P18 is connected to the collector of transistor Q6, the lower plate of capacitor C3, and the gate of NMOS transistor N8; the second terminal of resistor R2, the emitter of transistor Q2, the emitter of transistor Q5, the source of NMOS transistor N2, the source of NMOS transistor N4, the source of NMOS transistor N7, and the source of NMOS transistor N8 are grounded.

[0027] Transistors Q1, Q2, Q3, Q4, Q5, and Q6 are vertical bipolar transistors.

[0028] Please see Figure 2 When the positive temperature coefficient current generation module is powered on, because the gate voltages of the two sets of common-source cascode current mirror PMOS transistors P1 and P3, and P2 and P4 are the same, and the source voltages of PMOS transistors P1 and P3 are the same, all PMOS transistors P1, P2, P3, and P4 are in the saturation region. This results in the same leakage current for PMOS transistors P1 and P2. Since the ratio of transistors Q1 to Q2 is n3:1, where n3 is a positive integer, the Va of transistors flowing through different currents... BE The difference is positively correlated with temperature, so the voltage across resistor R2 is:

[0029]

[0030] Where V BEQ1 It is the voltage difference between the base and emitter of transistor Q1, V BEQ2 It is the voltage difference between the base and emitter of transistor Q2, V T This is the thermal voltage, n1 is the ratio of the number of transistors in transistor Q2 to Q1, k is the Hertzmann constant, q is the charge, and T is the thermodynamic temperature. Therefore, the current I flowing through resistor R2... R2 It is directly proportional to temperature.

[0031] The common-source, common-gate current mirror PMOS transistors P5 and P7 replicate the leakage current of PMOS transistor P1 at a 1:1 ratio, making I... P7 =I R2 I P7 This is the current flowing through PMOS transistor P7; similarly, the current mirror NMOS transistor N7 replicates the leakage current of NMOS transistor N2 at a 1:1 ratio, making I... N7 =I R2 I N7 This is the current flowing through NMOS transistor N7. NMOS transistor N6 is an inverting ratio transistor, and the current I...DN7 When the value is large, NMOS transistor N6 will provide negative feedback to I. DN7 It acts as a limiter. PMOS transistor P16 replicates the leakage current of PMOS transistor P15 at a 1:1 ratio, causing I... DP16 =I DN7 =I R2 I P16 I P18 The base currents of transistors Q3 and Q4, respectively, control the emitter currents of transistors Q5 and Q6, keeping them in the amplification region. Common-source cascode current mirrors PMOS transistors P17 and P18, and PMOS transistors P13 and P14, proportionally replicate the leakage current of PMOS transistor P1, causing I... DP17 =m1*I DP13 m1 is a positive integer; since the number of transistors Q5 and Q6 is n3:1, the current ratio flowing through transistors Q5 and Q6 is 1:m1, and the V0 of transistors flowing through different currents is... BE The difference is positively correlated with temperature, so the leakage voltage of resistor R2 is:

[0032]

[0033] V BEQ5 It is the voltage difference between the base and emitter of transistor Q5, V BEQ6 It is the base-emitter voltage difference of transistor Q6, where m2 is a positive integer; the current mirror NMOS transistor N4 replicates the leakage current of NMOS transistor N2 at a 1:1 ratio, making I... DN4 =I R2 NMOS transistor N3 is an inverting ratio transistor, connected to current I. DN4 When the value is large, NMOS transistor N6 will provide negative feedback to I. DN4 It acts as a limiting agent. PMOS transistor P8 replicates the leakage current of PMOS transistor P15 at a 1:1 ratio, causing I... DP8 =I DN4 =I R2 I DP18 The current flows to the bases of transistors Q3 and Q4, and to resistors R4 and R5, controlling the emitter currents of transistors Q5 and Q6, thus keeping them in the amplification region. Since resistors R4 and R5 are connected in series, and the output port VREF is connected between them, and transistor Q4 is connected in parallel with resistors R4 and R5, therefore:

[0034]

[0035] Common-source cascode current mirror PMOS transistors P17, P18, P13, and P14 replicate the leakage current of PMOS transistor P1 proportionally, making I... DP11 =m2*I DP9 Since the ratio of transistors Q3 to Q4 is n2:1, where n2 is a positive integer; and the ratio of current flowing through transistors Q5 and Q6 is 1:m2, the Va of transistors flowing with different currents... BE The difference is positively correlated with temperature, so the leakage voltage of resistor R2 is:

[0036]

[0037] Combining equations (3), (4), and (5), we can obtain VREF as:

[0038]

[0039] In formula (7) Voltage with a negative temperature coefficient For positive temperature coefficient voltage, set By setting appropriate values ​​for m1*m2*n2*n3, a voltage with zero temperature coefficient can be obtained. The bandgap reference voltage value obtained in this invention is 510mV. The value is 0.52, n1, n2, and n3 are all 9, and m1 and m2 are both 5.

[0040] This invention uses NMOS transistors N5 and N8 as equivalent resistors, which reduces the layout area and prevents the resistors from competing with current sources in the same branch for current control. Resistor R1 provides appropriate bias to the cascode current mirror, ensuring the current-carrying MOS transistors are in the saturation region. This improves the power supply rejection ratio and reduces circuit complexity and power consumption. Inverter transistors N3 and N6 are used, and negative feedback makes the circuit's quiescent operating point more stable. Appropriate capacitors C2 and C3 are used to compensate for the negative feedback loop in the circuit, preventing oscillations.

[0041] Based on the above analysis, this invention designs a low-voltage bandgap reference circuit by combining a positive temperature coefficient (PTC) current generation module, a PTC voltage generation module, and a reference voltage synthesis module. After generating a PTC current through the PTC current generation module, the PTC voltage generation module converts the current density difference into a PTC voltage difference. Similarly, the reference voltage synthesis module converts the current density difference into a PTC voltage difference, adds it to the first PTC voltage, and then adds it to the negative temperature coefficient voltage to generate a low-temperature coefficient low-voltage bandgap reference voltage. This invention uses a common-source cascode current mirror, improving the output power supply rejection ratio; it employs an op-amp-less structure, reducing circuit complexity and power consumption, and lowering output noise.

[0042] In addition, the present invention also provides an analog chip, which includes the above-mentioned bandgap reference circuit.

[0043] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A low-voltage bandgap reference voltage source circuit without operational amplifiers, characterized in that, include: The positive temperature coefficient current generation module generates a stable, temperature-proportional current required in the bandgap reference source. Positive temperature coefficient voltage generation module, utilizing V under different current densities BE The difference is proportional to the absolute temperature, resulting in the first positive temperature coefficient voltage; The reference voltage synthesis module utilizes V under different current densities. BE The difference is proportional to the absolute temperature, generating a second positive temperature coefficient voltage. The second positive temperature coefficient voltage is superimposed on the first positive temperature coefficient voltage to form a third temperature coefficient voltage; where V BE It is the voltage between the base and emitter of the transistor, which determines the transistor's Ve. BE A negative temperature coefficient voltage is obtained after voltage division by resistors; the third positive temperature coefficient voltage is added to the negative temperature coefficient voltage to obtain a reference voltage source with a near-zero temperature coefficient. The positive temperature coefficient current generating module includes PMOS transistors P1~P4, NMOS transistor N1, transistor Q1, transistor Q2, resistors R1~R3, and capacitor C1. The positive temperature coefficient voltage generation module includes PMOS transistors P5~P6, PMOS transistors P13~P18, NMOS transistors N2, NMOS transistors N4, NMOS transistors N6~N8, transistor Q5, transistor Q6, and capacitor C3. The reference voltage synthesis module includes PMOS transistors P7~P12, NMOS transistor N4, transistors Q3~Q4, resistors R4~R5, and capacitor C2; The sources of PMOS transistors P1, P3, P5, P7, P8, P9, P11, P13, P15, P16, and P17, the drain of NMOS transistor N1, and the upper plate of capacitor C1 are all connected to the power supply. The drain of PMOS transistor P1 is connected to the source of PMOS transistor P2, and the drain of PMOS transistor P2 is connected to the gates of PMOS transistors P1, P3, P5, P9, and P11. The base of transistor Q1 is connected to the gate of PMOS transistor P13, the gate of PMOS transistor P17, the lower plate of capacitor C1, and the first terminal of resistor R1. The second terminal of resistor R1 is connected to the gates of PMOS transistors P2, P4, P6, P10, P12, P14, and P18, the gate of NMOS transistor N1, and the collector of transistor Q1. The emitter of transistor Q1 is connected to the first terminal of resistor R2. The base of transistor Q1 is connected to the first terminal of resistor R3. The drain of PMOS transistor P3 is connected to the source of PMOS transistor P4, and the drain of PMOS transistor P4 is connected to the collector of transistor Q2. The electrodes and base of the PMOS transistor P5 are connected to the source of the PMOS transistor P6, and the drain of the PMOS transistor P6 is connected to the drain and gate of the NMOS transistor N2, the gate of the NMOS transistor N4, and the gate of the NMOS transistor N7. The gate of the PMOS transistor P7 is connected to the drain of the PMOS transistor P7 and the drain of the NMOS transistor N3, and the source of the NMOS transistor N3 is connected to the drain of the NMOS transistor N4. The drain of the PMOS transistor P8 is connected to the base of the transistor Q3, the base of the transistor Q4, and the first terminal of the resistor R4. The second terminal of the resistor R4 is connected to the first terminal of the resistor R5 and the output terminal VREF. The second terminal of the resistor R5 is connected to the transistor... The emitter of Q4, the drain of NMOS transistor N5, and the upper plate of capacitor C2 are connected; the drain of PMOS transistor P9 is connected to the source of PMOS transistor P10, the drain of PMOS transistor P10 is connected to the collector of transistor Q3, the emitter of transistor Q3 is connected to the source of NMOS transistor N5, the emitter of transistor Q6, the upper plate of capacitor C3, and the drain of NMOS transistor N8; the drain of PMOS transistor P11 is connected to the source of PMOS transistor P12, the drain of PMOS transistor P12 is connected to the collector of transistor Q4; the drain of PMOS transistor P13 is connected to the source of PMOS transistor P14, and the drain of PMOS transistor P14 is connected to the gate of NMOS transistor N6 and the collector of transistor Q5.The drain of PMOS transistor P15 is connected to the gate of PMOS transistor P15 and the drain of NMOS transistor N6; the source of NMOS transistor N6 is connected to the drain of NMOS transistor N7; the drain of PMOS transistor P16 is connected to the base of transistor Q5 and the base of transistor Q6; the drain of PMOS transistor P17 is connected to the source of PMOS transistor P18; the drain of PMOS transistor P18 is connected to the collector of transistor Q6, the lower plate of capacitor C3, and the gate of NMOS transistor N8; the second terminal of resistor R2, the emitter of transistor Q2, the emitter of transistor Q5, the source of NMOS transistor N2, the source of NMOS transistor N4, the source of NMOS transistor N7, and the source of NMOS transistor N8 are grounded.

2. The low-voltage bandgap reference voltage source circuit without operational amplifier as described in claim 1, characterized in that, The ratio of the number of transistors Q1 to Q2 is n1:1, the ratio of the number of transistors Q4 to Q3 is n2:1, the ratio of the number of transistors Q6 to Q5 is n3:1, the ratio of the common source cascode current mirrors P1 to P3 and P2 to P4 is 1:1, the ratio of the common source cascode current mirrors P9 to P11 and P10 to P12 is m1:1, and the ratio of the common source cascode current mirrors P13 to P17 and P14 to P18 is m2:1; where m1, m2, n1, n2, and n3 are positive integers.

3. The low-voltage bandgap reference voltage source circuit without operational amplifier as described in claim 1, characterized in that, Transistors Q1, Q2, Q3, Q4, Q5, and Q6 are vertical bipolar transistors.

4. The low-voltage bandgap reference voltage source circuit without operational amplifier as described in claim 1, characterized in that, The NMOS transistors N3 and N6 are inverted ratio transistors; wherein the gate length of the inverted ratio transistor is greater than its gate width.

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