Memory controller, operating method thereof, and memory device including same

Abstract

A memory controller, an operating method thereof, and a memory device including the same are provided. A memory controller includes a health level determination circuit that determines a health level of a memory block based on a combination of an error detection result of data read from at least one page of the memory block and block information related to a degree of degradation of the memory block, and an IO ratio setting circuit. An IO ratio setting circuit sets an IO ratio between the host IO operation and the internal IO operation according to the determined health level. The memory controller exchanges data with a memory device in response to a request from a host in the host IO operation, and exchanges data with a memory device in relation to a background operation in the internal IO operation. During a period in which the background operation is performed, the memory controller performs the host IO operation and the internal IO operation with the memory device according to the set IO ratio.

Description

Technical Field

[0001] The present disclosure relates to a memory controller for controlling background operations and an operating method thereof. Background Art

[0002] A flash memory device is a nonvolatile memory and can save data stored therein even if its power is cut off. Recently, storage devices including flash memory devices such as embedded multimedia cards (eMMC), universal flash memory (UFS), solid-state drives (SSDs), or memory cards have been widely used to store or move data.

[0003] The flash memory device may perform background operations such as reclamation (or read reclamation) or garbage collection. For example, since the flash memory device may lose data stored in some blocks due to degradation over time, a reclamation operation (or read reclamation operation) may be performed to copy the data stored in the degraded block to another block, or a garbage collection operation may be performed to selectively generate new free blocks.

[0004] However, due to the background operation, internal input / output operations (IO) (e.g., internal IO) may be performed between the memory controller and the memory device, and host IO operations (e.g., host IO) according to a host request cannot be performed during the background operation, and therefore, the performance of the flash memory device may be degraded, resulting in a delayed response to the host. Summary of the invention

[0005] The subject matter of the present application relates to a memory controller for performing efficient background operations by setting a ratio between host input / output (IO) operations and internal IO operations, an operating method of the memory controller, and a storage device.

[0006] Generally, according to some aspects, the subject matter of the present disclosure relates to a memory controller, the memory controller comprising: a health level determination circuit, the health level determination circuit being configured to determine the health level of a first block among a plurality of blocks included in a memory device based on a combination of an error detection result of data read from at least one page of the first block and block information related to determination of a degree of degradation of the first block; and an IO ratio setting circuit, the IO ratio setting circuit being configured to set an IO ratio between a host IO operation and an internal IO operation according to the determined health level, in which the memory controller exchanges data with the memory device in response to a request from a host, and in which the memory controller exchanges data with the memory device in relation to background operations of the memory device, wherein, during a period of performing the background operation on the first block, the memory controller performs the host IO operation and the internal IO operation with the memory device according to the set IO ratio.

[0007] Generally, according to some aspects, the present disclosure relates to an operating method of a memory controller, wherein the method includes: triggering a background operation on a first block among a plurality of blocks included in a memory device according to an error detection result of data read from at least one first page of the first block; setting an IO ratio between a host IO operation and an internal IO operation to a first value according to a health level of the first block, in which the memory controller exchanges data with the memory device in response to a request from a host, in which the memory controller exchanges data with the memory device in association with a background operation on the memory device, the health level of the first block being determined based on block information related to determination of a degree of degradation of the first block and an error detection result of data read from at least one second page of the first block; and performing the host IO operation and the internal IO operation with the memory device according to the IO ratio set to the first value during a period of performing the background operation on the first block.

[0008] Generally, according to some aspects, the present disclosure relates to a storage device, the storage device comprising: a non-volatile memory device, the non-volatile memory device comprising a plurality of blocks; and a memory controller, the memory controller being configured to perform a host IO operation and an internal IO operation, the host IO operation being used to exchange data with the non-volatile memory device in response to a request from a host, the internal IO operation being used to exchange data with the non-volatile memory device in association with a background operation of the non-volatile memory device, wherein the memory controller is further configured to: based on block information related to determination of a degree of degradation of a first block among the plurality of blocks, set an execution ratio of the internal IO operation and the host IO operation related to the first block to a first value, and based on block information related to determination of a degree of degradation of a second block among the plurality of blocks, set an execution ratio of the internal IO operation and the host IO operation related to the second block to a second value, and when the first value is greater than the second value, a speed of the background operation of the first block is faster than a speed of the background operation of the second block. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating an example of a memory system;

[0011] Figure 2 is a block diagram illustrating an example of a memory controller;

[0012] Figure 3 is a block diagram showing an example of performing input / output (IO) ratio setting by software;

[0013] Figure 4 is a flowchart illustrating an example of a method of operation of a memory system;

[0014] Figure 5 is a graph showing an example of differently setting IO ratios corresponding to read recovery to uncorrectable error correction code (RR to UECC) values;

[0015] Figure 6 is a block diagram illustrating an example of a memory device;

[0016] Figure 7 It is schematically shown Figure 1 A perspective view of an example structure of a memory device;

[0017] Figure 8 It shows Figure 1 A three-dimensional diagram of a memory cell array;

[0018] Fig. 9 is a perspective view showing an example of a storage block;

[0019] Fig. 10A and Fig. 10B is a table showing an example of health level determination;

[0020] Fig.11 is a block diagram illustrating an example of a memory system;

[0021] Fig.12 is a flow chart illustrating an example method of operation of a memory system;

[0022] Fig.13A and Fig. 13B is a block diagram showing an example in which the embodiments are applied to various memory systems;

[0023] Fig.14 illustrates a recycling operation according to some embodiments;

[0024] Fig.15 It shows that according to Fig.14 A flowchart of a method of operating a memory system of an example embodiment shown in ; and

[0025] Fig.16 is a block diagram showing an example in which a memory device is applied to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0026] Figure 1 is a block diagram illustrating an example of the memory system 10 .

[0027] refer to Figure 1 , the memory system 10 includes a memory controller 100 and a memory device 200 , and the memory device 200 may include a memory cell array 210 , a voltage generator 220 , and a control logic 230 .

[0028] For example, the memory system 10 can communicate with the host through various interfaces such as: a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded multimedia card (eMMC) interface, a peripheral component interconnect (PCI) interface, a PCI-Express (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA interface, a parallel ATA interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE) interface, a FireWire interface, a universal flash memory (UFS) interface, and a non-volatile memory express (NVMe) interface.

[0029] According to some embodiments, the memory device 200 may include an NVM device, such as a flash memory. In some embodiments, the memory system 10 may be implemented by an embedded or removable memory in an electronic device, and for example, the memory system 10 may be implemented in various forms, such as an embedded UFS memory device, an eMMC, a solid state drive (SSD), a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme digital (xD) card, and a memory stick. In addition, when data is stored in a non-volatile manner, the memory system 10 may be referred to as a storage device.

[0030] The memory controller 100 may control the memory device 200 in response to a write / read request from a host so as to read data stored in the memory device 200 or write data on the memory device 200. For example, the memory controller 100 may include a processor 110, and the processor 110 may control general internal operations of the memory controller 100 and control memory operations on the memory device 200. In particular, the memory controller 100 may control a write operation, a read operation, and an erase operation on the memory device 200 by providing an address ADD, a command CMD, and a control signal CTRL to the memory device 200. In addition, data DATA to be stored in the memory device 200 and data DATA read from the memory device 200 may be exchanged between the memory controller 100 and the memory device 200.

[0031] The memory cell array 210 may include a plurality of memory cells, such as flash memory cells. Hereinafter, the embodiments are described in detail by assuming that the plurality of memory cells are NAND flash memory cells. However, the inventive concept is not limited thereto, and in some embodiments, the plurality of memory cells may be resistive memory cells, such as resistive random access memory (ReRAM), phase change random access memory (PRAM), or magnetic random access memory (MRAM).

[0032] In some embodiments, the memory cell array 210 may include a three-dimensional memory cell array, which may include a plurality of NAND strings, and each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. However, the inventive concept is not limited thereto, and in some embodiments, the memory cell array 210 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings in row and column directions.

[0033] Voltage generator 220 may generate various voltages for use by memory device 200, such as a program voltage for a program operation and a read voltage for a read operation. In addition, voltage generator 220 may differently adjust the levels of the program voltage and the read voltage based on the control of control logic 230.

[0034] The control logic 230 may control the general operation of the memory device 200 based on the command CMD, the address ADD, and the control signal CTRL received from the memory controller 100, such as outputting various internal control signals to program data on the memory cell array 210 or read data from the memory cell array 210. In addition, the control logic 230 may output a voltage control signal (not shown) to adjust the levels of various voltages related to the program operation, the read operation, and the erase operation to be output from the voltage generator 220.

[0035] The memory system 10 may perform a memory operation in response to a request from a host, and the memory controller 100 may provide write data to the memory device 200 or receive read data from the memory device 200. That is, the memory controller 100 may perform host input / output (IO) with the memory device 200 in response to a request from the host.

[0036] In addition, the memory system 10 can perform background operations as internal processes that are unrelated to requests from the host, and for example, the background operations can include various operations such as recycling (or read recycling) and garbage collection. For example, the memory system 10 can copy the data stored in the degraded block (or source block) to another block (or destination block) by performing a recycling operation, and can also generate new free blocks by selectively copying valid data stored in multiple source blocks to one or more destination blocks in a garbage collection operation. In such background operations, data read from the memory device 200 can be provided to the memory controller 100, and in addition, data can be provided from the memory controller 100 to the memory device 200 to copy the data. That is, the memory controller 100 can perform internal IO related to the background operation with the memory device 200.

[0037] For example, during the time period after the triggering of the recycling until the recycling is completed, the memory system 10 may perform the recycling operation and the memory operation together in response to the request from the host. For example, according to a specific setting ratio, the memory controller 100 may send data to the memory device 200 and receive data from the memory device 200 in response to the request from the host and for the background operation that is not related to the host request. The memory controller 100 may set an IO ratio indicating the execution ratio of the internal IO operation ("internal IO") to the host IO operation "host IO", or otherwise, and execute the host IO and the internal IO according to the set IO ratio. Accordingly, when the execution ratio of the host IO is set very high, the response to the request from the host can be provided quickly, and thus the performance of the memory system 10 can be improved. However, when the execution ratio of the internal IO is set very low, because the speed of the background operation is reduced, the time spent on the background operation increases, and thus the data stored in the degraded block may be lost, thereby increasing the possibility of an uncorrectable error correction code (UECC) error.

[0038] In contrast, when the execution ratio of the internal IO is set high, because the speed of the background operation increases, the time taken for the background operation is reduced, and thus the possibility of a UECC error occurring can be reduced, thereby improving data stability. However, when the execution ratio of the host IO is set low, the response to a request from the host may be delayed, and thus the performance of the memory system 10 may be degraded. That is, it is necessary to perform efficient background operations so that the response performance to the host is not degraded while maintaining the reliability of the memory system 10.

[0039] Some example implementations are described below.

[0040] The memory controller 100 may further include an error correction code (ECC) circuit 120, a health level determination circuit (also referred to as a health level determiner) 130, and an IO ratio setting circuit (also referred to as an IO ratio setter) 140. The ECC circuit 120 may perform an error detection operation and an error correction operation on the data read from the memory device 200 based on a specific algorithm. For example, the ECC circuit 120 may detect the number of errors or the bit error rate (BER) occurring in a specific error detection unit (e.g., a page unit), and the memory controller 100 may determine whether to perform background operations in blocks based on the error detection result. In the description of the following embodiments, although the recycling operation is described as an example of a background operation, the embodiments are applicable to other various types of background operations for performing internal IO. In addition, the error detection result may include various detection results, including the number of errors occurring with respect to the data of a specific error detection unit, the BER, etc.

[0041] The health level determination circuit 130 may determine the health level of the block to be recycled. In addition, the IO ratio setting circuit 140 may adjust the speed of the recycling operation by setting the ratio between the host IO and the internal IO based on the determined health level to perform the recycling operation on the corresponding block. For example, if the ratio of the host IO is set very high, the frequency of data transmission and reception according to the request from the host between the memory controller 100 and the storage device 200 will increase. Otherwise, if the ratio of the internal IO is set very high, the frequency of data transmission and reception for recycling operation between the memory controller 100 and the storage device 200 will increase.

[0042] If it is determined based on error detection, etc. that the reliability of a block is reduced, a reclaim operation for the block may be triggered. In this case, it is necessary to complete the reclaim operation for the block before a UECC error occurs, and the memory controller 100 may set the IO ratio to complete the reclaim operation within a read reclaim (RR) to UECC value (the number of reads allowed after the reclaim is triggered). For example, when the RR to UECC value is large, a relatively large number of read operations are allowed even after the reclaim is triggered, and therefore, when setting the IO ratio, the host IO ratio may be set very high. However, because the reliability of a flash memory device (e.g., VNAND) may be reduced for some reason (such as an increase in the number of levels in the flash memory device, etc.), the RR to UECC value may decrease, and therefore, there may be a limit to how high the host IO ratio can be set. In addition, when the IO ratio is calculated based on the worst case of the RR to UECC values ​​of multiple NAND chips included in the flash memory device and the RR to UECC values ​​of multiple sub-blocks included in each NAND chip, the execution frequency of the host IO can be further reduced.

[0043] On the other hand, the IO ratio may be set based on the health level determined for the block on which the reclamation operation is actually to be performed, rather than the IO ratio being set based on the RR to UECC value of the most degraded block, and thus the host IO ratio may be prevented or avoided from being set much lower than the actual degradation of the block, thereby maintaining the optimal performance of the memory system 10. For example, according to the error detection result of the block on which reclamation is to be performed, IO ratios having different values ​​may be set for the block.

[0044] In addition, in an embodiment, the health level determination circuit 130 may also receive block information (not shown) related to a plurality of blocks included in the memory cell array 210, and determine the health level of each block based on a combination of the error detection result and the block information. For example, the block information may include at least some information such as a block write / erase count value, a current temperature, a block location (or block address information), and a reliability index (RI). The block information may be stored in the memory device 200 in a non-volatile manner, and the block information may be provided to the memory controller 100 when the memory system 10 is initially driven. Alternatively, the block information may be stored in a storage circuit (not shown) of the memory controller 100 in a non-volatile manner, and the block information may be provided to the health level determination circuit 130 when determining the health level.

[0045] In addition, part of the block information may be determined by testing during the manufacturing process of the memory system 10 and stored in the memory controller 100 and / or the memory device 200. In addition, another part of the block information may be detected or determined during the operation of the memory system 10 and determined and changed by various circuits in the memory controller 100 and / or the memory device 200. The health level may be determined differently for each block based on the above various information, and the health level may be related to the RR to UECC value of the corresponding block.

[0046] Despite Figure 1 In the embodiment shown in FIG. 1 , the health level determination circuit 130 and the IO ratio setting circuit 140 are separate functional blocks in the memory controller 100, but the health level determination circuit 130 and the IO ratio setting circuit 140 may be implemented by software and loaded and run in a working memory (not shown) in the memory controller 100. In some embodiments, when the memory system 10 is a flash memory system, the memory controller 100 may include a flash translation layer (FTL) having firmware, and the health level determination circuit 130 and the IO ratio setting circuit 140 may be included in the FTL.

[0047] In addition, although it has been described above that the IO ratio setting refers to block information, the term may be defined differently. For example, the IO ratio setting may refer to various information that affects the reliability of the memory device 200, such as chip unit information, information detected from the memory system 10, and other types of information. That is, in some embodiments, the block information may include not only information related to the corresponding block, but also various information related to the reliability of the memory system 10.

[0048] Figure 2 is a block diagram showing the memory controller 300 .

[0049] refer to Figure 2 , the memory controller 300 may include a host interface 310, a memory interface 320, a processor 330, an ECC circuit 340, a working memory 350, a health level determination circuit 360, an IO ratio setting circuit 370, and a block information storage circuit 380. The processor 330 may control the general operation of the memory controller 300 by executing firmware loaded in the working memory 350. For example, the memory controller 300 may output a command / address and a control signal for controlling a host IO and an internal IO of a memory device (e.g., an NVM device) under the control of the processor 330.

[0050] The working memory 350 may be implemented by various memories, for example, at least one of a cache memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), a PRAM, and an MRAM. In addition, as an example of firmware, an FTL may be loaded in the working memory 350, and various functions related to flash memory operations may be performed by driving the FTL.

[0051] The host interface 310 can communicate with the host through various interfaces according to the above embodiments. In addition, the memory interface 320 provides a physical connection between the memory controller 300 and the memory device. For example, commands / addresses, data, etc. can be exchanged between the memory controller 300 and the memory device through the memory interface 320.

[0052] The ECC circuit 340 can perform an ECC encoding process on the data requested to be written, and can perform an ECC decoding process on the read data. The ECC circuit 340 can generate an error detection result by performing an ECC decoding process on a specific unit of data read from the storage device. For example, data read from a page of a block in response to a read request from a host or an internal read of a memory system can be provided to the ECC circuit 340, and it can be determined whether to perform recycling of the block based on the error detection result of the ECC circuit 340. For example, if the number of errors occurring in the read data is greater than a specific reference value, or if the BER of the read data is greater than a specific reference value, the block can be selected as a recycling target.

[0053] The block information storage circuit 380 may include a storage element that stores specific information in a non-volatile manner, and may store a plurality of pieces of block information BLK Info about a plurality of blocks included in the memory device. For example, a test process may be performed on a plurality of blocks including a chip (e.g., a NAND chip) during the manufacturing process of the memory system, and a reliability index (RI) of the NAND chip and / or the plurality of blocks may be measured and stored in the block information storage circuit 380.

[0054] The health level determination circuit 360 may determine the health level of the block to be reclaimed by using the error detection result of the ECC circuit 340, the block information BLK Info from the block information storage circuit 380, and at least some of the information provided from various circuits included in the memory system. In addition, according to the above-mentioned embodiment, the IO ratio setting circuit 370 may set the IO ratio related to the reclaim operation of the block to be reclaimed based on the health level determined for the block to be reclaimed. For example, compared to the block whose health level is determined to indicate a relatively low degree of degradation, the block whose health level is determined to indicate a relatively high degree of degradation may be set to have a higher host IO execution rate.

[0055] Figure 2 The health level determination circuit 360 and the IO ratio setting circuit 370 shown in FIG. 3 may be implemented by hardware circuits or software executed by the processor 330. Alternatively, the health level determination circuit 360 and the IO ratio setting circuit 370 may be configured to have a combination of hardware and software. Figure 2 In the embodiment of FIG. 3 , the health level determination circuit 360 and the IO ratio setting circuit 370 are shown to be separate components, but in the embodiment, the health level determination circuit 360 and the IO ratio setting circuit 370 may be described as components implemented in any one functional block.

[0056] Figure 3 is a block diagram showing an example in which IO ratio setting is performed by software.

[0057] refer to Figure 3 , the health level determination function and the IO ratio setting function in the above-mentioned embodiment can be implemented by software. According to an example, the health level determination function can be implemented by the software of the health level determination module 410, the IO ratio setting function can be implemented by the software of the IO ratio setting module 420, and the health level determination module 410 and the IO ratio setting module 420 can be loaded into the working memory 400. In addition, a recycling module 430 configured to control a recycling operation as a background operation and a garbage collection module 440 configured to control a garbage collection operation as a background operation can be further loaded in the working memory 400. As described above, the FTL can be loaded into the working memory 400 in the form of firmware, and the health level determination module 410 and the IO ratio setting module 420 can be described as components included in the FTL.

[0058] Figure 4 is a flow chart illustrating a method of operation of a memory system.

[0059] refer to Figure 4 , a block (hereinafter referred to as a first block) may be selected as a reclamation target based on a read in response to a request from a host, a patrol read of a memory system, a read interval neighbor check (RINC), etc. If the first block is selected as the reclamation target, a read operation may be performed on at least one sample page included in the first block in operation S11, and an error bit may be determined through an error detection operation on the read data in operation S12. Therefore, a current error bit existing in the first block to be reclaimed may be determined.

[0060] At least one sample page may be selected from a plurality of pages included in the first block, and sample pages of the same or different positions may be set for a plurality of blocks. For example, in each block, the sample page may correspond to at least one page with relatively low reliability among the plurality of pages. In addition, in an embodiment, a sample page set of each block may be tested and determined during the manufacturing process of the memory device, and information indicating the location of the sample page may be stored in the memory device or the memory controller.

[0061] In addition, in operation S13, block information of the first block can be determined, and according to the above-mentioned embodiment, the block information may include various information, such as pre-stored information, multiple pieces of information generated by various circuit blocks in the memory system (e.g., write / erase count values, temperature information, etc.), and a block address indicating the location of the first block. In addition, in operation S14, the health level of the first block can be determined based on a combination of the error detection result and the block information, and the IO ratio of the first block can be set based on the determination result of the health level. The RR to UECC value of the first block can be calculated or estimated based on the determined health level, and the ratio between the host IO and the internal IO can be set to correspond to the determined health level. In addition, in the process of performing recycling on the first block, the host IO and the internal IO can be performed according to the set ratio in operation S15.

[0062] Although the above description illustrates that the recycling is triggered based on the error detection result of the random page requested by the host or read internally, and the health level is determined based on the error detection result of the sample page, various modifications can be made to the implementation. For example, the health level can be determined based on the error detection result of the random page requested by the host or read internally. Alternatively, the health level can be determined by combining the error detection result of the random page and the error detection result of the sample page.

[0063] Figure 5 is a graph showing an example of differently setting an IO ratio according to an RR to UECC value.

[0064] refer to Figure 5 , when the recycling of the first block is triggered, data can be read from the sample page of the first block, and the current error bit can be detected from the data of the sample page. In addition, the degree of degradation of the first block can vary according to the state of the first block, and according to the above embodiment, the health level related to the RR to UECC value of the first block can be determined based on the block information. As a result of the health level determination, if it is determined that the degree of degradation of the first block is low, it can be calculated that the RR to UECC value of the first block is relatively large, and if it is determined that the degree of degradation of the first block is high, it can be calculated that the RR to UECC value of the first block is relatively small.

[0065] If it is determined that the health level of the first block is low, a small number of reads are allowed before a UECC error occurs, and therefore, the internal IO ratio of the first block needs to be set relatively high compared to a case where the health level is high. Otherwise, if it is determined that the health level of the first block is high, a large number of reads are allowed before a UECC error occurs, and therefore, the internal IO ratio of the first block is set relatively low compared to a case where the health level is low. That is, when recycling is performed on any one block, depending on the degree of degradation of the block, the speed of the recycling operation can be increased by setting the internal IO ratio high (or setting the host IO ratio low), or a response to a request from the host can be quickly provided by setting the internal IO ratio low (or setting the host IO ratio high).

[0066] Figure 6 is a block diagram illustrating a memory device 500 .

[0067] refer to Figure 6 , the memory device 500 may include a memory cell array 510, an address decoder 520, a page buffer 530, a voltage generator 540, a control logic 550, and an IO circuit 560. Figure 6 Although not shown in the figure, the memory device 500 may further include an IO interface.

[0068] The memory cell array 510 may be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and bit lines BL. The memory cell array 510 may be connected to an address decoder 520 through the word lines WL, string selection lines SSL, and ground selection lines GSL, and to a page buffer 530 through bit lines BL. The memory cell array 510 may include a plurality of memory blocks BLK1 to BLKn.

[0069] Each of the plurality of memory blocks BLK1 to BLKn may include a plurality of pages PG1 to PGm. Each of the plurality of pages PG1 to PGm may correspond to a data programming unit or a data reading unit in one memory block. In some embodiments, the memory cells included in each of the plurality of pages PG1 to PGm may be connected to the same word line. The address decoder 520 may select one of the plurality of memory blocks BLK1 to BLKn in the memory cell array 510, select one of the word lines WL of the selected memory block, and select one of the string selection lines SSL.

[0070] The control logic 550 may output various control signals for performing a program operation, a read operation, and an erase operation on the memory cell array 510 based on the command CMD, the address ADD, and the control signal CTRL. The control logic 550 may provide a row address X-ADD to the address decoder 520, a column address Y-ADD to the page buffer 530, and a voltage control signal CTRL_Vol to the voltage generator 540.

[0071] In some embodiments, the control logic 550 may perform a recovery operation in a unit of each storage block in a plurality of storage blocks BLK1 to BLKn. For example, the control logic 550 may perform a read operation on a page of a source block that has triggered recovery among a plurality of storage blocks BLK1 to BLKn, copy the read data to a destination block, and perform an erase operation on the source block after the copy operation is completed. In addition, the control logic 550 may control a garbage collection operation on a plurality of storage blocks BLK1 to BLKn, for example, selectively reading valid data stored in two or more source blocks, and copying the read valid data to one or more destination blocks. The number of source blocks may be greater than the number of destination blocks, and accordingly, one or more blocks may become free based on a garbage collection operation.

[0072] The page buffer 530 may be used as a write driver or a sense amplifier according to an operation mode. In a read operation, the page buffer 530 may sense a bit line BL of a memory cell selected under the control of the control logic 550. The page buffer 530 may dump the sensed data to the IO circuit 560 under the control of the control logic 550. The IO circuit 560 may send and receive various signals / data to and from a memory controller (not shown) outside the memory device 500, and the host IO and internal IO in the above-described embodiment may be performed by the IO circuit 560.

[0073] The control logic 550 may receive an address (e.g., a host address HOST ADD) for a memory operation according to a request from the host or an address (e.g., an internal address Internal ADD) for an internal processing operation (e.g., a recycling operation) from the memory controller. In addition, when performing an IO operation using the memory controller, the IO circuit 560 may perform a host IO for sending and receiving data in response to a request from the host, or perform an internal IO for sending and receiving data related to an internal processing operation (such as a recycling operation). In addition, according to the above-described embodiment, the health level of a block for which recycling has been triggered among a plurality of memory blocks BLK1 to BLKn may be determined, and the ratio between the host IO and the internal IO of the block may be set according to the result of the determination.

[0074] In addition, a sample page may be set for each of the plurality of memory blocks BLK1 to BLKn, and the sample page may include one or more pages in each block. Address information of the sample page may be generated by a test operation during the manufacturing process of the memory device 500, and may be stored in the memory device 500 and / or the memory controller. Alternatively, the error occurrence frequency of the page in the block may be detected while the memory device 500 is driven, and at least one page with the lowest reliability may be determined as a sample page. Figure 6 It shows the case where the second page PG2 in the first block BLK1 is set as a sample page, and for other blocks, pages at different positions can be set as sample pages.

[0075] Figure 7 It is schematically shown Figure 1 A three-dimensional diagram of the structure of the memory device 200.

[0076] refer to Figure 1 and Figure 7 , the memory device 200 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked relative to the second semiconductor layer L2 in a vertical direction VD. In particular, the second semiconductor layer L2 may be located below the first semiconductor layer L1 in the vertical direction VD. In an embodiment, Figure 1 The memory cell array 210 may be formed in the first semiconductor layer L1, and a peripheral circuit (not shown) configured to drive the memory cell array 210 may be formed in the second semiconductor layer L2. Therefore, the memory device 200 may have a structure in which the memory cell array 210 is located on the peripheral circuit, that is, a cell on periphery (COP) structure. The COP structure can reduce the area in the horizontal direction and improve the integration of the memory device 200.

[0077] After forming the peripheral circuit in the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 210 may be formed, and a metal pattern may be formed to electrically connect the word lines WL and the bit lines BL of the memory cell array 210 to the peripheral circuit formed in the second semiconductor layer L2. For example, the bit lines BL may extend in a first horizontal direction or first direction HD1, and the word lines WL may extend in a second horizontal direction or second direction HD2.

[0078] Figure 8 It shows Figure 1 A three-dimensional diagram of a memory cell array 210 is shown.

[0079] refer to Figure 8, the memory cell array 210 may include a plurality of memory blocks BLK0 to BLKi, where i may be a positive integer. Each of the plurality of memory blocks BLK0 to BLKi may have a three-dimensional structure (or a vertical structure). Each of the plurality of memory blocks BLK0 to BLKi may include a plurality of NAND strings extending in a vertical direction VD. Herein, the plurality of NAND strings may be arranged to be separated from each other by a specific distance in a first direction HD1 and a second direction HD2.

[0080] Fig. 9 is a stereoscopic diagram showing the storage block BLKa.

[0081] refer to Fig. 9 , the storage block BLKa can correspond to Figure 8 One of a plurality of storage blocks BLK0 to BLKi. The storage block BLKa is formed in a vertical direction VD relative to a substrate SUB having a first conductivity type (e.g., p-type). A common source line CSL doped with impurities of a second conductivity type (e.g., n-type) may be provided on the substrate SUB. The substrate SUB may be implemented by polycrystalline silicon, and the plate-type common source line CSL may be located on the substrate SUB. A plurality of insulating layers IL extending in a second direction HD2 are sequentially provided on the substrate SUB along the vertical direction VD, and the plurality of insulating layers IL are separated from each other by a specific distance in the vertical direction VD. For example, the plurality of insulating layers IL may include an insulating material, such as silicon oxide.

[0082] A plurality of pillars P sequentially arranged in a first direction HD1 and passing through a plurality of insulating layers IL in a vertical direction VD are disposed on a substrate SUB. For example, the plurality of pillars P may contact the substrate SUB by passing through a plurality of insulating layers IL. Specifically, a surface layer S of each pillar P may include a silicon material having a first type and serve as a channel region. Therefore, the pillars P may be referred to as a vertical channel structure. An inner layer I of each pillar P may include an insulating material (such as silicon oxide) or an air gap.

[0083] The charge storage layer CS is arranged along the exposed surface of the insulating layer IL, the pillar P and the substrate SUB. The charge storage layer CS may include a gate insulating layer, a charge trapping layer and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, a gate electrode GE including a ground selection line GSL, a string selection line SSL and word lines WL0 to WL7 is arranged on the exposed surface of the charge storage layer CS. In addition, the charge storage layer CS, the surface layer S and the ground selection line GSL may be used as a gate selection transistor GST. The charge storage layer CS, the surface layer S and the string selection line SSL may be used as a string selection transistor SST. The drain DR is arranged on a plurality of pillars p. For example, the drain DR may include a silicon material doped with a second conductive type impurity. The bit lines BL1 to BL3 extending in the first direction HD1 and spaced apart from each other at a specific distance in the second direction HD2 are arranged on the drain DR.

[0084] Fig. 10A and Fig. 10B is a table showing an example of health level determination. Fig. 10A and Fig. 10B In the illustrated embodiment, although only block addresses, endurance-related write / erase cycles, temperature information, and a chip reliability index RI are shown together with error detection results of sample pages as block information, in other embodiments, various other types of block information may be used to determine the health level.

[0085] refer to Fig. 10A , the error detection results and the temperature information may be divided into a plurality of levels, and a specific point (e.g., a health point) may be assigned to each of the divided levels. As the health point value decreases, the block characteristics may improve, and in an embodiment, the health level may be calculated by summing the health point values ​​of a plurality of factors (e.g., the error detection results and the block information), and the health level may also be divided into a plurality of levels according to the sum value. In addition, although in Fig. 10A and Fig. 10B An example of summing up health points is shown in FIG. 1 , but the embodiment is not limited thereto, and the health level may be calculated by calculating the health points in various ways. For example, when summing up the health points, weight calculation may be performed by weighting at least some factors. Therefore, when determining the health level, if the importance of the false detection result increases, a relatively large weight may be assigned to the false detection result.

[0086] For example, the error detection result may indicate a ratio of the number of error bits occurring in the sample page to the number of error bits correctable by the ECC circuit employed in the memory system, and it may be determined that the degree of degradation of the block decreases as the ratio decreases. For example, when the value of the error detection result is less than 60%, the value of the health point may be 1, and when the value of the error detection result is greater than 90%, the value of the health point may be 5.

[0087] As another example, the health point may have any value from 1 to 5 depending on the temperature result inside the memory controller or the memory device. Fig. 10A , the value of the health point decreases as the temperature increases, but the embodiment is not limited thereto, and the health point may be set in various ways. For example, if the data retention characteristic is best when the internal temperature is about 20 degrees to about 60 degrees, a health point of a minimum value may be set when the temperature is about 20 degrees to about 60 degrees, and a health point of a larger value may be set when the temperature is less than or equal to 20 degrees or greater than or equal to 60 degrees.

[0088] As another example, the durability of a block may be determined based on various block information, and for example, the durability of a block may decrease as the write / erase count value of the block increases. For example, a write / erase count threshold allowed for a block may be defined, and a health point may be determined based on a ratio of a current write / erase count value of the block to the write / erase count threshold. For example, if the ratio is determined to be less than 30%, the value of the health point may be 1, and if the ratio is determined to be greater than 90%, the value of the health point may be 5.

[0089] As another example, a block address may indicate the location of a block in a storage device, and Fig. 10A In the example shown, when the block address value is small, the block may have a location with good characteristics (e.g., a location in the center area), and when the block address value is large, the block may have a location with poor characteristics (e.g., a location in the edge area). For example, due to process limitations and difficulties, the process characteristics of a block located in the edge area may be lower than the process characteristics of a block located in the center area, and therefore, as the block address value decreases, a small health point value may be set, and as the block address value increases, a large health point value may be set.

[0090] As another example, the RI of the chip may be applied to determine the health level of each block. For example, a test may be performed on a wafer on which a plurality of chips are formed, and an index indicating the reliability of each chip may be calculated and stored in the corresponding chip. The RI may be defined as a plurality of levels, and Fig. 10AA case where A indicating relatively high reliability to E indicating relatively low reliability are defined is shown. In an embodiment, the health point determined according to the RI of a chip can be generally applied to a plurality of blocks included in the chip. That is, even if the health points of all factors except RI are the same, different IO ratios can be set for each chip according to RI.

[0091] Fig. 10B Shown based on Fig. 10A The health points shown calculate the health rating for multiple levels.

[0092] Fig. 10B An example of determining the health level by summing the health points of a plurality of factors is shown, and for example, the first health level as the lowest health level has a value of 20 to 25 obtained by summing the health points, and in this case, the internal IO ratio may have a relatively high value. For example, a plurality of internal IO operations need to be performed in order to perform reclamation on any one block, and the ratio between the host IO and the internal IO during reclamation may be set to 90:10.

[0093] In contrast, the fourth health level, which is the highest health level, has a value of 5 to 10 obtained by summing the health points, and in this case, the internal IO ratio may have a relatively low value. For example, the ratio between the host IO and the internal IO during the recycling period may be set to 99:1. That is, because a large number of reads are allowed for the block with the highest health level until a UECC error occurs, the host IO ratio may be relatively increased.

[0094] Fig. 10A and Fig. 10B The values ​​shown in are only exemplary, and in an embodiment, the health level can be determined based on a combination of various different types of block information, and the IO ratio can also be set to different values. In addition, setting the health point and determining the health level based on the health point calculation can be performed in various other ways.

[0095] Fig.11 is a block diagram illustrating a memory system 600 . Fig.11 An example of generating and transmitting various information related to health level determination is shown. Fig.11 Although not shown in the figure, the memory controller 610 may further include various components such as a processor, a command / address generator, and a command queue, which are configured to perform IO with the memory device 620.

[0096] refer to Fig.11, the memory system 600 may include a memory controller 610 and a memory device 620, and the memory controller 610 and the memory device 620 may exchange commands / addresses CMD / ADD and data DATA with each other. The memory controller 610 may include a temperature sensor 611, a counter 612, an ECC circuit 613, and a health level determination circuit 614. In addition, the memory device 620 may include a memory cell array 621 and a control logic 622.

[0097] In the initial operation of the memory system 600, various information for making the memory system 600 work may be provided from the memory device 620 to the memory controller 610. For example, the memory cell array 621 may store at least one block information BLK-Info for health level determination, and the at least one block information BLK-Info may be provided to the memory controller 610. The memory cell array 621 may include one or more NAND chips, each NAND chip may include a plurality of blocks, and the at least one block information BLK Info may include information related to the reliability of each of the plurality of blocks and information related to the reliability of the NAND chip unit. The information related to reliability may include various information, such as information indicating whether the data retention characteristic of each block is high or low. In addition, the at least one block information BLK Info may be information generated and stored during the manufacturing process of the memory device 620 and having a fixed value. Alternatively, the at least one block information BLK Info may be information whose value is changed and updated as the operation progresses of the memory device 620, and may also include, for example, information indicating the progress state of block degradation and information about blocks determined to be bad blocks.

[0098] According to the above embodiment, the health level determination circuit 614 can determine the health level of the block by using the error detection result (e.g., the error detection result of the sample page) and at least one block information BLK Info. For example, the health level determination circuit 614 can receive temperature information from the temperature sensor 611, receive the block write / erase cycle count value from the counter 612, receive the error detection result from the ECC circuit 613, and receive the at least one block information BLK Info.

[0099] exist Fig.11 In the illustrated embodiment, since the temperature sensor 611 is included in the memory device 620, temperature information may be provided from the memory device 620 to the memory controller 610. In addition, at least one block information BLK Info for health level determination may be stored in the memory controller 610. Alternatively, at least one block information BLK Info may be stored in the memory controller 610 and the memory device 620.

[0100] Fig.12 is a flowchart illustrating an operating method of a memory system according to a modifiable embodiment. Fig.12 The illustrated implementation may include operations performed in a memory controller.

[0101] The memory controller may read one or more pages of the block in response to a request from the host, perform a patrol read or RINC independent of the request from the host in operation S21, and determine the number of errors occurring in the read data or determine whether the error rate of the read data is greater than or equal to a specific threshold in operation S22. If it is determined that the number of errors or the error rate is greater than or equal to the specific threshold, recycling of the corresponding block (hereinafter referred to as the first block) may be triggered in operation S23.

[0102] The degradation state of the first block can be estimated based on the above error detection result, and in operation S24, one or more sample pages with relatively low reliability can be selected from multiple pages of the first block, and error detection and determination can be performed on data read from the one or more sample pages. In addition, in operation S25, one or more block information related to the first block can be determined, and in operation S26, the health level of the first block can be determined based on a combination of the error detection result and one or more block information of the one or more sample pages, and the IO ratio of the first block can be set.

[0103] According to the above embodiment, the recycling triggering benchmark and the health level determination benchmark may be related to the error detection results of different pages of the first block. For example, if the number of errors in the random pages of the first block is greater than a specific threshold, the recycling of the first block is triggered, but the reliability of the sample pages of the first block may be lower than that of the random pages, so the RR to UECC value of the first block can be more accurately determined by the error detection results of the sample pages. That is, by setting the recycling triggering benchmark and the health level determination benchmark differently, the speed of the recycling operation on the first block before the UECC error occurs can be optimally set.

[0104] Fig.13A and Fig. 13B is a block diagram showing an example in which the embodiments are applied to various memory systems. Fig.13A A NAND chip 700A is shown, and Fig. 13B A case where super blocks are defined for a plurality of NAND chips (eg, first to Kth NAND chips NAND 1 to NAND K) and recycling is performed in super block units is shown.

[0105] refer to Fig.13A, the NAND chip 700A may include a plurality of blocks, for example, a first block BLK 1 to an A-th block BLK A, the number of errors occurring in a sample page of the first block BLK 1 is B, and the number of errors occurring in a sample page of the A-th block BLK A is also B. In addition, the sample page of the first block BLK 1 and the sample page of the A-th block BLK A may be located at the same position or at different positions.

[0106] In addition, when recycling is triggered on the first block BLK 1 and the A-th block BLK A, block information of each of the first block BLK 1 and the A-th block BLK A may be determined. In some embodiments, the block information may include a block address, and the reliability characteristics of the block may vary according to the position where the block is formed in the horizontal NAND or the vertical NAND. According to the block address, if it is determined that the block characteristic of the first block BLK 1 is lower than the block characteristic of the A-th block BLK A, even if the error detection result of the sample page of the first block BLK 1 is the same as the error detection result of the sample page of the A-th block BLK A, the first block BLK 1 may have a higher internal IO ratio than the A-th block BLK A, and the A-th block BLK A may have a higher host IO ratio than the first block BLK 1.

[0107] refer to Fig. 13B , the memory device 700B may include a first NAND chip NAND 1 to a Kth NAND chip NAND K, and blocks respectively included in the first NAND chip NAND 1 to the Kth NAND chip NAND K may be defined as one super block. As an implementation example, one block located at the same position in each of the first NAND chip NAND 1 to the Kth NAND chip NAND K may be included in the super block. In addition, sample pages defined for the K blocks included in the super block may be located at the same position or at different positions.

[0108] If recycling is triggered based on the error detection result of any block included in the super block, recycling operations can be performed on all blocks included in the super block at the same time. In this case, the error detection result and block information of the sample page can be used to perform a health level determination operation on each block in the super block. In addition, an IO ratio can be set based on the block determined to have the lowest health level, and recycling operations can be performed on all blocks included in the super block based on the set IO ratio.

[0109] Alternatively, error detection results may be generated from sample pages of all blocks included in the super block, and a health level determination operation using block information may be selectively performed only on blocks with the worst error characteristics. An IO ratio may be set according to the health level determined for a selected block, and the set IO ratio may be applied to all blocks included in the super block.

[0110] Alternatively, each of the first to Kth NAND chips NAND 1 to NAND K may include reliability information indicating the RI of the corresponding chip as block information. In this case, all blocks included in the super block may have the same position in the corresponding chips of the first to Kth NAND chips NAND 1 to NAND K, and since writing / erasing, etc. are performed at the same time, the degree of degradation of the blocks may be substantially the same. In addition, the temperature detected from the first to Kth NAND chips NAND 1 to NAND K included in the memory device 700B may be the same. In this case, factors affecting the health level of all blocks included in the super block may include the error detection result of a sample page of each of the K blocks included in the super block and the chip reliability information.

[0111] For example, a block serving as a reference for setting the IO ratio may be selected from among the K blocks included in the super block based on a result obtained by calculating a health point depending on an error detection result and a health point depending on the chip RI. In some embodiments, the chip RI may have a fixed value, and the block serving as a reference for setting the IO ratio may be determined based on the error detection results of the K blocks included in the super block. For example, even if the error characteristics of a sample page of a block in the first NAND chip NAND 1 are worse than the error characteristics of a sample page of a block in the Kth NAND chip NAND K, if the chip reliability of the Kth NAND chip NAND K is lower than the chip reliability of the first NAND chip NAND 1, the block in the Kth NAND chip NAND K may serve as a reference for setting the IO ratio. However, if the error characteristics of the sample page of a block in the first NAND chip NAND 1 become worse due to a greater increase in the degree of degradation of the block of the first NAND chip NAND 1, the block serving as a reference for setting the IO ratio may be changed from the block in the Kth NAND chip NAND K to the block in the first NAND chip NAND 1.

[0112] Fig.14 A recycling operation according to some embodiments is shown. Fig.14 A reclamation queue included in a memory controller is shown, wherein information about blocks for which reclamation has been triggered (eg, each block address information) is stored in the reclamation queue, and reclamation operations on multiple blocks can be sequentially performed based on the order of the information stored in the reclamation queue.

[0113] When the recycling of the ath block Block_a to the jth block Block_j is triggered, the address information of each block of the ath block Block_a to the jth block Block_j can be stored in the recycling queue. According to the current storage order of each block address information in the recycling queue, recycling can be performed in the order of the ath block Block_a to the jth block Block_j.

[0114] The degree of degradation of the information blocks stored in the recycling queue may be determined at regular intervals or irregularly, and the order in which the information is stored in the recycling queue may be changed according to the result of the determination. For example, the health level determination in the above embodiment may be used for order change, and Fig.14 As shown, if it is determined that the health levels of the g-th block Block_g, the h-th block Block_h, the i-th block Block_i, and the j-th block Block_j are relatively low, the storage position of each piece of block address information of the a-th block Block_a to the j-th block Block_j can be changed so that the recycling order of the g-th block Block_g, the h-th block Block_h, the i-th block Block_i, and the j-th block Block_j is earlier than that of other blocks in the recycling queue. In addition, if it is determined that the health levels of the a-th block Block_a, the b-th block Block_b, and the c-th block Block_c are relatively high, the storage position of each piece of block address information of the a-th block Block_a to the j-th block Block_j can be changed so that the recycling order of the a-th block Block_a, the b-th block Block_b, and the c-th block Block_c is later than that of other blocks in the recycling queue. That is, the recycling operation may be first performed on the g-th block Block_g, the h-th block Block_h, the i-th block Block_i, and the j-th block Block_j, and finally performed on the a-th block Block_a, the b-th block Block_b, and the c-th block Block_c.

[0115] In addition, when recycling is performed on a block whose information is stored in the recycling queue, the health level determination according to the above-described embodiment may be performed again when recycling is performed. For example, when recycling is performed on the g-th block Block_g, the health level of the g-th block Block_g may be determined, and the IO ratio may be set according to the determined result. Therefore, different IO ratios may be set for the a-th block Block_a to the j-th block Block_j, and recycling may be performed on the a-th block Block_a to the j-th block Block_j at different speeds.

[0116] In some embodiments, various other methods may be used to change the recycling order of blocks. For example, in terms of changing the recycling order, the error detection results of the sample pages of each of the a-th block Block_a to the j-th block Block_j may be used. According to the error detection results of the sample pages, the recycling order may be changed so that blocks with higher BER are recycled first. Alternatively, if the plurality of blocks stored in the recycling queue are blocks included in a plurality of NAND chips, the change of the recycling order may be performed based on a combination of the error detection results of the sample pages and the RIs of the plurality of NAND chips.

[0117] Fig.15 It shows that according to Fig.14 Flowchart of an operating method of a memory system according to an embodiment shown in FIG.

[0118] refer to Fig.15 , data of a random page in a block may be read based on a request of a host or an internal read, and whether to trigger the recycling of the block may be determined based on an error detection result of the random page. For example, whether to trigger recycling may be determined based on whether a sample page of the block determined in operation S31 is erroneous. In addition, if recycling is triggered, then in operation S32, block address information of the block may be included in a recycling queue.

[0119] The pieces of block address information of the plurality of blocks may be stored in a recycling queue, and errors of all blocks in the recycling queue may be scanned periodically or irregularly in operation S33. Error scanning may include operations of reading sample pages of all blocks in the recycling queue and detecting errors in data read from the sample pages. Furthermore, in operation S34, based on the error detection results of the sample pages, the pieces of the plurality of block address information stored in the recycling queue may be changed to change the recycling order of the plurality of blocks.

[0120] After changing each of the plurality of block address information stored in the recycle queue, the recycle of the block may be performed in the newly set order, and the block information of the block on which the recycle is to be performed may be determined in operation S35. In addition, in some embodiments, the error of the sample page of the block on which the recycle is to be performed may be detected again. According to the above-mentioned embodiment, in operation S36, the health level of the block may be determined based on the combination of the error detection result and / or the block information, and the IO ratio corresponding to the determined health level may be set.

[0121] According to some of the above embodiments, the information to be used for setting the recycling trigger, changing the order in the recycling queue, and the IO ratio setting can be set differently. Fig.15In the case of the method shown, the recycling trigger, the order change in the recycling queue, the IO ratio setting, etc. can be determined based on the error detection results of random pages, the error detection results of sample pages, and different combinations of block information.

[0122] Fig.16 is a block diagram showing an example in which a memory device is applied to an SSD system 800 .

[0123] refer to Fig.16 , the SSD system 800 may include a host 810 and an SSD 820. The SSD 820 exchanges signals with the host 810 through a signal connector SIG and receives power through a power connector PWR. The SSD 820 may include an SSD controller 821, an auxiliary power supply 822, and storage devices 823 to 825. The storage devices 823 to 825 may be vertically stacked NAND flash memory devices. Herein, the SSD 820 may be referred to as a SSD controller 821, an auxiliary power supply 822, and a storage device 823 to 825. Figures 1 to 15 That is, the SSD controller 821 may perform host IO and internal IO using the storage devices 823 to 825, and set the IO ratio according to the above-described embodiment to control background operations on the storage devices 823 to 825. Therefore, the SSD controller 821 may include a health level determination circuit and an IO ratio setting circuit, and determine the health level and set the IO ratio in units of NAND chips included in the storage devices 823 to 825 or in units of blocks for a plurality of blocks included in the NAND chips.

[0124] Although the present disclosure includes many specific implementation details, these details should not be construed as limiting the scope of the claims. The specific functions described in the present disclosure in different embodiments may also be implemented in combination in a single embodiment. On the contrary, the various features described in a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations, and even initially recorded as such, in some cases, one or more features of a combination may be deleted from the combination, and the combination may involve a sub-combination or a variant of a sub-combination.

[0125] While the inventive concept has been shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A memory controller, the memory controller communicating with a memory device including a plurality of blocks, the memory controller comprising: a health level determination circuit configured to determine a health level of a first block among the plurality of blocks based on a combination of an error detection result of data read from a first page of the first block and block information related to determination of a degree of degradation of the first block; as well as an IO ratio setting circuit, wherein the IO is input / output, and the IO ratio setting circuit is configured to set an IO ratio between a host IO operation and an internal IO operation according to the determined health level, wherein the host IO operation is performed by the memory controller to exchange data with the memory device in response to a request from the host, and wherein the memory controller is configured to exchange data with the memory device in association with a background operation of the memory device. During the period of executing the background operation on the first block, the memory controller performs the host IO operation and the internal IO operation with the memory device according to the set IO ratio.

2. The memory controller according to claim 1, wherein: The block information includes at least one of a block address of the first block, a write / erase cycle count of the first block, temperature information generated from the memory controller or the memory device, and a reliability index of the first block.

3. The memory controller according to claim 2, wherein: The block information includes at least one piece of information determined during a manufacturing process, and the memory controller further includes a storage circuit for storing the at least one piece of information in a non-volatile manner, Wherein, the at least one piece of information stored in the storage circuit is provided to the health level determination circuit.

4. The memory controller according to claim 1, wherein: The first block includes a plurality of pages, the first page includes a sample page having a reliability index lower than a threshold reliability among the plurality of pages, and the health level determination circuit determines the health level of the first block based on a combination of an error detection result of the sample page and block information of the first block.

5. The memory controller according to claim 4, wherein: When a number of errors greater than a specific reference value is detected in data read from the second page of the first block based on a request from the host or an internal read operation, a background operation of the first block is triggered, and the health level determination circuit is configured to determine the health level of the first block after the background operation is triggered.

6. The memory controller according to claim 5, wherein: The second page includes a page located at a different position from the sample page in the first block.

7. The memory controller according to claim 4, wherein: When positions of the sample pages set for the plurality of blocks are different from each other, the health level determination circuit determines the health levels of the plurality of blocks by using error detection results of the sample pages located at different positions among the plurality of blocks.

8. The memory controller according to claim 1, wherein: The block address information of the first block to the Nth block among the multiple blocks for which background operations have been triggered is stored in a queue, and the background operations on the first block to the Nth block are performed sequentially according to the storage order of the block address information in the queue, and wherein N is an integer of 2 or greater.

9. The memory controller according to claim 8, wherein: The first block to the Nth block each include the first page, the first page corresponds to a sample page with relatively low reliability among a plurality of pages included in each of the first block to the Nth block, and an order of background operations on the first block to the Nth block is changed based on error detection results of the sample pages of the first block to the Nth block.

10. The memory controller according to claim 9, wherein: The health levels of the first block to the Nth block are respectively determined based on a combination of the block information of the first block to the Nth block and the error detection results of the sample pages of the first block to the Nth block, and an order of background operations on the first block to the Nth block is changed based on the determined health levels.

11. A method for operating a memory controller, the memory controller communicating with a memory device including a plurality of blocks, the method comprising: triggering a background operation on a first block among the plurality of blocks according to an error detection result of data read from at least one first page of the first block; setting an IO ratio between a host IO operation in which the memory controller exchanges data with the memory device in response to a request from a host and an internal IO operation in which the memory controller exchanges data with the memory device in association with a background operation of the memory device to a first value according to a health level of the first block, the IO being input / output, wherein the health level of the first block is determined based on block information related to determination of a degree of degradation of the first block and an error detection result of data read from at least one second page of the first block; as well as During a period in which the background operation is performed on the first block, the host IO operation and the internal IO operation are performed with the memory device according to the IO ratio set to the first value.

12. The method according to claim 11, wherein: When the health level indicates that the degradation degree of the first block is low, the IO ratio is increased, and when the health level indicates that the degradation degree of the first block is high, the IO ratio is decreased.

13. The method according to claim 11, further comprising: triggering a background operation on a second block among the plurality of blocks; as well as When the degradation degree of the second block is higher than the degradation degree of the first block, setting the IO ratio of the second block to a second value based on the health level determined for the second block, The speed of the background operation of the second block is faster than the speed of the background operation of the first block.

14. The method according to claim 11, wherein: The at least one first page is selected by a request from the host or an internal read operation of the memory device, and the at least one second page is at least one sample page having a reliability index lower than a specific threshold among a plurality of pages included in the first block.

15. The method according to claim 11, wherein: The background operation includes a recycling operation of copying data in any source block to any destination block and a garbage collection operation of selectively copying valid data in multiple source blocks to at least one destination block.

16. The method according to claim 11, wherein: The block information includes at least one of a block address of the first block, a write / erase cycle count of the first block, temperature information generated from the memory controller or the memory device, and a reliability index of the first block.

17. The method according to claim 11, wherein: Each piece of block address information of a first block to an Nth block for which a background operation has been triggered among the plurality of blocks is stored in a queue, and the at least one second page corresponds to a sample page having a reliability index lower than a specific threshold among the plurality of pages included in each of the first block to the Nth block, wherein N is an integer of 2 or greater, and The method further comprises: detecting an error in the at least one second page in each of the first block to the Nth block; and An order of background operations on the first block to the Nth block is changed based on the error detection result of the at least one second page.

18. A storage device, comprising: a non-volatile memory device, the non-volatile memory device comprising a plurality of blocks; as well as a memory controller configured to perform a host IO operation and an internal IO operation, wherein the host IO operation is used to exchange data with the non-volatile memory device in response to a request from a host, and the internal IO operation is used to exchange data with the non-volatile memory device in association with a background operation of the non-volatile memory device, wherein the IO is input / output, Wherein, the memory controller is further configured as: setting an execution ratio of the internal IO operation and the host IO operation related to a first block to a first value based on block information related to determination of a degree of degradation of a first block among the plurality of blocks, and setting an execution ratio of the internal IO operation and the host IO operation related to a second block to a second value based on block information related to determination of a degradation degree of a second block among the plurality of blocks, and When the first value is greater than the second value, the speed of the background operation of the first block is faster than the speed of the background operation of the second block.

19. The storage device according to claim 18, wherein: The block information includes at least one of a block address indicating a location of a block, a write / erase cycle count of each of the first block and the second block, temperature information generated from the memory controller or the nonvolatile memory device, and a reliability index of each of the first block and the second block.

20. The storage device according to claim 19, wherein: At least one sample page having a reliability index lower than a specific threshold among a plurality of pages is defined for each of the first block and the second block, the first value being set based on the block information of the first block and an error detection result of the at least one sample page in the first block, and the second value being set based on the block information of the second block and an error detection result of the at least one sample page in the second block.

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