Processing system and electronic device

Abstract

The embodiment of the invention provides a processing system and electronic equipment. The processing system comprises a system-on-chip and a storage chip, the system-on-chip comprises a plurality of control units and a plurality of processing units; the memory chip comprises a plurality of groups of memory banks; the processing unit is connected with the at least two control units; the control unit is connected with at least one group of memory banks, and the control unit is connected with at least two processing units; wherein the control unit is used for distributing the connected memory banks to one or more processing units.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and more particularly to a processing system and an electronic device. Background Art

[0002] With the development of artificial intelligence (AI) technology, the number of parameters in AI models is growing exponentially, and AI applications are placing increasingly higher performance requirements on processors and memories, as well as increasingly higher requirements on the matching between processors and storage systems.

[0003] Dynamic Random Access Memory (DRAM) chips have evolved from two-dimensional to three-dimensional. It is becoming increasingly difficult to increase the capacity of DRAM chips themselves. Improving performance from the perspective of storage modules or system architecture has become a new research direction. Summary of the invention

[0004] In view of this, embodiments of the present application hope to provide a processing system and an electronic device.

[0005] To achieve the above purpose, the technical solution of the embodiment of the present application is implemented as follows:

[0006] On the one hand, an embodiment of the present application provides a processing system, including: a system-level chip and a memory chip;

[0007] The system-level chip includes multiple control units and multiple processing units;

[0008] The memory chip includes a plurality of memory banks;

[0009] The processing unit is connected to at least two of the control units;

[0010] The control unit is connected to at least one group of the storage bodies, and the control unit is connected to at least two of the processing units; wherein the control unit is used to allocate the connected storage bodies to one or more of the processing units.

[0011] In some embodiments, the storage body includes an available storage body and a faulty storage body; the storage space capacity of the faulty storage body is smaller than the storage space capacity of the available storage body;

[0012] The control unit is used to allocate the connected available storage banks to one or more of the processing units.

[0013] In some embodiments, a difference between the quantities of the available memory banks allocated to at least some of the processing units is less than or equal to 1.

[0014] In some embodiments, the memory chip further includes a redundant memory bank;

[0015] The control unit is used to allocate the connected redundant memory banks to one or more of the processing units.

[0016] In some embodiments, the control unit is used to determine the number of the memory banks allocated to the connected processing unit according to the credit value of the processing unit and the total amount of the memory banks;

[0017] The credit value is used to indicate the bandwidth requirement of the processing unit.

[0018] In some embodiments, at least part of the control units in the system-on-chip are connected to at least two of the processing units.

[0019] In some embodiments, some of the control units in the control unit are connected to one of the processing units;

[0020] Each of the processing units is connected to N of the control units; wherein N is an integer greater than 1;

[0021] The total number of the control units is the sum of N / 2 times the total number of the processing units and N / 2.

[0022] In some embodiments, each of the control units is connected to at least two of the processing units;

[0023] Each of the processing units is connected to N control units; wherein N is an integer greater than 1;

[0024] The total number of the control units is N / 2 times the total number of the processing units.

[0025] In some embodiments, a plurality of the memory chips are stacked in sequence in a direction perpendicular to the plane where the system-level chip is located.

[0026] On the other hand, an embodiment of the present application further provides an electronic device, including:

[0027] A processing system as described above;

[0028] A peripheral interface is connected to the processing system.

[0029] In the processing system provided by the embodiment of the present application, since at least one control unit on the system-level chip is connected to multiple processing units, the control unit can allocate part or all of the multiple storage bodies connected and controlled by it to each processing unit according to the storage space capacity of each storage body, so that the number of storage bodies obtained by each processing unit is equal or substantially equal, and the storage space capacity of the storage bodies obtained by each processing unit is equal or substantially equal. The dynamic allocation of storage space capacity and bandwidth in the processing system is realized, and the capacity consistency and bandwidth consistency between the processing units are improved. The storage space capacity of some storage bodies will not become the performance bottleneck of a certain processing unit due to their low storage space capacity, and the available storage space capacity and bandwidth of the entire processing unit will not be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1A to 1C A schematic diagram of the storage space capacity of a storage block provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 2 ;

[0033] Figure 4 A partial schematic diagram of the architecture of a processing system provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 3 ;

[0035] Figure 6 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 4 ;

[0036] Figure 7 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 5 ;

[0037] Figure 8 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 6 ;

[0038] Fig. 9 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 7 ;

[0039] Fig.10 A schematic diagram of the architecture of a processing system provided in an embodiment of the present application Figure 8 ;

[0040] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the embodiments of the present application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0045] AI chips can support complex model training and real-time data processing, which requires extremely high storage space capacity of memory chips and extremely high data transmission speed between memory chips and system-level chips. In order to meet the needs of high-performance computing of AI chips, the processing system is required to provide stable and reliable storage performance, and the capacity and bandwidth provided by the memory chip for each processing element (PE) are required to be consistent. The bandwidth of a PE refers to the amount of data that the PE can receive or send per unit time.

[0046] However, due to the yield problem of memory chips, especially after stacking multiple layers of memory chips, the yield is low and the yield distribution is irregular. This makes it difficult to ensure that the storage space capacity provided to each PE is equal. Specifically, Figure 1A As shown in the figure, a storage group includes four storage blocks. Due to yield issues, the available capacity of each storage block (the size of the available capacity is represented by the size of the rectangular area) is not consistent. If the available capacity of the storage blocks is inconsistent, it may become a performance bottleneck and reduce the bandwidth of the entire PE. In order to ensure that the capacity and bandwidth provided by each storage group are consistent, it is necessary to adjust the capacity of the storage blocks in the storage group to a uniform level, or adjust the capacity of all storage blocks on the storage chip to a uniform level. This process is called "alignment". Specifically, as Figure 1B As shown, taking the storage block BK1 with the lowest capacity as the reference, by giving up part of the available capacity of other storage blocks, the available capacity of each storage block is adjusted to be equal to the available capacity of the storage block BK1. Of course, if the available capacity of a storage block is particularly low, it may seriously affect the performance of the storage group. Figure 1C As shown, to ensure the reliability of the entire memory chip or memory module, the entire memory group (ie, memory blocks BK4 to BK7) can be discarded and the entire memory chip can be downgraded. Obviously, no matter which of the above methods is used, a large amount of memory chip resources will be wasted.

[0047] AI chips generally use a network on chip (NOC) architecture to organize different processing units and memories on the same chip. In the NOC architecture, each processing unit is connected to an internal network, and data is transmitted between nodes through routers. Each router is a network node, which uses routers to connect various processing units in the system on chip (SoC) by simulating a network. In order to provide consistent capacity and bandwidth for each processing unit, factors such as routing algorithms, traffic control, and network topology need to be considered, making the design of the NoC communication architecture much more complicated than the traditional bus design.

[0048] In view of this, an embodiment of the present application provides a processing system, such as Figure 2 As shown, the processing system includes: a system-level chip 201 and a memory chip 202;

[0049] The system-on-chip 201 includes a plurality of control units 203 and a plurality of processing units 204;

[0050] The memory chip 202 includes a plurality of memory banks 205;

[0051] The processing unit 204 is connected to at least two of the control units 203;

[0052] The control unit 203 is connected to at least one group of the storage bodies 205 , and the control unit 203 is connected to at least two of the processing units 204 ; wherein the control unit 203 is used to allocate the connected storage bodies 205 to one or more of the processing units 204 .

[0053] The memory chip 202 is used to store data, and it can be organized into multiple groups of memory bodies 205, wherein each memory body 205 can include multiple memory arrays or multiple memory cells. Each memory body 205 can independently perform read or write operations. For example, a DRAM chip that uses the amount of charge stored in a capacitor to store data includes multiple memory banks, and each memory bank has a certain amount of storage space. Specifically, each memory bank can include multiple memory arrays, and each memory array can include multiple memory cell cells (for example, a memory cell of a 1T1C structure includes a transistor and a capacitor). In addition, each memory bank has an independent row decoder (Row Decoder), column decoder (Column Decoder) and buffer (Row Buffer), and can independently perform operations such as activation (Activate), reading (Read), writing (Write) and precharge (Precharge).

[0054] The control unit 203, namely the memory controller (MC), is connected to the storage chip 202 through a specific interface. The system-level chip 201 includes multiple control units 203, each of which is used to manage and control the data transmission between the processing unit 204 and multiple storage bodies 205, and then implement the data read and write operations on these storage bodies 205. Specifically, the control unit 203 can translate the logical address of the data sent by the processing unit 204 into a physical address, and generate access commands such as read (Read), write (Write), refresh (Refresh), etc. according to the request of the processing unit 204.

[0055] The processing unit 204 is the smallest hardware unit in the system-on-chip 201 that can execute instructions. Exemplarily, the processing unit 204 can be a core in a central processing unit (CPU), a stream processor in a graphics processing unit (GPU), or a tensor core in a tensor processing unit (TPU). Multiple processing units 204 can be configured to process data in parallel to increase the processing speed of the entire processing system. It should be noted that the multiple processing units in the processing system provided in the embodiment of the present application can be the same core or different cores.

[0056] The processing unit 204 can access multiple storage bodies 205 through one or more control units 203. These storage bodies 205 can be regarded as a group of storage bodies 205 corresponding to the processing unit 204. Since at least one control unit 203 on the system-level chip 201 is connected to multiple processing units 204, part or all of the multiple storage bodies 205 connected and controlled thereto can be allocated to the corresponding processing units 204 according to the storage space capacity of each storage body, so that the number of storage bodies 205 obtained by each processing unit 204 is equal or substantially equal, and the storage space capacity of the obtained storage bodies 205 is equal or substantially equal. Some storage bodies 205 will not become performance bottlenecks due to their low storage space capacity, thereby reducing the bandwidth of the entire processing unit 204. Among them, the bandwidth of the processing unit 204 refers to the amount of data that the processing unit 204 can receive or send per unit time.

[0057] In a specific embodiment, if Figure 3As shown, the system-level chip 201 includes three control units 203 (control unit MC1, control unit MC2 and control unit MC3), two processing units 204 (processing unit PE0 and processing unit PE1). Each control unit 203 is connected to and controls four storage bodies 205. The control unit MC0 is connected to the processing unit PE0, the control unit MC1 is connected to the processing unit PE0 and the processing unit PE1, and the control unit MC2 is connected to the processing unit PE1. Since the control unit MC1 is connected to the two processing units 204, the control unit MC1 can distribute the storage bodies 205 (storage bodies B04 to storage bodies B07) to the processing unit PE0 and the processing unit PE1 according to the storage space capacity of each storage body 205, so that the number of storage bodies and the storage space capacity allocated to the processing unit PE0 and the processing unit PE1 are the same or substantially the same, thereby improving the consistency between the processing unit PE0 and the processing unit PE1. Since each processing unit 204 can obtain sufficient storage space, the data processing requirements of each processing unit 204 can be met.

[0058] In addition, it should be noted that, for multiple storage banks 205 connected to the same control unit 203, they can be configured as several storage bank groups. Figure 3 , the memory banks B00 and B01 may be configured as the memory bank set BG0, and the memory banks B02 and B03 may be configured as the memory bank set BG1. The control unit MC0 may operate the memory bank set BG0 and the memory bank set BG1 at the rising edge and the falling edge of a clock, respectively, to improve the bandwidth.

[0059] In the processing system provided by the application embodiment, since at least one control unit on the system-level chip is connected to multiple processing units, the control unit can allocate part or all of the multiple storage bodies connected and controlled by it to each processing unit according to the storage space capacity of each storage body, so that the number of storage bodies obtained by each processing unit is equal or substantially equal, and the storage space capacity of the storage bodies obtained by each processing unit is equal or substantially equal. The dynamic allocation of storage space capacity and bandwidth in the processing system is realized, and the capacity consistency and bandwidth consistency between the processing units are improved. Some storage bodies will not become the performance bottleneck of a certain processing unit due to their low storage space capacity, and the available storage space capacity and bandwidth of the entire processing unit will not be reduced.

[0060] In some embodiments, Figure 4 As shown, the storage body 205 includes an available storage body 215 and a faulty storage body 225; the storage space capacity of the faulty storage body 225 is smaller than the storage space capacity of the available storage body 215;

[0061] The control unit 203 is used to allocate the connected available storage 215 to one or more of the processing units 204 .

[0062] During the manufacturing process of the memory chip 202, due to process and other reasons, the yields of different memory banks 205 are different, that is, the storage space capacity that can be normally used in different memory banks 205 is different. If the storage space capacity that can be normally used in a certain memory bank 205 is particularly low, if the other memory banks in a group of memory banks are all pulled down to this level in order to align the memory bank, a large amount of storage space will be wasted. Figure 4 The area size of the storage body is used to indicate the size of the storage space capacity that can be normally used in the storage body. Among them, the storage space that can be normally used in the storage body B04 is the smallest. If the normally usable part of the storage body B04 is retained, in order to ensure consistency, most of the available storage space in the storage bodies B05 to B07 needs to be discarded, resulting in a large waste of storage space.

[0063] Continue to refer Figure 4 By abandoning the faulty storage body B04, the control unit 203 allocates other available storage bodies (storage bodies B05 to storage bodies B07) to the processing unit PE0 and / or the processing unit PE1, so that the number of storage bodies and the storage space capacity allocated to the processing unit PE0 and the processing unit PE1 are the same or basically the same. On the basis of ensuring the consistency between the processing unit PE0 and the processing unit PE1, the storage space of the system is increased and the utilization rate of the memory chip 202 is improved.

[0064] In some embodiments, the difference between the quantities of the available storage bodies 215 allocated to at least some of the processing units 204 is less than or equal to 1.

[0065] Based on the connection status of the available storage body 215 and the faulty storage body 225 , the connection relationship between the processing unit 204 and the available storage body 215 can be dynamically adjusted so that the available storage body 215 can be evenly distributed to each processing unit 204 .

[0066] like Figure 5 As shown, the four storage bodies connected to the control unit MC1 include one faulty storage body (storage body B04) and three available storage bodies (storage bodies B04 to B07); the four storage bodies connected to the control unit MC2 include one faulty storage body (storage body B10) and three available storage bodies (storage bodies B08, storage bodies B09 and storage bodies B11). The control unit MC1 can allocate the available storage body B05 to the processing unit PE0, and allocate the available storage bodies B06 and B07 to the processing unit PE1, so that the number of available storage bodies obtained by the processing unit PE0 is 5, which is equal to the number of available storage bodies obtained by the processing unit PE1.

[0067] In some embodiments, the number of available storage bodies may not be evenly distributed. Available storage bodies 215 may be allocated according to the needs of each processing unit 204, so that the number of available storage bodies 215 allocated to each processing unit 204 is not equal. However, in order to control the performance difference of each processing unit 204, the difference in number should not be too large. For example, the difference in the number of available storage bodies 215 allocated to each processing unit 204 may be 1. Figure 6 As shown, the four storage banks connected to the control unit MC1 include one faulty storage bank (storage bank B04) and three available storage banks (storage banks B04 to B07). The control unit MC1 can allocate available storage banks B05 and B06 to the processing unit PE0, and allocate available storage bank B07 to the processing unit PE1, so that the number of available storage banks obtained by the processing unit PE0 is 5, and the number of available storage banks obtained by the processing unit PE1 is 6.

[0068] In some embodiments, the memory chip 202 further includes a redundant memory bank 235;

[0069] The control unit 203 is used to allocate the connected redundant storage 235 to one or more of the processing units 204 .

[0070] Due to the complexity of the memory chip manufacturing process, memory chips may produce some defective memory cells during the production process. In order to improve the yield and reliability of memory chips, some additional storage space resources are usually configured in the memory chip. This allows the redundant repair technology to be used later to detect defective memory cells in the production process and replace defective rows / columns with redundant rows / columns. Specifically, the address mapping can be changed so that the original address accessing the defective is mapped to the redundant row / column, thereby ensuring that the memory chip can provide the expected storage space capacity and performance. Generally, the enabling and mapping of redundant rows / columns requires fine control at the physical level of the memory chip. For example, in DRAM chips, address decoding and mapping are performed by specific logic circuits, which map logical addresses to physical addresses. Through the built-in logic control of the memory chip, the design complexity of the system-level chip can be reduced. However, for memory chips with fewer defective memory cells, the number of defective rows / columns that need to be repaired is very small, and even redundant row / column resources are not required for corresponding repairs. This will result in the unusable available storage space in the redundant rows / columns, resulting in a waste of resources. In addition, for memory chips with a large number of defective memory cells, there will be insufficient redundant row / column resources. Even if they are repaired through redundant rows / columns, the available storage space capacity of the repaired memory body will not meet the target requirements. In particular, for stacked multi-layer memory chips, there is no distribution pattern for the yield of each layer of chips. Moreover, the yield difference of each layer may be very large, which results in a waste of memory body resources due to the fact that some layers of memory chips have too many defective memory cells and the capacity after repair does not meet the standard, and some layers of memory chips have too few defective memory cells and the redundant resources cannot be used, resulting in a waste of resources. This greatly reduces the utilization rate of multi-layer memory chip resources.

[0071] The redundant memory body 235 (i.e., redundant rows / columns) is directly managed by the control unit 203 in the system-level chip 201, which is equivalent to transferring the repair work of the memory chip from the inside of the memory chip to the system side. All redundant rows / columns can be opened to the system-level chip 201 to fully utilize the storage space resources in the redundant memory body, and there will be no waste of storage space caused by the remaining redundant rows / columns after the internal repair of the memory chip cannot be used by the system.

[0072] In some embodiments, the control unit 203 is used to determine the number of the storage bodies allocated to the connected processing unit according to the credit value of the processing unit 204 and the total amount of the storage bodies 205;

[0073] The credit value is used to indicate the bandwidth requirement of the processing unit.

[0074] In the control unit 203, different bandwidths can be allocated to the processing unit 204 through a credit mechanism. Exemplarily, when the processing unit 204 requests the control unit 203 to perform operations such as read and write, the control unit 203 indicates the number of requests that the control unit 203 can process for each processing unit 204, that is, the number of available storages 215 that can be allocated to each processing unit 204, based on the credit value of the processing unit 204 connected thereto and the storage space capacity of the storage body 205 connected to the control unit 203 (for example, the total amount of available storage bodies 215).

[0075] Continue to refer Figure 5 , both processing unit PE0 and processing unit PE1 can access control unit MC1. According to the bandwidth requirements of processing unit PE0 and processing unit PE1, control unit MC1 can allocate one of the three available storage banks to processing unit PE0 and the other two available storage banks to processing unit PE1 by configuring credit_PE0=1, credit_PE1=2.

[0076] In some embodiments, at least part of the control units 203 in the system-on-chip 201 are connected to at least two of the processing units 204 .

[0077] In some embodiments, part of the control unit 203 in the system-on-chip 201 is connected to two or more processing units 204. The storage bodies 205 accessible to these processing units 204 are formed into a storage pool. Through this part of the control unit 203, the accessible storage space of each processing unit can be dynamically adjusted according to the available storage bodies and faulty storage bodies in the storage pool, so that the unified management of the storage space in the storage pool can be achieved. Even if there is a faulty storage body, it does not affect the use of other available storage bodies in the control unit connected to it.

[0078] It should be noted that, according to the connection relationship between the processing unit and the control unit, the memory chip 202 can be divided into one or more memory pools, each memory pool includes memory bodies corresponding to multiple processing units, and each memory pool is independent of each other. Figure 7 As shown, the memory banks corresponding to the processing units PE0 and PE1 (including memory banks B00 to B11) can be divided into one memory pool, and the memory banks corresponding to the processing units PE2 and PE3 (including memory banks B12 to B23) can be divided into another memory pool.

[0079] In some embodiments, all control units 203 in the system-on-chip 201 are connected to two or more processing units 204. At this time, all storage bodies on the memory chip 202 can be regarded as a large storage pool. Each control unit 203 can adjust the number of storage bodies allocated to the processing unit 204 connected thereto according to the bandwidth requirements of the processing unit 204, further increasing the flexibility of the allocation of storage bodies in the processing system. It is understandable that, according to the connection relationship between the processing unit and the control unit, the memory chip 202 can also be divided into one or more smaller storage pools, each small storage pool includes storage bodies corresponding to multiple processing units, and the small storage pools are independent of each other.

[0080] In some embodiments, some of the control units in the control unit are connected to one of the processing units;

[0081] Each of the processing units is connected to N of the control units; wherein N is an integer greater than 1;

[0082] The total number of the control units is the sum of N / 2 times the total number of the processing units and N / 2.

[0083] In a resource pool consisting of m processing units and n control units, if each processing unit is connected to N control units, N of the n control units are connected to one processing unit, and the other control units are connected to two control units, then the total number of processing units m and the total number of control units n satisfy the following formula (1):

[0084]

[0085] Continue to refer Figure 5 In the system-on-chip 201, the control unit MC0 is only connected to the processing unit PE0; the control unit MC2 is only connected to the processing unit PE1; the control unit MC1 is connected to both the processing unit PE0 and the processing unit PE1. The multiple storage bodies connected to the three control units form a storage pool. Even if a faulty storage body (for example, storage bodies B04 and B10) occurs in the storage pool, by dynamically adjusting the available storage bodies allocated to the processing unit PE0 and the processing unit PE1 through the control unit MC1 connected to both the processing unit PE0 and the processing unit PE1, the system can evenly allocate the remaining available storage bodies 215 to the processing unit PE0 and the processing unit PE1.

[0086] In some embodiments, each of the control units 203 is connected to two of the processing units 204;

[0087] Each of the processing units 204 is connected to N control units; wherein N is an integer greater than 1;

[0088] The total number of the control units 203 is N / 2 times the total number of the processing units 204 .

[0089] In a resource pool consisting of m processing units and n control units, if each control unit 203 is connected to two processing units 204, and each processing unit is connected to N control units, then the total number of processing units m and the total number of control units n satisfy the following formula (2):

[0090]

[0091] like Figure 8 As shown in FIG. 1 , the system-level chip includes three processing units (PE0, PE1, and PE2) and three control units (MC0, MC1, and MC2). Each processing unit can access the memory chip through two control units. Each control unit can adjust the number of memory banks allocated to the processing unit connected to it according to the bandwidth requirements of the processing unit, thereby increasing the flexibility of the system.

[0092] It should be noted that, continue to refer to Figure 8 If the three processing units are arranged in a horizontal linear direction on the system-level chip 201, the connection circuit between the processing unit PE2 and the control unit MC0 may be too long, resulting in signal delay or inconsistent performance of each processing unit. Based on this, in other embodiments, each processing unit 204 and each control unit 203 can be arranged in a ring in the system-level core 201.

[0093] In some embodiments, a plurality of the memory chips are stacked in sequence in a direction perpendicular to the plane where the system-level chip is located.

[0094] Higher storage density and performance can be achieved by stacking multiple layers of memory chips in the vertical direction. For example, a 3D DRAM chip is obtained by stacking multiple DRAM layers in the vertical direction. By directly stacking the 3D DRAM chip with the SOC chip and connecting them through high-density through silicon vias (TSV), the data transmission path can be greatly shortened, thereby reducing signal delay and significantly improving data transmission bandwidth. It should be noted that the 3D DRAM chip and the SOC chip can also be laid on the same horizontal plane. As long as they are integrated in the same package, the operating efficiency within the system can be effectively improved.

[0095] The present application also provides a comparative example and a specific example:

[0096] Fig. 9 A processing system in a comparative embodiment is shown. Fig. 9As shown, the system-level chip 201 includes four processing units and eight control units, and each processing unit is connected to two control units. Each processing unit can independently position the corresponding eight storage bodies. Since there are two faulty storage bodies (storage body B24 and storage body B25) among the four storage bodies connected to the control unit MC5, in order to ensure that the storage space capacity of each processing unit is the same, a method is to configure the available storage bodies in all control units to two, so that the storage space of the entire memory chip 202 is halved. Alternatively, all the storage bodies (including available storage body B26 and available storage body B27) in the control unit MC6 are abandoned. Although only two available storage bodies are reduced, it will cause bandwidth loss of the control unit MC6.

[0097] like Fig.10 As shown, the memory chip 202 is a 3D DRAM chip, including multiple memory bodies. The system-level chip 201 includes three processing units and eight control units, each processing unit is connected to four control units, and the control unit is connected to one or two processing units. The 32 memory bodies connected by the three processing units through the eight control units form a resource pool, and this connection architecture can be called a "Butterfly" resource pool architecture. When some of the memory bodies in the resource pool are faulty memory bodies, the control unit can distribute all the available memory bodies evenly to each processing unit according to the distribution of the faulty memory bodies and the available memory bodies. Among them, the processing units and memory bodies with the same shading can be regarded as a group, and the software can control each processing unit to access the memory bodies in its corresponding group. For example, the processing unit PE0 can access the memory bodies B00, B01 and B02 through the control unit MC0; and access the memory body B04 through the control unit MC1.

[0098] The "Butterfly" resource pool architecture can realize dynamic allocation of storage space. Specifically, since the control unit MC1 is connected to two different processing units, it can be accessed by the processing unit PE0 and the processing unit PE1. The storage body connected to the control unit MC1 can be proportionally allocated to the processing unit PE0 and the processing unit PE1 as needed. Similarly, the storage bodies corresponding to the control unit MC2, the control unit MC5 and the control unit MC6 connected to the two processing units are proportionally allocated to each processing unit to realize unified management of the resource pool. Even if a certain storage body is a faulty storage body, it will not affect the normal use of other available storage bodies in the group or other available storage bodies on the storage chip.

[0099] In some extreme cases, for example, if the eight storage bodies corresponding to the control unit MC1 and the control unit MC5 are all faulty storage bodies, the storage bodies in the resource pool may not be evenly distributed. However, it is understandable that the probability of such an extreme situation is extremely small and can generally be ignored. In addition, it should be noted that in Figure 8In the ring connection architecture shown, even if the above extreme situation occurs, it will not affect the average distribution of available storage banks in the system.

[0100] The "Butterfly" resource pool architecture can realize dynamic allocation of bandwidth. Specifically, in the control unit MC1 or the control unit MC5, the bandwidth can be dynamically allocated by configuring credit_PE0 and credit_PE1, so that the processing unit PE0 and the processing unit PE1 have the same storage space capacity and the same bandwidth to meet the requirements of each processing unit in the AI ​​multi-core application.

[0101] The "Butterfly" resource pool architecture can achieve improved yield in 3D DRAM applications. Assuming that the yield of a memory bank or memory macro (DRAM Macro) including multiple memory cells is 90%, there are 640 memory banks or memory macros in the multi-layer stacked memory chip, and each control unit can control 10 memory banks or memory macros. The total available capacity of the 3D DRAM chip is greater than or equal to 80%, and the 3D DRAM chip is considered to meet the target requirements. Fig. 9 In the connection architecture of the processing system shown, one control unit is a body, and all 64 control units in the system need to meet the 80% yield requirement. Under the condition of calculating the yield according to the Poisson distribution, the yield of 3D DRAM chips that meet the target requirements is 0.47%. If the "Butterfly" resource pool architecture is adopted, assuming that the storage body or storage macro corresponding to the 8 control units is a resource pool, then only the 80% yield requirement needs to be met in every 8 control units. According to calculations, the probability that all 8 resource pools in the system meet the 80% yield requirement is 97%, that is, 97% of the memory chips can meet the target requirements. Compared with the former 0.47%, the use of the "Butterfly" resource pool architecture can greatly improve the yield of memory chips.

[0102] In addition, compared with the solution of using NOC bus to connect system-level chips and storage chips, the "Butterfly" resource pool architecture does not increase latency because there is a point-to-point bus between the processing unit and the control unit.

[0103] In addition, the redundant storage bodies in the storage chip 202 can be opened to the system-level chip 201, that is, the system-level chip 201 can access the redundant storage bodies, and then can make full use of this part of the storage space, reduce the waste of storage space, and improve the utilization rate of the storage space in the storage chip 202. Specifically, before bonding the system-level chip 201 and the storage chip 202, there is no need to use the redundant storage bodies to repair the storage chip 202. The repair work of the storage chip 202 is transferred to the system-level chip 201 side. The system selects part or all of the faulty storage bodies for repair according to the distribution of the faulty storage bodies in the entire storage chip. Even if the extreme situation discussed above occurs, the system may still achieve the average distribution of available storage bodies to each processing unit after repairing part of the storage bodies corresponding to the control unit MC1 or the control unit MC5. In addition, the system-level chip 201 can also access the redundant storage bodies remaining after the repair, which greatly increases the accessible storage space capacity of the system.

[0104] Based on the same inventive concept, the embodiment of the present application further provides an electronic device 300, such as Fig.11 The figure includes: the processing system 200 as described above;

[0105] The peripheral interface 301 is connected to the processing system 200 .

[0106] Since the system-level chip and the memory chip in the electronic device are connected to form the above-mentioned processing system 200, which has the same or similar beneficial effects as the above-mentioned processing system 200, the beneficial effects of the electronic device will not be repeated here.

[0107] The various embodiments / implementations provided in this application can be combined with each other without causing any contradiction.

[0108] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A processing system, characterized in that: include: System-on-chip and memory chips; The system-on-chip includes a plurality of control units and a plurality of processing units; The memory chip includes a plurality of memory banks; The processing unit is connected to at least two of the control units; The control unit is connected to at least one group of the storage bodies, and the control unit is connected to at least two of the processing units; wherein the control unit is used to allocate the connected storage bodies to one or more of the processing units.

2. The processing system according to claim 1, characterized in that The storage body includes an available storage body and a faulty storage body; the storage space capacity of the faulty storage body is smaller than the storage space capacity of the available storage body; The control unit is used to allocate the connected available storage banks to one or more of the processing units.

3. The processing system according to claim 2, characterized in that A difference between the quantities of the available storage banks allocated to at least some of the processing units is less than or equal to 1.

4. The processing system according to claim 1, characterized in that The memory chip also includes a redundant memory bank; The control unit is used to allocate the connected redundant memory banks to one or more of the processing units.

5. The processing system according to claim 1, characterized in that The control unit is used to determine the number of the storage bodies allocated to the connected processing unit according to the credit value of the processing unit and the total amount of the storage bodies; The credit value is used to indicate the bandwidth requirement of the processing unit.

6. The processing system according to any one of claims 1 to 5, characterized in that: At least part of the control units in the system-on-chip are connected to at least two of the processing units.

7. The processing system according to claim 6, characterized in that Some of the control units in the control unit are connected to one of the processing units; Each of the processing units is connected to N of the control units; wherein N is an integer greater than 1; The total number of the control units is the sum of N / 2 times the total number of the processing units and N / 2.

8. The processing system according to claim 6, characterized in that Each of the control units is connected to two of the processing units; Wherein, each of the processing units is connected to N control units; wherein N is an integer greater than 1; The total number of the control units is N / 2 times the total number of the processing units.

9. The processing system according to any one of claims 1 to 5, characterized in that: In a direction perpendicular to the plane where the system-level chip is located, a plurality of the memory chips are stacked in sequence.

10. An electronic device, characterized in that: include: The processing system according to any one of claims 1 to 9; A peripheral interface is connected to the processing system.

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