Memory management methods and memory storage devices

Abstract

This invention provides a memory management method and a memory storage device. The memory management method is used in a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical erase units. The memory management method includes: acquiring a plurality of state information corresponding to the plurality of physical erase units, wherein the plurality of state information reflects the operating mode of each physical erase unit and the effective count value of each physical erase unit; and performing a target merging operation based on the plurality of state information, wherein the target merging operation is a first data merging operation or a second data merging operation, the first data merging operation being different from the second data merging operation.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method and a memory storage device. Background Technology

[0002] The rapid growth of smartphones, tablets, and personal computers in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the various portable multimedia devices exemplified above due to their characteristics such as data non-volatility, low power consumption, small size, and lack of mechanical structure.

[0003] To improve the data processing capabilities of storage devices, data consolidation operations such as garbage collection (GC) can be performed to optimize storage space, thereby improving the performance and / or response speed of the storage device.

[0004] Improving the efficiency of waste recycling operations is a topic of concern for those skilled in the art. Summary of the Invention

[0005] Exemplary embodiments of the present invention provide a memory management method and a memory storage device that can improve conventional data merging operations (i.e., garbage collection operations) to enhance the performance of the memory storage device.

[0006] An exemplary embodiment of the present invention provides a memory management method for a rewritable non-volatile memory module, the rewritable non-volatile memory module including a plurality of physical erasure units, the memory management method including: acquiring a plurality of state information corresponding to the plurality of physical erasure units, wherein the plurality of state information reflects the operation mode of each physical erasure unit and the effective count value of each physical erasure unit; and performing a target merging operation based on the plurality of state information, wherein the target merging operation is a first data merging operation or a second data merging operation, the first data merging operation being different from the second data merging operation.

[0007] In an exemplary embodiment of the present invention, the operation mode of each entity erasure unit is one of a single-level storage unit mode, a two-level storage unit mode, a three-level storage unit mode, and a four-level storage unit mode.

[0008] In an exemplary embodiment of the present invention, the step of performing the target merging operation based on the plurality of state information includes: determining a source entity erasure unit from candidate entity erasure units according to the plurality of state information; collecting valid data from the source entity erasure unit; and moving the valid data to the target entity erasure unit and associating the source entity erasure unit with an idle area.

[0009] In an exemplary embodiment of the present invention, the memory management method further includes: based on the plurality of state information, selecting the entity erasure units among the plurality of entity erasure units that have an effective count value lower than a pre-designed value as the candidate entity erasure units.

[0010] In an exemplary embodiment of the present invention, the first data merging operation includes: selecting the source entity erasure unit from the candidate entity erasure units belonging to the single-level storage unit mode; collecting the valid data from the source entity erasure unit; and moving the valid data to the target entity erasure unit and associating the source entity erasure unit with the idle area.

[0011] In an exemplary embodiment of the present invention, the second data merging operation includes: selecting the source entity erasure unit from the candidate entity erasure units that do not belong to the single-level storage unit mode; collecting the valid data from the source entity erasure unit; and moving the valid data to the target entity erasure unit and associating the source entity erasure unit with the idle area.

[0012] In an exemplary embodiment of the present invention, the step of performing the target merging operation based on the plurality of state information includes: determining the number of candidate entity erase units belonging to the single-level storage cell mode; determining whether there are target candidate entity erase units whose number is greater than a preset number, wherein the target candidate entity erase units are at least one of the candidate entity erase units belonging to the single-level storage cell mode; and if there are target candidate entity erase units, performing the first data merging operation.

[0013] In an exemplary embodiment of the present invention, the memory management method further includes: if there is no target candidate entity erasure unit, calculating a total effective count value based on the effective count value of the candidate entity erasure unit belonging to the single-level memory cell mode; determining whether the total effective count value is greater than a preset total value; if the total effective count value is greater than the preset total value, performing the first data merging operation; and if the total effective count value is not greater than the preset total value, performing the second data merging operation.

[0014] In an exemplary embodiment of the present invention, the preset total value is associated with the capacity of the entity erasure unit.

[0015] In an exemplary embodiment of the present invention, the valid count value is used to represent the number of entity programmatic units in each entity erasure unit used to store valid data.

[0016] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The connection interface unit is used to couple to a host system. The rewritable non-volatile memory module includes a plurality of physical erase units. The memory control circuit unit is used to acquire a plurality of state information corresponding to the plurality of physical erase units, wherein the plurality of state information reflects the operating mode of each physical erase unit and the effective count value of each physical erase unit. The memory control circuit unit is further used to perform a target merging operation based on the plurality of state information, wherein the target merging operation is a first data merging operation or a second data merging operation, the first data merging operation being different from the second data merging operation.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine a source entity erasure unit from candidate entity erasure units based on the plurality of state information. The memory control circuit unit is also configured to collect valid data from the source entity erasure unit. The memory control circuit unit is further configured to move the valid data to a target entity erasure unit and associate the source entity erasure unit with an idle area.

[0018] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to, based on the plurality of state information, select the entity erasure units among the plurality of entity erasure units that have an effective count value lower than a pre-designed value as the candidate entity erasure units.

[0019] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to select the source entity erasure unit from the candidate entity erasure units belonging to the single-level memory cell mode. The memory control circuit unit is further configured to collect the valid data from the source entity erasure unit. The memory control circuit unit is further configured to move the valid data to the target entity erasure unit and associate the source entity erasure unit with the idle area.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to select the source entity erasure unit from the candidate entity erasure units that do not belong to the single-level memory cell mode. The memory control circuit unit is further configured to collect the valid data from the source entity erasure unit. The memory control circuit unit is further configured to move the valid data to the target entity erasure unit and associate the source entity erasure unit with the idle area.

[0021] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine the number of candidate entity erase units belonging to the single-level memory cell mode. The memory control circuit unit is further configured to determine whether there are target candidate entity erase units whose number is greater than a preset number, wherein the target candidate entity erase units are at least one of the candidate entity erase units belonging to the single-level memory cell mode. If the target candidate entity erase units exist, the memory control circuit unit is further configured to perform the first data merging operation.

[0022] In an exemplary embodiment of the present invention, if the target candidate entity erasure unit does not exist, the memory control circuit unit is further configured to calculate a total effective count value based on the effective count values ​​of the candidate entity erasure units belonging to the single-level memory cell mode. The memory control circuit unit is further configured to determine whether the total effective count value is greater than a preset total value. If the total effective count value is greater than the preset total value, the memory control circuit unit is further configured to perform the first data merging operation. If the total effective count value is not greater than the preset total value, the memory control circuit unit is further configured to perform the second data merging operation.

[0023] Based on the above, the present invention provides a memory management method and a memory storage device, which can perform a first data merging operation using a source entity eraser that belongs to a single-level memory cell mode or a second data merging operation using a source entity eraser that does not belong to a single-level memory cell mode (e.g., a two-level memory cell mode, a three-level memory cell mode, or a four-level memory cell mode) based on the state information of the entity eraser, so as to improve the performance of the memory storage device.

[0024] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0031] Figure 7 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention;

[0032] Figure 8 This is a flowchart illustrating the execution of the first data merging operation according to an exemplary embodiment of the present invention;

[0033] Figure 9 This is a flowchart illustrating the execution of the second data merging operation according to an exemplary embodiment of the present invention;

[0034] Figure 10 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Detailed Implementation

[0035] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0036] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0037] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0038] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be coupled to a system bus 110.

[0039] In one exemplary embodiment, the host system 11 can be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 can be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0040] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0041] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0042] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the host system 11 is an in-vehicle system. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0043] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0044] Please refer to Figure 3 The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0045] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0046] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0047] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0048] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0049] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0050] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0051] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0052] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In this exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0053] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0054] Please refer to Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0055] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0056] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware format. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are written to the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0057] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0058] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuitry is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuitry 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0059] The host interface 52 is coupled to the memory management circuitry 51. The memory management circuitry 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuitry 51 through the host interface 52. In addition, the memory management circuitry 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0060] The memory interface 53 is coupled to the memory management circuit 51 and used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals or data on the bus. These signals or data may include instruction codes or codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0061] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0062] Error checking and correction circuit 54 is coupled to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0063] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0064] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0065] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0066] Please refer to Figure 6 The memory management circuit 51 can logically group the physical cells 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602. A physical cell refers to a virtual block (VB). A virtual block may include multiple physical programmable units. For example, a virtual block may contain one or more physical erase units.

[0067] Entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 can store valid and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit can be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) can be erased. When new data is written, one or more entity units can be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0068] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in memory area 601. In an exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units.

[0069] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped to a logical unit, it means that the data currently stored in this physical unit contains valid data. Conversely, if a physical unit is not currently mapped to any logical unit, it means that the data currently stored in this physical unit does not contain any valid data.

[0070] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logical units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can perform data access operations on the memory storage device 10 according to the information in this logic-to-entity mapping table.

[0071] Most modern memory storage devices 10 have copyback functionality. In a copyback architecture, frequently accessed or updated data (also known as hot data) is stored in physical erase units based on single-level cell (SLC) mode. Infrequently accessed or updated data (also known as cold data) is stored in physical erase units based on two-level cell (MLC), three-level cell (TLC), or four-level cell (QLC) mode, depending on the specifications of the memory storage device 10.

[0072] It should be noted that conventional data merging operations (e.g., garbage collection) select the source entity erase unit based on the valid count value. Therefore, the memory management circuit 51 often uses a single-level memory cell mode entity erase unit as the source entity erase unit, so that hot data and cold data (e.g., data stored in a three-level memory cell mode entity erase unit) in the single-level memory cell mode entity erase unit are mixed in one entity erase unit (i.e., the target entity erase unit). Accordingly, when the hot data in this entity erase unit is overwritten in a write operation, the valid count value of this entity erase unit will decrease, and it will be used as the source entity erase unit for subsequent data merging operations.

[0073] As described above, under normal data merging operations, hot and cold data will be mixed, causing the same entity erase unit to be repeatedly used as the source entity erase unit, which will increase the frequency of data merging operations and cause wear on the rewritable non-volatile memory module 43, thereby reducing the performance of the memory storage device 10.

[0074] In view of this, the present invention provides a memory management method that can employ different data merging operations based on multiple state information corresponding to multiple entity erase units in a rewritable non-volatile memory module 43, in order to avoid the above-mentioned problems.

[0075] Figure 7 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Please refer to... Figure 7 The steps shown are as follows:

[0076] In step S701, the memory management circuit 51 can obtain multiple status information corresponding to multiple entity erasure units.

[0077] In one exemplary embodiment, the status information may, for example, reflect the operating mode and valid count value of the corresponding physical erase unit. The operating mode may include, but is not limited to, single-level cell (SLC) mode, two-level cell (MLC) mode, three-level cell (TLC) mode, or four-level cell (QLC) mode. That is, a physical erase unit may be written with data, for example, based on a single-level cell mode, a two-level cell mode, a three-level cell mode, or a four-level cell mode.

[0078] The valid count value represents the number of entity programmable units used to store valid data in an entity erasure unit. In other words, the valid count value reflects the occupied capacity of valid data stored in an entity erasure unit.

[0079] It should be noted that after receiving a write instruction from the host system 11, the memory management circuit 51 can write data to at least one physical programmable unit (e.g., two) in a corresponding physical erase unit according to the write instruction. After the memory management circuit 51 writes data to these two physical programmable units, the memory management circuit 51 can increment the valid count value of this physical erase unit by 2. On the other hand, when the data stored in at least one physical programmable unit (e.g., three) in a physical erase unit is deleted or marked as invalid data, the memory management circuit 51 can decrement the valid count value of this physical erase unit by 3.

[0080] In step S702, the memory management circuit 51 can select, based on multiple status information, the entity erasure units with valid count values ​​lower than the pre-designed value among the multiple entity erasure units as candidate entity erasure units.

[0081] In one exemplary embodiment, the memory management circuit 51 can determine whether the valid count value corresponding to each entity erase unit is lower than a pre-designed value, in order to select candidate entity erase units for subsequent target merging operations. Specifically, the valid count value corresponding to an entity erase unit can reflect the occupied capacity of the valid data it stores. The pre-designed value is used to represent the lower limit number of entity programmable units that need to be used to store valid data in an entity erase unit. That is, the pre-designed value can reflect the lower limit occupied capacity of the valid data stored in an entity erase unit. Regarding the pre-designed value, it can be designed by the user according to actual needs, and the present invention does not impose any limitations.

[0082] If the valid count value of a physical erase unit is lower than the pre-designed value, meaning that the occupied capacity of the valid data stored in this physical erase unit is lower than the preset capacity reflected by the pre-designed value, the memory management circuit 51 can select this physical erase unit as a candidate physical erase unit. Conversely, if the valid count value of a physical erase unit is not lower than the pre-designed value, meaning that the occupied capacity of the valid data stored in this physical erase unit is not lower than the preset capacity reflected by the pre-designed value, then this physical erase unit will not be selected as a candidate physical erase unit.

[0083] In step S703, the memory management circuit 51 can determine the number of candidate entity erase units belonging to the single-level memory cell mode.

[0084] In one exemplary embodiment, the operating mode of the candidate entity erase unit may be, for example, a single-level cell (SLC) mode, a three-level cell (TLC) mode, or a four-level cell (QLC) mode. The memory management circuit 51 can obtain the operating mode of each candidate entity erase unit based on the state information corresponding to each candidate entity erase unit, and calculate the number of candidate entity erase units belonging to the single-level cell mode among all candidate entity erase units.

[0085] In step S704, the memory management circuit 51 can determine whether there are target candidate entity erasure units in greater numbers than a preset number.

[0086] Specifically, the preset number can be designed by the user according to actual needs, and this invention does not impose any limitations. In an exemplary embodiment, the target candidate entity erasure unit is at least one of the candidate entity erasure units belonging to the single-level storage unit mode.

[0087] If a target candidate entity erasure unit exists, proceed to step S705 to perform a first data merging operation. This first data merging operation is performed on candidate entity erasure units in a single-level storage unit mode.

[0088] In step S705, the memory management circuit 51 can perform a first data merging operation. Details regarding the implementation of the first data merging operation are as follows: Figure 8 As shown, Figure 8 This is a flowchart illustrating the execution of the first data merging operation according to an exemplary embodiment of the present invention. Please refer to the simultaneous... Figure 7 and Figure 8 .

[0089] In step S7051, the memory management circuit 51 can select a source entity erasure unit from the candidate entity erasure units belonging to the single-level memory cell mode, and select a target entity erasure unit.

[0090] In one exemplary embodiment, the memory management circuit 51 uses a candidate entity erase unit belonging to a single-level memory cell mode as the source entity erase unit for the first data merge operation. That is, candidate entity erase units that do not belong to a single-level memory cell mode (i.e., a three-level or four-level memory cell mode) cannot be used as the source entity erase unit for the first data merge operation. Alternatively, the memory management circuit 51 may select an entity erase unit as the target entity erase unit for the first data merge operation.

[0091] In step S7052, the memory management circuit 51 can collect valid data from the source entity erasure unit. Next, in step S7053, the memory management circuit 51 can move the valid data to the target entity erasure unit and associate the source entity erasure unit with the idle area 602.

[0092] In one exemplary embodiment, after valid data in the source entity erasure unit is moved (or copied) to the target entity erasure unit, the memory management circuit 51 can erase the source entity erasure unit and release the erased source entity erasure unit to the idle area 602. That is, after valid data in the source entity erasure unit is moved (or copied), the memory management circuit 51 can perform an erasure operation on the source entity erasure unit that does not store valid data (i.e., only stores invalid data) to associate the source entity erasure unit with the idle area 602, thereby increasing the storage space of the rewritable non-volatile memory module 43.

[0093] Conversely, if no target candidate entity erase unit exists, the process proceeds to step S706, where the memory management circuit 51 calculates the total effective count value based on the effective count values ​​of the candidate entity erase units belonging to the single-level memory cell mode. In an exemplary embodiment, the memory management circuit 51 sums the effective count values ​​of all candidate entity erase units belonging to the single-level memory cell mode to calculate the total effective count value.

[0094] In step S707, the memory management circuit 51 determines whether the total valid count value is greater than a preset total value. In an exemplary embodiment, the preset total value is associated with the capacity of a physical erase unit. If the total valid count value is greater than the preset total value, for example, if the valid data in the candidate physical erase units belonging to the single-level memory cell mode among all candidate physical erase units is sufficient to fill the target physical erase unit, then step S705 is performed to execute the first data consolidation operation.

[0095] Conversely, if the total valid count value is not greater than the preset total value, then proceed to step S708 to perform the second data merging operation. The second data merging operation is performed on candidate entity erase units in either the three-level or four-level memory cell mode.

[0096] In step S708, the memory management circuit 51 can perform a second data merging operation. Details regarding the implementation of the second data merging operation are as follows: Figure 9 As shown, Figure 9 This is a flowchart illustrating the execution of the second data merging operation according to an exemplary embodiment of the present invention. Please refer to the simultaneous... Figure 7 and Figure 9 .

[0097] In step S7081, the memory management circuit 51 can select a source entity erase unit from the candidate entity erase units that do not belong to the single-level memory cell mode, and select a target entity erase unit.

[0098] In one exemplary embodiment, the memory management circuit 51 uses a candidate entity erase unit that does not belong to a single-level memory cell mode (i.e., belongs to a three-level or four-level memory cell mode) as the source entity erase unit for the second data merge operation. That is, candidate entity erase units belonging to a single-level memory cell mode cannot be used as the source entity erase unit for the second data merge operation. Alternatively, the memory management circuit 51 may select an entity erase unit as the target entity erase unit for the second data merge operation.

[0099] In step S7082, the memory management circuit 51 can collect valid data from the source entity erasure unit. Next, in step S7083, the memory management circuit 51 can move the valid data to the target entity erasure unit and associate the source entity erasure unit with the idle area 602.

[0100] In one exemplary embodiment, after valid data in the source entity erasure unit is moved (or copied) to the target entity erasure unit, the memory management circuit 51 may perform an erasure operation on the source entity erasure unit to associate the source entity erasure unit with the idle area 602, thereby increasing the storage space of the rewritable non-volatile memory module 43.

[0101] Specifically, in Figure 7 In the memory management method described above, before the target merge operation (i.e., the first data merge operation or the second data merge operation) is executed, the memory management circuit 51 performs a round of query operation to determine the source entity erase unit for the target merge operation. The query operation includes searching for entity erase units belonging to different operation modes such as single-level memory cell mode, three-level memory cell mode and four-level memory cell mode to determine the effective count value of entity erase units belonging to each operation mode.

[0102] Next, the memory management circuit 51 will select physical erase units with valid count values ​​lower than a pre-designed value as candidate physical erase units. Specifically, the valid count value corresponding to a physical erase unit reflects the occupied capacity of the valid data it stores. The pre-designed value reflects the lower limit occupied capacity of the valid data stored in a physical erase unit. The memory management circuit 51 can select physical erase units that do not store sufficient valid data as candidate physical erase units for the target merge operation.

[0103] Furthermore, the memory management circuit 51 can determine whether to use candidate entity erase units belonging to the single-level memory cell mode as the source entity erase units for the target merge operation. In this regard, if the following conditions are met: (1) the number of candidate entity erase units belonging to the single-level memory cell mode is greater than a preset number, or (2) the total effective count value of all candidate entity erase units belonging to the single-level memory cell mode is greater than a preset total value, then the memory management circuit 51 can use candidate entity erase units belonging to the single-level memory cell mode as the source entity erase units for the target merge operation (i.e., the first data merge operation). On the other hand, if neither of the above two conditions is met, then the memory management circuit 51 can use candidate entity erase units belonging to the three-level or four-level memory cell mode as the source entity erase units for the target merge operation (i.e., the second data merge operation).

[0104] Regarding point (1) above, in detail, if the number of candidate entity erase units (SLC Num) belonging to the single-level storage cell mode is greater than the preset number (assumed to be n, where n is a positive integer), it means that there are enough entity erase units belonging to the single-level storage cell mode among the candidate entity erase units that can be used as source entity erase units for the target merging operation. Therefore, the memory management circuit 51 can select to perform the first data merging operation. Here, n is a positive integer, and the value of n can be dynamically set according to the actual usage. That is, the memory management circuit 51 can dynamically adjust the preset value (n) according to the actual usage and performance indicators to achieve the best data merging performance.

[0105] Regarding point (2) above, in detail, in the application of the valid count value, in addition to considering the valid count value of each entity erase unit, the memory management circuit 51 will further calculate the total valid count value (Total Valid Cnt) of the candidate entity erase units belonging to the single-level memory cell mode, and determine whether to perform the first data merge operation or the second data merge operation based on the total valid count value.

[0106] Specifically, if the total effective count value is greater than the capacity of k entity erase units, it indicates that there is enough effective data in the candidate entity erase units belonging to the single-level memory cell mode to fill the target entity erase unit. Therefore, the memory management circuit 51 can select to perform the first data merging operation. Here, k is a positive integer, and the value of k can be dynamically set according to the actual usage. That is, the memory management circuit 51 can dynamically adjust the value of k according to the actual usage and performance indicators to achieve the best data merging performance.

[0107] Based on the above, in the exemplary embodiments of the present invention, by setting the above two points to determine whether to use the first data merge operation or the second data merge operation, the mixing of cold and hot data can be reduced. Further, since hot data has a higher probability of being stored in physical erase units belonging to the single-level storage cell mode, while cold data has a higher probability of being stored in physical erase units belonging to the triple or quadruple storage cell mode, by preferentially using physical erase units belonging to the single-level storage cell mode for data merge operations, the fast access performance of hot data can be maintained. In addition, by selecting an appropriate physical erase unit as the source physical erase unit for the data merge operation, unnecessary data movement and copying can be reduced, thereby improving the efficiency of the data merge operation.

[0108] Figure 10 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Please refer to... Figure 10 In step S1001, multiple state information corresponding to multiple entity erasure units are obtained, wherein the multiple state information reflects the operation mode of each entity erasure unit and the effective count value of each entity erasure unit. In step S1002, based on the multiple state information, a target merging operation is performed, wherein the target merging operation is either a first data merging operation or a second data merging operation, and the first data merging operation is different from the second data merging operation.

[0109] However, Figure 10 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 10 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 10The method can be used in conjunction with the above embodiments or alone, and the present invention does not limit it.

[0110] In summary, the memory management method and memory storage device proposed in the exemplary embodiments of the present invention can perform a first data merging operation using a source entity eraser that belongs to a single-level memory cell mode or a second data merging operation using a source entity eraser that does not belong to a single-level memory cell mode (e.g., a second-level memory cell mode, a third-level memory cell mode, or a fourth-level memory cell mode) based on the state information of the entity eraser. This avoids the situation where the same entity eraser is repeatedly used as the source entity eraser due to the mixing of hot and cold data, reduces the wear of rewritable non-volatile memory modules, and effectively improves the performance of the memory storage device.

[0111] Finally, it should be noted that the above examples and embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing examples and embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing examples and embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the examples and embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical erasure units, the memory management method includes: Obtain multiple state information corresponding to the plurality of entity erasure units, wherein the plurality of state information reflects the operation mode of each entity erasure unit and the effective count value of each entity erasure unit, wherein the operation mode of each entity erasure unit is one of a single-level memory cell mode, a two-level memory cell mode, a three-level memory cell mode, and a four-level memory cell mode; and Based on the multiple state information, a target merging operation is performed, specifically including the following steps: Based on the multiple state information, the entity erasure unit with a valid count value lower than the pre-designed value among the multiple entity erasure units is selected as a candidate entity erasure unit. Based on the multiple status information, the source entity erasure unit is determined from the candidate entity erasure units; Determine the number of candidate entity erase units belonging to the single-level storage cell pattern; Determine whether there exists a target candidate entity erasure unit with a quantity greater than a preset quantity, wherein the target candidate entity erasure unit is at least one of the candidate entity erasure units belonging to the single-level storage unit mode; and If the target candidate entity erasure unit exists, perform the first data merging operation. The target merging operation is either the first data merging operation or the second data merging operation. The first data merging operation is different from the second data merging operation. The first data merging operation includes selecting the source entity merging unit from the candidate entity merging units belonging to the single-level storage cell mode. The second data merging operation includes selecting the source entity merging unit from the candidate entity merging units that do not belong to the single-level storage cell mode.

2. The memory management method according to claim 1, wherein the step of performing the target merging operation based on the plurality of state information includes: Collect valid data from the source entity erasure unit; as well as The valid data is moved to the target entity erasure unit, and the source entity erasure unit is associated with the idle area.

3. The memory management method according to claim 2, wherein, The first data merging operation includes: The valid data is collected from the source entity erasure unit; and The valid data is moved to the target entity erasure unit, and the source entity erasure unit is associated with the idle area.

4. The memory management method according to claim 2, wherein the second data merging operation includes: The valid data is collected from the source entity erasure unit; as well as The valid data is moved to the target entity erasure unit, and the source entity erasure unit is associated with the idle area.

5. The memory management method according to claim 1, further comprising: If the target candidate entity erasure unit does not exist, the total effective count value is calculated based on the effective count value of the candidate entity erasure unit belonging to the single-level storage unit mode. Determine whether the total effective count value is greater than the preset total value; If the total valid count value is greater than the preset total value, the first data merging operation is performed; as well as If the total valid count value is not greater than the preset total value, the second data merging operation is performed.

6. The memory management method according to claim 5, wherein, The preset total value is associated with the capacity of the entity erasure unit.

7. The memory management method according to claim 1, wherein, The valid count value is used to represent the number of entity programmatic units in each entity erasure unit used to store valid data.

8. A memory storage device, characterized in that, include: A connection interface unit for coupling to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical erasure units; as well as The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Obtain multiple state information corresponding to the plurality of entity erasure units, wherein the plurality of state information reflects the operation mode of each entity erasure unit and the effective count value of each entity erasure unit, wherein the operation mode of each entity erasure unit is one of a single-level memory cell mode, a two-level memory cell mode, a three-level memory cell mode, and a four-level memory cell mode; and Based on the multiple state information, a target merging operation is performed, specifically including the following steps: Based on the multiple state information, the entity erasure unit with a valid count value lower than the pre-designed value among the multiple entity erasure units is selected as a candidate entity erasure unit. Based on the multiple status information, the source entity erasure unit is determined from the candidate entity erasure units. Determine the number of candidate entity erase units belonging to the single-level storage cell pattern; Determine whether there exists a target candidate entity erasure unit with a quantity greater than a preset quantity, wherein the target candidate entity erasure unit is at least one of the candidate entity erasure units belonging to the single-level storage unit mode; and If the target candidate entity erasure unit exists, perform the first data merging operation. The target merging operation is either the first data merging operation or the second data merging operation. The first data merging operation is different from the second data merging operation. The first data merging operation includes selecting the source entity merging unit from the candidate entity merging units belonging to the single-level storage cell mode. The second data merging operation includes selecting the source entity merging unit from the candidate entity merging units that do not belong to the single-level storage cell mode.

9. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: Collect valid data from the source entity erasure unit; and The valid data is moved to the target entity erasure unit, and the source entity erasure unit is associated with the idle area.

10. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to: The valid data is collected from the source entity erasure unit; and The valid data is moved to the target entity erasure unit, and the source entity erasure unit is associated with the idle area.

11. The memory storage device according to claim 9, wherein the memory control circuit unit is further configured to: The valid data is collected from the source entity erasure unit; and The valid data is moved to the target entity erasure unit, and the source entity erasure unit is associated with the idle area.

12. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: If the target candidate entity erasure unit does not exist, the total effective count value is calculated based on the effective count value of the candidate entity erasure unit belonging to the single-level storage unit mode. Determine whether the total effective count value is greater than the preset total value; If the total valid count value is greater than the preset total value, the first data merging operation is performed; as well as If the total valid count value is not greater than the preset total value, the second data merging operation is performed.

13. The memory storage device according to claim 12, wherein, The preset total value is associated with the capacity of the entity erasure unit.

14. The memory storage device according to claim 8, wherein, The valid count value is used to represent the number of entity programmatic units in each entity erasure unit used to store valid data.

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