Method and apparatus for ordering branch operations

Abstract

The invention relates to a method and equipment for sorting branch operations. An example apparatus includes address generation circuitry (250) configured to generate a first address associated with a first packet, a second address associated with a second packet, and a third address associated with a third packet, where the first packet includes a branch instruction, the branch instruction includes a first field specifying a branch target and a second field different from the first field, and the third packet includes the branch target of the branch instruction; buffer circuitry (215) configured to receive the first packet, the second packet, and the third packet; decoder circuitry (235) coupled to the buffer circuitry (215), the decoder circuitry (235) configured to decode the first packet, the second packet, and the third packet; and discontinuity controller circuitry (245) coupled to the buffer circuitry (215) and the decoder circuitry (235), and configured to determine whether to cause the address generation circuitry (250) to generate the second address.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of and priority to U.S. Provisional Patent Application Serial No. 63 / 517,369, filed on August 3, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present description relates generally to processing instructions and, more particularly, to methods and apparatus for ordering branch operations. Background Art

[0004] As electronic devices continue to advance, the processing speed and complexity of programmable circuit systems continue to increase. Some designers are developing increasingly complex programmable circuit system designs to increase the processing speed and complexity of each operation. Process improvements in the execution of machine instructions have further increased processing speeds and allowed for the addition of complex instructions. As programmable circuit systems become more and more common, designers are motivated to develop circuit systems that can efficiently execute machine instructions. Summary of the invention

[0005] For a method and apparatus for ordering branch operations, an example apparatus includes: an address generation circuit system configured to generate a first address associated with a first group, a second address associated with a second group, and a third address associated with a third group, wherein: the first group includes a branch instruction; the branch instruction includes a first field specifying a branch target and a second field different from the first field; and the third group includes the branch target of the branch instruction; a buffer circuit system configured to receive the first group, the second group, and the third group; a decoder circuit system coupled to the buffer circuit system, the decoder circuit system configured to decode the first group, the second group, and the third group; a discontinuity controller circuit system coupled to the buffer circuit system and the decoder circuit system and configured to determine whether to cause the address generation circuit system to generate the second address based on the second field of the branch instruction; and an execution circuit system coupled to the decoder circuit system, the execution circuit system configured to determine whether to cause the address generation circuit system to generate the third address based on the branch instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of example compiler circuitry for generating a machine-readable instruction list in response to a relatively high-level abstraction of operations, wherein the compiler circuitry is used to reorder branch instructions in an example memory.

[0007] Figure 2 is a block diagram of an example apparatus including programmable circuitry that performs Figure 1 Memory Figure 1 The programmable circuit system is configured to preemptively execute a branch instruction.

[0008] Figure 3A An example execution order of an example listing of machine-readable instructions is shown, where the execution order is preemptively executing branch instructions first.

[0009] Figure 3B Show Figure 3A The instructions in the machine-readable instruction list are in Figure 1 and 2 An example placement in an example memory of where the instruction is based on Figure 3A Placed in the order of execution.

[0010] Figure 3C Show Figure 2 Programmable circuit system using Figure 3A Execute in the order of execution Figure 3A and 3B Example operations of a machine readable instruction listing.

[0011] Figure 4A An example execution order of an example listing of machine-readable instructions is shown, where the execution order is to preemptively execute branch instructions for loop operations.

[0012] Figure 4B Show Figure 4A The instructions in the machine-readable instruction list are in Figure 1 and 2 An example placement in an example memory of where the instruction is based on Figure 4A Placed in the order of execution.

[0013] Figure 4C Show Figure 2 Programmable circuit system using Figure 4A Execute in the order of execution Figure 4A and 4B Example operations of a machine readable instruction listing.

[0014] Figure 5 is a diagram of an example branch instruction format including a delay bit.

[0015] Figure 6 Yes means you can use Figure 1 An example programmable circuitry implementation of a compiler circuitry is provided to execute, instantiate, and / or perform example machine-readable instructions in an order of execution to generate an example listing of machine-readable instructions and / or a flowchart of example operations.

[0016] Figure 7 Yes means you can use Figure 1 to execute, instantiate and / or perform to convert Figure 6 The machine readable instruction listings are placed in the memory as example machine readable instructions and / or flowcharts of example operations.

[0017] Fig. 8A and 8B Form means you can use Figure 2 The present invention provides a flowchart of example machine-readable instructions and / or example operations to be executed, instantiated and / or performed by example embodiments of programmable circuit systems.

[0018] Fig. 9 is a block diagram of an example processing platform including programmable circuitry structured to execute, instantiate and / or perform example machine-readable instructions and / or perform Figure 6 , 7 , 8A and / or 8B to implement the example operations Figure 1 Compiler circuitry and / or Figure 2 Programmable circuit system.

[0019] Fig.10 yes Fig. 9 A block diagram of an example implementation of a programmable circuit system.

[0020] Fig.11 yes Fig. 9 A block diagram of another example implementation of a programmable circuit system.

[0021] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0022] The drawings are not necessarily to scale. In general, the same reference numerals in the drawings and the specification refer to the same or similar parts. Although the drawings show regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be unobservable, mixed, and / or irregular.

[0023] As electronic devices continue to advance, the processing speed and complexity of programmable circuit systems continue to increase. Some designers are developing increasingly complex programmable circuit system designs to increase the processing speed and complexity of each operation. Process improvements in the execution of machine instructions have further increased processing speeds and allowed for the addition of complex instructions. As programmable circuit systems become more and more common, designers are motivated to develop circuit systems that can efficiently execute machine instructions.

[0024] Programmable circuitry (e.g., a central processing unit) implements a pipeline to execute machine instructions. Instructions may be grouped into groups, and in some instances, instructions in the groups are executed in parallel. The pipeline uses circuitry to fetch, decode, and execute machine instructions in the groups. In some instances, the pipeline fetches a memory block, decodes the instruction groupings contained in the memory block, and executes the machine instructions of the instruction groupings. The programmable circuitry cycles each machine instruction through the pipeline one step at a time based on the cycle of a cycle clock. The period of the cycle clock determines the duration that each stage of the pipeline can be used to perform an operation.

[0025] In operation, the first acquisition stage generates a read command and provides it to the memory, while the second acquisition stage receives and stores the memory block. In such an example, the first decoding stage decodes the memory block to determine the instruction grouping, and the second decoding stage executes the machine instructions of the decoded instruction grouping. In some example operations such as read operations and write operations, the additional stage operates to perform additional memory operations. In order to execute the machine instructions, the machine instructions pass through the pipeline of the programmable circuit system separately. Therefore, the programmable circuit system usually uses multiple cycles to request, receive and decode the machine instructions before executing the machine instructions. For example, a given instruction can be requested from the memory, received from the memory in the form of an instruction grouping, and decoded from the instruction grouping before it can be used for execution. In such an example, each operation of the pipeline occurs with reference to the cycle clock cycle.

[0026] During the first cycle, the programmable circuit system provides a read command to read a first memory block containing one or more instruction packets. During the second cycle, the programmable circuit system causes the first memory block to be stored in an instruction buffer inside the programmable circuit system. In addition, during the second cycle, the programmable circuit system may provide another read command specifying the second memory block. During the third cycle, the programmable circuit system decodes the first memory block and extracts an instruction packet having at least one machine instruction that can be used for execution from the first memory block. In addition, during the third cycle, the memory may store the third memory block in the instruction buffer by providing another read command to the memory. During the fourth cycle, the programmable circuit system causes the circuit system to perform an operation of the machine instruction of the first memory block. Such an operation of the circuit system performing an operation may be referred to as the execution of a machine instruction. After the fourth cycle, the programmable circuit system continues to fetch, decode, and execute instruction packets from the memory.

[0027] However, when the machine instruction is a branch instruction, the machine instruction specifies a memory block to be read from the memory. In such an instance, the programmable circuit system can fetch and decode the instruction packet from the memory block specified by the branch instruction. Assuming that the branch is taken during the cycle in which the programmable circuit system fetches and decodes the instruction packet specified by the target of the branch instruction, the programmable circuit system cannot execute any instructions because the instruction packet of the branch target is passing through the various stages of the pipeline.

[0028] The examples described herein include methods and devices for ordering branch operations. In some described examples, the compiler circuit system adjusts the execution order of machine instructions to preemptively call branch instructions, thereby causing the branch instructions to proceed out of order. In example operations, the programmable circuit system operates to execute instructions starting from the location specified by the branch instruction while continuing to execute instructions. In some examples, the compiler circuit system adjusts the execution order of the machine instruction group that was originally to be executed before the branch instruction was executed. By advancing the execution of the group with the branch and delaying the execution of other groups, the programmable circuit system executes the delayed group of machine instructions while acquiring one or more memory blocks and decoding the corresponding group of machine instructions from the memory block at the branch location. The exact number of groups delayed in order to advance the branch can depend on the properties of the programmable device that will execute the compiled instructions (e.g., pipeline depth, number of acquisition and / or decoding cycles), and each programmable device can have a unique reference number, which represents the ideal number of groups that can be rearranged to be after the group containing the branch instruction. Advantageously, the execution of the delayed group allows the programmable circuit system to acquire the instruction at the branch location and decode and continue to execute the instruction.

[0029] The compiler circuitry reorders the selected grouping to follow the branch instruction. During example operation, the programmable circuitry executes the machine instructions of the selected grouping after starting to execute the branch instruction while simultaneously retrieving and decoding the memory block specified by the branch instruction. In such an example, the programmable circuitry continues to execute the machine instructions using the first instruction buffer while simultaneously starting to store the memory block specified by the branch instruction using the second instruction buffer. When executing the last delayed grouping of the determined machine instructions, the programmable circuitry begins decoding the memory block from the second instruction buffer.

[0030] Advantageously, placing the machine instruction group after the branch instruction allows the programmable circuit system to continue to execute the machine instruction while the machine instruction for the branch instruction is fetched and decoded. Advantageously, preemptively executing the branch instruction reduces the number of cycles in which the programmable circuit system does not execute the machine instruction. Advantageously, using multiple instruction buffers allows the programmable circuit system to continue to execute the machine instruction while the machine instruction at the branch location is cycled through the pipeline. Advantageously, such ordering allows the compiler circuit system to reduce cycles in which no operations are performed for call operations (e.g., call instructions), call return operations (e.g., return instructions), loop operations, etc.

[0031] Figure 1 is a block diagram of an example assembler system 100. Figure 1 In the example of , the assembler system 100 includes example machine-readable instructions 104, example compiler circuitry 108, example operation determination circuitry 112, example storage 116, example processor-specific instructions 120, example instruction approximation circuitry 124, example group construction circuitry 126, example branch ordering circuitry 128, example branch detection circuitry 132, example flag checking circuitry 136, example branch relocation circuitry 140, example instruction buffer circuitry 144, example memory write circuitry 148, example group manager circuitry 152, example branch group controller circuitry 156, example delay encoder circuitry 160, example memory block buffer circuitry 164, example memory 168, a first example memory block 172, a first example instruction grouping 176, a second example instruction grouping 180, a second example memory block 184, a third example instruction grouping 188, a third example memory block 192, and a fourth example instruction grouping 196. The assembler system 100 assembles a list of instruction groups 176, 180, 188, 196 representing the machine-readable instructions 104. The assembler system 100 stores the list of instruction groups 176, 180, 188, 196 in the memory 168 for later execution.

[0032] The machine-readable instructions 104 form a list of operations that define the desired functionality of the programmable circuit system (e.g., Figure 2 104). In some instances, machine readable instructions 104 are defined using programming languages ​​such as C, C++, C#, etc. In such instances, a designer may use a programming language to create machine readable instructions 104, thereby defining the operations to be performed. For example, developing and / or debugging code to perform operations at compile time may be referred to as software. However, such operations represent general functions of a programmable circuit system as defined in machine readable instructions 104. In order to implement machine readable instructions 104 using a programmable circuit system, machine readable instructions 104 are converted into machine instructions specific to the programmable circuit system.

[0033] The machine instruction is an operation value that configures the programmable circuit system to instantiate the circuit system that performs a predefined operation. The programmable circuit system performs the operation of the machine-readable instruction 104 in response to sequentially executing multiple machine instructions representing the machine-readable instruction 104. In some instances, the machine instruction has an operation code and / or an operand, which form the operation value that configures the programmable circuit system. When configured, the programmable circuit system instantiates the circuit system to perform an operation corresponding to the operation code and / or operand of the machine instruction. In such an instance, the designer often uses assembly language to represent the machine instruction specific to the programmable circuit system. The compiler circuit system 108 converts the machine-readable instruction 104 into a machine instruction that can be executed by the programmable circuit system at a later time.

[0034] exist Figure 1 In the example of Figure 1 An example implementation of a compiler circuit system 108 of the present invention, which converts machine-readable instructions 104 into instruction packets in memory 168. In some instances, the instruction packets are one or more machine instructions and may include additional bits corresponding to one or more additional operations, such as delay operations. The compiler circuit system 108 may be instantiated (e.g., create an instance of any length of time, implement any length of time, concretize, implement, etc.) by, for example, a programmable circuit system of a central processor unit (CPU) that executes a first instruction. Additionally or alternatively, the compiler circuit system 108 may be instantiated (e.g., create an instance of any length of time, implement any length of time, concretize, implement, etc.) by (i) an application specific integrated circuit (ASIC) and / or (ii) a field programmable gate array (FPGA), which is structured and / or configured to perform operations corresponding to the first instruction in response to the execution of a second instruction. It should be understood that some or all of the compiler circuit system 108 may therefore be instantiated at the same or different times. Some or all of the compiler circuit system 108 may be instantiated, for example, in one or more threads that are executed simultaneously on hardware and / or serially on hardware. Furthermore, in some examples, some or all of compiler circuitry 108 may be implemented by microprocessor circuitry executing instructions and / or FPGA circuitry operating to implement one or more virtual machines and / or containers.

[0035] Compiler circuitry 108 receives machine readable instructions 104. Figure 1In an example of , compiler circuitry 108 includes operation determination circuitry 112, storage 116, processor specific instructions 120, instruction approximation circuitry 124, branch ordering circuitry 128, branch detection circuitry 132, flag checking circuitry 136, branch relocation circuitry 140, instruction buffer circuitry 144, memory write circuitry 148, packet manager circuitry 152, branch packet controller circuitry 156, delay encoder circuitry 160, and memory block buffer circuitry 164. Compiler circuitry 108 generates a list of machine instructions that, when executed, implement the operations of machine readable instructions 104. Compiler circuitry 108 encodes additional data, such as delay information, onto the machine instructions to form instruction packets. Compiler circuitry 108 reorders the instruction packets in the instruction list to preemptively perform branch operations. In some examples, compiler circuitry 108 encodes delays into the reordered branch instructions based on the location of the reordered instruction packets in one or more blocks of memory 168. Compiler circuitry 108 writes instruction groups 176 , 180 , 188 , 196 to memory 168 .

[0036] Operation determination circuitry 112 receives machine readable instructions 104. In some instances, operation determination circuitry 112 accesses machine readable instructions 104 at a memory address. In such instances, operation determination circuitry 112 may be coupled to a storage device corresponding to the memory address. In other instances, an operating system provides machine readable instructions 104 to operation determination circuitry 112. In such instances, operation determination circuitry 112 may be coupled to a programmable circuitry that executes instructions of the operating system. Operation determination circuitry 112 determines the operation (OPP) of machine readable instructions 104 in response to receiving machine readable instructions 104. 列表 ). Operation determination circuitry 112 sequentially lists the operations that the programmable circuitry is to perform to implement machine readable instructions 104 .

[0037] In some examples, operation determination circuitry 112 approximates the relatively complex operation of machine-readable instructions 104 to one or more relatively less complex operations that can be performed by programmable circuitry. In such examples, operation determination circuitry 112 may analyze machine-readable instructions 104 to determine an execution order. When the operation is performed using the execution order, the programmable circuitry instantiates circuitry to perform the operation of machine-readable instructions 104. Operation determination circuitry 112 provides the determined operation to instruction approximation circuitry 124. In some examples, operation determination circuitry 112 is configured to perform, for example, an operation determination instruction and / or an operation determination instruction. Figure 6The programmable circuitry instantiates the operations of those operations represented by the flowcharts.

[0038] Storage device 116 is coupled to instruction approximation circuitry 124. Figure 1 In an example of , the storage device 116 includes processor-specific instructions 120. In such an example, the storage device 116 is a volatile or non-volatile memory capable of storing data. The processor-specific instructions 120 are a plurality of instructions corresponding to a specific instance of a programmable circuit system (e.g., a specific version of an ARM core processor). Each instruction in the processor-specific instructions 120 corresponds to an operation of the programmable circuit system. For example, a first instruction in the processor-specific instructions 120 may correspond to a load operation, and a second instruction in the processor-specific instructions 120 may correspond to an add operation. In such an example, the first instruction may be referred to as a load instruction, and the second instruction may be referred to as an add instruction.

[0039] Instruction approximation circuitry 124 is coupled to operation determination circuitry 112, storage 116, and packet construction circuitry 126. Instruction approximation circuitry 124 receives an operation representing machine-readable instructions 104 from operation determination circuitry 112. Instruction approximation circuitry 124 accesses processor-specific instructions 120. Instruction approximation circuitry 124 compares the operation from operation determination circuitry 112 with processor-specific instructions 120. Instruction approximation circuitry 124 generates machine instructions (INS) in response to the comparison. Similar to the determined operation, instruction approximation circuitry 124 sequentially generates machine instructions representing the operation of the programmable circuitry to implement the machine-readable instructions 104. In some examples, instruction approximation circuitry 124 receives the operation from operation determination circuitry 112. In such an example, instruction approximation circuitry 124 selects an instruction in processor-specific instructions 120 that corresponds to the operation.

[0040] In example operation, the instruction approximation circuitry 124 determines an operation code (opcode) for each instruction in response to a comparison of the operation to the processor-specific instructions 120. In some instances, the instruction approximation circuitry 124 combines the opcode and operands to form a machine instruction. In such instances, the operands specify the location and / or value of data to be used to perform the opcode operation. For example, an addition instruction includes an opcode that identifies the addition operation to be performed and one or more operands that specify register values ​​to be added and / or locations to store the result. The instruction approximation circuitry 124 assembles the machine instructions using the processor-specific instructions 120. The instruction approximation circuitry 124 provides the machine instructions to the grouping construction circuitry 126. In some instances, the instruction approximation circuitry 124 determines the instruction by executing the operation and / or is configured to perform, for example, Figure 6The programmable circuitry instantiates the operations of those operations represented by the flowcharts.

[0041] The group construction circuit system 126 is coupled to the instruction approximation circuit system 124, the branch sorting circuit system 128, and the branch detection circuit system 132. The group construction circuit system 126 receives machine instructions from the instruction approximation circuit system 124. The group construction circuit system 126 converts the machine instructions into instruction packets by grouping the machine instructions and / or encoding additional data onto the machine instructions. In some instances, the group construction circuit system 126 adds multiple machine instructions to a single instruction packet. In such an instance, the additional data of the instruction packet corresponds to multiple machine instructions. The instruction packet represents data to be acquired by the programmable circuit system during runtime. In some instances, the group construction circuit system 126 encodes data that can be used by the decoding stage of the pipeline to be executed by the programmable circuit system. For example, the group construction circuit system 126 may include a delay bit that defines a delay operation of the programmable circuit system. The group construction circuit system 126 provides the instruction packet containing one or more machine instructions to the branch sorting circuit system 128.

[0042] Branch ordering circuitry 128 is coupled to packet construction circuitry 126 and instruction buffer circuitry 144. Branch ordering circuitry 128 receives machine instructions from packet construction circuitry 126. Figure 1 In the example of FIG. 1 , branch ordering circuitry 128 includes branch detection circuitry 132, flag checking circuitry 136, and branch relocation circuitry 140. Branch ordering circuitry 128 adjusts the execution order of instruction packets to reorder branch instructions. Advantageously, reordering branch instructions reduces the number of programmable circuitry cycles during which no machine instructions are executed but rather instruction packets for fetching and decoding branches are executed.

[0043] Branch detection circuitry 132 is coupled to instruction approximation circuitry 124, flag checking circuitry 136, branch relocation circuitry 140, and instruction buffer circuitry 144. Branch detection circuitry 132 receives instruction packets from instruction approximation circuitry 124. Branch detection circuitry 132 checks each of the instruction packets to determine whether the instruction packet contains a branch instruction. A branch instruction within an instruction packet may create an address discontinuity when a machine instruction is fetched from memory 168. When executed, the branch instruction adjusts the flow of operations by modifying the program counter and / or fetching a memory address of a subsequent instruction packet of the programmable circuitry. Such a modification of the memory address of the fetch operation is considered an address discontinuity. For example, the operation determination circuitry 112 may use a branch operation to represent a function call of the machine readable instruction 104. In such an instance, instruction approximation circuitry 124 selects an opcode of the branch instruction to represent the branch operation.

[0044] In some examples, branch detection circuitry 132 may determine that the instruction packet contains a branch instruction in response to the opcode. In such examples, when the opcode specifies the operation of the machine instruction as a branch operation, branch detection circuitry 132 determines the instruction containing the opcode as a branch instruction. When the instruction packet does not contain a branch instruction, branch detection circuitry 132 provides a non-branch instruction packet to instruction buffer circuitry 144.

[0045] When the instruction grouping includes a branch instruction, the branch detection circuit system 132 determines whether the branch instruction is one of a conditional branch instruction or an unconditional branch instruction. A conditional branch instruction is a branch instruction that occurs based on the condition of a flag when executed. A flag is an indication set before executing a machine instruction. For example, the operation determination circuit system 112 can represent a conditional function call of a machine-readable instruction 104 as a conditional branch operation. In such an example, the instruction approximation circuit system 124 selects an opcode representing a conditional branch operation. When the branch instruction is a conditional branch instruction, the branch detection circuit system 132 provides the conditional machine instruction to the flag checking circuit system 136.

[0046] An unconditional branch instruction is a branch instruction that will occur regardless of what machine instructions are executed before the unconditional branch instruction is executed. For example, operation determination circuitry 112 may represent an unconditional function call of machine-readable instructions 104 as an unconditional branch operation. In such an example, instruction approximation circuitry 124 selects an opcode representing an unconditional branch operation. When the branch instruction is an unconditional branch instruction, branch detection circuitry 132 provides the unconditional machine instruction to branch relocation circuitry 140. In some examples, branch detection circuitry 132 is configured to perform, for example, executing branch detection circuitry instructions and / or performing a branch relocation operation. Figure 6 The programmable circuitry instantiates the operations of those operations represented by the flowcharts.

[0047] Flag checking circuitry 136 is coupled to branch detection circuitry 132, branch relocation circuitry 140, and instruction buffer circuitry 144. Flag checking circuitry 136 receives a conditional branch instruction from branch detection circuitry 132. Flag checking circuitry 136 determines one or more flags on which the conditional branch instruction depends. In some examples, flag checking circuitry 136 determines the one or more flags based on an opcode of the conditional branch instruction. In such examples, the opcode identifies one or more flags that are conditional on the branch operation.

[0048] Flag checking circuitry 136 reads the machine instructions in instruction buffer circuitry 144. Figure 1In an example of the invention, the flag checking circuit system 136 determines whether any of the instruction groups that precede the branch instruction and can be moved after the branch instruction can adjust (e.g., set, clear) one or more flags of the conditional machine instruction. When any of the determined previous non-branch instructions can adjust one or more flags, it may not be possible to advance the branch instruction ahead of these instructions. However, the flag checking circuit system 136 can still advance the branch instruction ahead of other instructions that do not affect the branch result.

[0049] For pipeline management, the flag checking circuit system 136 can insert one or more no-operation (NoOp) instructions in the instruction buffer circuit system 144. A no-operation instruction is a machine instruction that delays the execution of a subsequent machine instruction by a single execution cycle of the programmable circuit system. The flag checking circuit system 136 adds one or more no-operation instruction packets after the instruction that can set the flag to ensure a reference number of instruction packets after the branch instruction when reordering. The flag checking circuit system 136 determines the number of no-operation instruction packets that are ordered after the instruction packet containing the machine instruction that can adjust one or more flags to set the flag in response to which instruction packet of the reference number of instruction packets before the branch instruction can adjust the one or more flags.

[0050] In an example operation, when the instruction grouping immediately preceding the original order of the branch instruction is capable of adjusting one or more flags, the flag checking circuit system 136 adds a reference number of no-operation instruction groups to the instruction buffer circuit system 144. For example, when the programmable circuit system executes three instructions after the branch instruction, and the machine instruction originally located immediately before the branch instruction is capable of setting the flag of the branch instruction, the flag checking circuit system 136 adds three no-operation instruction groups after the determined instruction and / or instruction grouping of the branch instruction. In some instances, the flag checking circuit system 136 adds three no-operation instruction groups after the branch instruction. In such instances, the branch instruction does not need to be reordered. In other instances, the flag checking circuit system 136 adds three no-operation instruction groups after the instruction grouping of the determined instruction. In such instances, the branch instruction is reordered to be executed after the determined instruction and before the added instruction grouping. When the branch instruction is reordered, the added no-operation instruction grouping is executed after the branch instruction. Advantageously, adding a no-op instruction grouping allows branch instructions to be reordered with reference to that number of instruction groups, regardless of whether the instruction is capable of adjusting flags.

[0051] In another example operation, when an instruction grouping within a reference number of instruction groups preceding a branch instruction is capable of adjusting one or more flags, the flag checking circuit system 136 adds at least one no-operation instruction grouping after the determined instruction grouping. In some instances, the flag checking circuit system 136 adds one or more no-operation instruction groups after the branch instruction. In such instances, the branch instructions are indeed reordered by subtracting the number of no-operation instruction groups added from the reference number of groups. In other instances, the flag checking circuit system 136 adds one or more no-operation instruction groups after the instruction grouping of the determined instruction. In such instances, the branch instructions are reordered by the reference number of instruction groups executed after the determined instruction. After adding any no-operation instruction groups, the flag checking circuit system 136 provides the conditional branch instruction to the branch relocation circuit system 140. In some instances, the flag checking circuit system 136 is executed by executing a flag checking instruction and / or is configured to perform, for example Figure 7 The programmable circuitry instantiates the operations of those operations represented by the flowcharts.

[0052] The branch relocation circuitry 140 is coupled to the branch detection circuitry 132, the flag checking circuitry 136, and the instruction buffer circuitry 144. The branch relocation circuitry 140 receives a branch instruction from the branch detection circuitry 132 and / or the flag checking circuitry 136. The branch relocation circuitry 140 adjusts the execution order of the machine instructions in the instruction buffer circuitry 144. The branch relocation circuitry 140 reorders the branch instruction so that it occurs before a reference number of instruction packets that precede the original location of the branch instruction. For example, when the reference number of instruction packets is three, the branch relocation circuitry 140 places the branch instruction between the fourth and third most recent instruction packets of the instruction buffer circuitry 144. In such an instance, the reordered branch instruction will be executed before the reordered instruction packets. Advantageously, executing a delay instruction after the branch instruction allows the programmable circuitry to fetch and decode the machine instruction at the branch target location. In some instances, the branch relocation circuitry 140 is configured to execute a branch relocation instruction and / or is configured to perform, for example Figure 6 The programmable circuitry instantiates the operations of those operations represented by the flowcharts.

[0053] Instruction buffer circuitry 144 is coupled to branch detection circuitry 132, flag checking circuitry 136, branch relocation circuitry 140, memory write circuitry 148, and packet manager circuitry 152. Instruction buffer circuitry 144 receives instruction packets. Instruction buffer circuitry 144 sequentially buffers instruction packets from branch detection circuitry 132 and flag checking circuitry 136. Branch relocation circuitry 140 relocates recently received instructions to adjust the execution order of machine instructions to accommodate branch instructions. The branch instruction reference number of instruction packets can be executed earlier in the adjusted execution order than in the original execution order. In some instances, instruction buffer circuitry 144 is a first-in-first-out (FIFO) buffer. Instruction buffer circuitry 144 provides instruction packets to memory write circuitry 148 and packet manager circuitry 152. In some instances, instruction buffer circuitry 144 is executed by executing instruction buffer instructions and / or is configured to perform, for example Figure 6 The programmable circuitry instantiates the operations of those operations represented by the flowcharts.

[0054] Memory write circuitry 148 is coupled to instruction buffer circuitry 144 and memory 168. Memory write circuitry 148 receives instruction packets from instruction buffer circuitry 144. Figure 1 In an example of the present invention, memory write circuitry 148 includes packet manager circuitry 152, branch packet controller circuitry 156, delay encoder circuitry 160, and memory block buffer circuitry 164. Memory write circuitry 148 encodes additional data, such as delay information, onto the instruction packets. In some examples, memory write circuitry 148 encodes delay information into the branch instruction packets. Memory write circuitry 148 stores the instruction packets as memory blocks in memory 168.

[0055] Packet manager circuitry 152 is coupled to instruction buffer circuitry 144, branch packet controller circuitry 156, delay encoder circuitry 160, and memory block buffer circuitry 164. Packet manager circuitry 152 receives instruction packets from instruction buffer circuitry 144.

[0056] Packet manager circuitry 152 determines whether an instruction packet is a branch instruction packet or a non-branch instruction packet. Similar to branch detection circuitry 132, packet manager circuitry 152 can determine whether an instruction packet contains a branch instruction in response to an opcode of a machine instruction. When the instruction packet is a branch instruction packet, packet manager circuitry 152 provides the branch instruction packet to branch packet controller circuitry 156. When the instruction packet is a non-branch instruction packet, packet manager circuitry 152 provides the non-branch instruction packet to memory block buffer circuitry 164. In some examples, packet manager circuitry 152 is executed by executing packet manager instructions and / or is configured to perform, for example, Figure 7 The programmable circuitry instantiates the operations of those operations represented by the flowcharts.

[0057] The branch packet controller circuit system 156 is coupled to the packet manager circuit system 152, the delay encoder circuit system 160, and the memory block buffer circuit system 164. The branch packet controller circuit system 156 receives the branch instruction packet from the packet manager circuit system 152. The branch packet controller circuit system 156 adds the delay bit to the branch instruction packet. This addition can be referred to as encoding the delay information into the branch instruction packet. Because the size of the packet and the alignment of the packet may vary, the number of blocks retrieved to return a given number of packets may vary. Therefore, the delay bit specifies the number of memory blocks to be retrieved for the reference number of instruction packets after executing the branch instruction packet. The branch packet controller circuit system 156 provides the branch instruction packet to the memory block buffer circuit system 164. The branch packet controller circuit system 156 tracks the location of the branch instruction packet in the memory block buffer circuit system 164. In some examples, the branch packet controller circuit system 156 tracks the memory address of the starting bit of the branch instruction packet. The branch packet controller circuit system 156 provides the location of the branch instruction packet in the memory block buffer circuit system 164 to the delay encoder circuit system 160. In some examples, the branch packet controller circuitry 156 is configured to execute branch controller instructions and / or to perform, for example, Figure 7 The programmable circuitry instantiates the operations of those operations represented by the flowcharts.

[0058] Delay encoder circuitry 160 is coupled to packet manager circuitry 152, branch packet controller circuitry 156, and memory block buffer circuitry 164. Delay encoder circuitry 160 receives the location of the branch instruction packet in memory block buffer circuitry 164. Delay encoder circuitry 160 determines the length of a reference number of instruction packets following the branch instruction packet. Delay encoder circuitry 160 determines the number of memory blocks storing the reference number of instruction packets following the branch instruction based on the determined length and location of the branch instruction packet.

[0059] When the branch instruction grouping and the reference number of instruction groups after the branch instruction grouping are to be stored in the same memory block, the delay encoder circuit system 160 retains the delay bit of the branch instruction grouping at a default value (e.g., 0x0). In such an example, the default value corresponds to all reference number of instruction groups after the branch instruction grouping to be acquired before and / or during the execution of the branch instruction. However, when the branch instruction grouping and the reference number of instruction groups after the branch instruction grouping are not stored in the same memory block, the delay encoder circuit system 160 modifies the delay bit of the branch instruction grouping.

[0060] When a branch instruction group and a reference number of instruction groups after the branch instruction group are stored in two memory blocks, the delay encoder circuit system 160 sets the delay bit of the branch instruction group to a first value (e.g., 0x1). The delay encoder circuit system 160 configures the delay bit to obtain two memory blocks after the block associated with the branch instruction. When the branch instruction group and the reference number of instruction groups after the branch instruction group are stored in three memory blocks, the delay encoder circuit system 160 sets the delay bit of the branch instruction group to a second value (e.g., 0x2). The delay encoder circuit system 160 configures the delay bit to the second value to obtain three memory blocks after executing the branch instruction. When the branch instruction group and the reference number of instruction groups after the branch instruction group are stored in four memory blocks, the delay encoder circuit system 160 sets the delay bit of the branch instruction group to a third value (0x3). The delay encoder circuit system 160 configures the delay bit to the third value to obtain four memory blocks after executing the branch instruction. In some instances, the delay encoder circuit system 160 is executed by executing a delay encoder instruction and / or is configured to perform, for example Figure 7 The programmable circuitry instantiates the operations of those operations represented by the flowcharts.

[0061] Memory block buffer circuitry 164 is coupled to packet manager circuitry 152, branch packet controller circuitry 156, delay encoder circuitry 160, and memory 168. Memory block buffer circuitry 164 receives instruction packets. Memory block buffer circuitry 164 buffers instruction packets from packet manager circuitry 152 and branch packet controller circuitry 156. Memory block buffer circuitry 164 receives delay bits from delay encoder circuitry 160. Memory block buffer circuitry 164 allows delay encoder circuitry 160 to set delay bits for branch instruction packets. In some instances, memory block buffer circuitry 164 is a first-in, first-out (FIFO) buffer. Memory block buffer circuitry 164 stores instruction packets in memory 168. In some instances, memory block buffer circuitry 164 is executed by executing memory block buffer instructions and / or is configured to perform, for example, Figure 7 The programmable circuitry instantiates the operations of those operations represented by the flowcharts.

[0062] The example memory 168 is coupled to the memory block buffer circuitry 164. The memory 168 receives instruction packets from the memory block buffer circuitry 164. Figure 1 In the example of , memory 168 includes memory blocks 172, 184, 192 and instruction packets 176, 180, 188, 196. Memory blocks 172, 184, 192 are fixed portions of memory 168. Memory 168 stores instruction packets from memory block buffer circuitry 164 in one or more of memory blocks 172, 184, 192. In some examples, memory 168 is a non-volatile memory.

[0063] At a first time, the memory 168 receives the first instruction packet 176. At the first time, the memory 168 stores the first instruction packet 176 in the first memory block 172. At a second time after the first time, the memory 168 receives the second instruction packet 180. At the second time, the memory 168 begins to store the second instruction packet 180 after the first instruction packet 176 in the first memory block 172. However, the second instruction packet 180 has a length that is longer than the available portion of the first memory block 172. In such an example, the memory 168 stores a portion of the second instruction packet 180 in the first memory block 172 and stores a second portion of the second instruction packet 180 in the second memory block 184.

[0064] At a third time after the second time, the memory 168 receives the third instruction packet 188. At the third time, the memory 168 stores the third instruction packet 188 after the second instruction packet 180 in the second memory block 184. The memory block buffer circuitry 164 then continues to write instruction packets to the memory 168 until the fourth instruction packet 196 is written to the third memory block 192. Figure 1 In the example of FIG. 1 , only memory blocks 172 , 184 , 192 and instruction groups 176 , 180 , 188 , 196 are shown, but according to the present description, the memory 168 may include any number of memory blocks and / or instruction groups.

[0065] Figure 2 is a block diagram of an example apparatus 200. Figure 2 In the example, the device 200 includes Figure 1 Memory 168, Figure 1 Memory blocks 172, 184, 192, Figure 1 The apparatus 200 executes in response to the programmable circuit system 205 executing the machine instructions of the instruction groups 176, 180, 188, 196. Figure 1 The operation of the machine readable instructions 104.

[0066] Programmable circuitry 205 is coupled to memory 168. Figure 2 In the example of , programmable circuitry 205 includes example demultiplexer circuitry 210, first example instruction buffer circuitry 215, second example instruction buffer circuitry 220, example multiplexer circuitry 225, example cycle clock circuitry 230, example decoder circuitry 235, example execution circuitry 240, example discontinuity controller circuitry 245, example address generation circuitry 250, and example buffer controller circuitry 255. Programmable circuitry 205 reads memory blocks 172, 184, 192 from memory 168. Programmable circuitry 205 decodes and executes machine instructions of instruction groups 176, 180, 188, 196. Programmable circuitry 205 stores one or more of memory blocks 172 in one of first instruction buffer circuitry 215 or second instruction buffer circuitry 220 based on execution of the machine instructions.

[0067] The address generation circuitry 250 may include a program counter and may be configured to provide addresses to the memory 168 according to the program counter. This in turn may cause the memory 168 to provide a memory block to the demultiplexer circuitry 210. The demultiplexer circuitry 210 is coupled to the memory 168, the instruction buffer circuitry 215, 220, and the buffer controller circuitry 255. The memory 168 provides one of the memory blocks 172, 184, 192 to the demultiplexer circuitry 210 in response to a read command from the address generation circuitry 250. The buffer controller circuitry 255 controls the demultiplexer circuitry 210. The demultiplexer circuitry 210 provides one of the memory blocks 172, 184, 192 to one of the instruction buffer circuitry 215, 220 in response to the buffer controller circuitry 255. In a first configuration, the demultiplexer circuitry 210 provides one of the memory blocks 172, 184, 192 to the first instruction buffer circuitry 215. In the second configuration, the demultiplexer circuitry 210 provides one of the memory blocks 172 , 184 , 192 to the second instruction buffer circuitry 220 .

[0068] The first instruction buffer circuitry 215 is coupled to the multiplexer circuitry 210, 225, the periodic clock circuitry 230, and the buffer controller circuitry 255. The first instruction buffer circuitry 215 receives the periodic clock signal from the periodic clock circuitry 230. When the demultiplexer circuitry 210 is in the first configuration, the first instruction buffer circuitry 215 receives one of the memory blocks 172, 184, 192. The first instruction buffer circuitry 215 is configured to store one or more of the memory blocks 172, 184, 192. The first instruction buffer circuitry 215 buffers one of the memory blocks 172, 184, 192. The first instruction buffer circuitry 215 has the capacity to buffer a plurality of the memory blocks 172, 184, 192. In some examples, when first instruction buffer circuitry 215 is approximately five hundred twelve bits and each of memory blocks 172 , 184 , 192 is one hundred twenty eight bits, first instruction buffer circuitry 215 may store up to four blocks of memory 168 .

[0069] When the first instruction buffer circuitry 215 has capacity to store another of the memory blocks 172, 184, 192, the first instruction buffer circuitry 215 accepts a read response from the memory 168 through a subsequent one of the memory blocks 172, 184, 192. When the first instruction buffer circuitry 215 is full, the buffer controller circuitry 255 determines that the first instruction buffer circuitry 215 no longer has capacity to store another of the memory blocks 172, 184, 192. Such a determination allows the buffer controller circuitry 255 to delay subsequent read commands to the memory 168. In some examples, the first instruction buffer circuitry 215 is a FIFO buffer. The first instruction buffer circuitry 215 provides the buffered memory blocks to the multiplexer circuitry 225.

[0070] The second instruction buffer circuitry 220 is coupled to the multiplexer circuitry 210, 225, the periodic clock circuitry 230, and the buffer controller circuitry 255. The second instruction buffer circuitry 220 receives the periodic clock signal from the periodic clock circuitry 230. When the demultiplexer circuitry 210 is in the second configuration, the second instruction buffer circuitry 220 receives one of the memory blocks 172, 184, 192. The second instruction buffer circuitry 220 is configured to store one or more of the memory blocks 172, 184, 192. The second instruction buffer circuitry 220 buffers one of the memory blocks 172, 184, 192. The second instruction buffer circuitry 220 has the capacity to buffer a plurality of the memory blocks 172, 184, 192. In some examples, when second instruction buffer circuitry 220 is approximately five hundred twelve bits and each of memory blocks 172 , 184 , 192 is one hundred twenty eight bits, second instruction buffer circuitry 220 may store up to four blocks of memory 168 .

[0071] When the second instruction buffer circuitry 220 has capacity to store another of the memory blocks 172, 184, 192, the second instruction buffer circuitry 220 accepts a read response from the memory 168 through a subsequent one of the memory blocks 172, 184, 192. When the second instruction buffer circuitry 220 is full, the buffer controller circuitry 255 determines that the second instruction buffer circuitry 220 no longer has capacity to store another of the memory blocks 172, 184, 192. Such a determination allows the buffer controller circuitry 255 to delay subsequent read commands to the memory 168. In some examples, the second instruction buffer circuitry 220 is a FIFO buffer. The second instruction buffer circuitry 220 provides the buffered memory blocks to the multiplexer circuitry 225.

[0072] Multiplexer circuitry 225 is coupled to instruction buffer circuitry 215, 220, decoder circuitry 235, and buffer controller circuitry 255. Buffer controller circuitry 255 controls multiplexer circuitry 225. Multiplexer circuitry 225 couples one of instruction buffer circuitry 215, 220 to decoder circuitry 235 in response to buffer controller circuitry 255. In a first configuration, multiplexer circuitry 225 couples first instruction buffer circuitry 215 to decoder circuitry 235. In a second configuration, multiplexer circuitry 225 couples second instruction buffer circuitry 220 to decoder circuitry 235.

[0073] The periodic clock circuit system 230 is coupled to the instruction buffer circuit systems 215, 220, the decoder circuit system 235, the execution circuit system 240, and the discontinuity controller circuit system 245. The periodic clock circuit system 230 generates a periodic clock of a predetermined frequency. In some examples, one or more components of the periodic clock circuit system 230 are external to the device 200. For example, when the periodic clock circuit system 230 uses a crystal oscillator circuit system, the crystal component of the crystal oscillator circuit system can be external to the device 200 to reduce electromagnetic interference (EMI). The periodic clock circuit system 230 provides the periodic clock to the instruction buffer circuit systems 215, 220, the decoder circuit system 235, the execution circuit system 240, and the discontinuity controller circuit system 245.

[0074] Decoder circuitry 235 is coupled to multiplexer circuitry 225, cycle clock circuitry 230, and execution circuitry 240. Decoder circuitry 235 is configured to decode a memory block in one of first instruction buffer circuitry 215 or second instruction buffer circuitry 220 to determine a machine instruction of one of instruction packets 176, 180, 188, 196. In some examples, decoder circuitry 235 may be configured to decode a packet from one of memory blocks 172, 184, 192. In such an example, decoder circuitry 235 sequentially decodes one of a plurality of instruction packets for each cycle of the cycle clock. Decoder circuitry 235 removes a memory block from first instruction buffer circuitry 215 or second instruction buffer circuitry 220 in response to decoding all instruction packets of the memory block. For example, decoder circuitry 235 may remove first memory block 172 from first instruction buffer circuitry 215 in response to decoding both instruction packets 176, 180. In such an example, decoder circuitry 235 decodes first instruction packet 176 during a first cycle and decodes second instruction packet 180 during a second cycle. Decoder circuitry 235 provides the decoded instruction packets to execution circuitry 240 in response to another cycle of the cycle clock.

[0075] Execution circuit system 240 is coupled to cycle clock circuit system 230, decoder circuit system 235 and discontinuity controller circuit system 245. In some examples, execution circuit system 240 may be coupled to one or more additional components, such as read circuit system, auxiliary execution circuit system, etc. Execution circuit system 240 receives decoded instruction grouping from decoder circuit system 235. When the machine instruction of the decoded instruction grouping is a non-branch instruction, execution circuit system 240 instantiates circuit system to perform the operation of the decoded instruction grouping. In such an example, execution circuit system 240 may instantiate circuit system to perform the operation of the decoded instruction grouping at each cycle of the cycle clock. When the machine instruction of the decoded instruction grouping is a branch instruction, execution circuit system 240 provides the decoded instruction to discontinuity controller circuit system 245. For example, when execution circuit system 240 determines that the opcode of the machine instruction of the decoded instruction grouping corresponds to a branch instruction, execution circuit system 240 provides the decoded instruction to discontinuity controller circuit system 245. In some examples, execution circuitry 240 instantiates discontinuity controller circuitry 245 in response to the machine instruction being a branch instruction. In such examples, execution circuitry 240 determines that the branch instruction is one of an unconditional branch instruction or a conditional branch instruction and is to be executed (e.g., a condition is satisfied).

[0076] The discontinuity controller circuit system 245 is coupled to the cycle clock circuit system 230, the execution circuit system 240, the address generation circuit system 250 and the buffer controller circuit system 255. The discontinuity controller circuit system 245 receives the branch instruction packet and the cycle clock. The discontinuity controller circuit system 245 determines the delay information and the branch target address in response to the branch instruction packet. The discontinuity controller circuit system 245 determines the delay information in response to the delay bit of the branch instruction packet. The delay information specifies the number of memory blocks to be obtained from the current address before obtaining from the branch target address location. The branch target address location is a memory address in the memory 168 that identifies the subsequent instruction packet.

[0077] As described above, some instructions that would appear before the branch instruction if executed in order may be delayed, starting after the branch instruction itself. In an example operation, the discontinuity controller circuit system 245 determines a plurality of subsequent memory blocks in the memory blocks 172, 184, 192 based on the delay information to decode and execute a reference number (e.g., three) of instruction packets that have been reordered to follow the branch instruction. For example, the delay information may specify that one, two, three, or four additional memory blocks are required. In such an instance, the specified additional memory blocks may not include the current memory blocks in the memory blocks 172, 184, 192 that the decoder circuit system 235 is decoding. In such an example operation, the discontinuity controller circuit system 245 receives an active buffer fill indication from the buffer controller circuit system 255, the indication specifying the number of memory blocks currently coupled to one of the decoder circuit system 235 in one of the instruction buffer circuit systems 215, 220. The discontinuity controller circuit system 245 determines the remaining number of memory blocks to be read from the memory 168 before reading from the branch target address.

[0078] The discontinuity controller circuitry 245 is configured to delay providing the branch target address to the address generation circuitry 250 for adjusting the program counter based on the remaining number of memory blocks to be read from the memory 168. For example, when the delay information specifies three memory blocks and the first instruction buffer circuitry 215 has two memory blocks, the discontinuity controller circuitry 245 waits for one additional cycle of the cycle clock before providing the branch target address to the address generation circuitry 250. In such an example, the discontinuity controller circuitry 245 determines that the first of the additional memory blocks is in the first instruction buffer circuitry 215 and the address generation circuitry 250 provides a first read command for the second of the additional memory blocks to the memory 168 during the current cycle. During the additional cycle, the memory 168 provides the second of the additional memory blocks to the first instruction buffer circuitry 215 and the address generation circuitry 250 generates a second read command for the third of the additional memory blocks. Advantageously, discontinuity controller circuitry 245 allows address generation circuitry 250 to generate read commands for a memory block a reference number of instruction packets after a branch instruction packet by delaying provision of the branch target address to address generation circuitry 250 .

[0079] The discontinuity controller circuitry 245 monitors the buffer controller circuitry 255 to determine when the additional memory block is in one of the instruction buffer circuitry 215, 220 coupled to the decoder circuitry 235. When the discontinuity controller circuitry 245 determines that the additional memory block is in one of the instruction buffer circuitry 215, 220, the discontinuity controller circuitry 245 generates a delayed completion indication. The discontinuity controller circuitry 245 provides the delayed completion indication to the buffer controller circuitry 255.

[0080] The address generation circuitry 250 is coupled to the cycle clock circuitry 230, the discontinuity controller circuitry 245, and the buffer controller circuitry 255. The address generation circuitry 250 receives the cycle clock, the branch target address, and the buffer status indication. The address generation circuitry 250 receives the buffer status indication from the buffer controller circuitry 255. The buffer status indication specifies whether one of the instruction buffer circuitry 215, 220 coupled to the memory 168 is full. When the available memory of the one of the instruction buffer circuitry 215, 220 is less than the size of the memory block, the one of the instruction buffer circuitry 215, 220 is considered to be full.

[0081] The address generation circuit system 250 generates a read command including the memory address of one of the memory blocks 172, 184, 192. The address generation circuit system 250 provides the read command to the memory 168. The memory 168 provides one of the memory blocks 172, 184, 192 at the memory address of the read command to one of the instruction buffer circuit systems 215, 220. In the example operation, the configuration of the demultiplexer circuit system 210 determines which one of the instruction buffer circuit systems 215, 220 to provide one of the memory blocks 172, 184, 192. Such an example operation is called a fetch operation. The fetch operation occurs over two cycles of the cycle clock. During the first cycle of the cycle clock, the address generation circuit system 250 generates a read command and provides it to the memory 168. During the second cycle of the cycle clock, after the first cycle, the memory 168 provides one of the memory blocks 172, 184, 192 to one of the instruction buffer circuit systems 215, 220.

[0082] The address generation circuitry 250 determines a subsequent memory address of a subsequent read command by incrementing the memory address of the previous read command. In some instances, the address generation circuitry 250 increments the memory address of the previous read command by a predetermined address increment. In such instances, the determined memory address may be a data identifier that specifies a location in the memory 168 specific to the data to be read. In other instances, the address generation circuitry 250 increments the memory address of the previous read command by the length of the memory block. In such instances, the determined memory address identifies the starting bit of the data to be read.

[0083] The address generation circuit system 250 stops incrementing the subsequent memory address for the read command in response to receiving the branch target address. In the example operation, the discontinuity controller circuit system 245 delays providing the branch target address to the address generation circuit system 250 for adjusting the programming counter based on the delay information. During the next cycle of the periodic clock, the address generation circuit system 250 generates a read command with the branch target address as the memory address. The address generation circuit system 250 resumes incrementing the memory address of the previous read command in response to providing the read command with the branch target address. For example, the address generation circuit system 250 determines the subsequent memory address by incrementing the branch target address. Advantageously, the address generation circuit system 250 starts fetching instructions at the branch target address in response to receiving the branch target address from the discontinuity controller circuit system 245.

[0084] However, the address generation circuitry 250 delays generating and providing read commands in response to a buffer status indication indicating that one of the instruction buffer circuitry 215, 220 coupled to the memory 168 is full. In some examples, the address generation circuitry 250 checks the buffer status indication before providing the read command to the memory 168. When one of the instruction buffer circuitry 215, 220 is full, the memory 168 may corrupt a memory block stored in the one of the instruction buffer circuitry 215, 220 by attempting to write to the other of the memory blocks 172, 184, 192. The address generation circuitry 250 resumes providing and generating read commands in response to a buffer status indication identifying that the one of the instruction buffer circuitry 215, 220 is available to receive one or more additional of the memory blocks 172, 184, 192.

[0085] Buffer controller circuitry 255 is coupled to multiplexer circuitry 210, 225, instruction buffer circuitry 215, 220, discontinuity controller circuitry 245, and address generation circuitry 250. Buffer controller circuitry 255 receives from discontinuity controller circuitry 245 a delayed completion indication.

[0086] The buffer controller circuitry 255 controls the multiplexer circuitry 210, 225 based on the delayed completion indication. For example, at startup, the buffer controller circuitry 255 adjusts the multiplexer circuitry 210, 225 to couple the first instruction buffer circuitry 215 to the memory 168 and the decoder circuitry 235. The buffer controller circuitry 255 determines the amount of available memory capacity in the instruction buffer circuitry 215, 220. The buffer controller circuitry 255 generates a valid buffer fill indication in response to the amount of available memory in one of the instruction buffer circuitry 215, 220 coupled to the decoder circuitry 235. The buffer controller circuitry 255 provides the valid buffer fill indication to the discontinuity controller circuitry 245. The buffer controller circuitry 255 generates a buffer status indication in response to the amount of available memory in one of the instruction buffer circuitry 215, 220 coupled to the memory 168. The buffer controller circuitry 255 provides the buffer status indication to the address generation circuitry 250.

[0087] Buffer controller circuitry 255 receives the delay completion indication from discontinuity controller circuitry 245. Buffer controller circuitry 255 coordinates demultiplexer circuitry 210 to switch which of instruction buffer circuitry 215, 220 is coupled to memory 168. For example, demultiplexer circuitry 210 switches from coupling first instruction buffer circuitry 215 to memory 168 to coupling second instruction buffer circuitry 220 to memory 168 in response to buffer controller circuitry 255 receiving the delay completion indication. In such an example, during the next cycle of the cycle clock, memory 168 begins writing the memory block to second instruction buffer circuitry 220.

[0088] The buffer controller circuitry 255 adjusts the multiplexer circuitry 225 to switch which of the instruction buffer circuitry 215, 220 is coupled to the decoder circuitry 235 approximately one cycle of the cycle clock after switching the demultiplexer circuitry 210. For example, the multiplexer circuitry 225 switches from coupling the first instruction buffer circuitry 215 to the decoder circuitry 235 to coupling the second instruction buffer circuitry 220 to the decoder circuitry 235 one cycle after adjusting the demultiplexer circuitry 210. In such an example, during the next cycle of the cycle clock, the decoder circuitry 235 begins decoding the memory block in the second instruction buffer circuitry 220.

[0089] Advantageously, buffer controller circuitry 255 allows decoder circuitry 235 to continue decoding a memory block in first instruction buffer circuitry 215 while memory writes a memory block at a branch target address to second instruction buffer circuitry 220. Advantageously, buffer controller circuitry 255 ensures that decoder circuitry 235 is continuously coupled to one of instruction buffer circuitry 215, 220. Advantageously, buffer controller circuitry 255 orders the use of instruction buffer circuitry 215, 220 to prevent delays between decoding and executing instruction packets at a branch target address.

[0090] Figure 3A Shown by Figure 2 An example listing of instruction grouping 300 for preemptively performing branch operations when executed by the programmable circuit system 205 of FIG. Figure 3AIn the example of , the list 300 of instruction groups includes a first example instruction set 302, a first example instruction grouping 304, a second example instruction grouping 306, a third example instruction grouping 308, a fourth example instruction grouping 310, a fifth example instruction grouping 312, a sixth example instruction grouping 314, a second example instruction set 316, a seventh example instruction grouping 318, an eighth example instruction grouping 320, a ninth example instruction grouping 322, a tenth example instruction grouping 324, an eleventh example instruction grouping 326, and a twelfth example instruction grouping 328. Before the compiler reorders, instruction grouping 308 is followed by instruction grouping 314, so the logical order of operation is instruction groups 304 and 306, followed by instruction groups 310, 312, and 314, and then instruction grouping 308. However, for efficient execution, the compiler advances instruction grouping 308 before instruction groups 310, 312, and 314. The list of instruction groups 300 is Figure 1 300 . The programmable circuit system 205 executes the list of instruction groups 300 sequentially during runtime. However, branch operations of the list of instruction groups 300 modify the execution order of the list of instruction groups 300. Figure 3C to illustrate and describe such example operations.

[0091] Instruction groups 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 represent the operation of programmable circuitry 205. Figure 3A In some examples, each of the instruction groups 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 includes at least a start bit, an opcode, and / or an operand. In some examples, each of the instruction groups 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 may include Figure 3A One or more additional elements not shown in the diagram. For example, a branch instruction packet may include a delay bit. Figure 3B As shown, each of the instruction groups 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 is in accordance with Figure 3A are stored in the order of execution shown.

[0092] The start bits of the instruction groups 304 , 306 , 308 , 310 , 312 , 314 , 318 , 320 , 322 , 324 , 326 , 328 represent the memory location of each of the instruction groups 304 , 306 , 308 , 310 , 312 , 314 , 318 , 320 , 322 , 324 , 326 , 328 . The starting bit of a subsequent one of the instruction packets 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 is determined based on the starting bit of the previous one of the instruction packets 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 and the length of the previous one of the instruction packets 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328. In some examples, the length of the instruction packets 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 may be from sixteen bits to one hundred twenty-eight bits. Programmable circuit system 205 sequentially fetches instruction groups 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 based on the start bit. The execution order of instruction groups 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 is determined by compiler circuit system 108. In some examples, Figure 1 The branch ordering circuitry 128 adjusts the execution order to preemptively execute one or more branch instructions.

[0093] In the example operation, Figure 1 The branch detection circuitry 132 provides the opcodes and / or operands of the instruction groups 304, 306, 310, 312, 314 to Figure 1 After placing the opcodes and / or operands of instruction groups 304, 306, 310, 312, 314 in instruction buffer circuitry 144, branch detection circuitry 132 determines that the opcode of third instruction group 308 corresponds to a branch operation. Branch detection circuitry 132 provides the opcode and operands of third instruction group 308 to instruction buffer circuitry 144 in response to determining that the branch operation of the opcode is an unconditional operation. Figure 1The branch relocation circuitry 140 adjusts the start bits of the opcodes and / or operands of the instruction groups 310, 312, 314 to reorder the opcodes and operands of the third instruction group 308. In such an example operation, the branch relocation circuitry 140 reorders the opcodes and operands of the third instruction group 308 from being executed after the sixth instruction group 314 to being executed after the second instruction group 306.

[0094] exist Figure 3A In the example of , the second instruction set 316 represents the operations to be performed in response to the execution of the branch instruction of the third instruction group 308. However, in combination Figure 3C Further discussed, programmable circuit system 205 continues to fetch, decode and / or execute instruction groups 310, 312, 314 while simultaneously fetching and decoding second instruction set 316. Figure 2 When the first instruction buffer circuit system 215 decodes and executes the instruction groups 310, 312, 314, Figure 2 The address generation circuitry 250 of the programmable circuitry 205 begins to fetch the memory blocks storing the instruction packets 318, 320, 322, 324, 326, 328. Advantageously, the programmable circuitry 205 may begin decoding the instruction packets 318, 320, 322, 324, 326, 328 immediately after decoding the sixth instruction packet 314.

[0095] Figure 3B Show Figure 3A The list of instruction packets 300 is placed in an example memory 330. Figure 3B In the example, memory 330 includes a first example memory block 332, a second example memory block 334, a third example memory block 336, a fourth example memory block 338, a fifth example memory block 340, a sixth example memory block 342, a seventh example memory block 344, an eighth example memory block 346 and a ninth example memory block 348. Figure 3B The memory 330 is Figure 1 and 2 168. Memory 330 is separated into memory blocks 332, 334, 336, 338, 340, 342, 344, 346, 348. Figure 3B In the example of , each of the memory blocks 332, 334, 336, 338, 340, 342, 344, 346, 348 has a length of one hundred and twenty-eight bits. Alternatively, the memory 330 can be separated into blocks with alternative lengths. For example, a length of sixty-four bits, two hundred and fifty-six bits, etc.

[0096] Memory blocks 332, 334, 336, 338, 340, 342, 344, 346, 348 represent portions of memory 330 that may store one or more of instruction packets 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328. Figure 3B In the example of , each of the memory blocks 332, 334, 336, 338, 340, 342, 344, 346, 348 can be addressed by a memory address and / or a data identifier. In the example operation, the memory 330 can be accessed from Figure 2 The address generation circuitry 250 of the memory 330 receives a read command including a memory address and / or data identifier identifying one of the memory blocks 332, 334, 336, 338, 340, 342, 344, 346, 348. In such an example, in response to receiving the read command, the memory 330 provides one of the memory blocks 332, 334, 336, 338, 340, 342, 344, 346, 348 to the memory 330. Figure 2 In one of the instruction buffer circuit systems 215, 220.

[0097] In the example operation, Figure 1 The compiler circuit system 108 sequentially stores each of the instruction groups 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 in the memory 330. In such an example operation, Figure 1 The memory block buffer circuitry 164 of the programmable circuitry 205 provides the first one hundred and twenty eight bits of the list of instruction packets 300 to fill the first memory block 332. For example, the memory block buffer circuitry 164 provides the instruction packets 304, 306, 308, and the first portion of the fourth instruction packet 310 to fill the first memory block 332. In such an example, the memory block buffer circuitry 164 provides the second portion of the fourth instruction packet 310 and the first portion of the fifth instruction packet 312 to fill the second memory block 334. The programmable circuitry 205 may retrieve the instruction packets 304, 306, 308, and the first portion of the fourth instruction packet 310 in response to a read command specifying an address (e.g., 0x00) of the first memory block 332.

[0098] In other examples, such as memory blocks 338, 340, 342, 344, 346, 348, only one of the instruction packets 318, 320, 322, 324, 326, 328 is stored. In such examples, the length of each of the instruction packets 318, 320, 322, 324, 326, 328 is substantially the same as the length of the memory blocks 338, 340, 342, 344, 346, 348. Figure 3B In the example of , each of the memory blocks 338, 340, 342, 344, 346, 348 stores one of the instruction packets 318, 320, 322, 324, 326, 328, but the memory block buffer circuitry 164 may separate the instruction packets 318, 320, 322, 324, 326, 328 into separate portions. In such an example, if a branch instruction is to be added to the second instruction set 316, the delay encoder circuitry 160 may determine the delay information for fetching the four memory blocks before fetching the instruction at the branch target address.

[0099] Figure 3C Show Figure 2 The programmable circuit system 205 from Figure 3B Memory 330 to obtain, decode and execute Figure 3A Example operations 350 of the list of instruction packets 300. Figure 3C In the example of Figure 2 The operation of the programmable circuit system 205 is described as a pipeline. In such an example, the pipeline includes a first acquisition stage (F1), a second acquisition stage (F2), a first decoding stage (D1), and a second decoding stage (D2).

[0100] The first acquisition level indicates Figure 2 Example operation of the address generation circuitry 250. Figure 3C In the example of , the information of the first acquisition stage represents the memory address of the read command from the address generation circuit system 250. The second acquisition stage represents Figure 2 Example operation of the instruction buffer circuitry 215, 220. Figure 3C In the example of the second acquisition stage, the information in the instruction buffer circuit system 215, 220 represents Figure 3B The first and second fetch stages represent the operation of the address generation circuitry 250 and the instruction buffer circuitry 215, 220 to fetch one of the memory blocks 332, 334, 336, 338, 340, 342, 344, 346, 348.

[0101] The first decoding level indicates Figure 2 Example operation of the decoder circuit system 235. Figure 3C In the example of , the information of the first decode stage represents one of the instruction groups 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 determined by decoding one of the memory blocks 332, 334, 336, 338, 340, 342, 344, 346, 348 in one of the instruction buffer circuit systems 215, 220. The second decode stage represents Figure 2 Example operation of the execution circuit system 240. Figure 3C In the example of the second decode stage, the information of the second decode stage represents one of the instruction groups 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328 to be executed by the execution circuitry 240. When in the second decode stage, the execution circuitry 240 instantiates the circuitry to perform the operation of one of the instruction groups 304, 306, 308, 310, 312, 314, 318, 320, 322, 324, 326, 328.

[0102] Operation 350 begins with a first cycle 352 in which the address generation circuitry 250 generates a first read command having a memory address of the first memory block 332. During the first cycle 352, the address generation circuitry 250 provides the first read command to the memory 168.

[0103] During the second cycle 354, the memory 168 provides the first memory block 332 to Figure 2 During the second cycle 354, Figure 2 The multiplexer circuitry 210, 225 will Figure 2 The first instruction buffer circuitry 215 is coupled to the memory 168 and the decoder circuitry 235. During the second cycle 354, the first instruction buffer circuitry 215 stores the first memory block 332. Additionally, during the second cycle 354, the address generation circuitry 250 generates a second read command having a memory address of the second memory block 334. During the second cycle 354, the address generation circuitry 250 provides the second read command to the memory 168.

[0104] During the third example cycle 356, the decoder circuitry 235 decodes the first memory block 332 in the first instruction buffer circuitry 215 to determine the first instruction group 304. During the third example cycle 356, the memory 168 provides the second memory block 334 to the first instruction buffer circuitry 215. In addition, during the third cycle 356, the address generation circuitry 250 generates a third read command having a memory address of the third memory block 336. During the third cycle 356, the address generation circuitry 250 provides the third read command to the memory 168.

[0105] During the fourth cycle 358, the execution circuitry 240 instantiates the circuitry to perform operations of the first instruction grouping 304. During the fourth cycle 358, the decoder circuitry 235 continues to decode the first memory block 332 in the first instruction buffer circuitry 215 to determine the second instruction grouping 306. During the fourth example cycle 358, the memory 168 provides the third memory block 336 to the first instruction buffer circuitry 215. In addition, during the fourth cycle 358, the address generation circuitry 250 generates a fourth read command with a memory address of a subsequent memory block. During the fourth cycle 358, the address generation circuitry 250 provides the fourth read command to the memory 168.

[0106] During the fifth cycle 360, the execution circuitry 240 instantiates the circuitry to perform operations for the second instruction group 306. During the fifth cycle 360, the decoder circuitry 235 continues to decode the first memory block 332 in the first instruction buffer circuitry 215 to determine the third instruction group 308. During the fifth example cycle 360, the memory 168 provides the subsequent memory block to the first instruction buffer circuitry 215. However, during the fifth cycle 360, Figure 2 The buffer controller circuitry 255 determines that the first instruction buffer circuitry 215 is full. During the fifth cycle 360, the buffer controller circuitry 255 prevents the address generation circuitry 250 from generating subsequent read commands.

[0107] During the sixth cycle 362, the execution circuitry 240 provides the third instruction group 308 to the execution circuitry 240 in response to determining that the opcode of the third instruction group 308 corresponds to a branch operation. Figure 2The discontinuity controller circuitry 245 of the execution circuitry 240. In some examples, the execution circuitry 240 instantiates the discontinuity controller circuitry 245 in response to the third instruction grouping 308. During the sixth cycle 362, the decoder circuitry 235 completes decoding of the first memory block 332 and begins decoding of the second memory block 334 to determine the fourth instruction grouping 310. During the sixth cycle 362, the discontinuity controller circuitry 245 determines the delay information of the third instruction grouping 308. During the sixth cycle 362, the discontinuity controller circuitry 245 determines that the instruction groups 310, 312, 314 are already in the first instruction buffer circuitry 215 based on the delay information. In the sixth cycle 362, the discontinuity controller circuitry 245 provides the branch target address from the third instruction grouping 308 to the address generation circuitry 250 and generates a delayed completion indication.

[0108] During the seventh cycle 364, the execution circuitry 240 instantiates the circuitry to perform operations of the fourth instruction grouping 310. During the seventh cycle 364, the decoder circuitry 235 completes decoding of the second memory block 334 and begins decoding of the third memory block 336 to determine the fifth instruction grouping 312. During the seventh cycle 364, the address generation circuitry 250 may update the program counter based on the branch target address and use the program counter to generate a fifth read command with a memory address of the fourth memory block 338. During the seventh cycle 364, the address generation circuitry 250 provides the fifth read command to the memory 168. Additionally, during the seventh cycle 364, the buffer controller circuitry 255 adjusts the demultiplexer circuitry 210 to couple the second instruction buffer circuitry 220 to the memory 168.

[0109] During the eighth cycle 366, the execution circuitry 240 instantiates the circuitry to perform operations of the fifth instruction grouping 312. During the eighth cycle 366, the decoder circuitry 235 continues to decode the third memory block 336 in the first instruction buffer circuitry 215 to determine the sixth instruction grouping 314. During the eighth cycle 366, the memory 168 provides the fourth memory block 338 to the second instruction buffer circuitry 220. Also, during the eighth cycle 366, the address generation circuitry 250 generates a sixth read command having a memory address of the fifth memory block 340. During the eighth cycle 366, the address generation circuitry 250 provides the sixth read command to the memory 168. After the eighth cycle 366, the buffer controller circuitry 255 adjusts the multiplexer circuitry 225 to couple the second instruction buffer circuitry 220 to the decoder circuitry 235.

[0110] During the ninth cycle 368, the execution circuitry 240 instantiates the circuitry to perform operations of the sixth instruction grouping 314. During the ninth cycle 368, the decoder circuitry 235 begins decoding the fourth memory block 338 in the second instruction buffer circuitry 220 to determine the seventh instruction grouping 318. During the ninth cycle 368, the memory 168 provides the fifth memory block 340 to the second instruction buffer circuitry 220. Additionally, during the ninth cycle 368, the address generation circuitry 250 generates a seventh read command having a memory address of the sixth memory block 342. During the ninth cycle 368, the address generation circuitry 250 provides the seventh read command to the memory 168.

[0111] During the tenth cycle 370, the execution circuitry 240 instantiates the circuitry to perform operations of the seventh instruction grouping 318. During the tenth cycle 370, the decoder circuitry 235 begins decoding the fifth memory block 340 in the second instruction buffer circuitry 220 to determine the eighth instruction grouping 320. During the tenth cycle 370, the memory 168 provides the sixth memory block 342 to the second instruction buffer circuitry 220. Additionally, during the tenth cycle 370, the address generation circuitry 250 generates an eighth read command having a memory address of the seventh memory block 344. During the tenth cycle 370, the address generation circuitry 250 provides the eighth read command to the memory 168.

[0112] During the eleventh cycle 372, the execution circuitry 240 instantiates the circuitry to perform operations of the eighth instruction grouping 320. During the eleventh cycle 372, the decoder circuitry 235 begins decoding the sixth memory block 342 in the second instruction buffer circuitry 220 to determine a ninth instruction grouping 322. During the eleventh cycle 372, the memory 168 provides the seventh memory block 344 to the second instruction buffer circuitry 220. Additionally, during the eleventh cycle 372, the address generation circuitry 250 generates a ninth read command having a memory address of the eighth memory block 346. During the eleventh cycle 372, the address generation circuitry 250 provides the ninth read command to the memory 168. The programmable circuitry 205 proceeds to proceed to the list of instruction groups 300.

[0113] Advantageously, programmable circuitry 205 continues to execute instructions (e.g., instructions of groups C3, C4, and C5) after executing the branch instruction. Advantageously, discontinuity controller circuitry 245 and buffer controller circuitry 255 order the use of instruction buffer circuitry 215, 220 to continue to provide instructions to decoder circuitry 235. Advantageously, preemptively executing third instruction group 308 allows programmable circuitry 205 to continue operating while second instruction set 316 is being fetched and decoded.

[0114] Figure 4A Another example listing of instruction group 400 is shown, when Figure 2 When executed by the programmable circuit system 205 of , the instruction grouping preemptively performs a branch operation to cycle through the list of instruction groups 400. Figure 4A In the example of , the list of instruction groups 400 includes a first example instruction group 404, a second example instruction group 406, a third example instruction group 408, a fourth example instruction group 410, a fifth example instruction group 412, and a sixth example instruction group 414. Similar to Figure 3A The list of instruction group 300 is Figure 1 408. Prior to the compiler performing the reordering, instruction grouping 408 is followed by instruction grouping 414, and thus the logical order of operations is instruction groupings 404 and 406, followed by instruction groupings 410, 412, and 414, followed by instruction grouping 408. However, for efficient execution, the compiler advances instruction grouping 408 to precede instruction groupings 410, 412, and 414. The programmable circuit system 205 sequentially executes the list of instruction groupings 400 during runtime. However, branch operations of the list of instruction groupings 400 change the order of execution of the list of instruction groupings 400. For example, the programmable circuit system 205 begins executing the first instruction grouping 404 in response to executing the third instruction grouping 408. As described below in conjunction with Figure 4C to illustrate and describe such example operations.

[0115] Instruction groups 404, 406, 408, 410, 412, 414 represent the operation of programmable circuit system 205. Figure 4A In some examples, each of the instruction groups 404, 406, 408, 410, 412, 414 includes at least a start bit, an opcode, and / or an operand. In some examples, each of the instruction groups 404, 406, 408, 410, 412, 414 may include brackets. Figure 4A One or more additional elements not shown in the diagram. For example, a branch instruction packet may include a delay bit. Figure 4BAs shown, each of the instruction groups 404, 406, 408, 410, 412, 414 is in accordance with Figure 4A are stored in the order of execution shown.

[0116] The start bit of the instruction grouping 404, 406, 408, 410, 412, 414 indicates the memory location of each of the instruction groupings 404, 406, 408, 410, 412, 414. The start bit of the subsequent one of the instruction groupings 404, 406, 408, 410, 412, 414 is determined based on the start bit of the previous one of the instruction groupings 404, 406, 408, 410, 412, 414 and the length of the previous one of the instruction groupings 404, 406, 408, 410, 412, 414. In some examples, the length of the instruction groupings 404, 406, 408, 410, 412, 414 can be from sixteen bits to one hundred and twenty-eight bits. The programmable circuit system 205 sequentially obtains the instruction groupings 404, 406, 408, 410, 412, 414 based on the start bit. The order in which instruction groups 404, 406, 408, 410, 412, 414 are executed is determined by compiler circuitry 108. In some examples, Figure 1 The branch ordering circuitry 128 adjusts the execution order to preemptively execute one or more branch instructions.

[0117] In the example operation, Figure 1 The branch detection circuitry 132 provides the opcodes and / or operands of the instruction groups 404, 406, 408, 412, 414 to Figure 1 After placing the opcodes and / or operands of instruction groups 404, 406, 408, 412, 414 in instruction buffer circuitry 144, branch detection circuitry 132 determines that the opcode of third instruction group 408 corresponds to a branch operation. Branch detection circuitry 132 provides the opcode and operands of third instruction group 408 to instruction buffer circuitry 144 in response to determining that the branch operation of the opcode is an unconditional operation. Figure 1 The branch relocation circuitry 140 adjusts the start bits of the opcodes and / or operands of the instruction groups 410, 412, 414 to reorder the opcodes and operands of the third instruction group 408. In such an example operation, the branch relocation circuitry 140 reorders the opcodes and operands of the third instruction group 408 from being executed after the sixth instruction group 414 to being executed after the second instruction group 406.

[0118] exist Figure 4AIn the example of , the programmable circuit system 205 re-fetches, decodes and executes the instruction groups 404, 406, 408, 410, 412, 414 in response to the execution of the branch instruction of the third instruction group 408. However, in combination Figure 4C Further discussed, programmable circuit system 205 continues to fetch, decode and / or execute instruction groups 410, 412, 414 while re-fetching and re-decoding instruction groups 404, 406, 408, 410, 412, 414. Figure 2 When the first instruction buffer circuit system 215 decodes and executes the instruction groups 410, 412, 414, Figure 2 The address generation circuitry 250 of the programmable circuitry 205 begins to fetch the memory blocks storing the instruction packets 404, 406, 408, 410, 412, 414. Advantageously, the programmable circuitry 205 may begin decoding the instruction packets 404, 406, 408, 410, 412, 414 immediately after decoding the sixth instruction packet 414.

[0119] Figure 4B Show Figure 4A An example placement of a list of instruction packets 400 in example memory 418. Figure 4B In the example of , the memory 418 includes a first example memory block 420 , a second example memory block 422 , and a third example memory block 424 . Figure 4B The memory 418 is Figure 1 , 2 Memory 418 is separated into memory blocks 420, 422, 424. Figure 4B In the example of , each of the memory blocks 420, 422, 424 has a length of one hundred twenty-eight bits. Alternatively, the memory 418 can be separated into blocks with alternative lengths. For example, a length of sixty-four bits, two hundred fifty-six bits, etc.

[0120] Memory blocks 420, 422, 424 represent portions of memory 418 that may store one or more of instruction packets 404, 406, 408, 410, 412, 414. Figure 4B In the example of , each of the memory blocks 420, 422, 424 can be addressed by a memory address and / or a data identifier. In the example operation, the memory 418 can be accessed from Figure 2 The address generation circuitry 250 of the memory 418 receives a read command including a memory address and / or a data identifier identifying one of the memory blocks 420, 422, 424. In such an example, in response to receiving the read command, the memory 418 provides one of the memory blocks 420, 422, 424 to the memory 418. Figure 2One of the instruction buffer circuit systems 215, 220.

[0121] In the example operation, Figure 1 The compiler circuit system 108 stores each of the instruction groups 404, 406, 408, 410, 412, 414 sequentially in the memory 418. In such an example operation, Figure 1 The memory block buffer circuitry 164 of the programmable circuitry 205 provides the first one hundred and twenty eight bits in the list of instruction packets 400 to fill the first memory block 420. For example, the memory block buffer circuitry 164 provides the instruction packets 404, 406, 408, and the first portion of the fourth instruction packet 410 to fill the first memory block 420. In such an example, the memory block buffer circuitry 164 provides the second portion of the fourth instruction packet 410 and the first portion of the fifth instruction packet 412 to fill the second memory block 422. The programmable circuitry 205 may retrieve the instruction packets 404, 406, 408, and the first portion of the fourth instruction packet 410 in response to a read command specifying an address (e.g., 0x00) of the first memory block 420.

[0122] In other examples, for example Figure 3B The memory blocks 338, 340, 342, 344, 346, 348, and memory blocks 420, 422, 424 of the embodiment of the present invention may store only one of the instruction packets 404, 406, 408, 410, 412, 414. In such an example, the length of each of the instruction packets 404, 406, 408, 410, 412, 414 is substantially the same as the length of the memory blocks 420, 422, 424.

[0123] Figure 4C Show Figure 2 The programmable circuit system 205 from Figure 4B Memory 418 retrieves, decodes and executes Figure 4A Example operation 426 of the list of instruction packets 400. Figure 4C In the example of Figure 2 The operation of the programmable circuit system 205 is described as a pipeline. In such an example, the pipeline includes a first acquisition stage (F1), a second acquisition stage (F2), a first decoding stage (D1), and a second decoding stage (D2).

[0124] The first acquisition level indicates Figure 2 Example operation of the address generation circuitry 250. Figure 4C In the example of , the information of the first acquisition stage represents the memory address of the read command from the address generation circuit system 250. The second acquisition stage represents Figure 2 Example operation of the instruction buffer circuitry 215, 220. Figure 4C In the example of the second acquisition stage, the information in the instruction buffer circuit system 215, 220 represents Figure 4B The first and second fetch stages represent the operation of the address generation circuitry 250 and the instruction buffer circuitry 215 , 220 to fetch one of the memory blocks 420 , 422 , 424 .

[0125] The first decoding level indicates Figure 2 Example operation of the decoder circuit system 235. Figure 4C In the example of , the information of the first decode stage represents one of the instruction groups 404, 406, 408, 410, 412, 414 determined by decoding one of the memory blocks 420, 422, 424 in one of the instruction buffer circuit systems 215, 220. The second decode stage represents Figure 2 Example operation of the execution circuit system 240. Figure 4C In the example of , the information of the second decode stage represents one of the instruction groups 404, 406, 408, 410, 412, 414 to be executed by the execution circuitry 240. When in the second decode stage, the execution circuitry 240 instantiates the circuitry to perform the operation of one of the instruction groups 404, 406, 408, 410, 412, 414.

[0126] Operation 426 begins with a first cycle 428, when the address generation circuitry 250 generates a first read command having a memory address of the first memory block 420. During the first cycle 428, the address generation circuitry 250 provides the first read command to the memory 168.

[0127] During the second cycle 430, the memory 168 provides the first memory block 420 to Figure 2 During the second cycle 430, Figure 2 The multiplexer circuitry 210, 225 will Figure 2 The first instruction buffer circuitry 215 is coupled to the memory 168 and the decoder circuitry 235. During the second cycle 430, the first instruction buffer circuitry 215 stores the first memory block 420. Additionally, during the second cycle 430, the address generation circuitry 250 generates a second read command having a memory address of the second memory block 422. During the second cycle 430, the address generation circuitry 250 provides the second read command to the memory 168.

[0128] During the third example cycle 432, the decoder circuitry 235 decodes the first memory block 420 in the first instruction buffer circuitry 215 to determine the first instruction grouping 404. During the third example cycle 432, the memory 168 provides the second memory block 422 to the first instruction buffer circuitry 215. Additionally, during the third cycle 432, the address generation circuitry 250 generates a third read command having a memory address of the third memory block 424. During the third cycle 432, the address generation circuitry 250 provides the third read command to the memory 168.

[0129] During the fourth cycle 434, the execution circuitry 240 instantiates the circuitry to perform operations of the first instruction grouping 404. During the fourth cycle 434, the decoder circuitry 235 continues to decode the first memory block 420 in the first instruction buffer circuitry 215 to determine the second instruction grouping 406. During the fourth example cycle 434, the memory 168 provides the third memory block 424 to the first instruction buffer circuitry 215. In addition, during the fourth cycle 434, the address generation circuitry 250 generates a fourth read command with a memory address of a subsequent memory block. During the fourth cycle 434, the address generation circuitry 250 provides the fourth read command to the memory 168.

[0130] During the fifth cycle 436, the execution circuitry 240 instantiates the circuitry to perform operations on the second instruction group 406. During the fifth cycle 436, the decoder circuitry 235 continues to decode the first memory block 420 in the first instruction buffer circuitry 215 to determine the third instruction group 408. During the fifth example cycle 436, the memory 168 provides the subsequent memory block to the first instruction buffer circuitry 215. However, during the fifth cycle 436, Figure 2 The buffer controller circuitry 255 determines that the first instruction buffer circuitry 215 is full. During the fifth cycle 436, the buffer controller circuitry 255 prevents the address generation circuitry 250 from generating subsequent read commands.

[0131] During the sixth cycle 438, the execution circuitry 240 provides the third instruction group 408 to the execution circuitry 240 in response to determining that the opcode of the third instruction group 408 corresponds to a branch operation. Figure 2The discontinuity controller circuitry 245 of the embodiment of the present invention is configured to execute the discontinuity controller circuitry 245. In some examples, the execution circuitry 240 instantiates the discontinuity controller circuitry 245 in response to the third instruction grouping 408. During the sixth cycle 438, the decoder circuitry 235 completes decoding of the first memory block 420 and begins decoding of the second memory block 422 to determine the fourth instruction grouping 410. During the sixth cycle 438, the discontinuity controller circuitry 245 determines the delay information of the third instruction grouping 408. During the sixth cycle 438, the discontinuity controller circuitry 245 determines that the instruction groups 410, 412, 414 are already in the first instruction buffer circuitry 215 based on the delay information. In the sixth cycle 438, the discontinuity controller circuitry 245 provides the branch target address from the third instruction grouping 408 to the address generation circuitry 250 and generates a delayed completion indication.

[0132] During the seventh cycle 440, the execution circuitry 240 instantiates circuitry to perform operations of the fourth instruction grouping 410. During the seventh cycle 440, the decoder circuitry 235 completes decoding of the second memory block 422 and begins decoding of the third memory block 424 to determine the fifth instruction grouping 412. During the seventh cycle 440, the address generation circuitry 250 may update a program counter based on the branch target address and use the program counter to generate another instance of a first read command having a memory address of the first memory block 420. During the seventh cycle 440, the address generation circuitry 250 provides the first read command to the memory 168. Additionally, during the seventh cycle 440, the buffer controller circuitry 255 adjusts the demultiplexer circuitry 210 to couple the second instruction buffer circuitry 220 to the memory 168.

[0133] During the eighth cycle 442, the execution circuitry 240 instantiates the circuitry to perform operations for the sixth instruction grouping 414. During the eighth cycle 442, the decoder circuitry 235 continues to decode the third memory block 424 in the first instruction buffer circuitry 215 to determine the sixth instruction grouping 414. During the eighth cycle 442, the memory 168 provides the first memory block 420 to the second instruction buffer circuitry 220. Additionally, during the eighth cycle 442, the address generation circuitry 250 generates another instance of a second read command having a memory address of the second memory block 422. During the eighth cycle 442, the address generation circuitry 250 provides the second read command to the memory 168. After the eighth cycle 442, the buffer controller circuitry 255 adjusts the multiplexer circuitry 225 to couple the second instruction buffer circuitry 220 to the decoder circuitry 235.

[0134] During the ninth cycle 444, the execution circuitry 240 instantiates the circuitry to perform operations of the sixth instruction grouping 414. During the ninth cycle 444, the decoder circuitry 235 begins decoding the first memory block 420 in the second instruction buffer circuitry 220 to determine the first instruction grouping 404. During the ninth cycle 444, the memory 168 provides the second memory block 422 to the second instruction buffer circuitry 220. Additionally, during the ninth cycle 444, the address generation circuitry 250 generates another instance of a third read command having a memory address of the third memory block 424. During the ninth cycle 444, the address generation circuitry 250 provides the third read command to the memory 168.

[0135] During the tenth cycle 446, the execution circuitry 240 instantiates the circuitry to perform operations of the first instruction grouping 404. During the tenth cycle 446, the decoder circuitry 235 continues to decode the first memory block 420 in the second instruction buffer circuitry 220 to determine the second instruction grouping 406. During the tenth cycle 446, the memory 168 provides the third memory block 424 to the second instruction buffer circuitry 220. Additionally, during the tenth cycle 446, the address generation circuitry 250 generates another instance of a fourth read command having a memory address of a subsequent memory block. During the tenth cycle 446, the address generation circuitry 250 provides the fourth read command to the memory 168.

[0136] During the eleventh cycle 448, the execution circuitry 240 instantiates circuitry to perform operations for the second instruction grouping 406. During the eleventh cycle 448, the decoder circuitry 235 continues to decode the first memory block 420 in the second instruction buffer circuitry 220 to determine the third instruction grouping 408. During the eleventh example cycle 448, the memory 168 provides subsequent memory blocks to the second instruction buffer circuitry 220. However, during the eleventh cycle 448, the buffer controller circuitry 255 determines that the second instruction buffer circuitry 220 is full. During the eleventh cycle 448, the buffer controller circuitry 255 prevents the address generation circuitry 250 from generating subsequent read commands until the second instruction buffer circuitry 220 is able to store additional memory blocks of the memory blocks 420, 422, 424.

[0137] During the twelfth cycle 450, the execution circuitry 240 provides the third instruction grouping 408 to the discontinuity controller circuitry 245 in response to determining that the opcode of the third instruction grouping 408 corresponds to a branch operation. In some examples, the execution circuitry 240 instantiates the discontinuity controller circuitry 245 in response to the third instruction grouping 408. During the twelfth cycle 450, the decoder circuitry 235 completes decoding of the first memory block 420 and begins decoding of the second memory block 422 to determine the fourth instruction grouping 410. During the twelfth cycle 450, the discontinuity controller circuitry 245 determines latency information for the third instruction grouping 408. During the twelfth cycle 450, the discontinuity controller circuitry 245 determines that the instruction groups 410, 412, 414 are already in the second instruction buffer circuitry 220 based on the latency information. In the twelfth cycle 450, the discontinuity controller circuitry 245 provides the branch target address from the third instruction grouping 408 to the address generation circuitry 250 and generates a latency completion indication.

[0138] During the thirteenth cycle 452, the execution circuitry 240 instantiates circuitry to perform operations for the fourth instruction grouping 410. During the thirteenth cycle 452, the decoder circuitry 235 completes decoding of the second memory block 422 and begins decoding of the third memory block 424 to determine the fifth instruction grouping 412. During the thirteenth cycle 452, the address generation circuitry 250 generates another collar of the first read command having the memory address of the first memory block 420. During the thirteenth cycle 452, the address generation circuitry 250 provides the first read command to the memory 168. Additionally, during the seventh cycle 452, the buffer controller circuitry 255 adjusts the demultiplexer circuitry 210 to couple the first instruction buffer circuitry 215 to the memory 168.

[0139] Advantageously, programmable circuitry 205 continues to execute instructions after executing the branch instruction. Advantageously, discontinuity controller circuitry 245 and buffer controller circuitry 255 order the use of instruction buffer circuitry 215, 220 to continue to provide instructions to decoder circuitry 235. Advantageously, preemptively executing third instruction packet 408 allows programmable circuitry 205 to continue operating while instruction packets 404, 408 are being fetched and decoded.

[0140] Figure 5 is a diagram of an example branch instruction 500, which shows an example branch instruction format. Figure 5In the example of FIG. 5 , the branch instruction 500 includes an opcode (OP_CODE(2:15)) 520, a condition bit (COND) 530, a delay bit (DELAY(0:1)) 540, a first address bit (ADDR(16:31)) 560, and a second address bit (ADDR(32:47)) 570. The branch instruction 500 is a 48-bit instruction. Alternatively, the branch instruction 500 may be an alternative length instruction, such as a 32-bit instruction, a 64-bit instruction, etc.

[0141] The operation code 520 identifies the operation of the branch instruction 500 as a branch operation. In the example operation, during the execution of the branch instruction 500, the operation code 520 will Figure 2 The execution circuit system 240 is configured to perform a branch operation. In such an example operation, the execution circuit system 240 may instantiate in response to the execution circuit system 240 executing the branch instruction 500. Figure 2 The discontinuity controller circuit system 245 of the embodiment of the present invention. In some examples, the opcode 520 includes a conditional bit 530. In such an example, the conditional bit 530 identifies the condition that the branch instruction 500 must meet to be executed. Such an example branch instruction is called a conditional branch instruction. In the example operation, the conditional bit 530 identifies the operation of checking one or more flags. In such an example operation, the execution circuit system 240 executes the branch operation of the branch instruction 500 in response to satisfying the condition corresponding to the conditional bit 530.

[0142] Delay bit 540 identifies the number of memory blocks that need to be acquired before acquiring the memory block at the branch target address. In one example, when set to a first value (e.g., 0x0), delay bit 540 specifies that no more memory blocks are to be read from memory. When set to a second value (e.g., 0x1), delay bit 540 specifies that two memory blocks are to be read from memory. When set to a third value (0x2), delay bit 540 specifies that three memory blocks are to be read from memory. When set to a fourth value (0x3), delay bit 540 specifies that three memory blocks are to be read from memory. In some examples, Figure 2 The programmable circuit system 205 can determine whether the number of memory blocks is already stored in Figure 2 In such an example, when one or more of the memory blocks specified by delay bits 540 are in one of the instruction buffer circuit systems 215, 220, the programmable circuit system 205 can reduce the number of memory blocks to be read from the memory. Advantageously, delay bits 540 allow programmable circuit system 205 to determine the number of memory blocks that contain the reference number of instruction packets.

[0143] In some examples, the first value of the delay bit 540 may correspond to a branch instruction 500 that is not a delayed branch instruction. In such an example, when the delay bit 540 corresponds to a non-delayed branch instruction, the programmable circuit system 205 stops executing instructions after the branch instruction 500 until the instruction at the branch target address is to be executed.

[0144] Address bits 560, 570 identify the target branch address of branch instruction 500. Figure 5 In the example of, address bits 560, 570 specify a target branch address in the memory, and the target branch address is thirty-two bits long. Alternatively, address bits 560, 570 may include an alternative address length, such as a sixteen-bit address, a sixty-four-bit address, etc. In some examples, address bits 560, 570 include multiple target branch addresses. In such an example, the first of the multiple target branch addresses corresponds to a first condition being satisfied, and the second of the multiple target branch addresses corresponds to a second condition being satisfied. For example, when the set flag is logically high, the execution circuit system 240 begins to execute a branch operation at the first target branch address, or when the set flag is logically low, begins to execute a branch operation at the second target branch address.

[0145] Figure 6 Yes means you can use Figure 1 A flowchart of example machine readable instructions and / or example operations 600 to be executed, instantiated, and / or performed by an example programmable circuitry implementation of compiler circuitry 108 to generate an example listing of instruction packets, such as Figure 3A and 4A The example operation 600 begins at block 605, at which time, Figure 1 The operation determination circuit system 112 determines whether there are machine-readable instructions to be converted. In some examples, the operation determination circuit system 112 receives and / or accesses Figure 1 In such an example, the machine-readable instructions 104 may represent Figure 2 The machine-readable instructions 104 may represent operations expressed in a programming language such as assembly, C, C++, C#, Java, etc. If the operation determination circuitry 112 determines that there are no machine-readable instructions to convert (e.g., block 605 returns a “no” result), control continues to return to block 605.

[0146] If the operation determination circuit system 112 determines that there are machine-readable instructions to be converted (e.g., block 605 returns a "yes" result), the operation determination circuit system 112 generates a sequence of operations representing the machine-readable instructions. (Block 610). In some examples, the operation determination circuit system 112 generates operations representing the operations of the machine-readable instructions. In such examples, the operation determination circuit system 112 can generate one or more relatively low-level operations to represent the operations of one of the machine-readable instructions 104. Advantageously, the relatively low-level operations of the operation determination circuit system 112 reduce the complexity of generating machine instructions specific to the programmable circuit system 205.

[0147] Figure 1 The instruction approximation circuitry 124 assembles a list of machine instructions based on the sequential operations. (Block 615). In some instances, the instruction approximation circuitry 124 approximates the relatively low-level operations from the operation determination circuitry 112 into machine instructions. In such instances, the instruction approximation circuitry 124 uses Figure 1 The processor specific instructions 120 determine the opcode and / or operands of the machine instruction.

[0148] Figure 1 The group construction circuitry 126 of the compiler 108 converts the list of machine instructions into instruction groups. (Block 620). In some examples, the group manager circuitry 152 adds additional bits and / or combines one or more machine instructions to form an instruction group. In such examples, the additional bits allow the compiler circuitry 108 to encode additional information into the one or more machine instructions.

[0149] Figure 1 The branch detection circuitry 132 of the instruction grouping determines whether there are any branch instructions in the instruction grouping. (Block 625) In some examples, the branch detection circuitry 132 determines whether any of the opcodes of the machine instructions from the grouping circuitry 126 corresponds to a branch operation.

[0150] If branch detection circuitry 132 determines that a branch instruction is present in the instruction group (e.g., block 625 returns a “yes” result), branch detection circuitry 132 selects one of the branch instructions. (Block 630). In some examples, branch detection circuitry 132 receives machine instructions sequentially from instruction approximation circuitry 124. In such examples, branch detection circuitry 132 processes branch instructions from instruction approximation circuitry 124 sequentially.

[0151] Branch detection circuitry 132 determines whether the branch instruction is conditional. (Block 635). In some examples, branch detection circuitry 132 determines whether the opcode of the branch instruction corresponds to a conditional operation. For example, whether the branch is taken depends on a flag set by a previous machine instruction. Branch detection circuitry 132 determines that the branch instruction is conditional when the branch instruction depends on the operation of the previous machine instruction.

[0152] If the branch detection circuitry 132 determines that the branch instruction is conditional (eg, block 635 returns a “yes” result), then Figure 1 The flag checking circuitry 136 of the branch detection circuitry 132 determines which flag(s) correspond to the condition. (Block 640). In some examples, the branch detection circuitry 132 uses the opcode of the machine instruction to determine which flag(s) to check in response to the conditional branch instruction. In such examples, the flag identifies the result of a previous operation.

[0153] The flag checking circuitry 136 determines whether any of the reference number of instruction groups preceding the branch instruction is capable of adjusting the flag. (Block 645). In some examples, the flag checking circuitry 136 accesses Figure 1 In such an example, the flag checking circuitry 136 uses the opcode of the machine instruction of the instruction packet to determine whether a reference number of instruction packets executed prior to the branch instruction can adjust any flags that pass the conditional check of the branch instruction.

[0154] If the flag checking circuitry 136 determines that one or more of the previous three machine instructions are capable of adjusting flags (e.g., block 645 returns a “yes” result), the flag checking circuitry 136 adds a no-operation (NoOp) instruction group after the determined instruction. (Block 650). In some examples, the flag checking circuitry 136 adds one or more no-operation instruction groups after the determined instruction in the instruction buffer circuitry 144 that is capable of adjusting flags. In such an example, the flag checking circuitry 136 adds one or more no-operation instruction groups to ensure that a reference number of instruction groups that do not adjust the flags checked by the conditional branch instruction will be executed after the conditional branch instruction. Advantageously, the flag checking circuitry 136 ensures that branch instructions can be reordered by the reference number of instruction groups without affecting the conditional operation of the branch operation.

[0155] If the branch detection circuitry 132 determines that the branch instruction is an unconditional branch instruction (e.g., block 635 returns a “no” result), the flag checking circuitry 136 determines that none of the reference number of instruction packets preceding the original location of the conditional branch instruction is capable of adjusting the flag of the conditional branch instruction (e.g., block 635 returns a “no” result), or control continues from block 650, then Figure 1 The branch relocation circuitry 140 of the programmable circuitry 205 reorders the branch instruction to execute before a reference number of instruction packets immediately preceding the branch instruction. (Block 655). In some examples, the branch relocation circuitry 140 reorders the branch instruction before a reference number of instructions immediately preceding the original location of the branch instruction (which may include one or more no-op instruction packets) in the instruction buffer circuitry 144. For example, the branch relocation circuitry 140 may reorder the branch instruction packet and three previous instructions including any no-op instruction packets to adjust the execution order of the instruction packets. Advantageously, the programmable circuitry 205 preemptively reorders the branch instruction packet to begin execution before the reference number of instruction packets in response to adjusting the order of the branch instructions.

[0156] The branch detection circuitry 132 determines whether there are more branch instructions in the instruction grouping. (Block 660). In some examples, the branch detection circuitry 132 continues to examine the opcode of the machine instruction from the instruction approximation circuitry 124 to determine whether the machine instruction is a branch instruction. If the branch detection circuitry 132 determines that all branch instructions of the instruction grouping have not been examined (e.g., block 660 returns a “yes” result), control continues to return to block 630.

[0157] If the branch detection circuitry 132 determines that there are no branch instructions in the instruction group (e.g., block 625 returns a “no” result) or the branch detection circuitry 132 determines that all branch instructions of the instruction group have been checked (e.g., block 660 returns a “no” result), then Figure 1 The memory writing circuit system 148 writes the instruction group into the memory. (Operation 665). Figure 7 An example operation of the memory write circuitry 148 is shown and further described. Control continues to end.

[0158] Although reference Figure 6 The flowchart shown in describes an example method, but many other methods of implementing compiler circuit system 108 may be used instead according to the present description. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0159] Figure 7 Yes means Figure 6 Example machine readable instructions and / or a flowchart of example operations 665, which may be used Figure 1 The memory write circuitry 148 and / or more generally Figure 1 to execute, instantiate and / or perform an exemplary programmable circuitry implementation of the compiler circuitry 108 to convert Figure 6 A list of machine-readable instructions is placed in a memory (e.g., Figure 1 , 2 , 3 and / or 4 in memory 168, 330, 418).

[0160] Example operations 665 begin at block 710 when: Figure 1 The packet manager circuitry 152 of the instruction packet determines whether the instruction packet contains a branch instruction. (Block 710) In some examples, the packet manager circuitry 152 uses the opcode of the machine instruction of the instruction packet to determine whether the operation of the machine instruction corresponds to a branch operation.

[0161] If the packet manager circuitry 152 determines that the machine instructions of the instruction packet include a branch instruction (e.g., block 710 returns a “yes” result), the branch packet controller circuitry 156 determines whether the branch instruction is a delayed branch instruction. (Block 715). In some examples, the branch packet controller circuitry 156 determines whether the delay bit (e.g., Figure 5 The delay bit 540 of the programmable circuit system 205 determines whether the branch operation is identified as a non-delayed branch instruction or one of the single blocks of memory reads. For example, when the delay bit is the default value, the reference number of instruction packets after the branch instruction have been stored in one of the instruction buffer circuit systems 215, 220. In such an instance, the reference number of instruction packets after the branch instruction may not yet be stored in one of the instruction buffer circuit systems 215, 220. However, the read command corresponding to the single block may have been sent to the memory. In such an instance, after the current cycle, the reference number of instruction packets after the branch instruction will be stored in one of the instruction buffer circuit systems 215, 220. In other instances, when the delay bit is the default value, the programmable circuit system 205 stops the execution of the instruction until the time when the branch instruction can be executed.

[0162] If the branch packet controller circuitry 156 determines that the branch instruction is a conditional branch instruction (e.g., block 715 returns a “yes” result), the packet manager circuitry 152 determines the length of the reference number of instruction packets following the branch instruction. (Block 720). In some examples, the branch packet controller circuitry 156 stores the branch instruction packets in Figure 1The memory block buffer circuit system 164 of the embodiment of the present invention provides the address of the branch instruction group to the memory block buffer circuit system 164 of the embodiment of the present invention. Figure 1 The delay encoder circuit system 160 of the embodiment of the present invention is provided. In such an example, the packet manager circuit system 152 determines the length of the reference number of instruction packets after the branch instruction packet in response to the difference between the stored address and the address after adding the reference number of instruction packets. The packet manager circuit system 152 stores the determined instruction packet in the memory block buffer circuit system 164 after the branch instruction packet.

[0163] The delay encoder circuit system 160 determines the number of memory blocks that contain the branch instruction grouping and the reference number of instruction groups after the branch instruction. (Block 725). In some examples, the delay encoder circuit system 160 determines the number of memory blocks that contain the branch instruction grouping and the reference number of instruction groups after the branch instruction in response to the starting address of the branch instruction grouping and the ending address of the reference number of instruction groups. In such an example, the delay encoder circuit system 160 determines the number of memory blocks that contain the determined address.

[0164] Delay encoder circuitry 160 sets the delay bit of the branch instruction packet based on the number of memory blocks. (Block 730). In some examples, delay encoder circuitry 160 sets the delay bit to one of four states based on the number of determined memory blocks containing the branch instruction packet and three subsequent instruction packets. In such examples, the state of the delay bit represents the number of memory blocks to be acquired before acquiring the instruction at the address specified by the branch instruction. Advantageously, the delay bit ensures that programmable circuitry 205 acquires the three subsequent instruction packets before acquiring the instruction for the branch instruction.

[0165] If the branch packet controller circuitry 156 determines that the branch instruction is not a delayed branch instruction (e.g., block 715 returns a “no” result), the delay encoder circuitry 160 sets the delay bit of the branch instruction packet to a default value. (Block 735). In some examples, the delay encoder circuitry 160 does not adjust the delay bit of the branch instruction in response to determining that the branch instruction is a conditional branch.

[0166] If the packet manager circuitry 152 determines that the machine instructions of the instruction packet do not include a branch instruction (e.g., block 710 returns a “no” result) or control proceeds from blocks 730, 735, the memory block buffer circuitry 164 writes the instruction packet to memory. (Block 740). In some examples, the memory block buffer circuitry 164 writes the instruction packet to memory. Figure 1 The instruction groups 176 and 180 are written Figure 1 The first memory block 172 is configured as follows.

[0167] The packet manager circuitry 152 determines whether all instruction packets are in memory. (Block 745). In some examples, the packet manager circuitry 152 determines that all instruction packets are in memory 168 in response to the instruction buffer circuitry 144 being empty. If the packet manager circuitry 152 determines that all instruction packets are in memory (e.g., block 745 returns a "yes" result), control proceeds to return.

[0168] If the packet manager circuitry 152 determines that not all instruction packets are in memory (eg, block 745 returns a “no” result), the packet manager circuitry 152 selects another instruction packet. (Block 750 ). Control continues back to block 710 .

[0169] Although reference Figure 7 The flowchart shown in 140 describes an example method, but many other methods of implementing the memory write circuit system 148 may be used instead according to the present description. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0170] Fig. 8A and 8B Form means you can use Figure 2 The example machine readable instructions and / or flowchart of the example operation 800 are executed, instantiated and / or performed by the example implementation of the programmable circuit system 205. The example operation 800 begins at block 804, at which time, Figure 2 The address generation circuit system 250 starts to fetch instructions. In some examples, the address generation circuit system 250 checks Figure 2 The buffer controller circuitry 255 is used to determine Figure 2 In such an example, the address generation circuitry 250 detects whether one of the instruction buffer circuitry 215, 220 is capable of storing a memory block. Figure 1 and 2 Whether the memory blocks 172, 184, 192 contain instruction groups.

[0171] The address generation circuitry 250 generates an address associated with the instruction packet to request a memory block from the memory. (Block 808). In some examples, the address generation circuitry 250 generates a read command including a memory address of one of the memory blocks 172, 184, 192. In such an example, the address generation circuitry 250 generates a read command in response to the instruction packet being sent to the memory block. Figure 1 The memory 168 provides a read command requesting one of the memory blocks 172, 184, 192.

[0172] The memory 168 stores the memory block in the first instruction buffer. (Block 812). In some examples, the buffer controller circuitry 255 configures the demultiplexer circuitry 210 to store the memory block in the first instruction buffer. Figure 2 The first instruction buffer circuitry 215 is coupled to the memory 168. In such an example, the memory 168 provides one of the memory blocks 172, 184, 192 to the first instruction buffer circuitry 215 in response to a read command.

[0173] Figure 2 The decoder circuitry 235 of the first instruction buffer decodes one or more instruction packets from the memory block in the first instruction buffer. (Block 816). In some examples, the buffer controller circuitry 255 Figure 2 The multiplexer circuitry 225 is configured to couple the first instruction buffer circuitry 215 to the decoder circuitry 235. In such an example, the decoder circuitry 235 decodes one of the memory blocks 172, 184, 192 to determine Figure 1 and 2 One of instruction groups 176, 180, 188, 196.

[0174] Figure 2 The execution circuitry 240 of the instruction grouping determines whether the instruction grouping has a branch instruction. (Block 820) In some examples, the execution circuitry 240 uses the opcode of the machine instruction of one of the instruction groups 176, 180, 188, 196 to determine whether the operation of the machine instruction corresponds to a branch operation.

[0175] If execution circuitry 240 determines that the instruction group does have a branch instruction (e.g., block 820 returns a “yes” result), execution circuitry 240 determines whether the branch instruction is unconditional or conditional and will be taken. (Block 824). In some examples, execution circuitry 240 determines whether to instantiate Figure 2 In such an example, the execution circuitry 240 instantiates the discontinuity controller circuitry 245 in response to executing the branch operation.

[0176] If execution circuitry 240 determines that the instruction grouping does not have a branch instruction (e.g., block 820 returns a "no" result), or execution circuitry 240 determines that the branch instruction is a conditional instruction that is not executed (e.g., block 824 returns a "no" result), execution circuitry 240 executes the machine instructions in one or more instruction groups. (Block 828). In some examples, execution circuitry 240 instantiates circuitry to perform the operation of the machine instruction. In such examples, the opcode of the machine instruction adjusts execution circuitry 240 to instantiate the circuitry, and the operands configure the inputs and / or outputs of the instantiated circuitry. For example, the operands may specify the location of input data and / or the location where outputs are stored.

[0177] The address generation circuitry 250 determines whether the first instruction buffer is full. (Block 832). In some examples, the buffer controller circuitry 255 determines whether the first instruction buffer circuitry 215 can store an additional one of the memory blocks 172, 184, 192. In such examples, the address generation circuitry 250 receives an indication from the buffer controller circuitry 255 specifying whether the first instruction buffer circuitry 215 is full.

[0178] If the address generation circuitry 250 determines that the first instruction buffer is not full (e.g., block 832 returns a “yes” result), the address generation circuitry 250 fetches another memory block from the memory to the first instruction buffer. (Block 836). In some examples, the address generation circuitry 250 provides another read command with the address of another of the memory blocks 172, 184, 192 to the memory 168. In such an example, the memory 168 stores the other of the memory blocks 172, 184, 192 in the first instruction buffer circuitry 215.

[0179] If the address generation circuitry 250 determines that the first instruction buffer is full (e.g., block 832 returns a "no" result) or control proceeds from block 836, the decoder circuitry 235 decodes one or more instruction packets from the memory block in the first instruction buffer. (Block 840). In some examples, the decoder circuitry 235 decodes another of the memory blocks 172, 184, 192 to determine another of the instruction packets 176, 180, 188, 196. Control proceeds to return to block 820.

[0180] Now go to Figure 8B If the execution circuit system 240 determines that the branch instruction is an unconditional instruction or a conditional instruction that is taken (eg, block 824 returns a "yes" result), then Figure 2The discontinuity controller circuitry 245 of the embodiment determines the number of memory blocks to be acquired before taking the branch. (Block 844). In some examples, the execution circuitry 240 instantiates the discontinuity controller circuitry 245 in response to the branch instruction from the decoder circuitry 235. In such examples, the discontinuity controller circuitry 245 determines the number of memory blocks to be acquired before acquiring from the branch location in response to the delay bit. For example, a first state of the delay bit (e.g., 0x0) corresponds to acquiring one of the memory blocks 172, 184, 192, and a second state of the delay bit (e.g., 0x1) corresponds to acquiring two of the memory blocks 172, 184, 192.

[0181] The discontinuity controller circuitry 245 determines whether the memory block is in the first instruction buffer. (Block 848). In some examples, the buffer controller circuitry 255 identifies which of the memory blocks 172, 184, 192 are in the first instruction buffer circuitry 215. In other examples, the buffer controller circuitry 255 identifies a plurality of memory blocks 172, 184, 192 stored in the first instruction buffer circuitry 215. In both examples, the discontinuity controller circuitry 245 determines whether the determined number of memory blocks are in the first instruction buffer circuitry 215.

[0182] If the discontinuity controller circuitry 245 determines that the memory block is not in the first instruction buffer (e.g., block 848 returns a "no" result), the address generation circuitry 250 generates another address associated with another instruction packet to request another memory block from the memory. (Block 852). In some examples, the address generation circuitry 250 generates a read command including a memory address of one of the memory blocks 172, 184, 192. In such an example, the address generation circuitry 250 requests one of the memory blocks 172, 184, 192 in response to providing the read command to the memory 168.

[0183] The memory 168 stores the memory block in the first instruction buffer. (Block 856) In some examples, the memory 168 provides one of the memory blocks 172, 184, 192 to the first instruction buffer circuitry 215 in response to the read command.

[0184] If the discontinuity controller circuitry 245 determines that the memory block is in the first instruction buffer (e.g., block 848 returns a "yes" result) or control proceeds from block 856, the decoder circuitry 235 decodes one or more instruction packets from the memory block in the first instruction buffer to determine another instruction packet. (Block 860). In some examples, the decoder circuitry 235 decodes one of the memory blocks 172, 184, 192 to determine one of the instruction packets 176, 180, 188, 196.

[0185] Execution circuitry 240 executes the machine instruction of the instruction group. (Block 864). In some examples, execution circuitry 240 instantiates circuitry to perform the operation of the machine instruction. In such examples, the opcode of the machine instruction adjusts execution circuitry 240 to instantiate the circuitry, and the operands configure the inputs and / or outputs of the instantiated circuitry.

[0186] The discontinuity controller circuit system 245 determines whether it is possible to start fetching instruction packets at the branch location. (Block 868). In some examples, the buffer controller circuit system 255 identifies which of the memory blocks 172, 184, 192 are in the first instruction buffer circuit system 215. In other examples, the buffer controller circuit system 255 identifies multiple memory blocks 172, 184, 192 stored in the first instruction buffer circuit system 215. In both examples, the discontinuity controller circuit system 245 determines whether the determined number of memory blocks are in the first instruction buffer circuit system 215. For example, the discontinuity controller circuit system 245 determines that the number of memory blocks in the first instruction buffer circuit system 215 contains the required instruction packets in response to one of the fields of the branch instruction. In such an example, the branch instruction may have a first field containing an opcode and a second field containing a branch location. If the discontinuity controller circuit system 245 determines that more memory blocks are needed to continue execution from the first instruction buffer (e.g., block 868 returns a "no" result), control continues to block 852.

[0187] If the discontinuity controller circuitry 245 determines that the memory block required to continue execution from the first instruction buffer is in the first instruction buffer (e.g., block 868 returns a "yes" result), the address generation circuitry 250 generates another address associated with the branch instruction to request the memory block at the branch location. (Block 872). In some examples, the address generation circuitry 250 generates a read command including the branch target address from the discontinuity controller circuitry 245. In such an example, the address generation circuitry 250 requests one of the memory blocks 172, 184, 192 at the branch target address in response to providing the read command to the memory 168.

[0188] The memory 168 stores the memory block in the second instruction buffer. (Block 876). In some examples, the buffer controller circuitry 255 configures the demultiplexer circuitry 210 to store the memory block in the second instruction buffer. Figure 2 The second instruction buffer circuitry 220 is coupled to the memory 168. In such an example, the memory 168 provides one of the memory blocks 172, 184, 192 to the second instruction buffer circuitry 220 in response to a read command.

[0189] The decoder circuitry 235 decodes one or more instruction groups from the memory block in the first instruction buffer. (Block 880) In some examples, the decoder circuitry 235 decodes one of the memory blocks 172, 184, 192 to determine another of the instruction groups 176, 180, 188, 196.

[0190] The execution circuit system 240 executes the machine instruction of the instruction group. (Block 884). In some instances, the execution circuit system 240 instantiates the circuit system to perform the operation of the machine instruction. In such an instance, the opcode of the machine instruction adjusts the execution circuit system 240 to instantiate the circuit system, and the operand configures the input and / or output of the instantiated circuit system. In some instances, the execution circuit system 240 determines that the execution of the branch instruction is completed in response to the decoder circuit system 235 decoding the last instruction group of the reference number of instruction groups after the branch instruction. For example, the execution circuit system 240 receives the final instruction that the decoder circuit system 235 has decoded from the first instruction buffer circuit system 215 before decoding the instruction group from the second instruction buffer circuit system 220. Such an example operation occurs Figure 3C The ninth cycle 368 period.

[0191] Figure 2The decoder circuitry 235 of the second instruction buffer decodes one or more instruction packets from the memory block in the second instruction buffer. (Block 888). In some examples, the buffer controller circuitry 255 configures the multiplexer circuitry 225 to couple the second instruction buffer circuitry 220 to the decoder circuitry 235. In such an example, the decoder circuitry 235 decodes one of the memory blocks 172, 184, 192 to determine one of the instruction packets 176, 180, 188, 196.

[0192] Programmable circuit system 205 continues to use the second instruction buffer to fetch, decode, and execute the branch instruction. (Block 892). In some examples, programmable circuit system 205 uses second instruction buffer circuit system 220 to perform the operations of blocks 808, 812, 816, 820, 824, 828, 832, 836, 840. In such examples, programmable circuit system 205 may repeat the operations of blocks 844, 848, 852, 856, 860, 864, 868, 872, 876, 880, 884, 888 in response to another branch instruction. Control continues to return to block 808.

[0193] Although reference Fig. 8A and 8B The flowchart shown in describes an example method, but many other methods of implementing the programmable circuit system 205 may be used instead according to the present description. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, between, or after the blocks shown in the illustrated example.

[0194] Despite Figure 1 and / or 2 shows the implementation Figure 1 The compiler circuitry 108 and / or Figure 2 Example of programmable circuit system 205, but Figure 1 One or more of the elements, processes and / or devices shown in and / or 2 may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other manner. In addition, the operation determination circuit system 112, the instruction approximation circuit system 124, the branch sorting circuit system 128, the branch detection circuit system 132, the flag checking circuit system 136, the branch relocation circuit system 140, the instruction buffer circuit system 144, the memory write circuit system 148, the packet manager circuit system 152, the branch packet controller circuit system 156, the delay encoder circuit system 160, the memory block buffer circuit system 164, and / or more generally Figure 1compiler circuitry 108, discontinuity controller circuitry 245, buffer controller circuitry 255, address generation circuitry 250, and / or most generally Figure 2 Programmable circuitry 205 may be implemented by hardware alone or by hardware in combination with software and / or firmware. Thus, for example, operation determination circuitry 112, instruction approximation circuitry 124, branch ordering circuitry 128, branch detection circuitry 132, flag checking circuitry 136, branch relocation circuitry 140, instruction buffer circuitry 144, memory write circuitry 148, packet manager circuitry 152, branch packet controller circuitry 156, delay encoder circuitry 160, memory block buffer circuitry 164, and / or more generally Figure 1 compiler circuitry 108, discontinuity controller circuitry 245, buffer controller circuitry 255, address generation circuitry 250, and / or most generally Figure 2 Any of the programmable circuit systems 205 may be implemented by programmable circuit systems in combination with machine-readable instructions (e.g., firmware or software), processor circuit systems, analog circuits, digital circuits, logic circuits, programmable processors, programmable microcontrollers, graphics processing units (GPUs), digital signal processors (DSPs), ASICs, programmable logic devices (PLDs), and / or field programmable logic devices (FPLDs) such as FPGAs. Figure 1 and / or as shown in 2 Figure 1 The compiler circuitry 108 and / or Figure 2 The programmable circuit system 205 may include in addition to Figure 1 and / or 2 may include one or more elements, processes and / or devices in addition to or in place of the elements, processes and / or devices shown, or may include more than one of any or all of the elements, processes and devices shown.

[0195] Figure 6 , 7 , 8A and 8B show that the programmable circuit system can be used to implement and / or instantiate Figure 1 The compiler circuitry 108 and / or Figure 2 The example machine-readable instructions and / or representations of the programmable circuit system 205 may be executed by the programmable circuit system to implement and / or instantiate Figure 1 The compiler circuitry 108 and / or Figure 2 The machine-readable instructions may be instructions for programmable circuit system (e.g., as described below in conjunction with Fig. 9The programmable circuit system 912 shown in the example processor platform 900 discussed above may be executed by one or more executable programs or portions of one or more executable programs, and / or may be described below in conjunction with Fig. 9 In some examples, machine-readable instructions cause operations, tasks, etc. to be performed and / or carried out in an automated manner in the real world. As used herein, "automatically" means without human intervention.

[0196] The program may be embodied in instructions (e.g., software and / or firmware) stored on one or more non-transitory computer-readable and / or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or optical disks (e.g., Blu-ray disks, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, ROMs, solid-state drives (SSDs), SSD memories, non-volatile memories (e.g., electrically erasable programmable read-only memories (EEPROMs), flash memories, etc.), volatile memories (e.g., any type of random access memories (RAMs), etc.), and / or any other storage devices or storage disks. The instructions of the non-transitory computer-readable and / or machine-readable media may be programmed and / or executed by programmable circuit systems located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed and / or instantiated and / or embodied in dedicated hardware by one or more hardware devices other than programmable circuit systems. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, a client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. Furthermore, although reference is made to Figure 6 , 7 , 8A and / or 8B describe example procedures, but may alternatively be implemented using Figure 1 The compiler circuitry 108 and / or Figure 2Many other methods of the programmable circuit system 205 of the present invention. For example, the execution order of the blocks of the flowchart can be changed, and / or some of the blocks described can be changed, eliminated or combined. In addition or alternatively, any or all of the blocks of the flowchart can be implemented by one or more hardware circuits (e.g., processor circuit systems, discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform corresponding operations without running software or firmware. The programmable circuit system can be distributed in different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPUs, etc.). For example, the programmable circuit system can be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit system (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed on multiple servers in a server rack, multiple processors distributed on one or more server racks, etc., and / or any combination thereof.

[0197] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bit stream (e.g., a computer-readable bit stream, a machine-readable bit stream, etc.), etc.) or a data structure (e.g., a portion of an instruction, a code, a representation of a code, etc.), which may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, and / or computing devices (e.g., servers) located in the same or different locations of a network or collection of networks (e.g., in the cloud, an edge device, etc.). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, decapsulation, distribution, redistribution, compilation, etc., in order to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and / or stored on separate computing devices, wherein the portions, when decrypted, decompressed, and / or combined, form a set of computer-executable and / or machine-executable instructions that implement one or more functions and / or operations that may together form, for example, the procedures described herein.

[0198] In another example, the machine-readable instructions may be stored in a state in which they can be read by the programmable circuit system, but a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., may need to be added in order to execute the machine-readable instructions on a particular computing device or another device. In another example, the machine-readable instructions and / or corresponding programs may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before they can be executed in whole or in part. Therefore, as used herein, machine-readable, computer-readable and / or machine-readable media may contain instructions and / or programs regardless of the specific format or state of the machine-readable instructions and / or programs.

[0199] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0200] As mentioned above, Figure 6 , 7The example operations of 8A and / or 8B may be implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media are expressly defined to include any type of computer-readable storage device and / or storage disk, and exclude propagating signals and exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage devices or storage disks, where information is stored for any duration (e.g., for an extended period of time, permanently, temporarily, temporarily buffered, and / or cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, and / or electrical) hardware to retain information over a period of time, but exclude propagating signals and exclude transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuit system, which may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or is manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0201] Fig. 9 is structured to execute and / or instantiate Figure 6 , 7 , 8A and / or 8B example machine readable instructions and / or example operations to implement Figure 1 The compiler circuitry 108 and / or Figure 2 205 of the programmable circuit system 205. The programmable circuit system platform 900 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, such as an iPad TMtablet computer), personal digital assistant (PDA), Internet appliance, DVD player, CD player, digital video recorder, Blu-ray player, game console, personal video recorder, set-top box, headsets (e.g., augmented reality (AR) headsets, virtual reality (VR) headsets, etc.) or other wearable devices, or any other type of computing and / or electronic device.

[0202] The programmable circuit system platform 900 of the illustrated example includes a programmable circuit system 912. The programmable circuit system 912 of the illustrated example is hardware. For example, the programmable circuit system 912 may be implemented by one or more integrated circuit systems, logic circuit systems, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit system 912 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 912 implements Figure 1 operation determination circuitry 112, instruction approximation circuitry 124, branch ordering circuitry 128, branch detection circuitry 132, flag checking circuitry 136, branch relocation circuitry 140, instruction buffer circuitry 144, memory write circuitry 148, packet manager circuitry 152, branch packet controller circuitry 156, delay encoder circuitry 160, memory block buffer circuitry 164, and / or more generally compiler circuitry 108; Figure 2 discontinuity controller circuitry 245 , buffer controller circuitry 255 , address generation circuitry 250 , and / or more generally programmable circuitry 205 .

[0203] The programmable circuit system 912 of the illustrated example includes a local memory 913 (e.g., cache, registers, etc.). The programmable circuit system 912 of the illustrated example communicates with a main memory 914, 916 via a bus 918, wherein the main memory includes a volatile memory 914 and a non-volatile memory 916. The volatile memory 914 may be composed of a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 916 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memories 914, 916 of the illustrated example is controlled by a memory controller 917. In some examples, the memory controller 917 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data to and from the main memories 914, 916.

[0204] The programmable circuit system platform 900 of the illustrated example also includes an interface circuit system 920. The interface circuit system 920 can be implemented by hardware that complies with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0205] In the example shown, one or more input devices 922 are connected to the interface circuitry 920. The input devices 922 allow a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuitry 912. The input devices 922 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isochronous device, and / or a voice recognition system.

[0206] One or more output devices 924 are also connected to the interface circuit system 920 of the illustrated example. The output device 924 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switch (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Therefore, the interface circuit system 920 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit system such as a GPU.

[0207] The interface circuitry 920 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate the exchange of data with external machines (e.g., any kind of computing device) over the network 926. Communications may occur over, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, and the like.

[0208] The programmable circuit system platform 900 of the illustrated example also includes one or more mass storage disks or devices 928 to store firmware, software and / or data. Examples of such mass storage disks or devices 928 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0209] can be Figure 6 , 7, 8A and / or 8B may be stored in the mass storage device 928, in the volatile memory 914, in the non-volatile memory 916 and / or on at least one non-transitory computer-readable storage medium such as a CD or DVD that may be removable.

[0210] Fig.10 yes Fig. 9 912 of the programmable circuit system. In this example, Fig. 9 The programmable circuit system 912 is implemented by the microprocessor 1000. For example, the microprocessor 1000 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit system). The microprocessor 1000 executes Figure 6 , 7 , 8A and / or 8B of the machine readable instructions to effectively Figure 1 The circuit system of and / or 2 is instantiated as a logic circuit for performing operations corresponding to those machine-readable instructions. In some such instances, Figure 1 The compiler circuitry 108 and / or Figure 2 The programmable circuit system 205 is instantiated by the hardware circuits of the microprocessor 1000 in combination with machine-readable instructions. For example, the microprocessor 1000 may be implemented by a multi-core hardware circuit system such as a CPU, DSP, GPU, XPU, etc. Although the microprocessor may include any number of example cores 1002 (for example, 1 core), the microprocessor 1000 of this example is a multi-core semiconductor device including N cores. The cores 1002 of the microprocessor 1000 may operate independently or may cooperate to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the cores 1002, or may be executed by multiple of the cores 1002 at the same or different times. In some instances, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores 1002. The software program may correspond to a thread executed by Figure 6 , 7 , 8A and / or 8B represent part or all of the machine-readable instructions and / or operations.

[0211] The cores 1002 can communicate via a first example bus 1004. In some examples, the first bus 1004 can be implemented by a communication bus to enable communications associated with one or more of the cores 1002. For example, the first bus 1004 can be implemented by at least one of an interconnect integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1004 can be implemented by any other type of computing or electrical bus. The cores 1002 can obtain data, instructions, and / or signals from one or more external devices via an example interface circuit system 1006. The cores 1002 can output data, instructions, and / or signals to one or more external devices via the interface circuit system 1006. Although the cores 1002 of this example include example local memory 1020 (e.g., a level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor 1000 also includes example shared memory 1010 (e.g., a level 2 (L2 cache)) that may be shared by the cores for high-speed access to data and / or instructions. Data and / or instructions may be transferred (e.g., shared) by writing to and / or reading from the shared memory 1010. The local memory 1020 and the shared memory 1010 of each of the cores 1002 may be a plurality of levels of cache memory and a main memory (e.g., Fig. 9 The cache memory is part of a storage device hierarchy of main memory 914, 916 of the main memory 914, 916. Generally, higher level memory in the hierarchy exhibits shorter access times and has smaller storage capacity than lower level memory. Changes to various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0212] Each core 1002 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit system. Each core 1002 includes a control unit circuit system 1014, an arithmetic and logic (AL) circuit system (sometimes referred to as an ALU) 1016, a plurality of registers 1018, a local memory 1020, and a second example bus 1022. Other structures may exist. For example, each core 1002 may include a vector unit circuit system, a single instruction multiple data (SIMD) unit circuit system, a load / store unit (LSU) circuit system, a branch / jump unit circuit system, a floating point unit (FPU) circuit system, etc. The control unit circuit system 1014 includes a semiconductor-based circuit structured to control (e.g., coordinate) data movement within the corresponding core 1002. The AL circuit system 1016 includes a semiconductor-based circuit structured to perform one or more mathematical and / or logical operations on data within the corresponding core 1002. The AL circuit system 1016 of some instances performs integer-based operations. In other examples, AL circuitry 1016 also performs floating point operations. In still other examples, AL circuitry 1016 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating point operations. In some examples, AL circuitry 1016 may be referred to as an arithmetic logic unit (ALU).

[0213] Registers 1018 are semiconductor-based structures for storing data and / or instructions, such as the results of one or more operations performed by the AL circuit system 1016 of the corresponding core 1002. For example, registers 1018 may include vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Registers 1018 may be as follows: Fig.10 The registers 1018 are shown arranged in a bank. Alternatively, the registers 1018 may be organized in any other arrangement, format, or structure, such as by being distributed throughout the core 1002 to reduce access time. The second bus 1022 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0214] Each core 1002 and / or more generally the microprocessor 1000 may include additional and / or alternative structures to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common grid stops (CMSs), one or more shifters (e.g., barrel shifters), and / or other circuitry. The microprocessor 1000 is fabricated to include a semiconductor device having many interconnected transistors to implement the structures described above in one or more integrated circuit systems (ICs) contained in one or more packages.

[0215] The microprocessor 1000 may include and / or collaborate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some instances, the accelerator is implemented by a logic circuitry to perform certain tasks faster and / or more efficiently than can be performed by a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those described herein. GPUs, DSPs, and / or other programmable devices may also be accelerators. The accelerator may be on board the microprocessor 1000, in the same chip package as the microprocessor 1000, and / or in one or more packages separate from the microprocessor 1000.

[0216] Fig.11 yes Fig. 9 1 is a block diagram of another example embodiment of programmable circuit system 912. In this example, programmable circuit system 912 is implemented by FPGA circuit system 1100. For example, FPGA circuit system 1100 can be implemented by an FPGA. FPGA circuit system 1100 can be used, for example, to perform operations that might otherwise be performed by executing corresponding machine-readable instructions. Fig.10 However, once configured, FPGA circuitry 1100 instantiates operations and / or functions corresponding to machine-readable instructions in hardware, and thus can typically perform operations / functions more quickly than if the operations / functions could be performed by a general-purpose microprocessor executing corresponding software.

[0217] More specifically, as described above Fig.10 The microprocessor 1000 (which can be programmed to execute Figure 6 , 7 , 8A and / or 8B, but whose interconnections and logic circuitry are fixed once manufactured. Fig.11 The FPGA circuit system 1100 of the example includes interconnects and logic circuit systems, which can be configured, structured, programmed and / or interconnected in different ways after manufacturing to instantiate, for example, Figure 6 ,7 , 8A, and / or 8B. Specifically, FPGA circuit system 1100 can be considered as an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected through the interconnects, effectively forming one or more dedicated logic circuits (unless and until FPGA circuit system 1100 is reprogrammed). The logic circuits are configured so that the logic gates can cooperate in different ways to perform different operations on the data received by the input circuit system. The operations may correspond to the operations performed by Figure 6 , 7 , 8A and / or 8B. Thus, FPGA circuit system 1100 can be configured and / or structured to effectively communicate with Figure 6 , 7 , 8A and / or 8B are instantiated as dedicated logic circuits to perform the operations / functions corresponding to those software instructions in a dedicated manner similar to an ASIC. Thus, the FPGA circuit system 1100 can be executed with a general-purpose microprocessor. Figure 6 , 7 , 8A and / or 8B to perform the operations / functions faster than some or all of the operations / functions corresponding to the machine-readable instructions.

[0218] exist Fig.11 In some instances, the FPGA circuit system 1100 is configured and / or structured in response to being programmed (and / or reprogrammed one or more times) based on a binary file. In some instances, a binary file can be compiled and / or generated based on instructions in a hardware description language (HDL) such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions in the HDL; the code / program can be translated into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) can be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some instances, Fig.11 The FPGA circuit system 1100 can access and / or load binary files to make Fig.11 The FPGA circuit system 1100 is configured and / or structured to perform one or more operations / functions. For example, the FPGA circuit system 1100 can be ... Fig.11The FPGA circuit system 1100 can access the machine-readable instruction implementation binary file to enable Fig.11 Configuration and / or structuring of FPGA circuit system 1100 or a portion thereof.

[0219] In some instances, the binary file is compiled, generated, converted, and / or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform may translate a first instruction (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into a second instruction corresponding to one or more operations / functions in an HDL. In some such instances, the binary file is compiled, generated, and / or otherwise output from the unified software platform based on the second instruction. In some instances, Fig.11 The FPGA circuit system 1100 can access and / or load binary files to make Fig.11 The FPGA circuit system 1100 is configured and / or structured to perform one or more operations / functions. For example, the FPGA circuit system 1100 can be ... Fig.11 The FPGA circuit system 1100 can access the machine-readable instruction implementation binary file to enable Fig.11 Configuration and / or structuring of FPGA circuit system 1100 or a portion thereof.

[0220] Fig.11 The FPGA circuit system 1100 includes an example input / output (I / O) circuit system 1102 for obtaining data from and / or outputting data to an example configuration circuit system 1104 and / or external hardware 1106. For example, the configuration circuit system 1104 can be implemented by an interface circuit system, which can obtain a binary file that can be implemented by a bit stream, data, and / or machine-readable instructions to configure the FPGA circuit system 1100 or a portion thereof. In some such instances, the configuration circuit system 1104 can obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), etc. and / or any combination thereof. In some instances, the external hardware 1106 can be implemented by an external hardware circuit system. For example, the external hardware 1106 can be implemented by Fig.10 The microprocessor 1000 is implemented as shown.

[0221] FPGA circuitry 1100 also includes an array of example logic gate circuitry 1108, a plurality of example configurable interconnects 1110, and example storage circuitry 1112. Logic gate circuitry 1108 and configurable interconnects 1110 may be configured to instantiate Figure 6 , 7 , 8A and / or 8B and / or one or more operations / functions corresponding to at least some of the machine-readable instructions and / or other desired operations. Fig.11 The logic gate circuit system 1108 shown in is manufactured in the form of blocks or groups. Each block includes a semiconductor-based electrical structure that can be configured into a logic circuit. In some examples, the electrical structure includes a logic gate (e.g., an AND gate, an OR gate, a NOR gate, etc.) that provides a basic building block for the logic circuit. An electrically controlled switch (e.g., a transistor) is present in each of the logic gate circuit system 1108 to enable the electrical structure and / or logic gate to be configured to form a circuit system that performs the desired operation / function. The logic gate circuit system 1108 may include other electrical structures, such as a lookup table (LUT), a register (e.g., a flip-flop or a latch), a multiplexer, etc.

[0222] The configurable interconnect 1110 of the illustrated example is a conductive path, trace, via, etc. that may include electrically controlled switches (e.g., transistors), the state of which can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit systems 1108 to program the desired logic circuit.

[0223] The storage circuit system 1112 of the illustrated example is structured to store the results of one or more operations performed by corresponding logic gates. The storage circuit system 1112 may be implemented by registers, etc. In the illustrated example, the storage circuit system 1112 is distributed among the logic gate circuit system 1108 to facilitate access and increase execution speed.

[0224] Fig.11The example FPGA circuit system 1100 also includes an example special operation circuit system 1114. In this example, the special operation circuit system 1114 includes a special circuit system 1116, which can be called to implement commonly used functions, thereby avoiding the need to program those functions on site. Examples of such special circuit systems 1116 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory, and multiplier-accumulator circuit systems. There may be other types of special circuit systems. In some examples, the FPGA circuit system 1100 may also include an example general programmable circuit system 1118, such as an example CPU 1120 and / or an example DSP 1122. There may be other general programmable circuit systems 1118 that can be programmed to perform other operations, such as GPUs, XPUs, etc., in addition or alternatively.

[0225] although Fig. 9 and 10 Shows Fig. 9 Two example implementations of programmable circuitry 912 are shown, but many other approaches are contemplated. For example, the FPGA circuitry may include an onboard CPU, such as Fig.11 One or more of the example CPUs 1120. Thus, Fig. 9 The programmable circuit system 912 can also be configured by at least combining Fig.10 An example microprocessor 1000 and Fig.11 In some such hybrid examples, Fig.10 One or more cores 1002 may execute Figure 6 , 7 , 8A and / or 8B to perform a first operation / function, Fig.11 The FPGA circuit system 1100 may be configured and / or structured to perform the same as represented by Figure 6 , 7 , 8A and / or 8B, and / or the ASIC may be configured and / or structured to perform the second operation / function corresponding to the second portion of the machine readable instructions of the flowcharts 8A and / or 8B, and / or the ASIC may be configured and / or structured to perform the same as represented by Figure 6 , 7 , a third operation / function corresponding to a third portion of the machine-readable instructions of the flowcharts of 8A and / or 8B.

[0226] It should be understood that Figure 1 The compiler circuitry 108 and / or Figure 2 Some or all of the programmable circuitry 205 may thus be instantiated at the same or different times. For example, Fig.10The same and / or different portions of microprocessor 1000 may be programmed to execute portions of machine-readable instructions at the same and / or different times. In some examples, Fig.11 The same and / or different portions of FPGA circuit system 1100 may be configured and / or structured to perform operations / functions corresponding to portions of the machine-readable instructions at the same and / or different times.

[0227] In some instances, Figure 1 The compiler circuitry 108 and / or Figure 2 Some or all of the programmable circuit system 205 may be instantiated, for example, in one or more threads that execute simultaneously and / or serially. Fig.10 The microprocessor 1000 can execute machine-readable instructions in one or more threads of execution simultaneously and / or serially. In some examples, Fig.11 The FPGA circuit system 1100 can be configured and / or structured to perform operations / functions simultaneously and / or serially. In addition, in some examples, Figure 1 The compiler circuitry 108 and / or Figure 2 Some or all of the programmable circuitry 205 may be Fig.10 The system is implemented in one or more virtual machines and / or containers executed on the microprocessor 1000.

[0228] In some instances, Fig. 9 The programmable circuit system 912 may be in one or more packages. For example, Fig.10 The microprocessor 1000 and / or Fig.11 The FPGA circuit system 1100 can be in one or more packages. In some examples, the XPU can be composed of Fig. 9 The XPU may be implemented in a programmable circuit system 912, which may be in one or more packages. For example, the XPU may be included in a CPU (e.g., Fig.10 Microprocessor 1000, Fig.11 CPU 1120, etc.), a DSP in another package (e.g., Fig.11 DSP 1122 of ), a GPU in yet another package, and an FPGA in yet another package (e.g., Fig.11 FPGA circuit system 1100).

[0229] Although referred to above as software, the distributed "software" may alternatively be firmware.

[0230] "Include" and "comprising" (and all forms and tenses thereof) are used herein as open terms. Thus, whenever a claim uses any form of "include" or "comprising" (e.g., comprises, comprising, includes, including, having, etc.) as a guide or in any type of claim recitation, it should be understood that additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or reference. As used herein, when the phrase "at least" is used as a transitional term, such as in the guide of a claim, it is open in the same manner as the terms "include" and "comprising" are open. The term "and / or" when used in the form of, for example, A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein, the phrase "at least one of A and B" in the context of describing structures, components, items, objects, and / or things is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein, the phrase "at least one of A or B" in the context of describing structures, components, items, objects, and / or things is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein, the phrase "at least one of A and B" in the context of describing the performance or execution of a process, instruction, action, activity, etc. is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, the phrase "at least one of A or B" used herein in the context of describing the performance or execution of a process, instruction, action, activity, etc., means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0231] As used herein, singular references (e.g., "a / an", "first", "second", etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of the objects. The terms "a" (or an), "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed individually, multiple components, elements, or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different instances or claims, these features may be combined, and the inclusion in different instances or claims does not imply that a combination of features is not feasible and / or advantageous.

[0232] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the earth. A first part is above a second part if the second part has at least one portion between the earth and the first part. Likewise, as used herein, a first part is "below" a second part when the first part is closer to the earth than the second part. As mentioned above, a first part can be above or below a second part with one or more of the following: with other parts in between, without other parts in between, the first and second parts touching, or the first and second parts not in direct contact with each other.

[0233] As used in this patent, stating that any part (e.g., a layer, film, region, area, or plate) is in any way located on another part (e.g., located on, positioned on, disposed on, or formed on, etc.) indicates that the referenced part is in contact with the other part, or that the referenced part is above the other part with one or more intermediate parts positioned therebetween.

[0234] As used herein, unless otherwise indicated, connection references (e.g., attached, coupled, connected, and joined) may include intermediate components between elements referenced by the connection reference and / or relative movement between those elements. Thus, connection references do not necessarily infer that two elements are directly connected and / or in fixed relation to each other. As used herein, stating that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0235] Unless specifically stated otherwise, descriptors such as "first," "second," "third," etc., are used herein without any import or otherwise indicating any meaning of priority, physical order, arrangement in a list, and / or ordering, but are used merely as labels and / or arbitrary names to distinguish elements to facilitate understanding of the described examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to by a different descriptor (such as "second" or "third") in the claims. In such cases, it should be understood that such descriptors are only used to clearly identify these elements in the context of the discussion (such as in the claims), for example, where these elements might otherwise share the same name.

[0236] As used herein, "substantially" and "approximately" modify their subject matter / values ​​to recognize that there may be variations in real-world applications. For example, as will be understood by one of ordinary skill in the art, "approximately" and "about" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections. For example, unless otherwise specified herein, "approximately" and "about" may indicate that such dimensions may be within a tolerance range of + / - 10%.

[0237] As used herein, "substantially real time" means occurring in a near-instantaneous manner, recognizing that there may be delays in real-world computation time, transmission, etc. Therefore, unless otherwise specified, "substantially real time" means real time + 1 second.

[0238] As used herein, the phrase "communicate" includes variations thereof covering direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals and / or one-time events.

[0239] As used herein, "programmable circuitry" is defined as including: (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) that are structured to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that are programmed with instructions to perform specific functions and / or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as: a central processing unit (CPU), which can execute a first instruction to perform one or more operations and / or functions; a field programmable gate array (FPGA), which can be programmed with a second instruction so that the configuration and / or structuring of the FPGA will instantiate one or more operations and / or functions corresponding to the first instruction; a graphics processing unit (GPU), which can execute a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP), which can execute a first instruction to perform one or more operations and / or functions; an XPU; a network processing unit (NPU); one or more microcontrollers, which can execute a first instruction to perform one or more operations and / or functions; and / or an integrated circuit, such as an application specific integrated circuit (ASIC). For example, the XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc. and / or any combination thereof) and an orchestration technology (e.g., an application programming interface (API)), which may allocate computing tasks to programmable circuit systems among the multiple types of programmable circuit systems that are suitable and available for performing computing tasks.

[0240] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), etc.

[0241] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, C, such as: (a) only A; (b) only B; (c) only C; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments that include any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0242] In this specification, the term "coupled" may encompass connections, communications, or signal paths that support a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, but the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0243] Numerical identifiers, such as "first", "second", and "third", etc., are only used to distinguish elements of substantially the same type in terms of structure and / or function. These identifiers used in the detailed description are not necessarily consistent with the identifiers used in the claims.

[0244] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0245] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless explicitly stated to the contrary, these terms are generally used to refer to the interconnection between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0246] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0247] The circuits described herein can be reconfigured to include replaced components to provide functions that are at least partially similar to the functions available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements that are coupled in series and / or in parallel to provide the impedance amount represented by the displayed resistor. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described as a single component in this article may actually be a plurality of resistors or capacitors coupled in series between two nodes that are the same as a single resistor or capacitor. Although some elements of the described examples are included in the integrated circuit and other elements are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as being outside the integrated circuit may be included in the integrated circuit, and / or some features shown as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0248] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the value, or if the value is zero, means a reasonable range of values ​​around zero.

[0249] Modifications are possible in the described embodiments and other embodiments are possible within the scope of the claims.

Claims

1. A device comprising: The address generation circuitry is configured to generate a first address associated with a first packet, a second address associated with a second packet, and a third address associated with a third packet, wherein: The first group includes branch instructions; The branch instruction includes a first field that specifies a branch target and a second field that is different from the first field; and The third group includes the branch target of the branch instruction; buffer circuitry configured to receive the first packet, the second packet, and the third packet; decoder circuitry coupled to the buffer circuitry, the decoder circuitry configured to decode the first packet, the second packet, and the third packet; discontinuity controller circuitry coupled to the buffer circuitry and the decoder circuitry and configured to determine whether to cause the address generation circuitry to generate the second address based on the second field of the branch instruction; and Execution circuitry is coupled to the decoder circuitry, the execution circuitry configured to determine whether to cause the address generation circuitry to generate the third address based on the branch instruction.

2. The apparatus of claim 1 , wherein the buffer circuitry is a first buffer circuitry, the apparatus further comprising: the address generation circuitry coupled to the execution circuitry, the address generation circuitry further configured to request a first memory block and a second memory block, the first memory block including at least one of the first packet, the second packet, or the third packet, the second memory block including a fourth packet; the first buffer circuitry configured to store the first memory block in the first buffer circuitry; as well as A second buffer circuitry is configured to store the second memory block in the second buffer circuitry in response to generating the third address based on the branch instruction.

3. The apparatus of claim 1 , wherein the buffer circuit system is a first buffer circuit system, the apparatus further comprising second buffer circuitry; and Wherein the second field of the branch instruction is delay information specifying a number of memory blocks to be stored in the first buffer circuitry before storing memory blocks in the second buffer circuitry. 4 . The apparatus of claim 3 , wherein the second buffer circuitry is configured to begin storing the memory block in response to execution of one of a call instruction or a return instruction.

5. The apparatus of claim 1 , wherein the buffer circuitry is a first buffer circuitry, the apparatus further comprising: a second buffer circuit system; and The decoder circuitry is further configured to flush the first buffer circuitry in response to the decoder circuitry being configured to decode a memory block from the second buffer circuitry.

6. The apparatus of claim 1 , wherein the buffer circuitry is a first buffer circuitry, the apparatus further comprising second buffer circuitry; and The execution circuitry is further configured to adjust which of the first buffer circuitry or the second buffer circuitry the decoder circuitry is configured to decode packets from.

7. A device comprising: a first buffer circuit system; a second buffer circuit system; decoder circuitry coupled to the first buffer circuitry and the second buffer circuitry, the decoder circuitry configured to determine an instruction by decoding a memory block in one of the first buffer circuitry or the second buffer circuitry; address generation circuitry configured to request a memory block; the first buffer circuitry being configured to store the memory block in the first buffer circuitry in response to a non-branch instruction; and The second buffer circuitry is configured to store the memory block in the second buffer circuitry in response to a branch instruction.

8. The apparatus of claim 7, further comprising execution circuitry coupled to the decoder circuitry, the execution circuitry configured to: executing the instructions from the decoder circuitry; and The decoder circuitry is configured to decode the memory block from either the first buffer circuitry or the second buffer circuitry in response to execution of a branch instruction.

9. The apparatus of claim 8, wherein the decoder circuit system is further configured to clear the first buffer circuit system in response to the execution circuit system adjusting which of the memory blocks from the first buffer circuit system or the second buffer circuit system the decoder circuit system is configured to decode.

10. The apparatus of claim 8, wherein the execution circuitry is further configured to delay a number of cycles of a cycle clock by adjusting which of the memory blocks from the first buffer circuitry or the second buffer circuitry the decoder circuitry is configured to decode.

11. The apparatus of claim 7, wherein the branch instruction includes delay information specifying a number of memory blocks to be stored in the first buffer circuitry before storing memory blocks in the second buffer circuitry.

12. The apparatus of claim 7, wherein the second buffer circuitry is configured to store the memory block in response to execution of one of a call instruction or a return instruction.

13. At least one non-transitory computer-readable storage medium comprising first instructions that, when executed, cause a first programmable circuit system to perform at least the following operations: Select a branch instruction from the list of machine instructions; determining a reference number of non-branch instructions preceding the branch instruction in the machine instruction list; and adjusting the execution order of the branch instructions in the machine instruction list based on the reference number of non-branch instructions; and The list of machine instructions is stored in a memory, the list of machine instructions being configured to be executed by a second programmable circuit system.

14. The at least one non-transitory computer-readable storage medium of claim 13, wherein the first instruction causes the first programmable circuitry to determine whether the branch instruction is one of a conditional branch instruction or an unconditional branch instruction.

15. The at least one non-transitory computer-readable storage medium of claim 14, wherein the first instruction causes the first programmable circuit system to: In response to determining that the branch instruction is a conditional branch instruction, determining a flag to be checked by the branch instruction; and The execution order of the branch instruction in the machine instruction list is adjusted to be after any one of the reference number of non-branch instructions capable of adjusting the flag.

16. At least one non-transitory computer-readable storage medium according to claim 15, wherein the first instruction causes the first programmable circuit system to adjust the flag in response to at least one of the reference number of non-branch instructions, adding at least one no-operation instruction after a non-branch instruction in the reference number of non-branch instructions that are capable of adjusting the flag.

17. At least one non-transitory computer-readable storage medium according to claim 14, wherein the first instruction causes the first programmable circuit system to adjust the execution order of the branch instructions in the machine instruction list to be executed before the reference number of instructions in response to determining that the branch instruction is an unconditional branch instruction.

18. The at least one non-transitory computer-readable storage medium of claim 13, wherein the first instruction causes the first programmable circuitry to: generating instruction groups based on the machine instructions in the machine instruction list; and A memory block is generated that includes one or more portions of the instruction packet, a memory block being a portion of the memory.

19. The at least one non-transitory computer-readable storage medium of claim 18, wherein the first instruction causes the first programmable circuit system to: Select branch instruction grouping; determining a reference number of non-branch instruction groups following the branch instruction group; as well as The number of memory blocks including the reference number of non-branch instruction packets following the branch instruction packet is determined.

20. The at least one non-transitory computer-readable storage medium of claim 19, wherein the first instruction causes the first programmable circuitry to adjust delay bits of the branch instruction packets based on a number of the memory blocks that include the reference number of non-branch instruction packets.

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