High-parallelism programming method for memory chip with crossbar switch structure

Abstract

The invention discloses a high-parallelism programming method for a memory chip with a crossbar switch structure. The method comprises the following steps: step 1, subtracting a target matrix from an initial value of a chip to obtain a programming step length matrix of current programming; step 2, according to the characteristics of the chip and a programming task target, adjusting a single programming pulse step length, adjusting the value of the programming step length matrix, and then according to a corresponding threshold range, re-dividing the programming step length matrix to obtain a programming series matrix; step 3, using a crossbar switch splitting method to split the programming series matrix into matrixes supported by single programming of a storage chip with the minimum total splitting times, and obtaining programming row and column information according to a splitting result; and step 4, completing programming operation according to the programming row and column information obtained in the step 3. According to the invention, the programming parallelism degree of the crossbar switch structure storage chip can be improved, and the programming speed of the crossbar switch structure storage chip is accelerated.

Description

Technical Field

[0001] The invention relates to a high-parallelism programming method for a storage and computing chip with a cross switch structure, and belongs to the field of programming of storage and computing chips. Background Art

[0002] The integrated storage and computing chip integrates computing and storage, greatly improving the energy efficiency ratio. It is one of the important research technologies to solve the current bottlenecks of the "memory wall" and "power consumption wall" of the von Neumann structure.

[0003] The crossbar switch structure is suitable for matrix-vector calculations and can be naturally and efficiently applied to deep neural networks, thus becoming the mainstream structure of storage and computing chips. However, at present, storage and computing integrated devices have problems such as poor consistency and complex programming processes. The crossbar switch structure can only control the chip array through row and column switches, and cannot achieve independent control of each unit in the array. Therefore, it is difficult to improve the parallelism of programming, which further amplifies the disadvantage of slow programming speed of storage and computing chips.

[0004] Chinese patent ZL201811398206.9 discloses a photoelectric computing unit, a photoelectric computing array, and a photoelectric computing method. The photoelectric computing array adopts a cross switch structure, and can be programmed by controlling the row and column switches to control each unit. However, since there is only one switch for each column and each row, only one row or one column can be programmed synchronously at most, and since the programming targets of each unit are different, the programming parallelism will further decrease as the programming progresses. In Chinese patent ZL202310341637.6 "A fast programming method for storage and computing integrated chips", this method takes into account the slow programming speed of 0 values, and programs the 0 value separately to increase the programming speed. However, when programming 0, it can only be programmed by row or column, and the maximum programming parallelism is not achieved, and the programming of non-0 values ​​cannot be accelerated. Summary of the invention

[0005] In order to improve the programming parallelism of a cross-switch structure storage and computing chip and speed up the programming speed, the present invention provides a high-parallelism programming method for a cross-switch structure storage and computing chip.

[0006] The technical solution adopted by the present invention is as follows:

[0007] A high parallel programming method for a crossbar switch structure storage and computing chip, the method comprising the following steps:

[0008] Step 1, obtain the initial value of the chip, subtract the target matrix from the initial value of the chip to obtain the programming step matrix of this programming;

[0009] Step 2, according to the characteristics of the chip and the programming task objectives, adjust the single programming pulse step size and adjust the value of the programming step size matrix, and then re-divide the programming step size matrix according to the corresponding threshold range to obtain a programming level matrix, where each level in the programming level matrix represents a programming operation;

[0010] Step 3, using a cross switch splitting method to split the programming level matrix into matrices supported by a single programming of the storage and computing chip with a minimum total number of splits, and obtaining programming row and column information according to the splitting result;

[0011] Step 4, completing the programming operation according to the programming row and column information obtained in step 3.

[0012] Furthermore, in step 3, the crossbar switch splitting method specifically includes the following steps:

[0013] Step 3-1, merge rows with the same column switch information from the row dimension, and merge columns with the same row switch information from the column dimension;

[0014] Step 3-2, remove all zero rows and all zero columns in the merged result to obtain the row dimension matrix and column dimension matrix, and then obtain the minimum number of splits in the row dimension and column dimension respectively;

[0015] Step 3-3, compare the minimum splitting numbers of the row dimension and the column dimension, and take the smaller minimum splitting number as the final splitting result. If the row dimension is split, the 1 in each row of the row dimension matrix represents open and the 0 represents closed, which is used as the column switch information of this programming operation. The positions of all the same rows of each row before the merge are set to 1, and the remaining positions are set to 0, which is the row switch information of the corresponding programming; if the column dimension is split, the 1 in each column of the column dimension matrix represents open and the 0 represents closed, which is the row switch information of this programming operation. The positions of all the same columns of each column before the merge are set to 1, and the remaining positions are set to 0, which is the column switch information of the corresponding programming.

[0016] Furthermore, in step 1, the initial value of the chip may be a factory value or a current reading result of the chip.

[0017] Furthermore, in step 2, the programming step matrix is ​​first divided into different threshold ranges according to the programming characteristic curve of the chip, and then the programming level is set according to the threshold range to obtain a programming level matrix, which is a matrix closer to the actual programming result of the storage and computing chip.

[0018] Furthermore, in step 3, the same row and column information obtained after splitting is merged as programming row and column information. At this time, the information programmed each time includes programming step information in addition to row information and column information, so as to save the setting time between programming links of the same row and column information.

[0019] Furthermore, in step 3, when the number of row switches is much larger than the number of column switches, the crossbar switch splitting method is used only from the row direction to save unnecessary calculations; conversely, when the number of column switches is much larger than the number of row switches, the crossbar switch splitting method is used only from the column direction.

[0020] Furthermore, the method supports both precise programming and rough programming; the rough programming is used as pre-programming before precise programming to program the chip to a value close to the target value, so as to speed up subsequent precise programming.

[0021] Furthermore, for precise programming, each time after the programming in step 4 is completed, it is necessary to read the chip result and verify whether it meets the accuracy requirements. If it does not meet the accuracy requirements, repeat steps 1 to 4 until the programming accuracy meets the requirements; for rough programming, the programming is completed after the programming in step 4 is completed, and no verification is required.

[0022] Furthermore, if the goal of the rough programming is to serve as a preprocessing for precise programming, adjusting the value of the programming step matrix in step 2 includes: before re-dividing the programming step matrix, multiplying the programming step matrix by a coefficient less than 1 so that the programming result is close to the target value while avoiding over-programming.

[0023] The present invention takes into account the fact that the existing cross-switch structure storage and computing chip can only control the chip array programming through row and column switches, and designs a matrix minimum splitting method suitable for the cross-switch structure. The programming method of the present invention first calculates the step length matrix of each programming, and processes the programming step length matrix into a programming level matrix suitable for control according to the chip characteristics and task objectives, and then applies the minimum splitting method in the row direction and / or column direction respectively to achieve the minimum number of splits, thereby achieving the maximum average parallelism of programming, shortening the total programming time, and having significant improvements over the existing methods of programming one by one or programming the entire row or column. Taking N*N matrix programming as an example, the present invention can achieve parallel programming of up to N*N devices, which can be N times faster than programming by row or column. If the programming operations of the same row and column information are merged to reduce the configuration time between two programmings, the acceleration ratio will be even greater. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a flow chart of a high-parallelism programming method of the present invention that does not merge the same programming information.

[0025] Figure 2 The flowchart of the high parallel programming method for merging the same programming information of the present invention is shown.

[0026] Figure 3 The figure is a flow chart of the crossbar switch splitting method of the present invention.

[0027] Figure 4 2 is a structural diagram of an optoelectronic storage and computing chip with a cross switch structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0029] The present invention provides a high parallel programming method for a cross-switch structure storage and computing chip, such as Figure 1 As shown, the following steps are included:

[0030] Step 1: Get the programming step matrix. First, get the initial value of the chip, and subtract the target matrix from the initial value of the chip to get the programming step matrix for this programming.

[0031] Step 2: The programming step matrix is ​​processed to obtain the programming level matrix. According to the selected chip characteristics and programming task objectives, the single programming pulse step is adjusted, and the value of the programming step matrix is ​​adjusted. Then, the programming level matrix is ​​re-divided according to the corresponding threshold requirements, and each level represents a programming operation. The programming level matrix is ​​a matrix that is closer to the actual programming result of the storage and computing chip.

[0032] Step 3, obtain the row and column information of programming. Use the cross switch splitting method to split the programming level matrix into matrices supported by the storage chip for single programming with the least total number of splits, and obtain the row and column information of programming according to the splitting result. The cross switch splitting method specifically includes the following steps:

[0033] Step 3-1, merge rows with the same column switch information from the row dimension, and merge columns with the same row switch information from the column dimension; for example, assuming the target matrix size is 3X3, in the row dimension merge, the column switch information of the first row is 001, the column switch information of the second row is 001, and the column switch information of the third row is 100, the first row and the second row can be merged, and the third row is retained, and the size of the merged new matrix becomes 2X3

[0034] Step 3-2, remove all zero rows and all zero columns in the merged result to obtain the row dimension matrix and column dimension matrix, and then obtain the minimum number of splits of the row dimension and column dimension respectively.

[0035] Step 3-3, compare the minimum split number of row dimension and column dimension, and take the smaller minimum split number as the final split result. If the row dimension is split, the 1 in each row in the row dimension matrix represents open and the 0 represents closed, which is used as the column switch information of this programming operation. The positions of all identical rows in each row before the merge are set to 1, and the remaining positions are set to 0, which is the row switch information of the corresponding programming; if the column dimension is split, the 1 in each column in the column dimension matrix represents open and the 0 represents closed, which is the row switch information of this programming operation. The positions of all identical columns in each column before the merge are set to 1, and the remaining positions are set to 0, which is the column switch information of the corresponding programming.

[0036] Step 4, start programming, that is, store the data in the chip. According to the programming row and column information obtained in step 3, complete all programming operations. Here, you can directly use the result of the split method for programming, or you can merge the same operations and then program, that is, merge the same row and column information obtained after splitting as the row and column information for programming. At this time, the information for each programming includes the programming step information in addition to the row information and column information, so as to save the setting time between the programming links of the same row and column information and further speed up the programming speed.

[0037] Therefore, the present invention can effectively improve the parallelism of programming by splitting the entire programming target matrix into matrix forms supported by multiple chips for single programming and then programming, wherein the fewer the number of matrices after splitting, the higher the average parallelism of programming and the faster the programming speed. Specific examples are given below.

[0038] Example 1

[0039] This embodiment uses an optoelectronic storage chip with a cross switch structure, and its structure is as shown in the attached figure. Figure 4 As shown, the chip controls the array through word lines WL, bit lines BL and source lines SL. In the programming state, the WL, BL and SL of the corresponding device are turned on. When switching to the verification state, WL and SL are kept unchanged, the corresponding BL is turned off, and the current value is converted into a voltage value through Sample & IV Circuits at the SL end, and finally the result is read out through ADC. Adder is used to realize the accumulation of multi-bit excitation calculation results, and does not involve programming.

[0040] In this embodiment, a random matrix with a value range of [0,64] and an array size of 512*512 is programmed into an optoelectronic storage chip with a crossbar switch structure. The method of the present invention is only used as a pre-programming before precise programming, that is, a rough programming scheme, which does not require verification and adopts a strategy of not merging the same programming information. The workflow is shown in the attached figure. Figure 1 ,The specific process of implementing the method is as follows.

[0041] First, in step 1 of the method of the present invention, the initial value of the corresponding area of ​​the selected optoelectronic storage chip is read. In this implementation, the chip is the factory value, and the initial value of the corresponding 512*512 area is 64. The initial value of the chip minus the matrix to be programmed is used to obtain the step length matrix of this programming. The value range of the programming step length matrix is ​​still [0,64].

[0042] In step 2, in order to prevent excessive pre-programming, the programming step matrix is ​​multiplied by 0.8. In addition, the programming curve of the optoelectronic storage chip is processed according to the ideal linear situation, and no additional processing is required for the programming step matrix. However, due to certain inconsistencies in the optoelectronic storage chip, there is no obvious benefit in dividing the number of segments too high in the pre-programming stage. In this embodiment, the programming step is divided into 5 segments, and the programming level in the threshold range of the programming step matrix (0,12] is set to 1, the programming level in the range of (13,24] is set to 2, the programming level in the range of (25,36] is set to 3, the programming level in the range of (37,48] is set to 4, and the programming level in the range of (49,60] is set to 5. At this time, the programming level matrix matrix is ​​obtained, and the value range is [0,5]. Each level in the programming level matrix represents a programming operation.

[0043] In step 3, all non-zero values ​​in the programming level matrix matrix are set to 1, and the target array matrix_sub for this programming is obtained, where 1 represents on and 0 represents off (no programming). The crossbar switch splitting method of the present invention is used to split matrix_sub into multiple matrices that support single-time programming of the optoelectronic storage and computing chip, and obtain the row switch information (corresponding to WL switch) and column switch information (corresponding to BL, SL switch) corresponding to these matrices. The specific process is shown in the attached figure. Figure 3As shown, matrix_sub is used as the input of the crossbar splitting method, and the same rows / columns are merged in the row direction and column direction respectively. The number of rows / columns after merging is the corresponding split number rowsplit and cowsplit. Then, all 0 rows / columns are removed, and the sizes of the new rowsplit and cowsplit are compared. If rowsplit is small, the number of splits in the row direction is small and the splitting effect is good. In this case, row splitting is selected. Each row (i.e., UniqueRows) after row splitting and merging represents a splitting result. The row switch information (WL) of each splitting result is the position row_idx corresponding to UniqueRows before the input matrix matrix is ​​merged, and the column switch information (BL, SL) is the value of UniqueRows itself. On the contrary, if cowsplit is small, column splitting is selected. Each row after column splitting and merging (i.e. UniqueCows) represents a split result. The row switch information (WL) of each split result is the value of UniqueCows itself, and the column switch information (BL, SL) is the position cow_idx corresponding to UniqueCows before the input matrix matrix is ​​merged.

[0044] In step 4, the WL, BL, and SL information obtained in step 3 is transferred to the chip, and programming begins. After the programming is completed, matrix_sub is subtracted from matrix to obtain a new matrix, and it is determined whether the matrix is ​​all 0. If it is all 0, the pre-programming is completed. If it is not all 0, steps 3 and 4 are repeated until the matrix becomes all 0.

[0045] To demonstrate the effect of the cross-switch splitting method of the present invention, taking the existing row-based programming method as an example, 5*512 programming operations are required to achieve the same pre-programming. Compared with row-based programming, the present invention can obtain a 1-512 times acceleration ratio. If the random matrix has values ​​only in the opposite direction, the cross-switch splitting method of the present invention cannot be accelerated. If the values ​​of each row of the random matrix are the same, the cross-switch splitting method can achieve a 512 times acceleration ratio. In actual situations, the cross-switch splitting method of the present invention can usually obtain a better acceleration effect.

[0046] Example 2

[0047] This embodiment uses the same optoelectronic storage chip as in Embodiment 1. In the 512*512 array to be programmed, the values ​​of the first 512*128 part are all 0, the values ​​of the middle 512*128 part are all 16, and the values ​​of the last 512*256 part are all 32. The initial values ​​of the 512*512 array corresponding to the chip are all 64. This embodiment uses the method of the present invention as precise programming and adopts the process of merging programming operations with the same row and column information. The workflow is shown in the attached figure. Figure 2 As shown, the same contents as those in Example 1 are not repeated here.

[0048] In step 1 of the method of the present invention, the current read result of the chip is directly used as the initial value of this programming, and the chip does not need to be restored to the factory value to obtain a programming step matrix, in which the values ​​of the first 512*256 part are all 64, and the values ​​of the second 512*256 part are all 32.

[0049] In step 2, since the programming curve of the optoelectronic storage chip can be approximately considered ideal, this implementation can divide the programming step into 4 segments, and the programming level in the programming step matrix (0,16] is set to 1, the programming level in the range of (17,32] is set to 2, the programming level in the range of (33,48] is set to 3, and the programming level in the range of (49,64] is set to 4. At this time, a 512*512 programming level matrix matrix is ​​obtained, the values ​​of the first 512*128 part are all 4, the values ​​of the middle 512*128 part are all 3, and the values ​​of the last 512*256 part are all 2.

[0050] In step 3, all non-zero values ​​in the programming level matrix matrix are set to 1 to obtain the target array matrix_sub for this programming, and the corresponding splitting result is obtained by using the cross switch splitting method. At this time, the splitting result is saved without programming, and the matrix_sub is subtracted from the matrix to obtain a new matrix, and a new matrix_sub is obtained again. Repeat this process until the matrix is ​​all 0. After merging the same row and column switch information, go to step 4 and start all programming operations. After programming is completed, enter the verification stage, read the current value of the chip and compare it with the array to be programmed. If it meets the requirements, the programming is completed. If it does not meet the requirements, repeat steps 1-4 until the programming accuracy meets the requirements.

[0051] In this embodiment, the existing row-based programming method requires 4*512 unit programming times, while this embodiment only requires 4 unit programming times, achieving a 512-fold acceleration ratio, and by merging the same row and column switch information, only 3 programming configuration operations are performed. If a non-merging strategy is adopted, 4 programming configuration operations are required. The programming efficiency improvement effect of the present invention is obvious.

[0052] The above is only one specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A high parallelism programming method for a crossbar switch structure storage and computing chip, characterized in that: The method comprises the following steps: Step 1, obtain the initial value of the chip, subtract the target matrix from the initial value of the chip to obtain the programming step matrix of this programming; Step 2, according to the characteristics of the chip and the programming task objectives, adjust the single programming pulse step size and adjust the value of the programming step size matrix, and then re-divide the programming step size matrix according to the corresponding threshold range to obtain a programming level matrix, where each level in the programming level matrix represents a programming operation; Step 3, using a cross switch splitting method to split the programming level matrix into matrices supported by a single programming of the storage and computing chip with a minimum total number of splits, and obtaining programming row and column information according to the splitting result; Step 4, completing the programming operation according to the programming row and column information obtained in step 3.

2. A high parallelism programming method for a crossbar switch structure storage and computing chip according to claim 1, characterized in that: In step 3, the crossbar switch splitting method specifically includes the following steps: Step 3-1, merge rows with the same column switch information from the row dimension, and merge columns with the same row switch information from the column dimension; Step 3-2, remove all zero rows and all zero columns in the merged result to obtain the row dimension matrix and column dimension matrix, and then obtain the minimum number of splits in the row dimension and column dimension respectively; Step 3-3, compare the minimum splitting numbers of the row dimension and the column dimension, and take the smaller minimum splitting number as the final splitting result. If the row dimension is split, the 1 in each row of the row dimension matrix represents open and the 0 represents closed, which is used as the column switch information of this programming operation. The positions of all the same rows of each row before the merge are set to 1, and the remaining positions are set to 0, which is the row switch information of the corresponding programming; if the column dimension is split, the 1 in each column of the column dimension matrix represents open and the 0 represents closed, which is the row switch information of this programming operation. The positions of all the same columns of each column before the merge are set to 1, and the remaining positions are set to 0, which is the column switch information of the corresponding programming.

3. A high parallelism programming method for a crossbar switch structure storage and computing chip according to claim 1, characterized in that: In step 1, the initial value of the chip may be a factory value or a current reading result of the chip.

4. A high parallelism programming method for a crossbar switch structure storage and computing chip according to claim 1, characterized in that: In step 2, the programming step matrix is ​​first divided into different threshold ranges according to the programming characteristic curve of the chip, and then the programming level is set according to the threshold range to obtain a programming level matrix, which is a matrix closer to the actual programming result of the storage and computing chip.

5. A high parallelism programming method for a crossbar switch structure storage and computing chip according to claim 1, characterized in that: In step 3, the same row and column information obtained after splitting is merged as the row and column information for programming. At this time, the information for each programming includes programming step information in addition to row information and column information, so as to save the setting time between programming links of the same row and column information.

6. A high parallelism programming method for a crossbar switch structure storage and computing chip according to claim 1, characterized in that: In step 3, when the number of row switches is much larger than the number of column switches, the crossbar switch splitting method is used only in the row direction to save unnecessary calculations; conversely, when the number of column switches is much larger than the number of row switches, the crossbar switch splitting method is used only in the column direction.

7. A high parallelism programming method for a crossbar switch structure storage and computing chip according to claim 1, characterized in that: The method supports both precise programming and rough programming; the rough programming is used as pre-programming before precise programming to program the chip to a value close to the target value, so as to speed up the subsequent precise programming.

8. A high parallelism programming method for a crossbar switch structure storage and computing chip according to claim 7, characterized in that: For precise programming, each time after the programming in step 4 is completed, it is necessary to read the chip results and verify whether they meet the accuracy requirements. If they do not meet the accuracy requirements, repeat steps 1 to 4 until the programming accuracy meets the requirements. For rough programming, the programming is completed after the programming in step 4 is completed, and no verification is required.

9. A high parallelism programming method for a crossbar switch structure storage and computing chip according to claim 8, characterized in that: If the goal of the rough programming is to serve as a preprocessing for precise programming, adjusting the value of the programming step matrix in step 2 includes: before re-dividing the programming step matrix, multiplying the programming step matrix by a coefficient less than 1 so that the programming result is close to the target value while avoiding over-programming.

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