Multi-core consistency processing method, system and device and storage medium

Abstract

The embodiment of the invention provides a multi-core consistency processing method, system and device and a storage medium, and relates to the technical field of semiconductors. The method comprises the following steps: in a multi-core processor, configuring an initial out-of-core backup memory for an initial processor core, and configuring a non-initial out-of-core backup memory for each non-initial processor core; after a multi-core consistency module in the multi-core processor receives a read request from the initial processor core, each non-initial out-of-core backup memory is looked up to judge whether each non-initial processor core has an address backup or not; and sending a sniffing request to each non-initial processor core with the address backup through the multi-core consistency module so as to respond to the read request. According to the method provided by the invention, before the specific operation is implemented, the judgment is firstly carried out so as to carry out directional transmission without entering the core, so that the access efficiency is improved, and the bandwidth is saved under the condition of ensuring that the data is correct.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a multi-core consistency processing method, system, device and storage medium. Background Art

[0002] In a multi-core processor system, data consistency is a crucial concept. When multiple processor cores access shared data at the same time, data consistency needs to be ensured to avoid potential errors and conflicts. In a multi-core processor system, since multiple processor cores operate shared data at the same time, various problems may occur if data consistency is not guaranteed, such as: data conflict: different processor cores perform different operations on the same data, resulting in uncertainty in data results; program errors: program errors caused by inconsistent data may cause system crashes or data corruption; performance degradation: data consistency issues may cause frequent communication and synchronization between processor cores, affecting the overall performance of the system.

[0003] In the prior art, multi-core consistency is generally achieved through broadcasting, that is, the multi-core consistency module broadcasts the read request of the sharable address from the initial cache to other cores.

[0004] However, the broadcast format is for all processor cores, and the cores that do not request address backup also need to perform sniffing operations, resulting in a large bus bandwidth and low data processing efficiency, especially when the number of cores is large. Summary of the invention

[0005] In order to solve one of the above technical defects, a multi-core consistency processing method, system, device and storage medium are provided in the embodiments of the present application.

[0006] According to a first aspect of an embodiment of the present application, a multi-core consistency processing method is provided, the method comprising: In a multi-core processor, an initial out-of-core backup storage is configured for an initial processor core, and a non-initial out-of-core backup storage is respectively configured for each non-initial processor core; According to the read request from the initial processor core, each non-initial off-core backup storage is consulted respectively to determine whether each non-initial processor core has an address backup corresponding to the read request; Sniff each non-initial processor core where an address copy exists and read the address copy in response to the read request.

[0007] In an optional embodiment of the present application, the step of respectively consulting each non-initial off-core backup storage according to the read request from the initial processor core to determine whether each non-initial processor core has an address backup corresponding to the read request further includes: Each non-initial out-of-core backup store is consulted separately in parallel.

[0008] In an optional embodiment of the present application, the step of respectively consulting each non-initial off-core backup storage according to the read request from the initial processor core to determine whether each non-initial processor core has an address backup corresponding to the read request further includes: The read request is received through a multi-core consistency module in the multi-core processor, and each non-initial core external backup storage is consulted through the multi-core consistency module to determine whether each non-initial processor core has an address backup corresponding to the read request.

[0009] In an optional embodiment of the present application, the step of sniffing each non-initial processor core having an address backup and reading the address backup to respond to the read request further includes: The multi-core consistency module sniffs each non-initial processor core where an address backup exists, and reads the address backup to respond to a read request.

[0010] In an optional embodiment of the present application, the step of sniffing each non-initial processor core having an address backup and reading the address backup to respond to the read request further includes: After receiving the sniff response, the multi-core consistency module synchronizes the cache line state to each non-initial processor core having an address backup according to the cache line state stored in the initial out-core backup.

[0011] In an optional embodiment of the present application, in a multi-core processor, the step of configuring an initial out-of-core backup storage for an initial processor core and configuring a non-initial out-of-core backup storage for each non-initial processor core further includes: Both the initial out-core backup storage and the non-initial out-core backup storage are shadow-tagged random storage. The content and state of the initial out-core backup storage are consistent with the data in the data cache in the initial processor core; the content and state of the non-initial out-core backup storage are consistent with the content and state of the data cache in the corresponding non-initial processor core.

[0012] In an optional embodiment of the present application, in a multi-core processor, the step of configuring an initial out-of-core backup storage for an initial processor core and configuring a non-initial out-of-core backup storage for each non-initial processor core further includes: The states of the data caches in the initial processor core and the non-initial processor core, and the states in the initial off-core backup storage and the non-initial off-core backup storage include at least one of exclusive and modified, exclusive, shared, invalid, and shared and modified states.

[0013] According to a second aspect of an embodiment of the present application, a multi-core consistency processing system is provided, the system comprising: A backup storage configuration unit, configured to configure an initial out-of-core backup storage for an initial processor core and a non-initial out-of-core backup storage for each non-initial processor core in a multi-core processor; An address backup judgment unit, used to refer to each non-initial core backup storage according to a read request from the initial processor core, to judge whether each non-initial processor core has an address backup corresponding to the read request; The sniff request processing unit is used to sniff each non-initial processor core that has an address backup, and read the address backup to respond to the read request.

[0014] According to a third aspect of an embodiment of the present application, there is provided a computer device, including: a memory; A processor; and a computer program; wherein the computer program is stored in a memory and is configured to be executed by the processor to implement the steps of any method of the first aspect of the embodiment of the present application.

[0015] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored; the computer program is executed by a processor to implement the steps of any method of the first aspect of the embodiment of the present application.

[0016] The multi-core consistency processing method provided in the embodiment of the present application has the following beneficial effects: The method of the present application establishes backup storage outside the core, and before sniffing, first determines whether there is an address backup through the backup storage of each processor core, and if so, then proceeds to the next operation; if not, it does not waste resources to perform the next operation in a directional manner. Based on this, the method of the present application first makes a judgment before implementing a specific operation, and does not need to enter the core, which improves access efficiency and saves bandwidth while ensuring data correctness. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A flowchart of a multi-core consistency processing method provided in an embodiment of the present application; Figure 2 A schematic diagram of multi-core consistency data flow provided in an embodiment of the present application; Figure 3 A structural diagram of a multi-core consistency processing system provided in an embodiment of the present application; Figure 4 A schematic diagram of the computer device structure provided for one embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0019] A multi-core processor is a processor that integrates two or more complete computing engines (cores). In this case, the processor can support multiple processors on the system bus, and the bus controller provides all bus control signals and command signals.

[0020] In a multi-core processor system, data consistency is a crucial concept. When multiple processor cores access shared data at the same time, data consistency needs to be ensured to avoid potential errors and conflicts. In a multi-core processor system, since multiple processor cores operate on shared data at the same time, various problems may occur if data consistency is not guaranteed, such as: data conflict: different processor cores perform different operations on the same data, resulting in uncertainty in data results; program errors: program errors caused by inconsistent data may cause system crashes or data corruption; performance degradation: data consistency issues may cause frequent communication and synchronization between processor cores, affecting the overall performance of the system.

[0021] The inventor of the present application has discovered that the existing method of uniformly broadcasting a read request to all other cores after receiving it also requires snooping operations on cores that do not have a backup of the request address, resulting in a large bus bandwidth and low data processing efficiency, especially when the number of cores is large.

[0022] Based on this, see Figure 1 : Embodiment 1:

[0023] The multi-core consistency processing method of the present application includes: S1: In a multi-core processor, an initial out-of-core backup storage is configured for an initial processor core, and a non-initial out-of-core backup storage is respectively configured for each non-initial processor core; S2: According to the read request from the initial processor core, each non-initial external core backup storage is consulted to determine whether each non-initial processor core has an address backup corresponding to the read request; S3: Sniff each non-initial processor core that has an address backup, and read the address backup to respond to the read request.

[0024] In the specific implementation, Figure 2As shown, there are multiple core processor cores in the multi-core processor, and when a request interaction occurs, there is an initial processor core (initial core) and multiple non-initial processor cores. Specifically, the initial processor core is the core that initiates the request, and the non-initial processor core is the other cores other than the initial processor core. In this embodiment, for each processor core, a backup storage is configured for it, and the backup storage is placed outside the core.

[0025] That is, in this embodiment, for each processor core, there is a backup placed outside the core for subsequent judgment. Specifically, in this embodiment, the initial outside-core backup storage can be a full backup of the initial processor core, or a partial backup of the initial processor core; the non-initial outside-core backup storage can be a full backup of the initial processor core, or a partial backup of the non-initial processor core.

[0026] In the specific implementation, to solve the cache consistency problem, the first thing to solve is the data propagation problem between multiple processor cores. In the prior art, the method used is the bus sniffing method, which broadcasts all read and write requests to all processor cores through the bus, and then lets each core "sniff" these requests and respond according to the local situation. Specifically, sniffing, also known as broadcasting (snoop), refers to requests for interaction between multiple cores.

[0027] In a specific implementation, after receiving a read request from the initial processor core, each backup storage is consulted, and then a snoop request is sent in a targeted manner, without the need for each core to snoop. Specifically, for consulting each backup storage, the address index and the address tag are compared, and if both match, it is considered a hit, that is, it is considered that the address backup exists in the backup storage.

[0028] Based on this, this embodiment establishes backup storage outside the core, and before performing snoop, first determines whether there is address backup through the backup storage of each processor core, and if so, then performs the next operation; if not, then does not waste resources to perform the next operation. This method of sending snoop requests in a targeted manner and not requiring each core to snoop improves snoop efficiency and avoids resource waste.

[0029] In addition, the backup storage configured in this embodiment is outside the core, and related judgments do not need to enter the core, which improves access efficiency and saves bandwidth while ensuring data correctness. Embodiment 2:

[0030] Based on the above embodiment, step S2 in this embodiment further includes: Each non-initial out-of-core backup store is consulted separately in parallel.

[0031] In a specific implementation, the above judgment is performed in parallel for each non-initial out-core backup storage. That is, in this embodiment, the above judgment is performed independently for different non-initial out-core backup storages, so that it is possible to determine in parallel whether there is an address backup for each non-initial processor core.

[0032] Based on this, compared with Example 1, this embodiment further optimizes the timing of operations based on a parallel mechanism, thereby further improving access efficiency and further saving bandwidth while ensuring data correctness. Embodiment 3:

[0033] Based on the above embodiment, step S2 in this embodiment further includes: The read request is received through a multi-core consistency module in the multi-core processor, and each non-initial core external backup storage is consulted through the multi-core consistency module to determine whether each non-initial processor core has an address backup corresponding to the read request.

[0034] Specifically, the multi-core consistency module is a physical module device configured in the multi-core processor, which is used to receive the request of the initial processor core, distribute the conversion request to other processor cores (i.e., non-initial processor cores) or the next level storage to obtain the desired data, and then return a response to the initial processor core.

[0035] Based on this, by configuring a multi-core consistency module in a multi-core processor, we can rely on its pre-configured consistency function to implement request reception, distribution conversion, response reception and return, which has stronger stability and reusability, making multi-core consistency operations in multi-core processors more convenient. Embodiment 4:

[0036] Based on the above embodiment, step S3 in this embodiment further includes: The multi-core consistency module sniffs each non-initial processor core where an address backup exists, and reads the address backup to respond to a read request.

[0037] Based on this, as mentioned above, in addition to using the multi-core consistency module in the address backup judgment link, the multi-core consistency module is also used in the snoop link to further enhance the stability of the processor and make multi-core consistency operations in multi-core processors more convenient. Embodiment 5:

[0038] Based on the above embodiment, step S3 in this embodiment further includes: After receiving the snoop response, the multi-core consistency module synchronizes the cache line state to each non-initial processor core that has an address backup based on the cache line state stored in the initial off-core backup.

[0039] The data in the cache is read in blocks. When the processor accesses a piece of data, it assumes that the data near the data will be accessed later. Therefore, when this area is accessed for the first time, the data is read into the cache together with the data in the nearby area (64 bytes in total). This block of data is called a cache line.

[0040] In a specific implementation, after receiving the snoop response, the cache line state of the initial off-core backup storage is referred to and the corresponding cache line state is returned to complete the synchronization of the cache line state.

[0041] Specifically, before sending a request, the multi-core consistency module first accesses other off-core backup storages in parallel except the initial off-core backup storage, waits for them to return data, determines the status of the cache in each processor core, and then sends the request to the corresponding processor core.

[0042] Specifically, Based on this, this embodiment can further improve the synchronization level of backup storage, can give full play to the role of backup storage, improve the accuracy of multi-core consistency, and avoid data conflicts, program errors, performance degradation and other problems caused by consistency issues. Embodiment 6:

[0043] Based on the above embodiment, step S1 in this embodiment further includes: Both the initial out-core backup storage and the non-initial out-core backup storage are shadow tag random storage (Shadow tagram). The content and state of the initial out-core backup storage are consistent with the content and state of the data cache (dCache) in the initial processor core; the content and state of the non-initial out-core backup storage are consistent with the content and state of the data cache in the corresponding non-initial processor core.

[0044] In a specific implementation, there is a data cache in each processor core, and there is a tagged random access memory (tagram) in the data cache. The tagged random access memory is a random access memory near the cache of the motherboard used to store the cache data index address. Its main function is to assist the communication and access addressing data between the cache, processor, and chipset.

[0045] In this embodiment, the backup storage configured outside the core is a shadow tag random storage that is consistent with the tag random storage in the core. Specifically, in this embodiment, each processor core maintains its own shadow tag random storage, and the content of the shadow tag random storage is consistent with the tag random storage of the data cache in the core, and each state bit is also consistent with the data cache in the core.

[0046] Furthermore, each time the tag random storage of the data cache of each processor core is updated, the corresponding shadow tag random storage will be updated, including the tag field and the status bit. Specifically, each time the tag random storage of the data cache in the core is updated, the shadow tag random storage of the core will be updated synchronously.

[0047] Based on this, we can further ensure that the out-of-core backup is highly consistent with the key information in the core, improve the degree of synchronization outside the core, and through the form of marked random storage, the out-of-core backup can have the key information required for multi-core consistency, avoiding data redundancy, and through the backup data cache marking mechanism, we can accurately find the core with the access request address backup, thereby improving access efficiency. Embodiment 7:

[0048] Based on the above embodiment, step S1 in this embodiment further includes: The states of the data caches in the initial processor core and the non-initial processor core, and the states in the initial off-core backup storage and the non-initial off-core backup storage include at least one of the states of modified, exclusive, shared, invalid, and shared and modified.

[0049] Specifically, as mentioned above, each update of the tag random storage of the data cache of each processor core will update the corresponding shadow tag random storage, including the tag field and status bit; specifically, each update of the tag random storage of the core's in-core data cache will synchronously update the shadow tag random storage of the core, including all the data and status (MESIO) therein; specifically, MESIO adds the shared and modified (O) state based on the MESI protocol, as follows: The MESI protocol is a cache coherence protocol and one of the most commonly used protocols that supports write-back cache. Its main contents are: 1. Exclusive and Modified (M): The cache line exists only in the current cache and is dirty. It has been modified from a value in main memory (M state). The cache is required to write the data back to main memory at some time in the future before any other reads of the (no longer valid) main memory state are allowed. The writeback changes the line to the Shared state (S).

[0050] 2. Exclusive (E): The cache line exists only in the current cache, but is clean - it matches the main memory. It can be changed to the shared state at any time in response to a read request. Alternatively, it can be changed to the modified state when written.

[0051] 3. Shared (S): Indicates that this cache line may be stored in other caches of the computer and is clean, it matches the main memory. The line can be discarded (changed to invalid state) at any time.

[0052] 4. Invalid (I): Indicates that this cache line is invalid (not used).

[0053] The shared and modified (O) state is: the value of the current cache is different from the value in the memory and is shared by multiple people. In this state, other caches will directly copy the modified data from the current cache, and then the state will change to the shared state (S) again.

[0054] Based on this, by utilizing the MESIO protocol, the use of write-back cache can save a lot of bandwidth that is usually wasted on write cache. There is always a dirty state in the write-back cache, indicating that the data in the cache is different from the data in the main memory. Compared with the MSI protocol, this protocol reduces the number of main memory transactions, and compared with the MESI protocol, it overcomes the defect that other caches must read data from the memory again when initiating a read operation, further improving processing efficiency.

[0055] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0056] See also Figure 3 One embodiment of the present application provides a multi-core consistency processing system, including: The backup storage configuration unit 10 is used to configure an initial out-of-core backup storage for an initial processor core and configure a non-initial out-of-core backup storage for each non-initial processor core in a multi-core processor; An address backup judgment unit 20, for respectively consulting each non-initial core backup storage according to a read request from the initial processor core, to judge whether each non-initial processor core has an address backup corresponding to the read request; The sniff request processing unit 30 is used to sniff each non-initial processor core that has an address backup, and read the address backup to respond to the read request.

[0057] For the specific limitations of the above-mentioned multi-core consistency processing system, please refer to the limitations of the multi-core consistency processing method above, which will not be repeated here. Each unit in the above-mentioned multi-core consistency processing system can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned units can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned units.

[0058] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 4 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a multi-core consistency processing method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the above video signal processing method is implemented.

[0059] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the multi-core consistency processing method described above can be implemented.

[0060] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program codes. The scheme in the embodiments of the present application may be implemented in various computer languages, for example, C language, VHDL language, Verilog language, object-oriented programming language Java, and literal scripting language JavaScript, etc.

[0061] The present application is described with reference to the flowcharts and / or block diagrams of the methods, systems, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0062] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0063] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0064] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0065] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0066] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A multi-core consistency processing method, characterized in that: include: In a multi-core processor, an initial out-of-core backup storage is configured for an initial processor core, and a non-initial out-of-core backup storage is respectively configured for each non-initial processor core; According to the read request from the initial processor core, each of the non-initial off-core backup storages is consulted respectively to determine whether each of the non-initial processor cores has an address backup corresponding to the read request; Sniffing is performed toward each of the non-initial processor cores where the address backup exists, and the address backup is read to respond to the read request.

2. The multi-core consistency processing method according to claim 1, characterized in that: The step of respectively consulting each of the non-initial off-core backup storages according to the read request from the initial processor core to determine whether each of the non-initial processor cores has an address backup corresponding to the read request further includes: Each of the non-initial out-of-core backup storages is consulted separately in parallel.

3. The multi-core consistency processing method according to claim 2, characterized in that: The step of respectively consulting each of the non-initial off-core backup storages according to the read request from the initial processor core to determine whether each of the non-initial processor cores has an address backup corresponding to the read request further includes: The read request is received by a multi-core consistency module in the multi-core processor, and each non-initial off-core backup storage is consulted by the multi-core consistency module to determine whether each non-initial processor core has an address backup corresponding to the read request.

4. The multi-core consistency processing method according to claim 3, characterized in that: The step of sniffing each non-initial processor core having the address backup and reading the address backup to respond to the read request also includes: The multi-core consistency module sniffs each non-initial processor core where the address backup exists, and reads the address backup to respond to the read request.

5. The multi-core consistency processing method according to claim 4, characterized in that: The step of sniffing each non-initial processor core having the address backup and reading the address backup to respond to the read request also includes: After receiving the sniff response, the multi-core consistency module synchronizes the cache line state to each non-initial processor core having the address backup according to the cache line state stored in the initial out-core backup.

6. The multi-core consistency processing method according to any one of claims 1 to 5, characterized in that: The step of configuring an initial out-of-core backup storage for the initial processor core and configuring a non-initial out-of-core backup storage for each non-initial processor core in the multi-core processor also includes: The initial out-core backup storage and the non-initial out-core backup storage are both shadow-tagged random storages; the content and state of the initial out-core backup storage are consistent with the data of the data cache in the initial processor core; the content and state of the non-initial out-core backup storage are consistent with the content and state of the data cache in the corresponding non-initial processor core.

7. The multi-core consistency processing method according to claim 6, characterized in that: The step of configuring an initial out-of-core backup storage for the initial processor core and configuring a non-initial out-of-core backup storage for each non-initial processor core in the multi-core processor also includes: The states of the data caches in the initial processor core and the non-initial processor core, and the states in the initial out-of-core backup storage and the non-initial out-of-core backup storage include at least one of exclusive and modified, exclusive, shared, invalid, and shared and modified states.

8. A multi-core consistency processing system, characterized in that: include: A backup storage configuration unit, configured to configure an initial out-of-core backup storage for an initial processor core and a non-initial out-of-core backup storage for each non-initial processor core in a multi-core processor; An address backup judgment unit, configured to refer to each of the non-initial off-core backup storages according to a read request from the initial processor core to judge whether each of the non-initial processor cores has an address backup corresponding to the read request; The sniff request processing unit is used to sniff each non-initial processor core where the address backup exists, and read the address backup to respond to the read request.

9. A computer device, characterized in that: include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and is configured to be executed by the processor to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon; the computer program is executed by a processor to implement the method according to any one of claims 1 to 7.

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