81 results about "Multicore computing" patented technology

The invention provides an AI reasoning optimization method and system for a dynamic model switching framework for edge equipment, and relates to the technical field of AI optimization, and the method comprises the steps: training a quantization compensation model through federated learning to correct a quantization error; constructing a hierarchical heterogeneous resource management system to realize multi-core collaborative scheduling; the compensation parameters are integrated to an FPGA acceleration circuit, and an intelligent power consumption equalization technology is adopted; and constructing a dynamic decision engine by using the graph neural network to trigger model switching. According to the invention, the balance between high-precision AI reasoning and low-power consumption requirements on the edge equipment is realized, the utilization efficiency of computing resources is improved, and the energy consumption is reduced.

The invention discloses a PLC scheduling algorithm based on a multi-core soft real-time operating system, and relates to the technical field of voltage control, and the algorithm comprises the following four steps: 1, starting a target industrial control system, completing hardware self-inspection, memory allocation and communication module starting, and sending an initialization ready signal after confirming that an assembly is normal; 2, according to PLC task functions and real-time performance, four types of standardized tasks are divided, priority levels are defined, sub-priorities are configured, a dependency relationship is identified, and a task chain is established; 3, counting the number of tasks and task chains, distributing resources by using multiple binding cores, and constructing a global ready queue to adapt to dynamic scheduling; and 4, monitoring an interrupt event through an interrupt manager, realizing high-priority task preemption by semaphores, and allocating tasks to corresponding CPU cores, so that the problems of soft real-time multi-core task preemption and data conflict are solved, the scheduling real-time performance and the data security are improved, the system failure rate is reduced, and the industrial control efficiency and stability are improved.

The invention discloses a method and device for calling a kernel function by a Triton operator and electronic equipment, and relates to the technical field of artificial intelligence. The method comprises the steps that a runtime structure of a Triton operator is constructed, if a kernel function is called for the first time and is a single core, the kernel function is compiled through JITFunction, if the kernel function is called for the first time and is a multi-core, compiling parameters with the best overall performance are obtained through overall adjustment, if the kernel function is not called for the first time, the kernel function is obtained through a mapping table in LibEntry, and if the kernel function is called for the second time, the kernel function is called for the first time and is a multi-core. Compilation parameters and corresponding kernel functions or optimal compilation parameters and corresponding kernel functions are written in the mapping table. Practice shows that according to the scheme provided by the invention, the end-to-end time overhead can be reduced by about 70% in small-scale function calling. Moreover, the parameter tuning space of the multi-core operator is expanded through a global tuning mode, the degree of freedom of configuration parameters is improved, and the calculation efficiency of reduction operators is improved.

The invention relates to the technical field of computer operating systems and audio processing, in particular to a real-time scheduling system for HIFI audio playing based on Linux, which comprises a real-time core for only processing real-time tasks, and a receiving buffer area and a playing buffer area maintained by a buffer management module, an audio real-time task is distributed to a plurality of real-time cores through a multi-core task distribution module, the real-time cores are preempted through an RTOS preemptive task scheduling module, a decoding task is executed based on data in a receiving buffer area through a decoding module, and the real-time cores are preempted through the RTOS preemptive task scheduling module. And executing a playing task based on the data in the playing buffer area through a playing module. Through a unique core isolation architecture, a preemptive scheduling mechanism and a double-buffer design, timely response of an audio real-time task is ensured, and the problem that in the prior art, an audio system based on Linux is difficult to meet the real-time requirement of HIFI audio is solved.

The embodiment of the invention provides a multi-core consistency processing method, system and device and a storage medium, and relates to the technical field of semiconductors. The method comprises the following steps: in a multi-core processor, configuring an initial out-of-core backup memory for an initial processor core, and configuring a non-initial out-of-core backup memory for each non-initial processor core; after a multi-core consistency module in the multi-core processor receives a read request from the initial processor core, each non-initial out-of-core backup memory is looked up to judge whether each non-initial processor core has an address backup or not; and sending a sniffing request to each non-initial processor core with the address backup through the multi-core consistency module so as to respond to the read request. According to the method provided by the invention, before the specific operation is implemented, the judgment is firstly carried out so as to carry out directional transmission without entering the core, so that the access efficiency is improved, and the bandwidth is saved under the condition of ensuring that the data is correct.

The present invention relates to the field of computer storage system structures. Disclosed is a heterogeneous multi-core system memory access management method for a deep neural network (DNN). According to the present invention, a CPU-GPU heterogeneous multi-core system is used to accelerate training of a DNN model, and a memory access controller is designed on the basis of the memory access characteristics of the CPU-GPU heterogeneous multi-core system; the last level cache shared by multiple cores is unloaded, prefetched, and released in the DNN training process; the data transmission process is fine-grained; and the utilization rate of the last level cache is significantly increased. In addition, a latency hiding mechanism is also designed for the memory access controller, and the access process and the calculation process of a large amount of intermediate data of a feature extraction layer are overlapped, so that the calculation performance loss caused by the last level cache miss and waiting of a DRAM memory access response in the model calculation process is reduced, improving the training efficiency.

The present disclosure provides a multi-core synchronization system and a system component. The system comprises a neural network processor and a system component. The neural network processor comprises a task scheduling processor and a plurality of cores. The system component is connected to the task scheduling processor and the plurality of cores respectively by means of a system bus. The system component is used for performing communication among the plurality of cores under the control of the task scheduling processor, so that the plurality of cores synchronously execute allocated model tasks.

The invention provides a multi-core synchronization system and system component in a neural network processor, and belongs to the technical field of computers. The system comprises a neural network processor and a system component, the neural network processor comprises a task scheduling processor and a plurality of cores; the system component is respectively connected with the task scheduling processor and each core through a system bus; and the system component is used for communicating among the cores under the control of the task scheduling processor so as to enable the cores to synchronously execute the distributed model tasks. The system is used for efficient inter-core communication and synchronization.

Method for accessing coherent data on a controller, wherein the method comprises the following steps: Providing a first buffer (72) and a second buffer (74), each of which can be read or written; Providing an indicator (76) that indicates which is read from the first or second buffer, while the other is written to by the first or second buffer; Executing a read synchronization protocol that allows the coherent data to be read from the buffer that indicator (76) specifies as the read buffer; and Executing a write synchronization protocol that allows the coherent data to be written to the buffer that indicator (76) specifies as the write buffer, and where the coherent data to be written together are grouped into data sets.

Methods and apparatus to reduce register access latency in split-die SoC designs. The method is implemented on a platform including a legacy socket and one or more non-legacy (NL) sockets comprising split-die System-on-Chips (SoC)s including multiple dielets interconnected with a plurality of Embedded Multi-Die Interconnect Bridges (EMIBs). The dielets include core dielets having cores, cache controllers and memory controllers. The method provides an affinity between a control and status registers (CSRs) memory range for the NL sockets such that CSRs in the memory controllers for multiple core dielets are programmed using transactions forwarded along core-to-cache controller datapaths that avoid crossing EMIBs. In one aspect, a transient map of address ranges is created that includes a respective Sub-NUMA Cluster (SNC) range allocated for the NL sockets, with a range of CSR addresses for accessing CSRs in the memory controllers for the NL sockets being stored in the respective SNC ranges.

The invention relates to a 5G signaling plane traffic screening method based on a multi-core processing unit, and the method comprises the steps: receiving network mirror image traffic through a physical interface unit, and screening out transmission control protocol traffic; the switching chip unit identifies HTTP / 2 protocol traffic from transmission control protocol traffic according to a target port number or an application layer protocol handshake feature, and forwards the HTTP / 2 protocol traffic to the multi-core processing unit; the binary framing structure of the HTTP / 2 protocol is analyzed, a data frame and a control frame are distinguished, and an HTTP request head is restored; analyzing and decoding an HTTP request header, and extracting a pseudo header field of a uniform resource identifier path in the HTTP request header; generating a traffic filtering rule corresponding to the service signaling traffic bearing the specific network function; and issuing the generated flow filtering rule to a switching chip unit, and outputting specified 5G signaling plane flow. The method automatically adapts to the dynamic change of the 5G network element, and effectively solves the problem of traffic loss or inaccuracy caused by difficult maintenance and untimely updating of the static work parameter data.

The embodiment of the invention provides a parallel simulation method, system and device of a multi-core processor and a storage medium, the parallel simulation method of the multi-core processor comprises the following steps: creating a context for each of a plurality of cores of the multi-core processor, the plurality of contexts corresponding to the plurality of cores being mutually independent; a system thread is created for each context of the plurality of contexts such that the plurality of cores are allocated in different contexts into different system threads that are automatically scheduled to different processor cores for execution. According to the parallel simulation method of the multi-core processor provided by the embodiment of the invention, the parallel simulation is realized based on a plurality of independent contexts, the problem of low simulation efficiency in a traditional simulation framework is effectively solved, and the execution speed of the simulation is remarkably improved through a multi-thread simulation technology.

The invention relates to the technical field of integrated circuit design and Internet of Things, in particular to a high-integration-level low-power-consumption system-level industry 5G AIoT chip which comprises a multi-core heterogeneous computing module, a high-integration-level radio frequency front-end module, a low-power-consumption storage and data management module and a power management and dynamic power consumption optimization module. The multi-core heterogeneous computing module comprises a reduced instruction set-V (RISC-V) core which is used as a main control core, adopts a 64-bit architecture and is used for task scheduling and system management; a dedicated AI acceleration core is based on in-memory computing (CIM) technology. According to the high-integration-level low-power-consumption system-level industry 5G AIoT chip, miniaturization, low power consumption and function diversification of industry terminal equipment are achieved by integrating a multi-core calculation module, a high-integration radio frequency module, a low-power-consumption storage module and an intelligent power management module, and the high-integration-level low-power-consumption system-level industry 5G AIoT chip is particularly suitable for 5G Internet of Things terminals of industry scenes such as industrial monitoring, intelligent power grids and intelligent cities; and the integrated functions of communication, calculation, storage and power management can be realized.

A system may comprise one or more devices in a network. The devices may be configured to: receive network slice performance data; and determine whether a network slice to which a User Equipment (UE) device is connected meets one or more criteria based on the network slice performance data. When the network slice does not meet the one or more criteria, the one or more devices may identify a different network slice that meets the one or more criteria; obtain an application identifier (app ID) or a traffic descriptor from a UE Route Selection Policy (URSP) rule whose slice ID matches a slice ID of the different network slice; and send the app ID or the traffic descriptor to the UE device.

This invention provides a method for improving the real-time performance of Linux operating system applications based on a multi-core CPU. The method includes, during system startup, modifying Linux kernel startup parameters to reallocate tasks across the cores of the multi-core CPU, concentrating basic Linux system tasks on the zeroth core; when the target application creates a task, it sets task affinity based on the task's real-time requirements by calling system functions; non-real-time critical tasks are assigned to the first core; real-time critical tasks are assigned to the second core; and sub-real-time critical tasks are assigned to the third core. This invention effectively reduces the response latency of specific interrupts with strict real-time requirements in the Linux system by utilizing different cores of a multi-core CPU to allocate different tasks, improving device real-time performance and meeting the real-time requirements of fields such as power distribution automation.

The present invention proposes a multi-core processor and a method for centralized cache consistency management thereof, which relates to the field of data processing technology. Data exchange and information access between various components are performed through the connection of a central exchange block, a system main memory and a core module; cache information of each core is recorded through the core module; data read application information is obtained, core data holding information is obtained according to the data read application information, and a core that sends a data read request is converted according to the core data holding information; core update cache demand information is obtained, a cache management unit updates a memory data block, and resets a cache management table. Through a unique central exchange block and high-speed memory design, etc., a more flexible and efficient cache consistency solution is provided, which is suitable for more multi-core processor application scenarios.

The invention relates to a task scheduling method, system and device based on a multi-core processor and a medium. In the application, cores of a processor are divided into different core pools, and when a target task sent by a user side is executed, a target core can be selected from the corresponding core pool to execute the target task based on priority information of the target task; through the mode, core resources in different core pools can be provided for tasks with different priorities, so that core resource competition is reduced, core scheduling distribution is planned, mutual interference among the tasks in the core pools is reduced, and the real-time task response capability is improved; when the target task is executed, if it is detected that the user side is in the inactive state, the target core is automatically released, core resources are prevented from being occupied, and the resource utilization rate is increased; moreover, when the user side is reconnected, the target task can be continuously executed according to the task operation record, the working state of the uncompleted task is recovered in time, and resource waste caused by repeated execution of the task is avoided.

This invention discloses a multi-agent collaboration method and system for domestically developed operating systems, belonging to the field of intelligent technology for domestically developed desktop operating systems. It aims to solve the core problems of existing solutions, such as lack of collaboration standards, black-box decision-making, and difficulty in reusing experience. The method establishes a collaboration system by building an MCP protocol stack and a native DBus mapping, generating a structured inference chain through the System-2 inference engine, and achieving a closed loop through dynamic task distribution, three-level memory reuse, and visual auditing. The system includes a main agent, a cluster of sub-agents, and multiple core modules to collaboratively support the implementation of the method. This solution enables plug-and-play intelligent agents, full traceability of decision-making, and improves the execution efficiency of similar tasks by more than 30%. It is deeply adapted to multiple versions of openKylin and domestically developed hardware, meeting the security compliance and efficient collaboration needs of key scenarios such as government affairs and finance.

This invention relates to a 5G traffic filtering method, system, device, and storage medium based on a multi-core processing unit. The method includes: receiving raw traffic; copying and performing basic parsing on the raw traffic; distributing filtered user plane traffic and signaling plane traffic to a multi-core processing unit; performing deep protocol parsing on the received user plane traffic; dynamically identifying 5G user plane interface traffic based on the protocol characteristics of the user plane traffic; generating a first dynamic rule; performing deep protocol parsing on the received signaling plane traffic; generating a second dynamic rule; distributing the first and second dynamic rules to a switching chip; performing final filtering on the traffic based on the first and second dynamic rules; and outputting the target 5G traffic. Through the synergistic effect of the first and second dynamic rules, the accuracy and automation level of signaling traffic filtering are improved, while significantly simplifying the configuration and maintenance complexity of the equipment.

Method and apparatus for dynamically selecting a super queue size for CPUs with a higher number of cores. An apparatus comprises a plurality of compute modules, each module comprising a plurality of processor cores with integrated first-level (L1) caches and a shared second-level (L2) cache, a plurality of last-level caches (LLCs) or LLC blocks, and a plurality of memory interface blocks connected via a mesh interconnect. A compute module is configured to arbitrate access to the shared L2 cache and enqueue L2 cache misses into a super queue (XQ). The compute module is further configured to dynamically adjust the size of the XQ during runtime operations. The compute module tracks parameters including an L2 miss rate or count and an LLC hit latency and adjusts the XQ size as a function of these parameters.A lookup table using the L2 miss rate / count and LLC hit latency can be implemented to dynamically select the XQ size.

The invention discloses a many-core system performance verification method based on a portable excitation standard, and belongs to the technical field of integrated circuit design verification, the implementation of the method comprises the following steps: designing PSS actions including atomic actions, composite actions and application-level actions, and realizing precise modeling of hardware resource and data dependence; the method comprises the following steps: optimizing the use of an L1 memory by adopting a double-buffer technology, dividing the L1 memory into independent buffer regions which comprise at least two input buffer regions and two output buffer regions, and realizing data circulation parallelization; quantizing component execution time based on a cost function, and providing a data basis for scheduling optimization; the action priority is determined based on a cost function, and scheduling is optimized for a single-core system and a multi-core system; and cross-stage verification is realized based on the portability of the PSS. According to the method, accurate positioning and optimization of the performance bottleneck of the many-core system are realized, rapid iteration of the AI algorithm and hardware can be adapted without reconstructing a verification framework, and the verification efficiency is effectively improved.

The invention relates to a method for determining whether an anomaly exists in a communication channel within at least one multicore processor or multicore microcontroller, in particular within a vehicle, wherein the at least one multicore processor or multicore microcontroller comprises a plurality of cores, characterized in that communication between at least two of the plurality of cores is monitored, and a decision is made based on a monitoring result as to whether the anomaly exists or not.

The invention relates to the technical field of computers, in particular to a chip verification method based on multi-core constraint solving, electronic equipment and a medium, and the method comprises the following steps: S1, a main thread obtains a candidate solver core set of a target constraint problem; s2, the main thread obtains M sub-threads; s3, the main thread copies the target constraint problem into M copies and sends the M copies to each Wm, and each Wm executes the target constraint problem in parallel; s4, returning a solving result of the optimal Cm by the main thread, and generating a target solver core set; s5, when the target constraint problem is obtained again, D1 is selected to solve the target constraint problem; s6, monitoring the function coverage rate increasing speed, and if the coverage rate increasing speed meets a preset coverage rate increasing speed reducing condition, executing S7; and S7, selecting a target Di, switching to the target Di to solve the target constraint problem, and returning to execute the step S6. According to the invention, the convergence speed of the chip function coverage rate is improved.

The invention relates to a 5G traffic screening method, system and device based on a multi-core processing unit, and a storage medium, and the method comprises the steps: accessing original traffic, carrying out the copying and basic analysis of the original traffic, distributing the screened user plane traffic and signaling plane traffic to the multi-core processing unit, carrying out the deep protocol analysis of the received user plane traffic, and transmitting the received user plane traffic to the multi-core processing unit; dynamically identifying 5G user plane interface traffic according to the protocol characteristics of the user plane traffic, and generating a first dynamic rule; performing deep protocol analysis on the received signaling plane flow to generate a second dynamic rule; and issuing the first dynamic rule and the second dynamic rule to a switching chip, performing final screening on the traffic according to the first dynamic rule and the second dynamic rule, and outputting a target 5G traffic. Through the cooperative effect of the first dynamic rule and the second dynamic rule, the accuracy and automation level of signaling traffic filtering are improved, and meanwhile, the configuration and operation and maintenance complexity of equipment are greatly simplified.

The present invention belongs to the technical field of multi-core interrupt processing, and particularly relates to an interrupt processing device, an interrupt method, and a high-performance server CPU. The present invention comprises: an interrupt receiving module for receiving and caching interrupt request packets from a core; the interrupt request data in the interrupt request packet includes the interrupt type and interrupt target number information; an internal interrupt processing module for processing interrupt requests from the core, and processing the interrupt request according to the status of the target core; an external interrupt processing module for processing interrupt requests from outside the core, synchronizing the external interrupt signal, combining and packaging the external interrupt request according to the interrupt register module and the status of the target core, and then sending the combined and packaged external interrupt request to the interrupt round-robin arbitration module; and an interrupt round-robin arbitration module for performing round-robin arbitration on the interrupt request. The present invention centrally manages interrupts in the chip, facilitates the management of system software, and improves the stability and reliability of the system.

The invention discloses a control method and device of a central processing unit, equipment and a medium, and generally relates to the technical field of computers. The method comprises the steps that using parameters of a central processing unit are obtained, the using parameters comprise the using parameters of the central processing unit, and the central processing unit is a multi-core central processing unit; according to the use parameters, obtaining the use rate of each core currently started by the central processing unit; under the condition that the utilization rate of each currently started core is within a preset utilization rate range, determining a first core with the lowest utilization rate in each currently started core, and determining a target process corresponding to the first core, releasing the corresponding relationship between the target process and the first core and interrupting the operation of the first core until the utilization rate of any one of the cores currently started by the central processing unit exceeds a preset utilization rate range; the first core is enabled. The power consumption of the CPU can be reduced in time on the premise that the performance and the service life of the CPU are guaranteed.

The invention relates to the technical field of industrial control, in particular to a program robustness test method, a computer readable storage medium and a program product.The method comprises the steps that a target program is compiled in multiple compiling modes, and program files of multiple versions are obtained; acquiring operation data of the PLC equipment when the PLC equipment operates the program file of each version; and determining the robustness of the target program according to the running data. The invention provides a program robustness test method based on multi-core execution and compilation optimization, which comprises the following steps: using different execution core numbers and compilation options in a program compilation stage, programming compiled programs into PLCs (Programmable Logic Controller) of the same type and the same batch, and monitoring the running states of the PLCs under different working conditions by using a test instrument, so as to test the robustness of the PLCs. And through KPI waveform clustering analysis, potential problems of the program are identified and positioned, and the method has important significance for guaranteeing stable operation of the PLC control system under various complex working conditions.

This invention provides a dynamic model switching framework for AI inference optimization methods and systems on edge devices, relating to the field of AI optimization technology. The methods include: correcting quantization errors by training a quantization compensation model through federated learning; constructing a hierarchical heterogeneous resource management system to achieve multi-core collaborative scheduling; integrating compensation parameters into FPGA acceleration circuits and employing intelligent power balancing technology; and utilizing graph neural networks to construct a dynamic decision engine to trigger model switching. This invention achieves a balance between high-precision AI inference and low-power consumption requirements on edge devices, improving computing resource utilization efficiency and reducing energy consumption.

The invention relates to the technical field of power grid control, in particular to an industrial green micro-grid multi-energy complementation and comprehensive energy efficiency evaluation method, which comprises the following steps: S1, standard adaptive networking construction: establishing industrial green micro-grid standard system requirements, and constructing a networking architecture including interface standardization, safety standardization and control standardization; s2, multi-scene adaptive scheduling control: selecting a proper optimization framework based on a prediction error-standard threshold value, and performing multi-type energy storage differential cooperative control and multi-core scene standardized control; s3, simulation and verification: verifying the validity of the scheme by simulation data; and S4, full-dimensional energy efficiency evaluation and closed-loop optimization: constructing a multi-dimensional evaluation system, determining an index weight by adopting an analytic hierarchy process, calculating an energy efficiency comprehensive score through a fuzzy comprehensive evaluation method, dynamically adjusting a weight coefficient in combination with micro-grid operation data, and adapting to configuration differences of equipment in different factory areas.

The application provides a solid state storage device temperature control method, including a solid state disk master control chip of a multi-CPU core architecture, a front-end core Core0 periodically sampling solid state disk disc each part sensor temperature value, and calculating a composite temperature, sending the composite temperature to an auxiliary core mCore4; a back-end core Core2, Core3 real-time collecting respective working logical unit number quantity, and feeding back to the auxiliary core mCore4; the auxiliary core mCore4 accumulates and averages the sampling data, and detects whether the composite temperature exceeds a conditional threshold value, if exceeding the threshold value, then according to the actual load level and temperature grade adjustment logical unit number maximum concurrent number limit value; the back-end core Core2, Core3 gets the concurrent number limit value from the auxiliary core mCore4, and adjusts the flash memory controller. The application saves computing power and improves input and output performance, ensures that the solid state disk temperature and power consumption are limited without losing too much performance, and guarantees the accuracy and real-time of the maximum logical unit number concurrent number calculation result.