31 results about "Multicore computing" patented technology

The invention discloses a PLC scheduling algorithm based on a multi-core soft real-time operating system, and relates to the technical field of voltage control, and the algorithm comprises the following four steps: 1, starting a target industrial control system, completing hardware self-inspection, memory allocation and communication module starting, and sending an initialization ready signal after confirming that an assembly is normal; 2, according to PLC task functions and real-time performance, four types of standardized tasks are divided, priority levels are defined, sub-priorities are configured, a dependency relationship is identified, and a task chain is established; 3, counting the number of tasks and task chains, distributing resources by using multiple binding cores, and constructing a global ready queue to adapt to dynamic scheduling; and 4, monitoring an interrupt event through an interrupt manager, realizing high-priority task preemption by semaphores, and allocating tasks to corresponding CPU cores, so that the problems of soft real-time multi-core task preemption and data conflict are solved, the scheduling real-time performance and the data security are improved, the system failure rate is reduced, and the industrial control efficiency and stability are improved.

The invention relates to a 5G signaling plane traffic screening method based on a multi-core processing unit, and the method comprises the steps: receiving network mirror image traffic through a physical interface unit, and screening out transmission control protocol traffic; the switching chip unit identifies HTTP / 2 protocol traffic from transmission control protocol traffic according to a target port number or an application layer protocol handshake feature, and forwards the HTTP / 2 protocol traffic to the multi-core processing unit; the binary framing structure of the HTTP / 2 protocol is analyzed, a data frame and a control frame are distinguished, and an HTTP request head is restored; analyzing and decoding an HTTP request header, and extracting a pseudo header field of a uniform resource identifier path in the HTTP request header; generating a traffic filtering rule corresponding to the service signaling traffic bearing the specific network function; and issuing the generated flow filtering rule to a switching chip unit, and outputting specified 5G signaling plane flow. The method automatically adapts to the dynamic change of the 5G network element, and effectively solves the problem of traffic loss or inaccuracy caused by difficult maintenance and untimely updating of the static work parameter data.

The embodiment of the invention provides a parallel simulation method, system and device of a multi-core processor and a storage medium, the parallel simulation method of the multi-core processor comprises the following steps: creating a context for each of a plurality of cores of the multi-core processor, the plurality of contexts corresponding to the plurality of cores being mutually independent; a system thread is created for each context of the plurality of contexts such that the plurality of cores are allocated in different contexts into different system threads that are automatically scheduled to different processor cores for execution. According to the parallel simulation method of the multi-core processor provided by the embodiment of the invention, the parallel simulation is realized based on a plurality of independent contexts, the problem of low simulation efficiency in a traditional simulation framework is effectively solved, and the execution speed of the simulation is remarkably improved through a multi-thread simulation technology.

A system may comprise one or more devices in a network. The devices may be configured to: receive network slice performance data; and determine whether a network slice to which a User Equipment (UE) device is connected meets one or more criteria based on the network slice performance data. When the network slice does not meet the one or more criteria, the one or more devices may identify a different network slice that meets the one or more criteria; obtain an application identifier (app ID) or a traffic descriptor from a UE Route Selection Policy (URSP) rule whose slice ID matches a slice ID of the different network slice; and send the app ID or the traffic descriptor to the UE device.

This invention provides a method for improving the real-time performance of Linux operating system applications based on a multi-core CPU. The method includes, during system startup, modifying Linux kernel startup parameters to reallocate tasks across the cores of the multi-core CPU, concentrating basic Linux system tasks on the zeroth core; when the target application creates a task, it sets task affinity based on the task's real-time requirements by calling system functions; non-real-time critical tasks are assigned to the first core; real-time critical tasks are assigned to the second core; and sub-real-time critical tasks are assigned to the third core. This invention effectively reduces the response latency of specific interrupts with strict real-time requirements in the Linux system by utilizing different cores of a multi-core CPU to allocate different tasks, improving device real-time performance and meeting the real-time requirements of fields such as power distribution automation.

This invention discloses a multi-agent collaboration method and system for domestically developed operating systems, belonging to the field of intelligent technology for domestically developed desktop operating systems. It aims to solve the core problems of existing solutions, such as lack of collaboration standards, black-box decision-making, and difficulty in reusing experience. The method establishes a collaboration system by building an MCP protocol stack and a native DBus mapping, generating a structured inference chain through the System-2 inference engine, and achieving a closed loop through dynamic task distribution, three-level memory reuse, and visual auditing. The system includes a main agent, a cluster of sub-agents, and multiple core modules to collaboratively support the implementation of the method. This solution enables plug-and-play intelligent agents, full traceability of decision-making, and improves the execution efficiency of similar tasks by more than 30%. It is deeply adapted to multiple versions of openKylin and domestically developed hardware, meeting the security compliance and efficient collaboration needs of key scenarios such as government affairs and finance.

This invention relates to a 5G traffic filtering method, system, device, and storage medium based on a multi-core processing unit. The method includes: receiving raw traffic; copying and performing basic parsing on the raw traffic; distributing filtered user plane traffic and signaling plane traffic to a multi-core processing unit; performing deep protocol parsing on the received user plane traffic; dynamically identifying 5G user plane interface traffic based on the protocol characteristics of the user plane traffic; generating a first dynamic rule; performing deep protocol parsing on the received signaling plane traffic; generating a second dynamic rule; distributing the first and second dynamic rules to a switching chip; performing final filtering on the traffic based on the first and second dynamic rules; and outputting the target 5G traffic. Through the synergistic effect of the first and second dynamic rules, the accuracy and automation level of signaling traffic filtering are improved, while significantly simplifying the configuration and maintenance complexity of the equipment.

The invention discloses a many-core system performance verification method based on a portable excitation standard, and belongs to the technical field of integrated circuit design verification, the implementation of the method comprises the following steps: designing PSS actions including atomic actions, composite actions and application-level actions, and realizing precise modeling of hardware resource and data dependence; the method comprises the following steps: optimizing the use of an L1 memory by adopting a double-buffer technology, dividing the L1 memory into independent buffer regions which comprise at least two input buffer regions and two output buffer regions, and realizing data circulation parallelization; quantizing component execution time based on a cost function, and providing a data basis for scheduling optimization; the action priority is determined based on a cost function, and scheduling is optimized for a single-core system and a multi-core system; and cross-stage verification is realized based on the portability of the PSS. According to the method, accurate positioning and optimization of the performance bottleneck of the many-core system are realized, rapid iteration of the AI algorithm and hardware can be adapted without reconstructing a verification framework, and the verification efficiency is effectively improved.

The invention relates to a 5G traffic screening method, system and device based on a multi-core processing unit, and a storage medium, and the method comprises the steps: accessing original traffic, carrying out the copying and basic analysis of the original traffic, distributing the screened user plane traffic and signaling plane traffic to the multi-core processing unit, carrying out the deep protocol analysis of the received user plane traffic, and transmitting the received user plane traffic to the multi-core processing unit; dynamically identifying 5G user plane interface traffic according to the protocol characteristics of the user plane traffic, and generating a first dynamic rule; performing deep protocol analysis on the received signaling plane flow to generate a second dynamic rule; and issuing the first dynamic rule and the second dynamic rule to a switching chip, performing final screening on the traffic according to the first dynamic rule and the second dynamic rule, and outputting a target 5G traffic. Through the cooperative effect of the first dynamic rule and the second dynamic rule, the accuracy and automation level of signaling traffic filtering are improved, and meanwhile, the configuration and operation and maintenance complexity of equipment are greatly simplified.

The invention relates to the technical field of power grid control, in particular to an industrial green micro-grid multi-energy complementation and comprehensive energy efficiency evaluation method, which comprises the following steps: S1, standard adaptive networking construction: establishing industrial green micro-grid standard system requirements, and constructing a networking architecture including interface standardization, safety standardization and control standardization; s2, multi-scene adaptive scheduling control: selecting a proper optimization framework based on a prediction error-standard threshold value, and performing multi-type energy storage differential cooperative control and multi-core scene standardized control; s3, simulation and verification: verifying the validity of the scheme by simulation data; and S4, full-dimensional energy efficiency evaluation and closed-loop optimization: constructing a multi-dimensional evaluation system, determining an index weight by adopting an analytic hierarchy process, calculating an energy efficiency comprehensive score through a fuzzy comprehensive evaluation method, dynamically adjusting a weight coefficient in combination with micro-grid operation data, and adapting to configuration differences of equipment in different factory areas.

The application provides a solid state storage device temperature control method, including a solid state disk master control chip of a multi-CPU core architecture, a front-end core Core0 periodically sampling solid state disk disc each part sensor temperature value, and calculating a composite temperature, sending the composite temperature to an auxiliary core mCore4; a back-end core Core2, Core3 real-time collecting respective working logical unit number quantity, and feeding back to the auxiliary core mCore4; the auxiliary core mCore4 accumulates and averages the sampling data, and detects whether the composite temperature exceeds a conditional threshold value, if exceeding the threshold value, then according to the actual load level and temperature grade adjustment logical unit number maximum concurrent number limit value; the back-end core Core2, Core3 gets the concurrent number limit value from the auxiliary core mCore4, and adjusts the flash memory controller. The application saves computing power and improves input and output performance, ensures that the solid state disk temperature and power consumption are limited without losing too much performance, and guarantees the accuracy and real-time of the maximum logical unit number concurrent number calculation result.

The invention relates to the technical field of data analysis, in particular to an analysis terminal for employee growth process monitoring and ability portraying, which integrates a multi-core function unit and an AI big data model and realizes whole-process intelligentization of employee growth management. Wherein the weak link, the lifting strategy generation unit and the growth path optimization unit are respectively provided with a special embedded processing module, so that quick calling of an algorithm and efficient processing of data are guaranteed; through comparison of post standards and employee ability data, weak links are accurately identified and roots are mined, a strategy is intelligently matched and individually optimized and improved, and a growth path is dynamically planned in combination with employee portraits and weak spots. The terminal also has the functions of data encryption storage, visual presentation, multi-terminal synchronization and the like, meets the requirements of large, medium and small enterprises, greatly improves the talent management efficiency and precision, and provides scientific data support and decision basis for the talent cultivation of the enterprises.

This invention relates to the fields of computer operating systems and audio processing technology, specifically to a real-time scheduling system for Hi-Fi audio playback based on Linux. The system includes a real-time core that handles only real-time tasks, a buffer management module that maintains a receive buffer and a playback buffer, a multi-core task allocation module that distributes real-time audio tasks to multiple real-time cores, an RTOS preemptive task scheduling module that preempts real-time cores, a decoding module that performs decoding tasks based on data in the receive buffer, and a playback module that performs playback tasks based on data in the playback buffer. This invention, through its unique core isolation architecture, preemptive scheduling mechanism, and dual-buffer design, ensures timely response to real-time audio tasks, solving the problem that existing Linux-based audio systems struggle to meet the real-time requirements of Hi-Fi audio.

A multicore computing device includes a memory and a processor coupled to the memory. The processor includes plural cores and a multiple input multiple output (MIMO) block coupled to the cores. The MIMO block receives a halt request from a first core of the cores, transmits a core-halt request to one or more other cores other than the first core, to halt execution of the one or more other cores, and permits the first core to lock with a shared resource.

This invention discloses a multi-core-based task scheduling method, apparatus, device, and medium, relating to the field of task processing. The method includes: a main core iterating through the trigger functions of all application tasks via a main task, and determining at least one application task to be scheduled based on the trigger functions; each application task has its corresponding trigger function and task main function; the main task scheduling at least one application task to the main core and / or slave cores according to a task scheduling strategy; the main core and / or slave cores obtaining the at least one application task scheduled by the main task through slave tasks; the slave tasks executing the corresponding application task's task main function according to the application task cycle, and feeding back the task execution status of the application task and the real-time remaining computing power of the main core and / or slave cores to the main core. This invention fully utilizes the computing power of multiple cores to execute user business logic, improving the overall system throughput, reducing the worst-case execution time of tasks, and enhancing real-time performance.

The application relates to the chip technical field and provides a bus access permission allocation method, device, equipment, medium and product.The method comprises the following steps: acquiring all source units initiating access requests for a target interface; generating a random number, the random number falling within a numerical range determined by the number of the source units; establishing a mapping relationship between the physical identifiers of the source units and the continuous index values within the numerical range; searching the mapping relationship according to the random number, selecting the source unit with the consistent index value and the random number as a target source unit according to the mapping relationship, and allocating the bus access permission to the target source unit.The application avoids the problem that the performance of individual cores is limited due to the fixed polling sequence, eliminates the damage of the barrel effect to the overall performance of the GPU, and improves the bus bandwidth utilization and the cooperative operation efficiency of the multi-core processor under complex working conditions.

The application provides a relay protection load balancing method based on a multi-core architecture, and relates to the technical field of relay protector control.The application judges the load of each core module according to the daily task being executed by each core module and the weight and execution time of the daily task in the queue, obtains the load conditions of all core modules, then distributes the emergency task caused by the abnormal equipment to the lowest core module according to the weight of the emergency task, and finally sorts the emergency task in the core module according to the running time of the emergency task, so as to ensure the smooth completion of the emergency task, realize the load balancing of the multi-core module, and enable the relay protector to make a decision for the abnormal equipment within a specified time, thereby ensuring the safety of the equipment.

The application relates to a 5G signaling surface flow screening method based on a multi-core processing unit, which comprises the following steps: receiving network mirror flow through a physical interface unit, and screening out transmission control protocol flow; a switching chip unit identifies HTTP / 2 protocol flow from the transmission control protocol flow according to a target port number or an application layer protocol handshake feature, and forwards the HTTP / 2 protocol flow to a multi-core processing unit; a binary framing structure of the HTTP / 2 protocol is parsed, data frames and control frames are distinguished, and an HTTP request header is restored; the HTTP request header is analyzed and decoded, and a uniform resource identifier path pseudo header field in the HTTP request header is extracted; flow filtering rules corresponding to service signaling flow bearing specific network functions are generated; the generated flow filtering rules are issued to the switching chip unit, and specified 5G signaling surface flow is output. The application automatically adapts to the dynamic change of 5G network elements, effectively solves the problem of flow loss or inaccuracy caused by the difficulty in maintaining static work parameter data and the delay in updating.

The subject technology relates to scheduling resources. For instance, an example method determines containers running on cores of a processor. The method further includes acquiring parameters of the containers. The method further includes determining a designated core from the cores that is adapted to a target container in the containers based on the parameters and a scheduling policy. The method further includes scheduling the target container in the containers to run on the designated core adapted to the container. In this way, containers can be scheduled to processor cores that are most suitable for their running, so that the response speed of services is increased and the mutual interference of resource contention between cores is reduced, thus improving the resource utilization and overall performance of the system.

The invention discloses a power-off method and device of a multi-core server, a power-on method and device of the multi-core server, equipment and a medium, and the method comprises the steps: determining a first processor core to be powered off, and controlling the first processor core to execute preparatory work before power-off; the preparatory work is used for controlling the first processor core to enter an idle state; after the preparatory work is executed, determining a second processor core from the processor cores which are in the running state at present; the processor cores in the running state at present comprise processor cores except the first processor core; switching the operation mode of the second processor core from the first mode to a second mode, and controlling the second processor core to turn off the power supply of the first processor core in the second mode; the first mode is a mode for operating an operating system, and the second mode is a mode for accessing system firmware, so that the reliability and success rate of powering off the processor core are improved.

The application provides a loop current method-based parallel simulation implementation method of a power electronic system, and belongs to the application of computer simulation technology in the field of power electronics. The application comprises a processor and memory allocation method and a parallel simulation calculation control process. The processor and memory allocation method utilizes the decoupling characteristics of the simulation algorithm data structure based on the loop current method, preferentially realizes the matching of the processor and the local memory, and improves the access efficiency between the processor and the memory in the calculation process. The parallel simulation calculation process control utilizes the parallelizable characteristics of the simulation algorithm calculation process based on the loop current method, preferentially realizes the parallel calculation of the unit circuit, and improves the calculation efficiency of the power electronic model in the calculation process. The application is suitable for the simulation of a power electronic model comprising a large number of repetitive power electronic modules, can utilize the advantages of the multi-processor and multi-core of a high-performance computer, and significantly improves the simulation efficiency of a large-scale power electronic system.

The invention discloses a Flash updating method based on a microcontroller. The method comprises the following steps: carrying out capacity-based partition configuration on a multi-CPU core program flash memory of the microcontroller, and configuring a first partition for storing stable firmware and a second partition for firmware to be updated for each core; remapping a fast serial interface of the information security core to the main control core, and establishing a parallel link between the main control core operation data flash memory and the information security core flash program flash memory; stable firmware is written into the first partition, a partition switching function is enabled, and when an update request is received during operation, new firmware is written into the second partition through a remapping interface in a multi-sector erasing and burst writing mode; and after the new firmware is subjected to integrity and function verification, modifying the starting configuration and switching to the second partition for starting. The technical effects that vehicle operation and firmware updating are parallel and do not interfere with each other, and the updating efficiency is high are achieved.

The invention discloses a task scheduling method, device and equipment based on multiple cores and a medium, and relates to the field of task processing, and the method comprises the steps that a main core traverses trigger functions of all application tasks through a main task, and determines at least one application task to be scheduled according to the trigger functions; each application task has a corresponding trigger function and a task main function; the master task schedules at least one application task to the master core and / or the slave core according to a task scheduling strategy; the master core and / or the slave core obtains at least one application task scheduled by the master task through the slave task, the slave task executes a task main function of the corresponding application task according to an application task period, and the task execution state of the application task and the real-time residual computing power of the master core and / or the slave core are fed back to the master core. According to the method, the multi-core computing power is fully utilized to execute the service logic of the user, the overall throughput of the system is improved, the execution time of the worst case of the task is shortened, and the real-time performance is enhanced.

The invention relates to the technical field of debugging of large pumped storage power stations, in particular to a combined virtual simulation debugging system for a large pumped storage power station, which comprises a mathematical model of a pumped storage power station unit constructed in a Simulink environment, a switch logic and time sequence control model, a real-time communication and data interaction module, a virtual simulation module and a virtual simulation module, the control and human-computer interaction interface is established in an APP Designer environment; the mathematical model is divided into a plurality of simulation models after being decoupled, the simulation models are deployed on different cores of the multi-core CPU respectively, and independent simulation step length and simulation rate are set; and the switch logic and time sequence control model is used for performing logic and time sequence processing to realize time sequence and logic control simulation of each flow in the operation process of the pumped storage power station and corresponding working condition sub-flow control of different working condition conversion. Through the debugging system, deep fusion of multi-rate parallel simulation, real-time data interaction and intelligent process control can be realized, and high-precision and strong-interaction virtual debugging requirements are supported.

The application discloses a kind of server circuit and server, it is related to computer technical field, the server circuit includes: multiple mainboards;Fan plate is provided with substrate management controller, substrate management controller includes multiple cores, multiple cores are divided into shared core and multiple groups of management cores, multiple groups of management cores and multiple mainboards one-to-one correspondence;Shared core is used to receive the management instruction of any mainboard issued by management terminal, and sends management instruction to the management core of mainboard corresponding;Management core is used to manage the component of the corresponding mainboard based on management instruction.It is not necessary to configure substrate management controller for each mainboard by the application, and the hardware complexity and cost of server circuit are greatly reduced by the functional division of cores in single multi-core substrate management controller, to realize the parallel management of multiple mainboards.

The invention relates to a cooperative control method for improving the fault ride-through capability of a grid-forming type grid-connected system, belongs to the technical field of new energy grid-connected control and intelligent power grids, and aims to solve the problem that when the grid-forming type grid-connected system encounters a three-phase asymmetric fault, the fault ride-through capability of the grid-forming type grid-connected system cannot be improved. The problems of negative-sequence current accumulation, transient peak current impact, reactive power support imbalance, steady-state power deviation and the like generally exist. The method comprises the following steps: firstly, establishing an asymmetric fault mathematical model under the control of a network construction type VSG; secondly, constructing a positive and negative sequence separation virtual admittance model, and determining a core optimization variable; then, establishing a multi-core parameter objective function, and performing optimization by using an improved particle swarm algorithm containing adaptive inertia weight and covariance learning; finally, the optimized parameters are introduced into a VSG current control link, and active suppression of the current and stable support of the system voltage are achieved. According to the method, the fault current peak value can be remarkably reduced, the reactive power supporting capacity is improved, power balance is maintained, and therefore the fault ride-through performance of the grid-forming type grid-connected system is enhanced.

The invention discloses a chip computing power dynamic scheduling method based on proportional stress points, and relates to the technical field of chip computing power optimization and integrated circuit control. According to the method, a proportion reference model between chip operation parameters is established, operation data such as load, frequency, power consumption and temperature are collected in real time, proportion stress points influencing system stability are identified, and dynamic allocation and scheduling of computing power resources are carried out on the basis of the proportion stress points. And when the operation proportion deviates from the safety interval, operations such as migration, frequency limiting and load convergence are automatically carried out on the multi-core computing power, so that the chip always works in the optimal proportion interval. According to the method, the power consumption fluctuation and the performance jitter can be reduced while the computing power efficiency is ensured, the service life of the chip is prolonged, and the method is suitable for real-time computing power scheduling of various general and special computing chips such as a CPU, a GPU and an NPU.

The present application relates to the technical field of computer, especially to a chip verification method based on multi-core constraint solving, electronic equipment and medium, comprising: S1, the main thread acquires the candidate solver core set of the target constraint problem; S2, the main thread acquires M sub-threads; S3, the main thread copies M copies of the target constraint problem, and sends each W m , Each W m performs the target constraint problem in parallel; S4, the main thread returns the optimal C m solution result, and generates the target solver core set; S5, when the target constraint problem is acquired again, the target constraint problem is solved by selecting D1 first; S6, the coverage rate improvement speed is monitored, if the coverage rate improvement speed meets the preset coverage rate improvement speed reduction condition, then S7 is executed; step S7 selects a target D i , switches to the target D i to solve the target constraint problem, and returns to step S6. The present application improves the convergence speed of chip function coverage rate.

The invention relates to the technical field of artificial intelligence algorithms, and discloses a technical demand achievement matching evaluation method and system based on multi-core collaboration, and the method comprises the following steps: carrying out the collaborative analysis through combining an enterprise technical demand prediction agent, an achievement matching agent, a technical broker agent, an industry-university-research cooperation agent and a collaborative agent; the problems of butt joint gaps and low cooperation efficiency caused by information asymmetry in industry-university-research cooperation are solved. According to the method, an information barrier of technology supply and demand can be broken through, accurate and efficient matching of supply and demand parties is realized, and key data driven decision support is provided for industrial chain cooperation and achievement promotion.

This invention discloses a multi-core CPU power consumption dynamic adjustment system for an all-in-one computer, comprising: a parameter acquisition unit, a benchmark setting unit, a demand analysis unit, and a dynamic adjustment unit. The parameter acquisition unit collects operating status parameters of the all-in-one computer's CPU. The benchmark setting unit sets adjustment benchmarks and dynamic adjustment mechanisms for each parameter based on the type of the operating status parameters. This invention relates to the field of computer hardware power consumption management technology. This multi-core CPU power consumption dynamic adjustment system for an all-in-one computer collects real-time operating frequency, operating voltage, core temperature, load rate, and instantaneous power consumption parameters of each CPU core. Combined with the adjustment benchmarks and dynamic adjustment mechanisms set by the benchmark setting unit, and the precise comparison and analysis of parameters by the demand analysis unit, it can accurately determine the direction and magnitude of power consumption adjustment based on the actual operating status of the CPU, achieving precise power consumption adjustment and avoiding unnecessary power waste.