Method and device for synchronizing forwarding table of ultra-bandwidth multi-core Ethernet switch chip

Abstract

The invention discloses a method and a device for synchronizing a forwarding table of an ultrahigh-bandwidth multi-core Ethernet switch chip. The method comprises the following steps of: configuring amaster working core and a slave working core; establishing an inter-core communication interface between the master working core and the slave working core; enabling the master working core to receive the processing request of the master working core and writes a processing result into the master working core, meanwhile, sending the processing result to the auxiliary working core, and enabling the auxiliary working core to write information into the master working core; enabling the slave working core to receive the processing request of the slave working core and send the processing requestto the master working core, enabling the master working core to write a processing result into the slave working core and sends the processing result to the slave working core, and the slave working core writes information into the slave working core; and enabling the master working core to perform entry synchronization according to a preset period. According to the invention, the interoperation problem of two cores on one package is effectively solved, so that the external system behavior of the multi-core Ethernet switch chip is the same as that of a single core.

Description

technical field [0001] The invention belongs to the technical field of network communication, and in particular relates to a method and a device for synchronizing forwarding tables of an ultra-bandwidth multi-core Ethernet switching chip. Background technique [0002] With the development of scenarios such as ultra-large-scale cloud networks, storage networks, and HPC (High Performance Computing, high-performance computer clusters), the amount of data exchange on the network is increasing, and the processing capacity of single chips is constantly increasing, from Gbps to Tbps Magnitude. The current chip production process usually adopts 14nm / 12nm or 7nm / 6nm, and its intellectual property core (IP core) can run at a maximum clock frequency of 1.05GHz or 1.7GHz. Under the premise of a single pipeline core, it cannot support processing up to 25.6Tbps ability. In order to cope with the rapidly rising packet processing bandwidth, multi-core design has become the development dir...

AI Technical Summary

Problems solved by technology

The current chip production process usually adopts 14nm / 12nm or 7nm / 6nm, and its intellectual property core (IP core) can run at a maximum clock frequency of 1.05GHz or 1.7GHz. Under the premise of a single pipeline core, it cannot support processing up to 25.6Tbps ability

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