A method for time synchronization of multi-core Ethernet switching chips

A chip exchange and time synchronization technology, applied in transmission systems, electrical components, etc., can solve problems such as inconsistencies in counter reset signals and differences in counter values

Active Publication Date: 2022-01-11
SUZHOU CENTEC COMM CO LTD
View PDF18 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The two Dies are initialized independently. After the initialization is completed, since the two Dies have counters, the time to release the counter reset signal is not consistent. Therefore, even if the two counters can use the same reference clock, the counter values ​​​​on the two Dies will still be different. has a difference

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A method for time synchronization of multi-core Ethernet switching chips

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0028] A method for time synchronization of a multi-core Ethernet switching chip disclosed by the present invention implements synchronization between two cores by adding a set of self-synchronization mechanisms to free counters of the two cores.

[0029] Such as figure 1 As shown, a method for time synchronization of a multi-core Ethe...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a method for time synchronization of a multi-core Ethernet switching chip. By adding a set of self-synchronization mechanism to the free counters of the two cores, the calibration between the two cores is completed, and the two cores are packaged in one package. Due to the interoperability problem on the Internet, the switch chip designed using this scheme has no difference in behavior from the single-core chip when supporting the time synchronization protocol.

Description

technical field [0001] The invention belongs to the technical field of time synchronization of multi-core Ethernet switching chips, and in particular relates to a method for time synchronization of multi-core Ethernet switching chips. Background technique [0002] With the development of ultra-large-scale cloud networks, storage networks, and HPC (high-performance computing) scenarios, the amount of data exchanged on the network is increasing, and the highest single-chip processing capacity continues to rise, from Gbps to Tbps. However, the current chip production process is 14nm / 12nm or 7nm / 6nm, and its IP core (Intellectual Property core, intellectual property core) can run at a clock frequency of up to 1.05GHz or 1.7GHz respectively. Under the premise of a single pipeline core, it cannot support a processing capacity of up to 25.6Tbps. [0003] From an engineering point of view, in order to cope with the rapidly increasing packet processing bandwidth, multi-core design h...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): H04L49/10H04L49/351H04L49/109
CPCH04L49/10H04L49/351H04L49/109
Inventor 蒋震方沛昱夏杰龚海东
Owner SUZHOU CENTEC COMM CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap