A method for time synchronization of multi-core Ethernet switching chips

Abstract

The invention discloses a method for time synchronization of a multi-core Ethernet switching chip. By adding a set of self-synchronization mechanism to the free counters of the two cores, the calibration between the two cores is completed, and the two cores are packaged in one package. Due to the interoperability problem on the Internet, the switch chip designed using this scheme has no difference in behavior from the single-core chip when supporting the time synchronization protocol.

Description

technical field [0001] The invention belongs to the technical field of time synchronization of multi-core Ethernet switching chips, and in particular relates to a method for time synchronization of multi-core Ethernet switching chips. Background technique [0002] With the development of ultra-large-scale cloud networks, storage networks, and HPC (high-performance computing) scenarios, the amount of data exchanged on the network is increasing, and the highest single-chip processing capacity continues to rise, from Gbps to Tbps. However, the current chip production process is 14nm / 12nm or 7nm / 6nm, and its IP core (Intellectual Property core, intellectual property core) can run at a clock frequency of up to 1.05GHz or 1.7GHz respectively. Under the premise of a single pipeline core, it cannot support a processing capacity of up to 25.6Tbps. [0003] From an engineering point of view, in order to cope with the rapidly increasing packet processing bandwidth, multi-core design h...

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Problems solved by technology

The two Dies are initialized independently. After the initialization is completed, since the two Dies have counters, the time to release the counter reset signal is not consistent. Therefore, even if the two counters can use the same reference clock, the counter values ​​​​on the two Dies will still be different. has a difference

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