Memory device

Abstract

A memory device in a microprocessor, in which the microprocessor is coupled to a host, includes a volatile memory cell, a non-volatile memory array, and a controller. Write data is written into a first memory page of the nonvolatile memory array corresponding to a write instruction issued by a host, and the controller loads data of the first memory page into the volatile memory unit and updates the volatile memory unit by using the write data.

Description

Technical Field

[0001] The present invention relates to a memory device and a data access method thereof, and in particular to a non-volatile memory device combining a flash memory and a static random access memory and a data access method thereof. Background Art

[0002] Flash memory is a non-volatile memory that allows data to be deleted and written multiple times and is widely used in various electronic devices. A flash memory includes multiple memory pages, and each memory page includes multiple bit groups. When the flash memory performs read operations, write operations, and erase operations, it is often necessary to operate in memory pages.

[0003] When an external host wants to write to the internal flash memory of a microprocessor, the external host usually needs to compare the data stored in the flash memory with the write data to see if they match, then determine whether to erase the flash memory, and then write the write data into the flash memory.

[0004] However, for the external host, comparing data will generate a huge burden, and the operation of accessing the flash memory is cumbersome, and the slightest mistake will cause the write operation to fail, thereby reducing the data access efficiency. If the access method of the flash memory can be simplified to be similar to the access method of static random access memory, it will help improve the data access efficiency of the flash memory device. Summary of the invention

[0005] The present invention proposes a memory device and a data access method thereof. By mapping a non-volatile memory array to a volatile memory unit and allowing the memory device to automatically determine whether to perform an erase operation, the host accesses the non-volatile memory array in a manner similar to that of a static random access memory, which not only greatly reduces the system burden generated by the host accessing the non-volatile memory array, but also effectively improves the data access efficiency of the non-volatile memory array.

[0006] In view of this, the present invention provides a memory device located in a microprocessor, wherein the microprocessor is coupled to a host. The memory device includes a volatile memory unit, a non-volatile memory array, and a controller. In response to a write instruction issued by the host, a write data is written into a first memory page of the non-volatile memory array, the controller loads the data of the first memory page into the volatile memory unit, and updates the volatile memory unit using the write data.

[0007] According to an embodiment of the present invention, before the controller loads the data of the first memory page into the volatile memory unit, the controller determines whether the first memory page is mapped to the volatile memory unit. When it is determined that the first memory page is not mapped to the volatile memory unit, the controller maps the first memory page to the volatile memory unit.

[0008] According to an embodiment of the present invention, when it is determined that the first memory page has been mapped to the volatile memory unit, the controller directly updates the volatile memory unit using the write data.

[0009] According to an embodiment of the present invention, when it is determined that the first memory page is not mapped to the volatile memory unit, the controller further determines whether the volatile memory unit is mapped to a second memory page. When the controller determines that the volatile memory unit is mapped to the second memory page, the controller writes the data of the volatile memory unit to the second memory page of the non-volatile memory array.

[0010] According to an embodiment of the present invention, the controller further determines whether the data of the volatile memory cell is the same as the data of the second memory page of the non-volatile memory array. When the data of the volatile memory cell is the same as the data of the second memory page of the non-volatile memory array, the controller does not perform an erase operation on the second memory page or write the data of the volatile memory cell into the second memory page of the non-volatile memory array, but directly loads the data of the first memory page into the volatile memory cell.

[0011] According to one embodiment of the present invention, when the data of the volatile memory cell is different from the data of the second memory page of the non-volatile memory array, the controller first performs the erase operation on the second memory page, then writes the data of the volatile memory cell into the second memory page of the non-volatile memory array, and then loads the data of the first memory page into the volatile memory cell.

[0012] According to an embodiment of the present invention, when the controller loads the data of the second memory page into the volatile memory unit, the controller resets an erase indicator corresponding to the second memory page to a first state.

[0013] According to an embodiment of the present invention, when the data of the second memory page is loaded into the volatile memory unit and the controller updates the data of the volatile memory unit, the controller further determines whether the data of the volatile memory unit is the same as the data of the second memory page of the non-volatile memory array. When it is determined that the data of the volatile memory unit is different from the data of the second memory page of the non-volatile memory array, the controller sets the erase indicator to a second state.

[0014] According to one embodiment of the present invention, when the controller writes the data of the volatile memory cell into the second memory page of the non-volatile memory array, the controller corresponds to the erase indicator in the second state, first performs the erase operation on the second memory page of the non-volatile memory array, and then writes the data of the volatile memory cell into the second memory page.

[0015] According to an embodiment of the present invention, in response to a read command issued by the host to read a third memory page of the non-volatile memory array, the controller first determines whether to write the data of the volatile memory unit into the non-volatile memory array according to the erase indicator, and then loads the data of the third memory page into the volatile memory unit.

[0016] The present invention further provides a data access method, which is applicable to a memory device, wherein the memory device is coupled to a host and includes a volatile memory unit and a non-volatile memory array. The data access method includes: receiving a write command issued by the host, wherein the write command is used to write a write data into a first memory page of the non-volatile memory array; loading the data of the first memory page into the volatile memory unit; and updating the volatile memory unit using the write data.

[0017] According to one embodiment of the present invention, the data access method further includes: before loading the data of the first memory page into the volatile memory unit, determining whether the first memory page is mapped to the volatile memory unit; and when determining that the first memory page is not mapped to the volatile memory unit, mapping the first memory page to the volatile memory unit.

[0018] According to an embodiment of the present invention, the data access method further comprises: when it is determined that the first memory page has been mapped to the volatile memory unit, directly using the write data to update the volatile memory unit.

[0019] According to one embodiment of the present invention, the data access method further includes: when it is determined that the first memory page is not mapped to the volatile memory unit, further determining whether the volatile memory unit is mapped to a second memory page; and when it is determined that the volatile memory unit is mapped to the second memory page, writing the data of the volatile memory unit to the second memory page of the non-volatile memory array.

[0020] According to an embodiment of the present invention, the data access method further comprises: determining whether the data of the volatile memory cell is the same as the data of the second memory page of the non-volatile memory array; and when it is determined that the data of the volatile memory cell is the same as the data of the second memory page of the non-volatile memory array, directly loading the data of the first memory page into the volatile memory cell without performing an erase operation on the second memory page or writing the data of the volatile memory cell into the second memory page of the non-volatile memory array.

[0021] According to an embodiment of the present invention, the data access method further comprises: when it is determined that the data of the volatile memory cell is different from the data of the second memory page of the non-volatile memory array, performing the erase operation on the second memory page of the non-volatile memory array; after the erase operation, writing the data of the volatile memory cell into the second memory page of the non-volatile memory array; and after the step of writing the data of the volatile memory cell into the second memory page of the non-volatile memory array, loading the data of the first memory page into the volatile memory cell.

[0022] According to an embodiment of the present invention, when the data of the second memory page is loaded into the volatile memory unit, an erase indicator corresponding to the second memory page is reset to a first state.

[0023] According to an embodiment of the present invention, the data access method further includes: when the data of the second memory page is loaded into the volatile memory unit and the data of the volatile memory unit is updated, further determining whether the data of the volatile memory unit is the same as the data of the second memory page of the non-volatile memory array; and when it is determined that the data of the volatile memory unit is different from the data of the second memory page of the non-volatile memory array, setting the erase indicator to a second state.

[0024] According to one embodiment of the present invention, the step of writing the data of the volatile memory cell into the second memory page of the non-volatile memory array further includes: performing the erase operation on the second memory page of the non-volatile memory array corresponding to the erase indicator in the second state; and after the erase operation, writing the data of the volatile memory cell into the second memory page.

[0025] According to an embodiment of the present invention, the data access method further comprises: in response to a read command issued by the host to read a third memory page of the non-volatile memory array, determining whether to write the data of the volatile memory unit into the non-volatile memory array according to the erase indicator; and after the step of determining whether to write the data of the volatile memory unit into the non-volatile memory array according to the erase indicator, loading the data of the third memory page into the volatile memory unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram showing a microprocessor according to an embodiment of the present invention;

[0027] Figure 2 is a schematic diagram showing a judgment logic according to an embodiment of the present invention;

[0028] Figure 3 is a flow chart showing a data access method according to an embodiment of the present invention;

[0029] Figure 4 is a block diagram showing a microprocessor according to another embodiment of the present invention;

[0030] Figure 5 is a flow chart showing a data writing method according to another embodiment of the present invention; and

[0031] Figure 6 is a flow chart showing a data reading method according to another embodiment of the present invention.

[0032]

Explanation of symbols

[0033] 10: Host

[0034] 20: Communication interface

[0035] 100,400: Microprocessor

[0036] 110: Memory device

[0037] 111: Volatile memory cell

[0038] 112: Non-volatile memory array

[0039] 113: Controller

[0040] 300:Data access method

[0041] 500:Data writing method

[0042] 600:Data reading method

[0043] CW: Write command

[0044] CR: Read instruction

[0045] CLD: Load instruction

[0046] CUD: Update Command

[0047] CPG: Programming instructions

[0048] PG1: First memory page

[0049] PG2: Second memory page

[0050] PG3: Third memory page

[0051] PGER: Erasure Indicator

[0052] WDT: write data

[0053] ODT: Original Data

[0054] ADT: and data

[0055] S310~S340, S510~S560, S660: Step Flow DETAILED DESCRIPTION

[0056] The following description is an embodiment of the present application, which is intended to illustrate the general principles of the present application and should not be regarded as limiting the present application, the scope of which shall be determined by the claims.

[0057] It is worth noting that the content of the following application may provide multiple embodiments or examples for practicing different features of the present application. The specific component examples and arrangements described below are only used to briefly and concisely explain the spirit of the present application and are not used to limit the scope of the present application. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of reusing is only to provide a simplified and clear description, and is not used to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0058] In addition, the description of a feature being connected to, coupled to and / or formed on another feature described in the following specification may actually include multiple different embodiments, including that the features are directly in contact, or that other additional features are formed between the features, etc., so that the features are not in direct contact.

[0059] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "lower" side will become the element on the "upper" side.

[0060] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present application.

[0061] Some embodiments of the present application can be understood together with the drawings, and the drawings of the embodiments of the present application are also considered as part of the description of the embodiments of the present application. It should be understood that the drawings of the embodiments of the present application are not drawn in proportion to the actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present application. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present application.

[0062] Here, the terms "about", "approximately" and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The numbers given here are approximate numbers, that is, in the absence of specific description of "about", "approximately" or "generally", the meanings of "about", "approximately" or "generally" can still be implied.

[0063] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which this application belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this application, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this application.

[0064] In some embodiments of the present application, terms such as "connection" and "interconnection" may refer to two structures being in direct contact with each other, or two structures not being in direct contact with each other, with another structure disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable or both structures are fixed.

[0065] In the drawings, similar components and / or features may have the same reference numerals. Various components of the same type may be distinguished by adding letters or numbers after the reference numerals to distinguish similar components and / or similar features.

[0066] Figure 1 is a block diagram showing a microprocessor according to an embodiment of the present invention. Figure 1 As shown, the microprocessor 100 includes a memory device 110, wherein the memory device 110 includes a volatile memory unit 111, a non-volatile memory array 112, and a controller 113. According to some embodiments of the present invention, the volatile memory unit 111 may be a static random access memory, and the non-volatile memory array 112 may be a flash memory array.

[0067] like Figure 1 As shown, the host 10 is coupled to the microprocessor 100 through the communication interface 20, and sends a load instruction CLD, an update instruction CUD, and a programming instruction CPG to the microprocessor 100 through the communication interface 20 to perform corresponding operations on the memory device 110. According to an embodiment of the present invention, the host 10 can be a personal computer. The load instruction CLD, the update instruction CUD, and the programming instruction CPG will be described in detail below.

[0068] When the host 10 issues a load command CLD for loading data of the first memory page PG1, the controller 113 reads the data of the first memory page PG1 of the non-volatile memory array 112, and writes the data of the first memory page PG1 into the volatile memory unit 111. According to an embodiment of the present invention, the volatile memory unit 111 further includes an erase indicator PGER. When the controller 113 loads the data of the first memory page PG1 into the volatile memory unit 111, since the original data stored in the first memory page PG1 is the same as the data on the volatile memory unit 111, the erase indicator PGER is reset to the first state.

[0069] When the host 10 issues an update command CUD and a write data WDT, the controller 113 updates the data stored in the volatile memory unit 111 by using the write data WDT, and then compares whether the data stored in the volatile memory unit 111 is consistent with the data of the first memory page PG1 of the non-volatile memory array 112. When it is determined that the original data stored in the volatile memory unit 111 is inconsistent with the data of the first memory page PG1 of the non-volatile memory array 112, the controller 113 sets the corresponding erase indicator PGER to the second state, indicating that when writing the data on the volatile memory unit 111 back to the first memory page PG1 of the non-volatile memory array 112, an erase operation must be performed first, so that the data stored in the volatile memory unit 111 can be correctly written back to the non-volatile memory array 112.

[0070] When the host 10 issues a programming command CPG, the controller 113 first determines whether to perform an erase operation on the first memory page PG1 according to the erase indicator PGER, and then writes back the data stored on the volatile memory unit 111 to the first memory page PG1. According to an embodiment of the present invention, when the erase indicator PGER is in the first state, it means that the data on the volatile memory unit 111 is the same as the data stored in the first memory page PG1, so there is no need to perform an erase operation on the first memory page PG1, and even no need to perform a write operation.

[0071] According to another embodiment of the present invention, when the erase indicator PGER is in the second state, it means that the data on the volatile memory unit 111 is different from the data stored in the first memory page PG1. Therefore, the controller 113 first performs an erase operation on the first memory page PG1, and then writes the data of the volatile memory unit 111 into the first memory page PG1.

[0072] Figure 2 is a schematic diagram showing the judgment logic according to an embodiment of the present invention. Figure 2 As shown, the controller 113 performs a logical AND operation on the write data WDT and the original data ODT of the first memory page PG1 to generate the AND data ADT, and then performs a logical exclusive OR operation on the AND data ADT and the write data WDT to generate the erase indicator PGER. According to one embodiment of the present invention, when the controller 113 determines that any bit of the write data is different from the corresponding bit of the original data ODT, the erase indicator PGER is set to the second state.

[0073] Figure 3 is a flow chart showing a data access method according to an embodiment of the present invention. Figure 3 The description of the flowchart will be paired with Figure 1The block diagram is explained in detail.

[0074] like Figure 3 As shown, when the host 10 wants to operate the memory device 110, it first executes the load command CLD through the communication interface 20 (step S310) to load the data of the first memory page PG1 of the non-volatile memory array 112 into the volatile memory unit 111. According to an embodiment of the present invention, when the host 10 wants to read the data of the memory page of the non-volatile memory array 112, the host 10 can directly read the data of the volatile memory unit 111.

[0075] When the host 10 wants to modify the data of the memory page, the host 10 executes the update command CUD (step S320) through the communication interface 20, and uses the write data WDT to update the volatile memory unit 111. According to an embodiment of the present invention, the controller 113 compares whether the write data WDT is the same as the original data of the first memory page PG1 of the non-volatile memory array 112. When the write data WDT is different from the original data of the first memory page PG1 of the non-volatile memory array 112, the controller 113 sets the erase indicator PGER to the second state. Otherwise, the erase indicator PGER is maintained in the first state.

[0076] Next, the host 10 determines whether to re-update the memory device 110 (step S330). When it is determined that re-update is required, the host 10 returns to step S320 and executes the update command CUD again. When it is determined that re-update is not required, the host 10 executes the programming command CPG through the communication interface 20 (step S340), so that the controller 113 will determine whether to perform an erase operation on the first memory page PG1 according to the erase indicator PGER, and then write the data of the volatile memory unit 111 back to the first memory page PG1.

[0077] like Figure 3As shown in the flowchart, when the host 10 wants to read the data of the non-volatile memory array 112, the host 10 first executes the load instruction CLD, and then the required data can be read from the volatile memory unit 111. When the host 10 wants to write the write data WDT to the corresponding memory page of the non-volatile memory array 112, the host 10 executes the load instruction CLD, the update instruction CUD and the programming instruction CPG, eliminating the burden of the host 10 comparing the write data WDT and the original data ODT to determine whether to perform an erase operation first. In addition, since the data of the memory page is loaded into the volatile memory unit 111, the host 10 can perform multiple update instructions CUD on the volatile memory unit 111, and finally execute the programming instruction CPG once to write the data back to the corresponding memory page, thereby improving the efficiency of the write operation.

[0078] In other words, Figure 3 In the flowchart of , when the host 10 wants to access the non-volatile memory array 112, the host 10 loads the data of the corresponding memory page into the volatile memory unit 111 through the load instruction CLD and the update instruction CUD, and performs a read operation and a write operation on the volatile memory unit 111. When the data of the volatile memory unit 111 needs to be written back to the corresponding memory page, the host 10 can execute the programming instruction CPG, so that the controller 113 writes the data of the volatile memory unit 111 back to the corresponding memory page, and the controller 113 will first determine whether an erase operation needs to be performed, thereby reducing the burden of the host 10.

[0079] Figure 4 FIG. 1 is a block diagram showing a microprocessor according to another embodiment of the present invention. Figure 4 The microprocessor 400 and Figure 1 Compared with the microprocessor 100, the microprocessor 400 is Figure 1 The same as the microprocessor 100, wherein Figure 4 The host 10 executes the write instruction CW and the read instruction CR, and Figure 1 The host 10 executes a load instruction CLD, an update instruction CUD and a program instruction CPG.

[0080] Figure 5 is a flow chart showing a data writing method according to another embodiment of the present invention. Figure 5 The data writing method 500 will be described in detail in conjunction with the microprocessor 400.

[0081] For example, when the host 10 transmits a write command CW to the microprocessor 100 through the communication interface 20 to write the write data WDT to the first memory page PG1, the controller 113 first determines whether the data of the first memory page PG1 to be written by the host 10 is mapped to the volatile memory unit 111 (step S510) in response to the write command CW transmitted by the host 10. According to one embodiment of the present invention, when the first memory page PG1 is mapped to the volatile memory unit 111, the volatile memory unit 111 is used as a cache memory of the first memory page PG1.

[0082] When the controller 113 determines in step S510 that the first memory page PG1 is not mapped to the volatile memory unit 111, the controller 113 further determines whether other memory pages are mapped to the volatile memory unit 111 (step S520). According to one embodiment of the present invention, the controller 113 can determine which memory page is currently mapped to the volatile memory unit 111 according to a mapping table stored in the volatile memory unit 111.

[0083] For example, when it is determined in step S520 that the second memory page PG2 is mapped to the volatile memory unit 111, the controller 113 first performs an erase operation on the second memory page PG2 (step S530), and then writes the data stored in the volatile memory unit 111 to the second memory page PG2 of the non-volatile memory array 112 (step S540). Subsequently, the controller 113 maps the first memory page PG1 to the volatile memory unit 111, and loads the data of the first memory page PG1 into the volatile memory unit 111 (step S550).

[0084] According to some embodiments of the present invention, the controller 113 may determine whether to execute step S530 and step S540 according to the erase indicator PGER. For example, when the erase indicator PGER is in the first state, it means that the data stored in the volatile memory unit 111 is the same as the data stored in the second memory page PG2, so the controller 113 may skip step S530 and step S540 and directly execute step S550.

[0085] On the other hand, when the erase indicator PGER is in the second state, it means that the data stored in the volatile memory unit 111 is different from the data stored in the second memory page PG2. Therefore, the controller 113 executes steps S530 and S540 to write back the data stored in the volatile memory unit 111 to the second memory page PG2.

[0086] After step S550, the controller 113 updates the data stored in the volatile memory unit 111 using the write data WDT provided by the host 10 (step S560). Returning to step S510, when the controller 113 determines that the first memory page PG1 to be written by the host 10 has been mapped to the volatile memory unit 111, the controller 113 directly updates the volatile memory unit 111 using the write data WDT provided by the host 10 (step S560).

[0087] Figure 6 FIG. 1 is a flow chart showing a data reading method according to another embodiment of the present invention. Figure 6 The data reading method 600 will be described in detail with the microprocessor 400. Figure 5 Compared with the data writing method 500 of FIG. 5 , step S560 of the data writing method 500 is replaced by step S660 .

[0088] For example, when the host 10 transmits a read command CR to the microprocessor 100 through the communication interface 20 to read data of the third memory page PG3, the controller 113 responds to the read command CR transmitted by the host 10 and first determines whether the third memory page PG3 is mapped to the volatile memory unit 111 (step S510).

[0089] When it is determined in step S510 that the third memory page PG3 is not mapped to the volatile memory unit 111, the controller 113 uses steps S520, S530 and S540 to write the data stored in the volatile memory unit 111 back to the corresponding memory page of the non-volatile memory array 112, and uses step S550 to load the data of the third memory page PG3 into the volatile memory unit 111.

[0090] Next, the controller 113 transmits the data stored in the volatile memory unit 111 to the host 10 (step S660). Returning to step S510, when the controller 113 determines that the third memory page PG3 to be read by the host 10 has been mapped to the volatile memory unit 111, the controller 113 directly transmits the data stored in the volatile memory unit 111 to the host 10 (step S660).

[0091] According to one embodiment of the present invention, referring to Figure 5 In the data writing method 500, since the data of the last memory page written may remain on the volatile memory cell 111 and not be written back to the non-volatile memory array 112, by executing the data reading method 600 to read another memory page, the data remaining in the volatile memory cell 111 can be written to the non-volatile memory array 112.

[0092] According to some embodiments of the present invention, the combination of the data writing method 500 and the data reading method 600 is: Figure 4 In addition, step S550 corresponds to Figure 3 The operation of the load instruction CLD, step S560 corresponds to Figure 3 The operation of the update instruction CUD, step S530 and step S540 correspond to Figure 3 The programming instructions for the CPG operation.

[0093] Compared to Figure 1 The microprocessor 100 and Figure 3 The data access method 300 changes the access instruction of the host 10 into a load instruction CLD, an update instruction CUD and a program instruction CPG. Figure 4 The microprocessor 400 and Figure 5 as well as Figure 6 The combined data access method maintains the access command of the host 10 as the write command CW and the read command CR. For the host 10, the method of accessing the non-volatile memory array 112 is very similar to the method of accessing the random access memory, and the host 10 does not need to determine whether to perform an erase operation on the non-volatile memory array 112, thereby reducing the burden of the host 10 in accessing data.

[0094] The present invention proposes a memory device and a data access method thereof. By mapping a non-volatile memory array to a volatile memory unit and allowing the memory device to automatically determine whether to perform an erase operation, the host accesses the non-volatile memory array in a manner similar to that of a static random access memory, which not only greatly reduces the system burden generated by the host accessing the non-volatile memory array, but also effectively improves the data access efficiency of the non-volatile memory array.

[0095] Although the embodiments and advantages of the present application have been applied as above, it should be understood that any person with ordinary knowledge in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present application. In addition, the scope of protection of the present application is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person with ordinary knowledge in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of some embodiments of the present application. As long as the same functions can be implemented in the embodiments described herein or the same results can be obtained, they can be used according to some embodiments of the present application. Therefore, the scope of protection of the present application includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present application also includes the combination of each claim and embodiment.

Claims

1. A memory device, located in a microprocessor, characterized in that: The microprocessor is coupled to a host and includes: a volatile memory unit; a non-volatile memory array; and A controller writes write data into a first memory page of the non-volatile memory array in response to a write command issued by the host, the controller loads the data of the first memory page into the volatile memory unit, and updates the volatile memory unit with the write data.

2. The memory device according to claim 1, wherein: Before the controller loads the data of the first memory page into the volatile memory unit, the controller determines whether the first memory page is mapped to the volatile memory unit, wherein when it is determined that the first memory page is not mapped to the volatile memory unit, the controller maps the first memory page to the volatile memory unit.

3. The memory device according to claim 2, wherein: When it is determined that the first memory page has been mapped to the volatile memory unit, the controller directly updates the volatile memory unit using the write data.

4. The memory device according to claim 2, wherein: When it is determined that the first memory page is not mapped to the volatile memory unit, the controller further determines whether the volatile memory unit is mapped to a second memory page, wherein when the controller determines that the volatile memory unit is mapped to the second memory page, the controller writes the data of the volatile memory unit to the second memory page of the non-volatile memory array.

5. The memory device according to claim 4, wherein: The controller further determines whether the data of the volatile memory cell is the same as the data of the second memory page of the non-volatile memory array, wherein when the data of the volatile memory cell is the same as the data of the second memory page of the non-volatile memory array, the controller does not perform an erase operation on the second memory page or write the data of the volatile memory cell into the second memory page of the non-volatile memory array, but directly loads the data of the first memory page into the volatile memory cell.

6. The memory device according to claim 5, wherein: When the data of the volatile memory cell is different from the data of the second memory page of the non-volatile memory array, the controller first performs the erase operation on the second memory page, then writes the data of the volatile memory cell into the second memory page of the non-volatile memory array, and then loads the data of the first memory page into the volatile memory cell.

7. The memory device according to claim 5, wherein: When the controller loads the data of the second memory page into the volatile memory unit, the controller resets an erase indicator corresponding to the second memory page to a first state.

8. The memory device according to claim 7, wherein: When the data of the second memory page is loaded into the volatile memory cell and the controller updates the data of the volatile memory cell, the controller further determines whether the data of the volatile memory cell is the same as the data of the second memory page of the non-volatile memory array, wherein when it is determined that the data of the volatile memory cell is different from the data of the second memory page of the non-volatile memory array, the controller sets the erase indicator to a second state.

9. The memory device according to claim 8, wherein: When the controller writes the data of the volatile memory cell into the second memory page of the non-volatile memory array, the controller corresponds to the erase indicator in the second state, first performs the erase operation on the second memory page of the non-volatile memory array, and then writes the data of the volatile memory cell into the second memory page.

10. The memory device according to claim 8, wherein: In response to a read command issued by the host to read a third memory page of the non-volatile memory array, the controller first determines whether to write the data of the volatile memory unit into the non-volatile memory array according to the erase indicator, and then loads the data of the third memory page into the volatile memory unit.

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