Information synchronization method and device

Abstract

The invention provides an information synchronization method and device, relates to the technical field of computers, and is used for improving the information synchronization efficiency. The information synchronization method comprises the steps that a queue manager receives a first request from a first processing unit, the first request comprises a first address and first data, the first request is used for indicating that the first data is written into a first queue corresponding to the first address, and the first address is a storage address of the first data in a storage; the memory is used for storing data in the queue group; if the queue group comprises the first queue, the queue manager responds to the first request and writes the first data into the first queue; the queue manager receives a second request from the second processing unit and sends the target data to the bus, and the second request comprises the first address and is used for indicating to read the target data in the first queue.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an information synchronization method and device. Background Art

[0002] For a central processing unit (CPU) that includes multiple threads or multiple cores, there are synchronization problems between threads or between cores. Among them, synchronization can include state information synchronization and data information synchronization. For example, when multiple cores work together to complete a large task, some steps need to be completed before other steps can be executed. This execution order is called state information synchronization; or the calculation results of a core need to be shared with other cores. This synchronization is called data information synchronization. There are also synchronization problems between different computing units (such as CPU, GPU graphics processing unit (GPU), and vector processor (tensor processing unit, TPU)). Therefore, a method of information synchronization is needed to achieve information synchronization between different objects.

[0003] In the prior art, information synchronization between different computing units is achieved through shared memory. Specifically, multiple computing units (including computing unit A) need to repeatedly access the same address in the memory to obtain the global state. The address is used to store the value representing the global state. Once the value in the address becomes the value representing the free state, computing unit A atomically writes the value representing the occupied state in the address, thereby obtaining execution authority. Only one computing unit can obtain execution authority at the same time, thereby achieving state information synchronization. Among them, atomic row writing means that all data are written or all data are not written in one write operation. When computing unit A obtains execution authority, computing unit A performs corresponding read and write operations. When the data in the memory is updated, the public cache of multiple computing units synchronizes the data in the memory using a synchronization protocol and a bus. For example, the protocol can be a (modify-excluive-shared-invalid, MESI) synchronization protocol to let the remaining computing units except computing unit A know that the data in the memory has changed, thereby achieving data information synchronization between different computing units. In actual applications, data information synchronization may not be required in the case of state information synchronization.

[0004] However, in the case of state information synchronization, data information synchronization may not be necessary. Using a synchronization protocol and a bus to achieve data information synchronization results in a large amount of invalid data being generated on the bus, thereby reducing synchronization efficiency. Summary of the invention

[0005] The present application provides an information synchronization method and device, which relate to the field of computer technology and are used to improve the efficiency of information synchronization.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, an information synchronization method is provided, which is applied to an electronic device, wherein the electronic device includes a queue manager, a bus, multiple processing units and a memory, the queue manager and the processing units communicate through the bus, the queue manager includes a queue group, the queue group includes multiple queues, and the multiple processing units include a first processing unit and a second processing unit. The method includes: the queue manager receives a first request from the first processing unit, the first request includes a first address and first data, the first request is used to indicate that the first data is written to a first queue corresponding to the first address, wherein the first address is a storage address of the first data in the memory, and the memory is used to store data in the queue group; if the queue group includes the first queue, the queue manager responds to the first request and writes the first data to the first queue; the queue manager receives a second request from the second processing unit and sends target data to the bus, the second request includes the first address, and the second request is used to indicate reading the target data in the first queue.

[0008] In the technical solution provided by the present application, after the first processing unit writes the first data into the first queue corresponding to the first address through the first request, the second processing unit can read the target data in the first queue through the second request, thereby realizing information synchronization between different objects through the queue; on the other hand, the first queue sends the target data to the bus only after receiving the second request to read the target data. During this process, a large amount of invalid data is not generated on the bus. Compared with memory sharing, as long as there is new data, it is shared to the remaining computing units through the bus and the synchronization protocol, which improves the efficiency of synchronization.

[0009] In a possible implementation of the first aspect, if the queue group does not include the first queue, the queue manager determines an idle queue in the queue group; the queue manager determines the idle queue as the first queue corresponding to the first address. In the above possible implementation, the uniqueness of the first queue is guaranteed.

[0010] In a possible implementation of the first aspect, the queue manager determines the idle queue as the first queue corresponding to the first address, including: the queue manager uses the first address as index information of the idle queue to determine the idle queue as the first queue. In the above possible implementation, the uniqueness of the first queue is guaranteed.

[0011] In a possible implementation of the first aspect, the queue manager determines an idle queue in the queue group, including: if the queue group does not include the first queue and there is no idle queue in the queue group, the queue manager writes the second data in the second queue in the queue group into the second address of the memory, where the second address is the storage address of the second data in the memory; the queue manager initializes the second queue to determine the second queue as an idle queue; the queue manager writes the data in the second address into the idle queue. In the above possible implementation, the capacity of the queue is increased.

[0012] In a possible implementation of the first aspect, writing the first data into the first queue includes: the queue manager writes the first data into a storage area indicated by a first data pointer, where the first data pointer is a data pointer corresponding to the storage area in the first queue where the first data is stored; and writing the first data pointer into the first queue.

[0013] In a possible implementation of the first aspect, the first data pointer and the first data are deleted according to the position of the first data pointer in the first queue and the identification information of the first data pointer. In the above possible implementation, the utilization rate of the first queue is improved.

[0014] In a possible implementation of the first aspect, the memory includes a main memory or a cache. In the above possible implementation, the diversity of choices is increased.

[0015] In a second aspect, an information synchronization method is provided, which is applied to an electronic device, wherein the electronic device includes a queue manager, a bus, multiple processing units and a memory, the queue manager and the processing units communicate with each other through the bus, the multiple processing units include a first processing unit and a second processing unit, and the method includes: the queue manager receives a first request from the first processing unit, the first request includes a first address and first data, the first request is used to indicate that the first data is written to the first address, wherein the first address is a storage address of the first data in the memory, and the memory is used to store data; the queue manager responds to the first request, and writes the first data to the first address in a queuing order, and the queuing order is determined by the queue manager according to the data status in the first address and the capacity of the first address; the queue manager receives a second request from the second processing unit, and sends the target data to the bus, the second request includes the first address, and the second request is used to indicate reading the target data in the first address.

[0016] According to a third aspect, an information synchronization device is provided, which is applied to an electronic device. The electronic device also includes a bus, multiple processing units and a memory. The device and the processing unit communicate with each other through the bus. The device includes a queue group, the queue group includes multiple queues, and the multiple processing units include a first processing unit and a second processing unit. A receiving unit is used to receive a first request from the first processing unit, the first request includes a first address and first data, and the first request is used to indicate that the first data is written to a first queue corresponding to the first address, wherein the first address is a storage address of the first data in the memory, and the memory is used to store data in the queue group; an execution unit is used to respond to the first request and write the first data to the first queue when the queue group includes the first queue; the receiving unit is also used to receive a second request from the second processing unit, the second request includes a first address, and the second request is used to indicate reading target data in the first queue; a sending unit is used to send the target data to the bus.

[0017] In a possible implementation manner of the third aspect, the device further includes a determining unit, which is used to: when the queue group does not include the first queue, determine an idle queue in the queue group; and determine the idle queue as the first queue corresponding to the first address.

[0018] In a possible implementation manner of the third aspect, the determining unit is further configured to: use the first address as index information of the idle queue to determine the idle queue as the first queue.

[0019] In a possible implementation of the third aspect, the determination unit is also used to: when the queue group does not include the first queue and there is no idle queue in the queue group, write the second data in the second queue in the queue group to a second address in the memory, where the second address is the storage address of the second data in the memory; initialize the second queue to determine the second queue as an idle queue; and write the data in the second address to the idle queue.

[0020] In a possible implementation of the third aspect, the execution unit is also used to: write the first data into a storage area indicated by a first data pointer, where the first data pointer is a data pointer corresponding to the storage area storing the first data in the first queue; and write the first data pointer into the first queue.

[0021] In a possible implementation manner of the third aspect, the device further includes: a deleting unit, which is used to delete the first data pointer and the first data according to the position of the first data pointer in the first queue and the identification information of the first data pointer.

[0022] In a possible implementation manner of the third aspect, the memory includes a main memory or a cache.

[0023] In a fourth aspect, an information synchronization device is provided, which includes a processor and a memory, the memory is used to store instructions, and the processor is used to execute the information synchronization method provided by the above-mentioned first aspect or any possible implementation method of the first aspect or the second aspect.

[0024] In another aspect of the present application, a computer-readable storage medium is provided, the computer-readable storage medium including a computer request, when the computer request runs on an information synchronization device, causes the information synchronization device to execute the information synchronization method provided in the first aspect or any possible implementation of the first aspect or the second aspect.

[0025] In another aspect of the present application, a computer program product comprising a request is provided. When the computer program product is run on a computer device, the computer device executes the information synchronization method provided in the first aspect or any possible implementation of the first aspect or the second aspect.

[0026] It can be understood that the above-mentioned information synchronization device, computer-readable storage medium and computer program product can be used to execute the above and will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of state information synchronization;

[0028] Figure 2 A schematic diagram of a shared memory;

[0029] Figure 3 This is a schematic diagram of another shared memory;

[0030] Figure 4 A schematic diagram of a hardware queue;

[0031] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0032] Figure 6 A flowchart of an information synchronization method provided in an embodiment of the present application;

[0033] Figure 7 A flowchart of another information synchronization method provided in an embodiment of the present application;

[0034] Figure 8 A schematic diagram of a process for determining a first queue provided in an embodiment of the present application;

[0035] Fig. 9 A schematic diagram of an information synchronization method provided in an embodiment of the present application;

[0036] Fig.10A schematic diagram of the structure of an information synchronization device provided in an embodiment of the present application;

[0037] Fig.11 A schematic diagram of the structure of another information synchronization device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated with each other are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple. In addition, the embodiments of the present application use words such as "first" and "second" to distinguish between the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only to distinguish different thresholds, and do not limit their order. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0039] Optionally, in this application, the words "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way.

[0040] To facilitate understanding, before introducing the embodiments of the present application, the relevant knowledge of memory semantics provided by the embodiments of the present application is first introduced and explained.

[0041] Usually, each computing unit of a computer can share the same memory, such as dynamic random access memory (DRAM). These memories are generally called main memory, which can also be called physical memory. Since the computing unit accesses the main memory slowly, in order to improve the access efficiency, a cache is set inside the computing unit. The cache is used to temporarily store part of the data in the main memory, which is the data frequently accessed by the computing unit. In the following text, the main memory and cache are collectively referred to as memory, that is, the memory includes the main memory and cache. Among them, the computing unit can be a central processing unit (CPU), a graphics processing unit (GPU) or a tensor processing unit (TPU) and other related processors.

[0042] When the computing unit reads data, it first searches for the data to be read in the cache. If the data to be read is stored in the cache, it reads it immediately (read acceleration). If the data to be read is not in the cache, it reads it in the main memory and stores the data block where the data is located in the cache so that the entire data block can be directly read in the cache the next time it is read. When the computing unit writes data, it first writes the data to the cache (write acceleration). If there is no remaining storage space in the cache, the old data in the cache is updated to the main memory, and then the data is written to the cache.

[0043] Due to the existence of cache, when the computing unit accesses the main memory through a request, it does not directly access the main memory, but first accesses the cache. If the cache cannot meet the access requirements, it then accesses the main memory. For example, when the computing unit reads data through a read request, it first accesses the cache. If the cache does not store the data to be read, it then accesses the main memory. In this article, the request that combines the behavior of accessing the cache and accessing the main memory is called memory semantics.

[0044] A cache coherence (CC) protocol is maintained between the computing unit and the main memory. The CC protocol allows each computing unit to semantically consider the above accesses to be the same as the perception of not being cached. However, the CC protocol is only valid for this computing unit and may not be valid for multiple computing units. Therefore, memory semantics also includes memory barriers (MB).

[0045] Among them, MB is a synchronization point, which is used to force all computing units to perceive that all operations before this point are valid for all computing units, or to make all operations before this point be executed before starting to execute operations after this point. MB is also called memory fence, memory barrier or barrier request, etc.

[0046] Before introducing the embodiments of the present application, the information synchronization problem between different objects is first introduced and explained.

[0047] For CPUs with multiple threads or multiple cores, there are synchronization issues between threads or cores. Among them, synchronization can include state information synchronization and data information synchronization. For example, when multiple cores work together to complete a large task, some steps need to be completed before other steps can be executed. This execution order is called state information synchronization; or the calculation results of a core need to be shared with other cores. This synchronization is called data information synchronization. Different computing units (such as CPU, GPU, and TPU, etc.) also have synchronization issues with each other.

[0048] For example, Figure 1 A schematic diagram of state information synchronization is shown in FIG. Figure 1 As shown, computing unit A, computing unit B and computing unit C are used to jointly complete task 1, wherein task 1 includes subtask 11, subtask 12, subtask 13 and subtask 14. Subtask 11 and subtask 12 are scheduled to computing unit A (i.e., computing unit A is used to complete subtask 11 and subtask 12), subtask 13 is scheduled to computing unit B (i.e., computing unit B is used to complete subtask 13), and subtask 14 is scheduled to computing unit C (i.e., computing unit C is used to complete subtask 14). Due to the dependency between different subtasks, for example, subtask 12 and subtask 13 can only be executed after task 11 is completed, and subtask 14 can only be executed when subtask 12 and subtask 13 are completed at the same time. Therefore, in the process of completing task 1, the working states of different computing units of computing unit A, computing unit B and computing unit C are as follows:

[0049] When computing unit A is completing subtask 11, computing unit B and computing unit C are in a waiting state; when computing unit A is completing subtask 12 and computing unit B is executing subtask 13, computing unit C is in a waiting state; when computing unit C is completing subtask 14, computing unit A and computing unit B are in a waiting state.

[0050] Therefore, an information synchronization method is needed to achieve information synchronization between different objects. Currently, information synchronization between different objects is achieved through the following two solutions.

[0051] Solution 1: Synchronize information between different computing units through shared memory.

[0052] Specifically, multiple computing units (including computing unit A) need to repeatedly access the same address in the memory to obtain the global state. The address is used to store the value representing the global state. Once the value in the address becomes the value representing the free state, computing unit A atomically writes the value representing the occupied state in the address. The computing unit can obtain execution authority for any one of the multiple computing units, thereby realizing state information synchronization. Among them, atomic row writing means that all data are written or all data are not written in one write operation. When computing unit A obtains execution authority, computing unit A performs corresponding read and write operations. When the data in the memory is updated, the public cache of multiple computing units synchronizes the data in the memory using the synchronization protocol and bus. For example, the protocol can be a (modify-excluive-shared-invalid, MESI) synchronization protocol to let the remaining computing units except computing unit A know that the data in the memory has changed, thereby realizing data information synchronization between different computing units. In actual applications, data information synchronization may not be required in the case of state information synchronization.

[0053] For example, Figure 2 A schematic diagram of a shared memory is shown in FIG. Figure 2 As shown, computing unit A, computing unit B and computing unit C jointly access the same address add1 in the memory, where address add1 is used to store a value representing the memory state. The memory can be a shared cache of computing unit A, computing unit B and computing unit C, such as Figure 3 As shown, computing unit A has a corresponding cache a (also called the local cache of computing unit A), computing unit B has a corresponding cache b (also called the local cache of computing unit B), computing unit C has a corresponding cache c (also called the local cache of computing unit C), cache d and main memory are public cache and public main memory respectively, that is, computing unit A, computing unit B and computing unit C can all access cache d and main memory, and main memory can also be called physical memory.

[0054] If computing unit A atomically writes the value representing the occupied state to address add1 of cache d, that is, computing unit A obtains the execution permission of the memory, cache d synchronizes the value representing the occupied state to cache b and cache c through the bus and synchronization protocol, and computing unit B and computing unit C know that the data in address add1 has changed, thereby realizing data information synchronization between computing unit A, computing unit B and computing unit C. When computing unit A writes new data to cache d and there is no remaining storage space in cache d, cache d first updates the old data to the main memory, and computing unit A then writes the new data to cache d. Figure 3 The bus is not shown.

[0055] However, in the case of state information synchronization, data information synchronization may not be necessary. Using a synchronization protocol and a bus to achieve data information synchronization results in a large amount of invalid data being generated on the bus, thereby reducing synchronization efficiency.

[0056] Solution 2: Use queues to synchronize information between different computing units.

[0057] Specifically, queues are allocated to different computing units respectively. The queues are used to sort the data sent by the corresponding computing units according to the order of sending. When a computing unit reads data in the queue, the queue forwards the data according to the first-in-first-out principle.

[0058] For example, Figure 4 As shown, the queue includes queue 1, and queue 1 is assigned to computing unit A and computing unit B. Computing unit A sends a write request to queue 1 through a bus. The write request includes identification information and data of queue 1. Queue 1 sorts the data in the order in which the write requests are received and writes the data into queue 1. Computing unit B sends a read request to queue 1 through a bus. The read request is used to indicate reading the data in queue 1. After queue 1 receives the read request from computing unit B, it forwards the data to computing unit B according to the first-in-first-out principle, that is, computing unit B reads the data from queue 1 after computing unit A writes the data into queue 1, thereby completing information synchronization between computing units. Figure 4 The bus is not shown.

[0059] However, in this solution, the number of queues is limited, which can hardly meet the needs of general computing.

[0060] Based on this, the present application provides an information synchronization method for improving the efficiency of information synchronization. Applied in an electronic device, the electronic device includes a queue manager, a bus, multiple processing units and a memory, the queue manager and the processing unit communicate through the bus, the queue manager includes a queue group, the queue group includes multiple queues, the multiple processing units include a first processing unit and a second processing unit, and the method includes: the queue manager receives a first request from the first processing unit, the first request includes a first address and a first data, the first request is used to indicate that the first data is written into the first queue corresponding to the first address, wherein the first address is the storage address of the first data in the memory, and the memory is used to store the data in the queue group; if the queue group includes the first queue, the queue manager responds to the first request and writes the first data into the first queue; the queue manager receives a second request from the second processing unit and sends the target data to the bus, the second request includes the first address, and the second request is used to indicate reading the target data in the first queue.

[0061] During this process, after the first processing unit writes the first data into the first queue corresponding to the first address through the first request, the second processing unit can read the target data in the first queue through the second request, thereby realizing information synchronization between different objects through the queues; on the other hand, the first queue sends the target data to the bus only after receiving the second request to read the target data. During this process, a large amount of invalid data is not generated on the bus. Compared with memory sharing, as long as there is new data, it is shared to the other computing units through the bus and the synchronization protocol, which improves the efficiency of synchronization.

[0062] Optionally, the code processing method provided in this embodiment can be applied to an electronic device. The electronic device may include a terminal device. The terminal device may include but is not limited to a personal computer, a server computer, a mobile device (such as a mobile phone, a tablet computer, a media player, etc.), a wearable device, a vehicle-mounted device, a consumer terminal device, a mobile robot, and a drone, etc.

[0063] Combine the following Figure 5 The structure of the electronic device is introduced and described. For example, Figure 5 The electronic device 50 is a schematic diagram of a structure of an electronic device provided in an embodiment of the present application. The electronic device 50 may include: a processor 510, a bus 520, a memory 530, a communication interface 540 and a queue manager 550. The processor 510, the memory 530, the communication interface 540 and the queue manager 550 are connected via the bus 520.

[0064] It should be understood that in this embodiment, the processor 510 may be a CPU, and the processor 510 may also be other general-purpose processors, digital signal processors (digital signal processing, DSP), (application-specific integrated circuit, ASIC), field-programmable gate arrays (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0065] The processor 510 may also be a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the present application. In the embodiment of the present application, the processor may also be referred to as a computing unit.

[0066] In the embodiment of the present application, the processor 510 may be used to send a request to the queue manager 550. For example, the processor 510 may be used to send a first request to the queue manager 550, and the first request may be used to instruct to write first data to the first queue corresponding to the first address; the processor 510 may be used to send a second request to the queue manager 550, and the second request may be used to instruct to read the target data in the first queue corresponding to the first address. The first request and the second request may be sent by different processors, and the processor may also be called a processing unit, and the processor may also be called a computing unit.

[0067] The communication interface 540 is used to implement communication between the electronic device 50 and an external device or component.

[0068] The bus 520 may include a path for transmitting information between the above components (such as the processor 510 and the memory 530). In addition to the data bus, the bus 520 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are labeled as bus 520 in the figure. The bus 520 may be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 520 can be divided into an address bus, a data bus, a control bus, etc.

[0069] As an example, the electronic device 50 may include multiple processors. The processor may be a multi-core (multi-CPU) processor. The processor here may refer to one or more devices, circuits, and / or computing units for processing data (e.g., computer program requests).

[0070] It is worth mentioning that Figure 5 In the example, an electronic device 50 including a processor 510 and a memory 530 is taken as an example. Here, the processor 510 and the memory 530 are respectively used to indicate a type of device or equipment. In a specific embodiment, the number of each type of device or equipment can be determined according to business requirements.

[0071] The memory 530 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct memory bus random access memory (DRRAM).

[0072] In the embodiment of the present application, the above memory may be referred to as main memory or physical memory. The memory 530 may further include a cache, which is used to store part of the data in the main memory.

[0073] The queue manager 550 can be used to receive information, send information, store target data, and manage queues. For example, the queue manager 550 can be used to receive a request from the processor 510 through the bus 520, and the request can include a first request and a second request. The queue manager 550 can be used to send target data to the processor 510 through the bus 520. The queue manager 550 can include multiple queues, and each queue in the multiple queues can be used to store target data. The queue manager 550 can be used to manage queues. The queue manager 550 can also be called a queuing agent.

[0074] Combine the following Figure 5 The electronic device shown in the figure introduces the information synchronization method provided by the embodiment of the present application. Each step in the information synchronization method provided by the embodiment of the present application is Figure 5 The queue manager in the .

[0075] Figure 6A flowchart of an information synchronization method provided in an embodiment of the present application, the method comprising:

[0076] S601. The queue manager receives a first request from a first processing unit. The first request includes a first address and first data. The first request is used to indicate that the first data is written into a first queue corresponding to the first address. The first address is a storage address of the first data in a memory, and the memory is used to store data in the queue group.

[0077] The first processing unit may include a thread, a core, a CPU or any processor involved in computing or communication. The processor may be the above-mentioned Figure 5 The processor described in. The first processing unit may also be referred to as a first computing unit. Furthermore, the first request may also be referred to as a write request, and the first request may be implemented by an instruction, for example, the instruction may include a gqm_push instruction.

[0078] In addition, the memory may be the above Figure 5 The memory described in. The memory can be used to store data, for example, the memory can be used to store data in the queue group, for example, the data in any queue in the queue group can be updated to the memory. Optionally, the memory can be a main memory or a cache.

[0079] In a first possible implementation manner, the memory may be a main memory, and the first address is a storage address of the target data in the main memory.

[0080] In a second possible implementation manner, the memory may be a cache, and the first address is a storage address of the target data in the cache.

[0081] In addition, the queue group may include multiple queues, each of the multiple queues may be used to store data, and each of the multiple queues may be a first input first output (FIFO) queue. The first queue is a queue in the multiple queues corresponding to the first address.

[0082] Exemplarily, assume that the length of the first queue is 10, and its identification information can be represented as 0-9 in sequence. Assume that the identification information of the head of the queue is 0, the identification information of the tail of the queue is 9, and a data pointer is read each time. When writing data to the first queue, the data is stored in the storage area indicated by the data pointer, and the data pointer is written in the tail of the queue 9; when reading data in the first queue, the data pointer stored in the head of the queue 0 is read, and the data in the storage area indicated by the data pointer is read. When the data is read next time, the position indicated by the identification information 1 is the head, and the position indicated by the identification information 0 is the tail, thereby realizing first-in-first-out. When there is only one area in the queue with a data pointer, for example, only the position indicated by the identification information 9 has a data pointer, then the position indicated by the identification information 9 is both the head of the first queue and the tail of the first queue.

[0083] For example, Figure 7 As shown, before step S601, the method provided in the embodiment of the present application further includes step S602: the first processing unit sends a first request to the queue manager through the bus.

[0084] In practical applications, the identification information of each queue in the queue group can be queried to determine whether the first queue exists in the queue group. If the identification information contains the first address, or there is identification information corresponding to the first address, the first queue exists in the queue group. If the identification information does not contain the first address, and there is no identification information corresponding to the first address, it is determined that there is no first queue in the queue group.

[0085] Optionally, there may be a first queue or there may not be a first queue in the queue group. The two situations are respectively introduced and explained below.

[0086] In a first possible embodiment, there is a first queue in the queue group, and the method includes step S603.

[0087] S603: If the queue group includes the first queue, the queue manager responds to the first request and writes the first data into the first queue.

[0088] Specifically, the identification information of each queue in the multiple queues is queried. If the identification information of a queue includes the first address, or the identification information of a queue corresponds to the first address, then the queue is the first queue corresponding to the first address, and the target data is written into the first queue.

[0089] In one possible implementation, writing the first data into the first queue may specifically be: the queue manager writes the first data into a storage area indicated by a first data pointer, where the first data pointer is a data pointer corresponding to the storage area in the first queue where the first data is stored; the queue manager writes the first data pointer into the first queue, specifically, the queue manager writes the first data pointer to the end of the first queue.

[0090] In a second possible embodiment, there is no first queue in the queue group, for example, Figure 7 As shown, the method also includes step S604.

[0091] S604: If the queue group does not include the first queue, the queue manager determines an idle queue in the queue group; the queue manager determines the idle queue as the first queue corresponding to the first address.

[0092] The idle queue means that the queue is not occupied by addresses in other memories, that is, the queue does not have a corresponding address, or the identification information of the queue does not contain an address.

[0093] Specifically, the queue manager queries the identification information of each queue in the queue group, and determines an idle queue in the queue group whose identification information does not have an address in the memory, or whose identification information has no corresponding relationship with the address in the memory.

[0094] Further, the queue manager determines the idle queue as the first queue corresponding to the first address, including: the queue manager uses the first address as index information of the idle queue to determine the idle queue as the first queue corresponding to the first address.

[0095] Optionally, the first address may be used as index information of the idle queue in two different ways, and the two ways are described in detail below.

[0096] In the first mode, the first address is directly used as the identification information of the idle queue. In this mode, the first address is directly used as the identification information of the idle queue, and the first queue can be directly determined in the queue group according to the first address, thereby improving the speed of determining the first queue.

[0097] In the second method, a correspondence is established between the first address and the identification information of the space queue; the idle queue is determined as the first queue. In this method, a correspondence is established between the identification information of the space queue and the first address, the corresponding identification information can be determined using the first address, and the first queue can be uniquely determined based on the identification information, thereby ensuring the uniqueness of the first queue.

[0098] In a possible embodiment, if there is no idle queue in the queue group, that is, each queue in the queue group has a corresponding address, and the address is different from the first address included in the first request, then an idle queue can be created in the queue group, or the queue group can wait for a first preset time in place until an idle queue appears in the queue group. In the following, the process of determining the idle queue in the two possible situations is described respectively.

[0099] In the first case, if the queue group does not include the first queue, and there is no idle queue in the queue group. For example, Figure 8 As shown, the method provided in the embodiment of the present application also includes:

[0100] S801: If the queue group does not include the first queue and there is no idle queue in the queue group, the queue manager writes the second data in the second queue in the queue group into the second address of the memory, where the second address is the storage address of the second data in the memory.

[0101] Optionally, the second queue may be any queue in the queue group. The second queue may also be the queue with the lowest utilization rate in the queue group. This embodiment of the application does not make specific limitations on this.

[0102] S802: The queue manager initializes the second queue to determine the second queue as an idle queue.

[0103] S803: The queue manager writes the data in the second address into the idle queue.

[0104] Initializing the second queue is resetting the identification information of the second queue. Since the identification information of the second queue may include the above two possible methods, the following describes the initialization of the second queue in the two methods respectively.

[0105] In the first mode, the identification information of the second queue is the first address. Initializing the second queue includes deleting the identification information of the second queue.

[0106] In a second manner, the identification information of the second queue corresponds to the first address. Initializing the second queue includes releasing the correspondence between the identification information of the second queue and the first address, so that the identification information of the second queue does not have a corresponding address.

[0107] In the first case, by writing the data in the second queue into the memory, an idle queue is determined in the queue group, so that the capacity of the queue group is equal to the capacity of the memory, thereby increasing the utilization rate of the queue group.

[0108] In the second case, if the queue group does not include the first queue and there is no idle queue in the queue group, the queue group waits for a first preset time period until an idle queue appears in the queue group.

[0109] Furthermore, the method provided in the embodiment of the present application further includes: if the queue group does not include the first queue and there is no idle queue in the queue group, waiting in place for a first preset time length until there is an idle queue in the queue group. In the second case, by waiting to obtain an idle queue, selectivity is increased.

[0110] Furthermore, the method further includes step S605:

[0111] S605: The queue manager receives a second request from the second processing unit and sends target data to the bus, where the second request includes the first address and is used to instruct to read the target data in the first queue.

[0112] The second processing unit may be a thread, a core, a CPU or any processor involved in computing or communication. The processor may be the above-mentioned Figure 5 The processor described in. The processor may also be referred to as a computing unit. In a first possible implementation, the first processing unit and the second processing unit are both threads. In a second possible implementation, the first processing unit and the second processing unit are both cores. In a third possible implementation, the first processing unit and the second processing unit are both processors. In addition, the second request may also be referred to as a read request. The second request may be implemented by an instruction, for example, the instruction may include a gqm_pop instruction.

[0113] Optionally, before step S605, the method provided in the embodiment of the present application further includes S606: the second processing unit sends a second request to the queue manager through the bus.

[0114] Furthermore, if the second request is sent before the first request, that is, there is no target data in the first queue, the method further includes: the queue manager waits for a second preset time until there is target data in the first queue. That is, the queue manager waits for the second preset time until the target data is written into the first queue.

[0115] In actual applications, there may be a situation where multiple second processing units read the same target data. If a second processing unit reads the target data in the first queue, the target data will no longer exist in the first queue, resulting in the inability of the remaining second queues to read the target data in the first queue. Therefore, in this scenario, a spinlock is generally used to read the target data, so that when the second processing unit reads the target data, the remaining second processing units cannot read the target data in the first queue, that is, only one second processing unit accesses the first queue at the same time; and after the second processing unit reads the target data, the target data can be rewritten into the first queue to ensure that the remaining second units can read the target data in the first queue.

[0116] Furthermore, the second instruction includes a spinlock, and the information synchronization method provided in the embodiment of the present application also includes: the queue manager reads the target data according to the second request; the queue manager receives and executes a third request from the second processing unit, the third request includes the target data and the first address, and the third request is used to indicate that the target data is written into the first queue.

[0117] Optionally, the request in the embodiment of the present application may include GQM semantics, which is a semantics independent of memory semantics. Exemplarily, the specific function of the above spinlock can be implemented by code, for example, the code can be:

[0118] gqm_lock_t*gqm_lock_create(){

[0119] gqm = malloc(...);

[0120] gqm_init(qm,1);

[0121] gqm_push_block(qm); / / Send a message

[0122] return qm;}

[0123] gqm_lock(qm_lock_t*qm){gqm_pop_block(qm);}

[0124] gqm_unlock(qm_lock_t*t){gqm_push_nonblock(qm); / / Send message to activate other waiters}.

[0125] Optionally, before receiving the third request, the information synchronization method provided in the embodiment of the present application also includes: the second processing unit sends the third request to the queue manager.

[0126] Optionally, in a scenario where reading is frequent and writing is seldom done, a read-first lock is implemented. A read-first lock refers to deleting old data pointers that are no longer used in the queue and the data in the storage area indicated by the old data pointers. Assuming that the data pointer corresponding to the first data is the first data pointer, the process of reading the first data pointer in the first queue does not change the first data itself. Therefore, the position of the first data pointer in the first queue remains unchanged during the reading process; when the first data needs to be updated, the queue manager will write the data pointer corresponding to the updated first data at the end of the queue, so that the position of the first data pointer in the first queue changes, that is, the first data pointer is no longer at the end of the queue. At this time, the first data and the first data pointer are the old data and the old pointer in the first queue. When no processing unit accesses the first data pointer, the first data and the first data pointer can be deleted.

[0127] Furthermore, the information synchronization method provided by the embodiment of the present application also includes: the queue manager deletes the first data pointer and the first data according to the position of the first data pointer in the first queue and the identification information of the first data pointer.

[0128] In a possible embodiment, the queue manager does not include a queue, the electronic device includes a queue manager, a bus, multiple processing units and a memory, the queue manager and the processing unit communicate through the bus, the multiple processing units include a first processing unit and a second processing unit, and the method includes: the queue manager receives a first request from the first processing unit, the first request includes a first address and a first data, the first request is used to indicate that the target data is written to the first address, wherein the first address is the storage address of the first data in the memory, and the memory is used to store data; the queue manager responds to the first request and writes the first data to the first address in a queuing order, and the queuing order is determined by the queue manager according to the data state in the first address and the capacity of the first address; the memory receives a second request from the second processing unit and sends the target data to the bus, the second request includes the first address, and the second request is used to indicate reading the target data in the first address. In this embodiment, the first data can be directly stored in the memory to achieve information synchronization, thereby improving the efficiency of information synchronization.

[0129] For ease of understanding, combined Fig. 9 The information synchronization method provided in the embodiment of the present application is described. Fig. 9 The information synchronization method shown is applied to an electronic device, which includes multiple processing units, a queue manager, a memory and a bus. The multiple processing units and the queue manager communicate with each other through the bus, and the queue manager may include multiple queues. The multiple processing units include a first processing unit and a second processing unit.

[0130] Among them, the first processing unit can be used to send a first request to the queue manager through the bus, the first request includes a first address and first data, the first request is used to indicate that the target data is written into the first queue corresponding to the first address, and the first address is the storage address of the first data in the memory; the queue manager receives the first request, determines the first queue among multiple queues, and writes the first data into the first queue; the queue manager is also used to receive a second request sent by the second processing unit, the second request includes the first address, and the second request is used to indicate reading the target data in the first queue.

[0131] According to the information synchronization method provided by the embodiment of the present application, after the first processing unit writes the first data into the first queue through the first request, the second processing unit can read the target data in the first queue through the second request, and use the target data to execute subsequent steps, thereby realizing information synchronization between different objects through the queue; on the other hand, the first queue sends the target data to the bus only after receiving the second request to read the target data. During this process, a large amount of invalid data is not generated on the bus. Compared with memory sharing, as long as there is new data, the data is shared to the other computing units through the bus and the synchronization protocol, the efficiency of synchronization is improved.

[0132] It is understandable that, in order to realize the above functions, the information synchronization device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the information synchronization method steps of each example described in the embodiments of this document, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0133] The embodiment of the present application can divide the functional modules of the information synchronization device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. Optionally, the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation.

[0134] In the case of dividing each functional module into corresponding functional modules, Fig.10A possible structural schematic diagram of an information synchronization device involved in the above-mentioned embodiment is shown, and the information synchronization device includes: a receiving unit 111, an execution unit 112 and a sending unit 113, wherein the receiving unit 111 is used to support the information synchronization device to execute the relevant steps in S601 and S605 in the above-mentioned method embodiment; the execution unit 112 is used to support the information synchronization device to execute S603 in the above-mentioned method embodiment; the sending unit 113 is used to support the information synchronization device to execute the relevant steps in S605 in the above-mentioned method embodiment.

[0135] Optional, such as Fig.11 As shown, the information synchronization device further includes: a determination unit 114 and a deletion unit 115. The determination unit 114 is used to support the information synchronization device to execute steps S801 to S803 in the above method embodiment; the deletion unit 115 is used to delete the first data pointer and the first data according to the position of the first data pointer in the first queue and the identification information of the first data pointer.

[0136] In hardware implementation, the information synchronization device can be the above Figure 5 The queue manager shown in . For a detailed description of the queue manager, see Figure 3 The specific description in the embodiments of the present application will not be repeated here.

[0137] Optionally, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, which will not be repeated here. The device provided in the embodiment of the present application is used to perform the corresponding functions in the above embodiment, so it can achieve the same effect as the above control method.

[0138] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0139] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0140] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several requests for the device to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks or optical disks.

[0141] Another aspect of the present application provides a queue manager, the queue manager includes a processor and a memory, the memory is used to store requests, the processor is used to execute the relevant steps in the above method embodiment, the queue manager can be the above Figure 5 The queue manager provided in .

[0142] Another aspect of the present application provides an information synchronization device, the information synchronization device includes a processor and a memory, the memory is used to store the request, the processor is used to execute the relevant steps in the above method embodiment, the processor can be the above Figure 5 The processors provided in.

[0143] In another aspect of the present application, a computer-readable storage medium is provided, which includes a computer request. When the computer request is executed on an information synchronization device, the information synchronization device executes the relevant steps in the above method embodiment.

[0144] In yet another aspect of the present application, a computer program product comprising a request is provided. When the computer program product is executed on a computer device, the computer device is enabled to execute relevant steps in the above method embodiments.

[0145] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An information synchronization method, characterized in that: Applied in an electronic device, the electronic device comprises a queue manager, a bus, a plurality of processing units and a memory, the queue manager and the processing unit communicate via the bus, the queue manager comprises a queue group, the queue group comprises a plurality of queues, the plurality of processing units comprises a first processing unit and a second processing unit, the method comprises: The queue manager receives a first request from the first processing unit, the first request including a first address and first data, the first request being used to instruct writing the first data into a first queue corresponding to the first address, wherein the first address is a storage address of the first data in a memory, and the memory is used to store the data in the queue group; If the queue group includes the first queue, the queue manager writes the first data into the first queue in response to the first request; The queue manager receives a second request from the second processing unit and sends target data to a bus, wherein the second request includes the first address and is used to instruct to read the target data in the first queue.

2. The method according to claim 1, characterized in that The method further comprises: If the queue group does not include the first queue, the queue manager determines an idle queue in the queue group; The queue manager determines the idle queue as the first queue corresponding to the first address.

3. The method according to claim 2, characterized in that The queue manager determines the idle queue as the first queue corresponding to the first address, including: The queue manager uses the first address as index information of the idle queue to determine the idle queue as the first queue.

4. The method according to claim 2 or 3, characterized in that: The queue manager determines an idle queue in the queue group, including: If the queue group does not include the first queue and there is no idle queue in the queue group, the queue manager writes the second data in the second queue in the queue group into the second address of the memory, where the second address is the storage address of the second data in the memory; The queue manager initializes the second queue to determine the second queue as the idle queue; The queue manager writes the data in the second address into the idle queue.

5. The method according to any one of claims 1 to 4, characterized in that: Writing the first data into the first queue comprises: The queue manager writes the first data into a storage area indicated by a first data pointer, where the first data pointer is a data pointer corresponding to the storage area storing the first data in the first queue; The queue manager writes the first data pointer to the first queue.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: The queue manager deletes the first data pointer and the first data according to the position of the first data pointer in the first queue and the identification information of the first data pointer.

7. The method according to any one of claims 1 to 6, characterized in that: The memory includes a main memory or a cache.

8. An information synchronization method, characterized in that: Applied in an electronic device, the electronic device comprises a queue manager, a bus, a plurality of processing units and a memory, the queue manager and the processing unit communicate with each other via the bus, the plurality of processing units comprise a first processing unit and a second processing unit, the method comprises: The queue manager receives a first request from the first processing unit, the first request including a first address and first data, the first request being used to instruct writing the first data into the first address, wherein the first address is a storage address of the first data in a memory, and the memory is used to store data; The queue manager responds to the first request by writing the first data into the first address in a queuing order, wherein the queuing order is determined by the queue manager according to a state of data in the first address and a capacity of the first address; The queue manager receives a second request from the second processing unit and sends target data to the bus, wherein the second request includes the first address, and the second request is used to instruct to read the target data in the first address.

9. An information synchronization device, characterized in that: Applied in an electronic device, the electronic device further comprises a bus, a plurality of processing units and a memory, the device and the processing unit communicate via the bus, the device comprises a queue group, the queue group comprises a plurality of queues, the plurality of processing units comprises a first processing unit and a second processing unit, and the device further comprises: a receiving unit, configured to receive a first request from the first processing unit, wherein the first request includes a first address and first data, and the first request is used to instruct to write the first data into a first queue corresponding to the first address, wherein the first address is a storage address of the first data in a memory, and the memory is used to store the data in the queue group; an execution unit, configured to, when the queue group includes the first queue, respond to the first request and write the first data into the first queue; The receiving unit is further used to receive a second request from the second processing unit, where the second request includes the first address and is used to instruct to read target data in the first queue; A sending unit is used to send the target data to a bus.

10. The device according to claim 9, characterized in that The device further comprises a determining unit, wherein the determining unit is configured to: When the queue group does not include the first queue, determining an idle queue in the queue group; The idle queue is determined to be the first queue corresponding to the first address.

11. The device according to claim 10, characterized in that The determining unit is further configured to: The first address is used as index information of the idle queue to determine the idle queue as the first queue.

12. The device according to claim 10 or 11, characterized in that The determining unit is further configured to: When the queue group does not include the first queue and there is no idle queue in the queue group, writing the second data in the second queue in the queue group into a second address in the memory, where the second address is a storage address of the second data in the memory; Initializing the second queue to determine the second queue as the idle queue; The data in the second address is written into the idle queue.

13. The device according to any one of claims 9 to 12, characterized in that: The execution unit is also used for: Writing the first data into a storage area indicated by a first data pointer, where the first data pointer is a data pointer corresponding to the storage area storing the first data in the first queue; The first data pointer is written into the first queue.

14. The device according to any one of claims 9 to 13, characterized in that: The device further includes: a deleting unit, the deleting unit being configured to: The first data pointer and the first data are deleted according to the position of the first data pointer in the first queue and the identification information of the first data pointer.

15. The device according to any one of claims 9 to 14, characterized in that: The memory includes a main memory or a cache.

16. An information synchronization device, characterized in that: The information synchronization device includes a processor and a memory, the memory is used to store instructions, and the processor is used to execute the information synchronization method according to any one of claims 1 to 7 or claim 8.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a computer request, and when the computer request is executed on the information synchronization device, the information synchronization device executes the information synchronization method according to any one of claims 1 to 7 or claim 8.

18. A computer program product comprising a request, characterized in that When the computer program product is run on a computer device, the computer device executes the information synchronization method according to any one of claims 1 to 7 or claim 8.

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