Processor and computer system

Abstract

The invention discloses a processor and a computer system, the processor comprises a plurality of processing cores and an internal network, each processing core comprises an input data storage unit, an output data storage unit, a private storage unit and a private processing unit, and the input data storage unit is used for caching data input into the processing cores from the internal network; the output data storage unit is used for caching data output to the internal network by the processing core; the private storage unit is used for storing programs and data of the processing core; the private processing unit is used for calculating and processing according to the program and data of the processing core; and the plurality of processing cores are in one-way or two-way connection to form an internal network and are used for transmitting data in the output data storage unit of the sender to the input data storage unit of the receiver so as to realize communication or joint calculation of the plurality of processing cores. The method can support general calculation and greatly improve the degree of parallelism, thereby being beneficial to improving the calculation performance on the premise of maintaining the universality.

Description

Technical Field

[0001] The present invention relates to the field of computer computing, and in particular to a processor computer system. Background Art

[0002] Entering the era of artificial intelligence, the demand for computing power is getting higher and higher. Traditional processors are difficult to meet the needs of artificial intelligence. The main manifestations are as follows:

[0003] The CPU is good at general computing, but due to the limitations of the von Neumann architecture, the processor and memory are physically independent and far apart. Data is transmitted through a shared bus, and the processor is faster than the memory, resulting in higher latency and lower bandwidth for the processor to access the memory, which limits the improvement of computing performance. The use of technical solutions such as cache can improve the situation to a certain extent, but it cannot completely solve the problem. In addition, the number of cores in the CPU is small, and the cost of maintaining data consistency between cores is high, which limits the improvement of parallelism and thus computing performance.

[0004] GPU has a large number of cores and is good at parallel computing, but not good at processing complex logic, so it usually works with the CPU as a computing accelerator for the CPU. The main logic of the software runs on the CPU, and the parts of the software that are suitable for parallel computing are accelerated by the GPU. However, this GPU+CPU architecture also has shortcomings. Due to problems such as communication delays and bandwidth between the CPU and GPU, as well as CPU performance limitations, they have become important factors limiting the improvement of computing performance. In addition, when developing software, it is necessary to develop for both the CPU and GPU and handle the coordination between the two, which greatly increases the threshold and cost of learning and developing software.

[0005] FPGA has a programmable hardware structure, which makes it more flexible than fixed-architecture CPUs and GPUs, and can be optimized more finely according to application requirements. However, using FPGA requires selecting a specific configuration of FPGA according to application requirements, unlike CPUs and GPUs, which can be used directly. In addition, developing software for FPGA is equivalent to developing a digital circuit, and the threshold and cost of learning and developing software are very high. When FPGA is used to accelerate software runtime, similar to GPU, which can work as a computing accelerator for CPU, there are also similar problems such as mutual communication. Although FPGA can be optimized more finely, it may not be the best for specific applications. For example, GPU is better at image rendering.

[0006] Systolic arrays and wavefront arrays are good at parallel computing, but their structures and functions are usually closely related to specific computing tasks and algorithms. Although some of them have certain programmable or reconfigurable capabilities, they still have a certain degree of specificity, which limits their scope of application. For example, a systolic array with a fixed structure, function, and size is used as part of a TPU (Tensor Processing Unit), specifically responsible for matrix calculations. In addition, other parts of the TPU are required to adjust the data into a suitable form and input it into the systolic array in a suitable order, and then adjust the data output by the systolic array appropriately for subsequent processing.

[0007] In the past decade, artificial intelligence, especially artificial neural networks and large models, has made great progress and will continue to develop rapidly in the foreseeable future. Artificial neural networks and large models often require huge amounts of computation, and a large number of computations are suitable for parallel processing, and new models are constantly emerging. The huge amount of computation requires processors with high enough performance, and parallel computing is an effective way to improve computing performance. The various models that have already appeared and the new models that will appear in the future require processors that are sufficiently general to reduce the cost and risk of hardware investment. Therefore, there is an urgent need to develop new general-purpose parallel processors and computer architectures. Summary of the invention

[0008] In order to overcome the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a processor, comprising a plurality of processing cores and an internal network, wherein:

[0009] The processing core includes an input data storage unit, an output data storage unit, a private storage unit and a private processing unit, wherein:

[0010] The input data storage unit is used to cache the data input from the internal network to the processing core;

[0011] The output data storage unit is used to cache the data output by the processing core to the internal network;

[0012] The private storage unit is used to store programs and data of the processing core;

[0013] The private processing unit is used to perform calculations and processing according to the program and data of the processing core;

[0014] The unidirectional or bidirectional connections between the plurality of processing cores constitute an internal network, which is used to transmit data in the output data storage unit of the sender to the input data storage unit of the receiver, so as to realize communication or joint computing of the plurality of processing cores.

[0015] Furthermore, the private storage unit, the input data storage unit and the output data storage unit are independent storage entities.

[0016] Furthermore, the private storage unit, the input data storage unit and the output data storage unit are functional units divided based on the same storage entity.

[0017] Furthermore, the storage entity is a RAM or a register.

[0018] Furthermore, the internal network includes a static network and a dynamic network, wherein:

[0019] Static networks consist of pre-defined connections between several processing cores;

[0020] The dynamic network is composed of a number of routing nodes, connections between a number of routing nodes, and connections between a number of processing cores and a number of routing nodes.

[0021] Furthermore, the static network is implemented based on a topological structure of an on-chip network.

[0022] Furthermore, the dynamic network is implemented based on a network on a chip.

[0023] Furthermore, the processor is composed of 16 processing cores in a 4×4 two-dimensional layout;

[0024] The internal network includes static network and dynamic network, among which:

[0025] The network formed by each processing core being interconnected with the adjacent processing cores is a static network;

[0026] Each processing core is provided with a corresponding routing node. Each processing core is connected to the corresponding routing node, and each routing node is connected to an adjacent routing node, to form a dynamic network together.

[0027] The present invention also provides a computer system, comprising the processor and a plurality of device nodes, wherein:

[0028] Processors are used to perform control and computing tasks;

[0029] Device nodes are used to connect external devices;

[0030] Device nodes, like processing cores, are connected to the processor's internal network and communicate with each other through the internal network.

[0031] The present invention also provides an electronic device, comprising the computer system and an external device, wherein the computer system is connected to the external device via a device node to achieve communication with the external device.

[0032] Compared with the prior art, a processor of the present invention can process a large number of computing tasks in parallel by a large number of processing cores, and can also be parallelized in a pipeline manner. If there are dependencies between the tasks undertaken by some processing cores, they can also cooperate through mutual communication between the processing cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the structure of the processor of the present invention.

[0034] Figure 2 Schematic diagram of the structure of the processing core of the present invention.

[0035] Figure 3 The figure is a schematic diagram of the structure of a processor embodiment of the present invention.

[0036] Figure 4 The figure is a schematic diagram of a static network structure in a processor embodiment of the present invention.

[0037] Figure 5 A schematic diagram of a computer system of the present invention.

[0038] Figure 6 It is a schematic diagram of an electronic device of the present invention. DETAILED DESCRIPTION

[0039] The following describes the implementation of the present invention through specific examples and in conjunction with the accompanying drawings. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] The processor of the present application is composed of a plurality of processing cores interconnected through an internal network. The processor needs a plurality of processing cores to communicate and cooperate with each other through the internal network when running a software.

[0041] like Figure 1 As shown, a processor of the present invention includes several processing cores and an internal network, wherein:

[0042] The processing core includes an input data storage unit, an output data storage unit, a private storage unit and a private processing unit.

[0043] The unidirectional or bidirectional connections between the plurality of processing cores constitute an internal network, which is used to transmit data in the output data storage unit of the sender to the input data storage unit of the receiver, so as to realize communication or joint computing of the plurality of processing cores.

[0044] Each processing core can complete a certain amount of work by itself, and multiple processing cores can communicate with each other through the internal network to cooperate to complete more complex and additional tasks, thus having general parallel computing capabilities.

[0045] The technical solution of the present application is described in detail below in conjunction with various embodiments.

[0046] like Figure 2 As shown, the processing core described in the present application includes an input data storage unit, an output data storage unit, a private storage unit and a private processing unit, wherein:

[0047] The input data storage unit is used to cache the data input from the internal network to the processing core;

[0048] The output data storage unit is used to cache the data output by the processing core to the internal network;

[0049] The private storage unit is used to store programs and data of the processing core;

[0050] The private processing unit is used to perform calculations and processes according to the program and data of the processing core.

[0051] The private processing unit is an independent general-purpose CPU, ALU, vector computing unit, matrix computing unit or other specialized processing unit, and as a variation of the implementation, it may also be composed of several of these units. A single processing core may be Turing complete or not, and a single processing core may be of von Neumann architecture or other architectures, i.e., a unit known to those skilled in the art that can independently execute program instructions and perform data processing.

[0052] The input data storage unit is used to cache the data input from the internal network to the processing core. The internal network writes data to the input data storage unit, and the private processing unit retrieves data from the input data storage unit.

[0053] The output data storage unit is used to cache the data output by the processing core to the internal network.

[0054] In a processing core, as a preferred implementation, the private storage unit, the input data storage unit, and the output data storage unit are independent storage units. The private storage unit, the input data storage unit, and the output data storage unit are each a storage unit, which can be a RAM based on a technical solution such as SRAM, or can be composed or implemented by a number of registers. Of course, as a variation of the implementation, a larger storage unit can also be logically divided into the above three storage units (private storage unit, input data storage unit, and output data storage unit), each of which is used according to the corresponding purpose, all within the scope of protection of this application.

[0055] As a variation of the implementation, the RAM may be implemented or replaced by SRAM, DRAM, Flash, MRAM, PRAM, RRAM, etc.

[0056] In a processing core, the storage space of the private storage unit is small, and it can be based on faster and more expensive technical solutions such as SRAM. The distance between the private storage unit and the private processing unit is very close. The private storage unit is exclusively accessed by the private processing unit and cannot be accessed from outside the processing core. The private storage unit does not need to synchronize data with other processing cores and maintain data consistency, thereby reducing the delay of the private processing unit accessing the private storage unit. Each processing core calculates in parallel and accesses its own private storage unit in parallel.

[0057] The private storage unit stores the program of the processing core, as well as the data required and generated during the execution of the program. The specific data depends on the specific program.

[0058] From this, it can be seen that the technical solution of the present application, the entire processor composed of multiple processing cores, has greatly improved the degree of parallelism in computing processing and memory access compared to the processor of the von Neumann architecture, and the delay of the processor accessing the memory is greatly reduced, and the total bandwidth is greatly improved.

[0059] In addition, as a variant implementation, the processing cores in the processor of the present application may be completely the same or different. The differences between the processing cores involve aspects such as the processing core architecture, the storage space size and access performance of the three storage units (private storage unit, input data storage unit, and output data storage unit), the computing performance and supported functions of the private processing unit, and the power consumption of the processing core. If the processing cores are completely the same, a simple and consistent abstraction can be provided to the software, making it simpler and more flexible to allocate hardware resources to the software. If the processing cores are different and different processing cores have different advantages, the advantages of different processing cores can be reasonably utilized, so that the software can obtain optimizations such as higher operating performance, less hardware resource usage, and lower power consumption. For example, some processing cores are specially optimized for specific tasks, such as matrix calculations that are widely used in artificial neural networks, such as including matrix multiplication units to accelerate matrix multiplication.

[0060] The present application realizes communication between processing cores through an internal network, and the internal network includes a static network and a dynamic network. Among them: the static network is composed of a plurality of pre-set connections between processing cores; the dynamic network is composed of a plurality of routing nodes, a plurality of connections between routing nodes, and a plurality of connections between processing cores and a plurality of routing nodes.

[0061] The following takes a specific processor implementation as an example to illustrate the structure and working mode of the processor of the present application. Figure 3 As shown, it is a schematic diagram of the processor structure of an embodiment of the present application. In the processor of this embodiment, there are a total of 16 processing cores, which are arranged in a 4×4 two-dimensional layout. The network formed by each processing core being connected to several adjacent processing cores (indicated by solid lines) is a static network; each processing core is provided with a corresponding routing node, each processing core is connected to the corresponding routing node (indicated by dotted lines), and each routing node is connected to several adjacent routing nodes (indicated by dotted lines), together forming a dynamic network.

[0062] like Figure 3 As shown in FIG. 1 , the dynamic network is a typical two-dimensional grid based on a network on chip (NoC). Only through the dynamic network, any processing core can send data to any other processing core at any time.

[0063] The dynamic in this application means that it is not necessary to determine which processing cores running the software will communicate through the dynamic network and which will not before the software is run, such as during software design, writing, and compilation. Instead, it can be determined during the software running process, which is called dynamic.

[0064] The process of sending data over a dynamic network consists of the following steps:

[0065] First, the data to be sent and the receiving processing core are determined in the sending processing core, and written into the output data storage unit of the sending processing core by the private processing unit of the sending processing core;

[0066] Secondly, the output data storage unit of the sender's processing core is transmitted to the corresponding routing node connected to the sender's processing core. The routing node determines which of the corresponding processing core and several routing nodes connected to it is forwarded to according to the receiving processing core, routing protocol and routing algorithm;

[0067] Then, similarly, it is relayed through a series of connected routing nodes;

[0068] Finally, it is transmitted to the input data storage unit of the receiving processing core and taken away by the private processing unit of the receiving processing core.

[0069] like Figure 3 As shown in FIG. 1 , the static network directly connects adjacent processing cores, so that some processing cores are directly connected to each other. The static network adopts a typical on-chip network, which is a two-dimensional grid, in terms of topology: the processing cores correspond to the nodes of the on-chip network, and the connections between the processing cores correspond to the edges of the on-chip network.

[0070] The static network of this application means that only interconnected processing cores can communicate, and those that are not interconnected cannot. Therefore, before the software is run, such as software design, writing, and compilation, it is necessary to determine which processing cores running the software will communicate through the static network and which will not, and this does not change during the software running process, which is called static. Of course, even if it is determined before the software runs that the processing cores may communicate through the static network, during the actual operation of the software, they may not communicate through the static network according to actual conditions. Conversely, before the software runs, it is determined that the processing cores will not communicate through the static network, during the actual operation of the software, they will not communicate through the static network.

[0071] The process of sending data through a static network is: first, the data to be sent and the receiving processing core are determined in the sending processing core, and the private processing unit of the sending processing core writes it into the output data storage unit of the sending processing core; then, based on the receiving processing core, it is decided which connected processing core to transmit it to; finally, it is transmitted to the input data storage unit of the receiving processing core and taken away by the private processing unit of the receiving processing core.

[0072] In the above embodiment, there are 16 processing cores in total, in a 4×4 two-dimensional layout, the dynamic network is based on a two-dimensional grid, and the static network is based on a two-dimensional grid topology structure to connect adjacent processing cores. As a variation of the embodiment, in an actual processor, a larger number of processing cores can be built, using a one-dimensional, two-dimensional, or three-dimensional layout, and a more complex internal network can be built according to the inventive idea of ​​the present application.

[0073] From the above, it can be seen that since each processing core has certain storage and computing functions, and is interconnected through an internal network, a general-purpose parallel complex processor can be realized.

[0074] The connections between processing cores that belong to the static network are called static connections. A static connection is like a dedicated communication line. Different static connections will not share hardware resources such as connections, which is conducive to reducing latency, increasing bandwidth, ensuring that the order of data transmission remains unchanged, and ensuring that latency and bandwidth are as stable and predictable as possible for each static connection. Since the latency and bandwidth of static connections are as stable and predictable as possible, the software can be optimized based on these predicted parameters, so that the software can achieve higher operating performance and other optimizations. For example, in software logic, processing cores A and B communicate frequently, while processing cores C and D only communicate occasionally. Then the processing cores A, B, C, D in the software logic, and the static interconnections between them, respectively correspond to which processing core and static interconnection on the hardware, which can be determined according to the actual hardware situation, with a relatively higher priority to ensure the latency and bandwidth of the static interconnection between processing cores A and B, and a relatively lower priority to ensure the latency and bandwidth of the static interconnection between processing cores C and D. In addition, if the parameters of both the processing core and the static network are used at the same time, the software can be optimized more finely.

[0075] Static networks are pre-set, that is, they are set before the software runs or even when the processor is designed or produced, and remain unchanged during the software operation. In addition, the parameters of the static connections in the static network are as stable and predictable as possible, so that before the software runs, it can be determined which functions of the software run in the static network and which run in the dynamic network based on the parameters of the static network and the dynamic network. The preset settings of the static network first pre-set a physically connected physical circuit. Which processing cores are connected and which are not can be set by selecting a topology structure, or by a programmable method, or by using circuit switching, so that the static network can be set as a series of dedicated communication lines before the software runs or even when the processor is designed or produced. For example Figure 3 The static network in the illustrated embodiment is set by selecting a two-dimensional grid topology structure.

[0076] Another example: Assuming that the number of processing cores is small, the static network supports programmable interconnection between any two processing cores, and limits each processing core after static network programming to no more than X static input connections and no more than Y static output connections, it can be implemented based on a crossbar network. The input data storage unit of each processing core corresponds to X static input connections and X output connections of the crossbar network; the output data storage unit of each processing core corresponds to Y static output connections and Y input connections of the crossbar network. If a processing core has less than X static input connections, the extra output connections in the crossbar network are idle; if a processing core has less than Y static output connections, the extra input connections in the crossbar network are idle. If there are N processing cores in total, the crossbar network has N·X output connections and N·Y input connections in total.

[0077] It can be seen from this that the processor of the present application, when applied to some relatively complex computing tasks, can be decomposed into multiple simpler tasks, which are processed in parallel on multiple processing cores, and the processing cores can communicate with each other for cooperation. For a large number of computing tasks, a large number of processing cores can be used to process them in parallel, and they can also be processed in parallel in a pipeline manner. If there is a dependency relationship between the tasks undertaken by some processing cores, they can also be coordinated through mutual communication between the processing cores. For example:

[0078] With a Figure 3 The processor shown is almost the same as the one shown, but is larger in scale and has more processing cores. The technical solution for its implementation is explained by taking matrix multiplication, a typical computing task in artificial neural networks, as an example. After the processor is programmed, a certain part simulates a two-dimensional systolic array or wavefront array, and uses the corresponding systolic algorithm to calculate matrix multiplication. Among them, the processing core implements the processing element (PE) of the systolic array and wavefront array, and the internal network implements the connection between the PEs of the systolic array and the wavefront array. Obviously, as long as the processing cores that implement PEs can communicate with each other through the internal network, there is no need to make the PEs adjacent in space like the systolic array and wavefront array. Usually, a processing core implements a part of the systolic array and wavefront array, including several PEs and the communication between PEs, rather than a single PE. From Figure 3It can be seen that programming the processor can realize a local simulation of a two-dimensional pulsation array or wavefront array, and can be used to implement the pulsation algorithm. Of course, after the processor is programmed, other parts are required to adjust the data into a suitable form and input it into the pulsation array or wavefront array in a suitable order, and then the data output by the pulsation array or wavefront array is appropriately adjusted for subsequent processing. The pulsation array requires all PEs to work synchronously with a unified clock, while the wavefront array has no such limitation and is a data-driven method, which can be realized by the processors constituted by the present application. For processors that support data flow graphs as computing models, it is also feasible to program to implement other functions. Compared with special-purpose pulsation arrays and wavefront arrays, programmable processors that support data flow graph models are more flexible and versatile.

[0079] Depend on Figure 3 The static network in the processor composed of 16 processing cores in the embodiment of the present application is a 2D mesh topology. As a variation of the implementation method, other topologies may be used. For example, Figure 4 For a static network based on Hypercube ( Figure 4 The dynamic network is omitted in the figure), that is, the topology structure is based on the typical on-chip network, the Hypercube network: the processing cores correspond to the nodes of the on-chip network, and the connections between the processing cores correspond to the edges of the on-chip network. In this embodiment, the processing cores of this row, such as the processing core (1,1), are connected to several processing cores (1,2) and processing core (1,3) of this row, and are also connected to the processing cores (2,1) and processing core (3,1) of this column, forming a static network of a hypercube, thereby realizing long-distance connection and balancing the number of connections and the connection distance.

[0080] The static network of the present application may also have other implementation methods to connect multiple processing cores. Similar to the method based on the hypercube network, the static network may also be implemented based on a two-dimensional mesh (2D Mesh), a two-dimensional ring network (2DTorus), an ILLIAC network, a cube connected cycle (CCC), a one-dimensional linear array (1D Linear Array), a ring (Ring), a chordal ring (Chordal Ring), a fully connected network, a barrel shifter network (Barrel Shifter), a multi-level PM2I network, a tree (Tree), a tree network (Mesh of Tree), a star network (Star), other networks in the k-ary d-dimensional Mesh topology family, other networks in the k-ary d-dimensional Torus topology family, and the like.

[0081] The dynamic network of the present application usually adopts a bus (Bus) or a technical solution based on a network on chip (NoC). Different data transmission paths in the dynamic network share hardware resources such as communication lines, buses, connections, routing nodes, etc., thereby ensuring flexible connections between a large number of processing cores under limited hardware resources.

[0082] For different application scenarios, dynamic networks can have different implementation schemes. For example, if the number of processing cores is small, a bus can be used. For example, if the number of processing cores is large, a two-dimensional mesh (2DMesh) can be used. In addition to the above two examples, dynamic networks can also use two-dimensional torus, ILLIAC network, hypercube network, cube connected cycle (CCC), one-dimensional linear array (1D LinearArray), ring, token ring, chordal ring, fully connected network, barrel shifter, multi-level PM2I network, tree, mesh of tree, fat tree, star network, other networks in k-ary d-dimensional mesh topology family, other networks in k-ary d-dimensional torus topology family, etc.

[0083] Known multi-core processors, various innovative AI accelerators, etc., basically use dynamic network solutions for a large number of core interconnections, but this application uses a combination of dynamic and static networks to give full play to the advantages of dynamic and static networks. For example, since the communication lines of static networks are exclusive, low-latency, high-bandwidth, as stable and predictable as possible, the software tries to use static networks to improve performance, but some of the logic in the software is too complex, or related to external input, or related to unknown modules, resulting in some of the processing core interconnections required to run the software. The relationship cannot be determined or there are too many possibilities before the software is run, such as software design, writing, and compilation. At this time, it is more flexible and general to use dynamic networks.

[0084] From this, it can be seen that the processor of the present application can not only realize complex general-purpose calculations, but also realize a large number of parallel calculations, meeting the various computing power and performance requirements required by today's complex and continuously innovative artificial intelligence models.

[0085] See also Figure 5 Based on the processor of the above embodiment, the present application further provides a computer system, including several processing cores, at least one device node and an internal network, wherein the several processing cores and the device nodes are connected to the internal network, wherein:

[0086] Several processing cores are used to perform control and computing tasks;

[0087] Device nodes are used to connect external devices such as input devices, output devices, and storage devices, and to enable indirect communication between the processing core and external devices.

[0088] See also Figure 6 Based on the above embodiments, the present application also provides an electronic device, including the computer system and an external device, wherein the external device is connected to a device node in the computer system via a special connection associated with the external device.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person skilled in the art may modify and alter the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the claims.

Claims

1. A processor, characterized in that: It includes several processing cores and internal networks, including: The processing core includes an input data storage unit, an output data storage unit, a private storage unit and a private processing unit, wherein: The input data storage unit is used to cache the data input from the internal network to the processing core; The output data storage unit is used to cache the data output by the processing core to the internal network; The private storage unit is used to store programs and data of the processing core; The private processing unit is used to perform calculations and processing according to the program and data of the processing core; The unidirectional or bidirectional connections between the plurality of processing cores constitute an internal network, which is used to transmit data in the output data storage unit of the sender to the input data storage unit of the receiver, so as to realize communication or joint computing of the plurality of processing cores.

2. The processor according to claim 1, wherein: The private storage unit, the input data storage unit and the output data storage unit are independent storage entities.

3. The processor according to claim 1, wherein: The private storage unit, the input data storage unit and the output data storage unit are functional units divided based on the same storage entity.

4. The processor according to claim 1, wherein: The storage entity is a RAM or a register.

5. The processor according to claim 1, wherein: The internal network includes a static network and a dynamic network, wherein: Static networks consist of pre-defined connections between several processing cores; The dynamic network is composed of a number of routing nodes, connections between a number of routing nodes, and connections between a number of processing cores and a number of routing nodes.

6. The processor according to claim 5, characterized in that: The static network is implemented based on the topology structure of the on-chip network.

7. The processor according to claim 5, characterized in that: The dynamic network is implemented based on a network on chip.

8. The processor according to claim 1, wherein: The processor consists of 16 processing cores in a 4×4 two-dimensional layout; The internal network includes static network and dynamic network, among which: The network formed by each processing core being interconnected with the adjacent processing cores is a static network; Each processing core is provided with a corresponding routing node. Each processing core is connected to the corresponding routing node, and each routing node is connected to an adjacent routing node, to form a dynamic network together.

9. A computer system, characterized in that: The method comprises the processor according to any one of claims 1 to 8 and a plurality of device nodes, wherein: Processors are used to perform control and computing tasks; Device nodes are used to connect external devices; Device nodes, like processing cores, are connected to the processor's internal network and communicate with each other through the internal network.

10. An electronic device, characterized in that: The computer system comprises the computer system as claimed in claim 9 and an external device, wherein the computer system is connected to the external device via a device node to achieve communication with the external device.

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