High performance communication processor application verification system and method

Abstract

The invention belongs to the field of integrated circuit application verification and development, and discloses a high-performance communication processor application verification system and method. Comprising a DDR controller interface application verification module, a USB application verification module, an Ethernet application verification module, a display control application verification module, an SDHC application verification module, an IFC application verification module and a function multiplexing high-speed serial communication interface application verification module. Application verification design of a DDR controller interface, an IFC controller interface, an SDHC controller interface, a display control interface, a function-multiplexing high-speed serial communication interface, a USB, an Ethernet and other functional modules can be carried out, application verification and performance testing of design functions of the functional modules can be completed, application examples and development modes of the functional modules are designed, the design examples are provided for user application, and the development efficiency of the functional modules is improved. A platform is provided for application development of a user, and application verification and development of integrated design of all design functions of a high-performance communication processor such as LT1022 are achieved.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit application verification and development, and relates to a high-performance communication processor application verification system and method. Background Art

[0002] LT1022 is a dual-core high-performance communication processor chip that integrates two 64-bit Power e5500 cores (Power Architecture enhanced 5500 series cores). The main frequency can reach 1.5GHz, each core has a private L1 I-Cache (first-level instruction cache) of 32KB, L1 D-Cache (first-level data cache) of 32KB, and L2 Cache (second-level cache) of 256KB. The dual-core shared L3-Cache (third-level cache) is not less than 256KB; it supports 32-bit and 64-bit DDR3L (800MHz) / DDR4 (800MHz) with ECC (error checking and correction) function, 2-way USB2.0 / 3.0 controller and matching USB PHY (physical layer); when the Ethernet interface is configured as SGMII (Serial Gigabit Media Independent Interface) or QSGMII (Quad Small Form-factor Pluggable Gigabit Media Independent Interface), it supports 2 / 3 layer switching function, 8K MAC address table, 4K VLAN address table; the Ethernet interface supports 2 RGMII (Reduced Gigabit Media Independent Interface) or 1 MII (Media Independent Interface) interface; the high-speed interface supports 8 channels of 5Gbps / 2.5Gbps, which can be configured as 8 or 5 SGMII, or 2 QSGMII, or 4 PCIe3.0 (Peripheral Component Interconnect Express 3.0, the third generation of fast peripheral component interconnect standard), or 2 SATA3.0 (Serial Advanced Technology Attachment 3.0, the third generation of Serial Advanced Technology Attachment), or 1 Aurora (a high-speed serial communication protocol); integrated with 4 I2C (Inter-Integrated Circuit, two-wire serial bus) controllers, 2 DUART (Dual Universal Asynchronous Receiver / Transmitter, dual universal asynchronous receiver / transmitter), GPIO (General Purpose Input / Output, general purpose input / output) controller, SPI (Serial Peripheral Interface, serial peripheral interface) controller, IFC (Inter-Flash Controller, an interface controller for connecting and managing flash memory devices) controller; 2 8-channel DMA (Direct Memory Access, direct memory access); the internal interconnect bus supports consistent transmission, priority and bandwidth allocation; DPAA (Data Path Acceleration Architecture, data path acceleration architecture) supports message hardware parsing (2-layer VLAN (virtual LAN), 4-layer MPLS (multi-protocol label switching), L3 layer (network layer) and L4 layer (transport layer)), classification and distribution, and supports 1588 protocol (Precision Time Protocol, Precision Time Protocol), supports hardware accelerated security engine; QUICC engine is a 32-bit RISC (Reduced Instruction Set Computing) communication coprocessor core, supports TDM (Time Division Multiplexing) interface / HDLC (High-Level Data Link Control) interface / UART (Universal Asynchronous Receiver / Transmitter) interface. .

[0003] The existing application verification implementation methods for ordinary processors or integrated circuits cannot meet the application verification requirements of LT1022. The application verification implementation block diagram of ordinary processors or integrated circuits is as follows: Figure 1As shown. First, ordinary processors generally have a low operating frequency, and the corresponding memory interface rate is low, and the accessible storage space is also small, which cannot meet the application verification requirements of the high-speed, large-bit-width and large-storage-space memory controller interface of LT1022; secondly, due to performance reasons, the integrated communication interface of existing ordinary processors or integrated circuits is generally a low-speed interface, and its application verification and development design cannot meet the application verification and testing of LT1022's multiple high-speed interfaces and the design function of high-speed interfaces reusing the same pins; finally, ordinary processors or integrated circuits generally integrate a dedicated timing memory controller interface, which cannot meet the application verification and development of LT1022's IFC control interface that is compatible with many memories with different timing requirements. Summary of the invention

[0004] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a high-performance communication processor application verification system and method.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions: The first aspect of the present invention provides a high-performance communication processor application verification system, including a DDR controller interface application verification module, a USB application verification module, an Ethernet application verification module, a display control application verification module, an SDHC application verification module, an IFC application verification module and a high-speed serial communication interface application verification module with multiple functions; the DDR controller interface application verification module adopts a DIMM module connector; the USB application verification module includes a 2-way USB3.0 application verification circuit that is backward compatible with the USB2.0 working mode; the Ethernet application verification module includes 2-way Ethernet application verification units, one of which is a GMII / MII compatible working mode and the other is an RGMII working mode; the display control application verification module includes a differential signal converter, a connector and a display control adapter connected in sequence; the SDHC application verification module includes a connector and an SD card, an eSDHC memory card and an eMMC device card connected to the connector; the IFC application verification module includes a Nand FLASH device, a NorFLASH device, a SRAM device and a connector, and the Nand FLASH device, the Nor FLASH devices and SRAM devices are used to complete the functional verification of memory compatibility with different timing requirements and lead out to the connector; the functionally reused high-speed serial communication interface application verification module includes the high-speed connector FMC and the FMC_SGMII daughter board, FMC_QSGMII daughter board, FMC_SATA daughter board, FMC_EYE_AURORA daughter board and FMC_PCIe daughter board connected to the high-speed connector FMC; the FMC_SGMII daughter board is used for the application verification design of 8-way high-speed Ethernet and the application verification of the high-speed SerDes interface multiplexing into 8-way SGMII working mode; the FMC_QSGMII daughter board is used for the application verification of the QSGMII multiplexing function; the FMC_SATA daughter board is used for the application verification of 2 groups of SATA interfaces; the FMC_EYE_AURORA daughter board is used for eye diagram testing and interface interconnection testing with corresponding devices; the FMC_PCIe daughter board is used for the application verification of PCIe design functions.

[0006] Optionally, the DIMM module connector includes 5 DDR3 SDRAM and 5 DDR4 SDRAM memory cards, which are used for application verification of the design function of the 72-bits wide DDR controller interface being compatible with DDR3 and DDR4.

[0007] Optionally, the USB3.0 application verification circuit that is backward compatible with the USB2.0 working mode includes a USB3.0 Type-A Female connector, a PUSB3FR4 front-end protector, a differential reference crystal oscillator module, a SY6280AAC power supply module and an ESD05V14T-LC ESD protection device; the PUSB3FR4 front-end protector is used to connect to the communication processor USB interface; the differential reference crystal oscillator module is used to provide a 100 MHz differential reference clock for the communication processor USB interface; the SY6280AAC power supply module is used to enable the output of its power conversion through the communication processor USB interface and to power the VBUS of the USB3.0 Type-A Female connector; the ESD05V14T-LC ESD protection device is used to connect to the communication processor USB interface.

[0008] Optionally, the 2-way Ethernet application verification unit includes an Ethernet controller 88E1111 designed for a GMII / MII compatible working mode, and an Ethernet controller DP83867IRPAP designed for a RGMII working mode.

[0009] Optionally, the connector of the display control application verification module adopts the connector DF14-20P-1.25H, the connector and the display control adapter are connected through the connector QSH060-01-FDA, and the differential signal converter adopts the differential signal converter DS90C387R, which is used to connect the LCD function pins of the communication processor.

[0010] Optionally, the display control application verification module also includes a signal extraction device; the signal extraction device is used to extract the signal of the communication processor that is not multiplexed with the LCD function pin, and use it as a trigger signal.

[0011] Optionally, the Nand FLASH device of the IFC application verification module is a 1GB 8-BIT NAND FLASH device MT29F8G08ABBCAH4:C, the Nor FLASH device is a 128MB 16-BIT NOR FLASH device JS28F00AM29EWHA, and the SRAM device is an SRAM device IS62WV51216BLL-55TLI.

[0012] Optionally, the FMC_SGMII daughter board includes a power module, a high-speed SerDes interface module, an Ethernet PHY chip 88E1145-1 and an Ethernet PHY chip 88E1145-2; the power module is connected to the power supply through the FMC connector and converted into the voltage required on the FMC_SGMII daughter board, and the high-speed SerDes interface module is configured as an 8-way SGMII working mode, of which 4 are connected to the Ethernet PHY chip 88E1145-1, and the other 4 are connected to the Ethernet PHY chip 88E1145-2, for realizing the application verification of 8-way high-speed Ethernet and the application verification of the function of multiplexing the high-speed SerDes interface into the SGMII working mode; the FMC_QSGMII daughter board includes a power module, a high-speed SerDes interface, two Ethernet switch chips F104S8A, ICS843004-01 clock generator, eight H5008 network transformers and RJ45_LED_8 indicator light module; receive power and four pairs of high-speed differential signals through FMC connector; the power module is used to convert voltage, the high-speed SerDes interface is configured as two-way QSGMII mode, connected to two Ethernet switch chips F104S8A respectively, each Ethernet switch chip F104S8A extends four QSGMII ports, the ICS843004-01 clock generator generates two differential reference clocks, which are supplied to the two Ethernet switch chips F104S8A respectively, and the eight QSGMII ports are connected to the RJ45_LED_8 indicator light module through eight H5008 network transformers respectively, which is used for application verification of QSGMII multiplexing function.

[0013] Optionally, the FMC_SATA daughter board includes a SATA interface connector SATA_CONN0, a SATA interface connector SATA_CONN1 and two SATA devices; the two groups of differential signals of the communication processor are respectively transmitted to the SATA interface connector SATA_CONN0 and the SATA interface connector SATA_CONN1 through the FMC connector; the two SATA devices are respectively connected to the SATA interface connector SATA_CONN0 and the SATA interface connector SATA_CONN1; the FMC_EYE_AURORA daughter board includes a SATA interface connector SATA_CONN0, a first SMA connector and a second SMA connector; the three groups of differential signals SATA0, SATA1 and AURORA of the communication processor are respectively transmitted to the SATA interface connector SATA_CONN0, the first SMA connector and the second SMA connector through the FMC connector, and the SATA interface connector SATA_CONN0 Used to connect standard SATA interface devices; the first SMA connector is used for eye diagram testing, and the SATA1 wiring is consistent with SATA0; the second SMA connector is used for interface interconnection testing with corresponding devices; the FMC_PCIe daughter board includes a 4X PCIe connector PCIE-064-02-FD-TH, a PCIECARD_EDGE connector and a transfer cable; the 8 groups of differential signals SD_TX / RX0~SD_TX / RX7 of the communication processor and 4 groups of differential signals SD_TX / RX0~SD_TX / RX3 and a pair of differential reference clocks are connected to the 4X PCIe connector PCIE-064-02-FD-TH through the FMC connector, and the 4 groups of differential signals SD_TX / RX4~SD_TX / RX7 are connected to the PCIECARD_EDGE connector; the PCIe connector PCIE-064-02-FD-TH and the PCIECARD_EDGE connector are interconnected through a transfer cable.

[0014] According to a second aspect of the present invention, a high-performance communication processor application verification method based on the above-mentioned high-performance communication processor application verification system is provided, comprising: performing application verification of the design function of the communication processor's 72-bit DDR controller interface being compatible with DDR3 and DDR4 through a DDR controller interface application verification module; performing application verification of the design function of the communication processor's USB interface through a USB application verification module; performing application verification of three different working modes designed for the communication processor's Ethernet module through an Ethernet application verification module; performing application verification of the communication processor's 24-bit display control module through a display control application verification module; performing application verification of the design function of the communication processor's high-speed memory controller interface through an SDHC application verification module; performing application verification of the communication processor's IFC controller's compatibility with different memory timings through an IFC application verification module; and performing application verification of the communication processor's 8-channel high-speed interface with function multiplexing through a function-multiplexing high-speed serial communication interface application verification module.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The high-performance communication processor application verification system of the present invention can design application verification of functional modules such as DDR controller interface, IFC controller interface, SDHC controller interface, display control interface, high-speed serial communication interface with function reuse, USB and Ethernet, etc., complete application verification of its design functions and performance test, design its application examples and development mode, provide design examples for user applications, provide a platform for user application development, and solve the application verification and development of high-performance communication processors such as LT1022 with integrated design of all design functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Verify the implementation block diagram for applications of existing common processors or integrated circuits.

[0017] Figure 2 The figure is a structural block diagram of a high-performance communication processor application verification system according to an embodiment of the present invention.

[0018] Figure 3 This is a structural block diagram of a DDR controller interface application verification module according to an embodiment of the present invention.

[0019] Figure 4 This is a structural block diagram of a USB application verification module according to an embodiment of the present invention.

[0020] Figure 5This is a structural block diagram of an Ethernet application verification module according to an embodiment of the present invention.

[0021] Figure 6 It is a structural block diagram of a display control application verification module according to an embodiment of the present invention.

[0022] Figure 7 FIG. 4 is a structural block diagram of an SDHC application verification module according to an embodiment of the present invention.

[0023] Figure 8 This is a structural block diagram of a high-speed serial communication interface application verification module with multiplexing functions according to an embodiment of the present invention.

[0024] Fig. 9 The figure is a block diagram of the principle structure of the FMC_SGMII daughter board according to an embodiment of the present invention.

[0025] Fig.10 The figure is a block diagram of the principle structure of the FMC_QSGMII daughter board according to an embodiment of the present invention.

[0026] Fig.11 The figure is a block diagram of the principle structure of the FMC_SATA daughter board according to an embodiment of the present invention.

[0027] Fig.12 This is a block diagram of the principle structure of the FMC_EYE_AURORA daughter board according to an embodiment of the present invention.

[0028] Fig.13 The figure is a block diagram of the principle structure of the FMC_PCIe daughter board according to an embodiment of the present invention.

[0029] Fig.14 This is a structural block diagram of an IFC application verification module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] The present invention is further described in detail below in conjunction with the accompanying drawings: See also Figure 2 In one embodiment of the present invention, a high-performance communication processor application verification system is provided, including a DDR controller interface application verification module, a USB application verification module, an Ethernet application verification module, a display control application verification module, an SDHC application verification module, an IFC application verification module and a high-speed serial communication interface application verification module with functional reuse.

[0033] Among them, the DDR controller interface application verification module adopts a DIMM module connector; the USB application verification module includes 2 USB3.0 application verification circuits that are backward compatible with the USB2.0 working mode; the Ethernet application verification module includes 2 Ethernet application verification units, one for the GMII / MII compatible working mode, and the other for the RGMII working mode; the display control application verification module includes a differential signal converter, a connector and a display control adapter connected in sequence; the SDHC application verification module includes a connector and an SD card, eSDHC memory card and eMMC device card connected to the connector; the IFC application verification module includes a Nand FLASH device, a Nor FLASH device, a SRAM device and a connector, and the Nand FLASH device, Nor FLASH devices and SRAM devices are used to complete the functional verification of memory compatibility with different timing requirements and lead out to the connector; the functionally reused high-speed serial communication interface application verification module includes the high-speed connector FMC and the FMC_SGMII daughter board, FMC_QSGMII daughter board, FMC_SATA daughter board, FMC_EYE_AURORA daughter board and FMC_PCIe daughter board connected to the high-speed connector FMC; the FMC_SGMII daughter board is used for the application verification design of 8-way high-speed Ethernet and the application verification of the high-speed SerDes interface multiplexing into 8-way SGMII working mode; the FMC_QSGMII daughter board is used for the application verification of the QSGMII multiplexing function; the FMC_SATA daughter board is used for the application verification of 2 groups of SATA interfaces; the FMC_EYE_AURORA daughter board is used for eye diagram testing and interface interconnection testing with corresponding devices; the FMC_PCIe daughter board is used for the application verification of PCIe design functions.

[0034] In a possible implementation, the DIMM module connector includes 5 DDR3 SDRAM and 5 DDR4 SDRAM memory cards, which are used for application verification of the design function of a 72-bits wide DDR controller interface being compatible with DDR3 and DDR4.

[0035] For details, see Figure 3, because the high-performance communication processor integrates a 72-bit DDR controller interface, a DIMM module is designed to complete the compatibility function verification of DDR3 SDRAM and DDR4 SDRAM. According to the 72-bit DDR controller interface designed by LT1022, it supports 32-bit and 64-bit DDR3L (800MHz) / DDR4 (800MHz) with ECC function, and is designed into a DIMM module connector mode, 64-bit data width + 8-bit ECC function, and 5 DDR3L SDRAM and 5 DDR4 SDRAM memory cards are designed respectively, of which the first 4 pieces form a 16-bit*4=64-bit data width, and the lower 8 bits of the 5th piece are used as the verification of the ECC function, completing the application verification and development of the design function of the 72-bit DDR controller interface compatible with DDR3L and DDR4.

[0036] In a possible implementation, the USB3.0 application verification circuit that is backward compatible with the USB2.0 working mode includes a USB3.0 Type-A Female connector, a PUSB3FR4 front-end protector, a differential reference crystal oscillator module, a SY6280AAC power supply module and an ESD05V14T-LC ESD protection device; the PUSB3FR4 front-end protector is used to connect to the USB interface of the communication processor; the differential reference crystal oscillator module is used to provide a 100MHz differential reference clock for the USB interface of the communication processor; the SY6280AAC power supply module is used to enable the output of its power conversion through the USB interface of the communication processor and to power the VBUS of the USB3.0 Type-A Female connector; the ESD05V14T-LC ESD protection device is used to connect to the USB interface of the communication processor.

[0037] For details, see Figure 4 , the 2-way USB interface designed according to the high-performance communication processor adopts a USB2.0 / 3.0 compatible design. Based on the 2-way USB2.0 / 3.0 controller integrated in LT1022 and the matching USB PHY, two independent differential reference crystal modules are used to provide accurate 100MHz differential reference clocks for the two USBs respectively; +5V input is 2 SY6280AAC, and the USB0_PWREN and USB1_PWREN of LT1022 respectively enable their power conversion outputs to power the VBUS of the connector; ESD05V14T-LC is used to provide ESD and voltage sensitivity protection for high-speed differential signals; USB3_0_A_Female and PUSB3FR4 are connected, and the two USB interfaces are designed as USB3.0, which are backward compatible with USB2.0 working mode.

[0038] In a possible implementation manner, the 2-way Ethernet application verification unit includes an Ethernet controller 88E1111 designed in a GMII / MII compatible working mode, and an Ethernet controller DP83867IRPAP designed in an RGMII working mode.

[0039] For details, see Figure 5 , based on the 2-way Ethernet module integrated with high-performance communication processor, the application verification of GMII / MII working mode and RGMII working mode is designed respectively. LT1022 integrates 2-way Ethernet MAC interface, one is connected to 88E1111 and designed to be GMII / MII compatible working mode, and the other is connected to DP83867IRPAP and designed to be RGMII working mode, completing the application verification of three different working modes of Ethernet module design.

[0040] In a possible implementation, the connector of the display control application verification module uses the connector DF14-20P-1.25H, the connector and the display control adapter are connected via the connector QSH060-01-FDA, and the differential signal converter uses the differential signal converter DS90C387R, which is used to connect the LCD function pins of the communication processor.

[0041] Optionally, the display control application verification module also includes a signal extraction device; the signal extraction device is used to extract the signal of the communication processor that is not multiplexed with the LCD function pin, and use it as a trigger signal.

[0042] For details, see Figure 6 According to the multiplexing of LCD controller interface and GPIO function pins of high-performance communication processor, the 24-bit display control application verification and GPIO function reservation are designed. LT1022 integrates LCD control interface, and the pins are multiplexed with GPIO functions. The LCD function pins are connected to DS90C387R, and the output high-speed differential signals are connected to the connector DF14-20P-1.25H, and equipped with QSH060-01-FDA to complete the 24-bit display control module application verification design; the remaining signals that are not multiplexed with LCD function pins are led out and used as trigger signals for other modules.

[0043] In one possible implementation, see Figure 7, the high-performance communication processor integrates a high-speed memory interface, and the design is compatible with the functional verification of high-speed memory interfaces such as SD / eSDHC / eMMC. According to the high-speed memory controller interface integrated in LT1022, it is compatible with high-speed memories such as SD / eSDHC / eMMC, connects relatively common high-speed connectors, develops corresponding SD cards, eSDHC memory cards and eMMC device cards, and completes the application verification of all design functions.

[0044] In a possible implementation, the functionally multiplexed high-speed serial communication interface application verification module includes a high-speed connector FMC and an FMC_SGMII daughter board, an FMC_QSGMII daughter board, an FMC_SATA daughter board, an FMC_EYE_AURORA daughter board and an FMC_PCIe daughter board connected to the high-speed connector FMC.

[0045] For details, see Figure 8 , using the multi-function multiplexed SerDes interface integrated in the high-performance communication processor, the key signals and control signals are brought out through the FMC interface, and different FMC daughter boards are plugged in to complete functional verification and performance testing.

[0046] In a possible implementation, the FMC_SGMII daughter board includes a power module, a high-speed SerDes interface module, an Ethernet PHY chip 88E1145-1 and an Ethernet PHY chip 88E1145-2; the power module is connected to the power supply through the FMC connector and converted into the voltage required on the FMC_SGMII daughter board, and the high-speed SerDes interface module is configured as an 8-way SGMII working mode, of which 4 are connected to the Ethernet PHY chip 88E1145-1, and the other 4 are connected to the Ethernet PHY chip 88E1145-2, for realizing the application verification of 8-way high-speed Ethernet and the application verification of the function of multiplexing the high-speed SerDes interface into the SGMII working mode.

[0047] For details, see Fig. 9 To verify the SGMII function, the FMC_SGMII daughter board was designed. After the FMC connector, the +12V power supply and high-speed interface were connected from the motherboard. The power module was designed on the daughter board to complete the power supply design of multiple power supplies on the daughter board; the high-speed SerDes interface was set to 8-way SGMII working mode, where Port 0-3 was connected to 88E1145-1, and Port4-7 was connected to 88E1145-2, completing the application verification design of 8-way high-speed Ethernet, and completing the application verification of high-speed SerDes interface multiplexing to 8-way SGMII working mode.

[0048] In a possible implementation, the FMC_QSGMII daughter board includes a power module, a high-speed SerDes interface, two Ethernet switch chips F104S8A, an ICS843004-01 clock generator, eight H5008 network transformers and an RJ45_LED_8 indicator light module; power and four pairs of high-speed differential signals are received through the FMC connector; the power module is used to convert voltage, the high-speed SerDes interface is configured as a two-way QSGMII mode, which is respectively connected to the two Ethernet switch chips F104S8A, each Ethernet switch chip F104S8A extends four QSGMII ports, the ICS843004-01 clock generator generates two differential reference clocks, which are respectively supplied to the two Ethernet switch chips F104S8A, and the eight QSGMII ports are respectively connected to the RJ45_LED_8 indicator light module through eight H5008 network transformers for application verification of the QSGMII multiplexing function.

[0049] For details, see Fig.10 , designed the FMC_QSGMII daughter board to verify the QSGMII function. After passing through the FMC connector, connect the +12V power supply and 4 pairs of high-speed differential signals from the motherboard. Design the power module on the daughter board to complete the power supply design of multiple power supplies on the daughter board; set the high-speed SerDes interface to 2-way QSGMII working mode, QSGMII1 connects to F104S8A-1, expands QSG1- QSG4, QSGMII2 connects to F104S8A-2, expands QSG5- QSG8; use ICS843004-01 to generate 2 differential reference clocks, respectively for 2 F104S8A, 8 network ports are connected to 8 H5008, and then connected to RJ45_LED_8, completing the application verification of the designed QSGMII multiplexing function.

[0050] In a possible implementation, the FMC_SATA daughter board includes a SATA interface connector SATA_CONN0, a SATA interface connector SATA_CONN1, and two SATA devices; two groups of differential signals of the communication processor are respectively transmitted to the SATA interface connector SATA_CONN0 and the SATA interface connector SATA_CONN1 through the FMC connector; and the two SATA devices are respectively connected to the SATA interface connector SATA_CONN0 and the SATA interface connector SATA_CONN1.

[0051] For details, see Fig.11In order to verify the reused SATA function, the FMC_SATA daughterboard is designed. Through the FMC connector, the two groups of differential signals of SATA0 and SATA1 are connected to SATA_CONN0 and SATA_CONN1 respectively, and then the standard SATA devices are plugged in to complete the application verification of the designed two groups of SATA interfaces.

[0052] In a possible implementation, the FMC_EYE_AURORA daughter board includes a SATA interface connector SATA_CONN0, a first SMA connector and a second SMA connector; the three groups of differential signals SATA0, SATA1 and AURORA of the communication processor are transmitted to the SATA interface connector SATA_CONN0, the first SMA connector and the second SMA connector respectively through the FMC connector, and the SATA interface connector SATA_CONN0 is used to connect a standard SATA interface device; the first SMA connector is used to perform an eye diagram test, and the SATA1 wiring is consistent with SATA0; the second SMA connector is used for interface interconnection testing with the corresponding device.

[0053] For details, see Fig.12 , in order to verify SATA functions, compare and analyze signal quality, and verify AURORA functions, the FMC_EYE_AURORA daughterboard is designed. Three groups of differential signals are derived from the FMC connector: SATA0, SATA1, and AURORA. SATA0 is connected to SATA_CONN0, which can connect to devices with standard SATA interfaces; SATA1's two groups of transceiver signals are connected to the SMA connector for eye diagram testing during comparative testing. Its wiring method is consistent with SATA0, which facilitates the comparison of communication quality and eye diagram test results; AURORA is connected to the SMA connector for interface interconnection testing with corresponding devices in application verification.

[0054] In a possible implementation, the FMC_PCIe daughter board includes a 4X PCIe connector PCIE-064-02-FD-TH, a PCIECARD_EDGE connector and a transfer cable; 8 groups of differential signals SD_TX / RX0~SD_TX / RX7 of the communication processor and 4 groups of differential signals SD_TX / RX0~SD_TX / RX3 and a pair of differential reference clocks are connected to the 4X PCIe connector PCIE-064-02-FD-TH through the FMC connector, and 4 groups of differential signals SD_TX / RX4~SD_TX / RX7 are connected to the PCIECARD_EDGE connector; the PCIe connector PCIE-064-02-FD-TH and the PCIECARD_EDGE connector are interconnected through the transfer cable.

[0055] For details, see Fig.13 , and complete the verification of different functional modes of PCIe by designing FMC_PCIe daughterboard. Lead out 8 groups of differential signals and a pair of differential reference clocks from the FMC connector, and connect SD_TX / RX0- SD_TX / RX3 and differential reference clock SD_REFCLKP / N to the 4X PCIe connector PCIE-064-02-FD-TH according to the configuration to verify the RC function of PCIe of 1X-4X, and connect SD_TX / RX4- SD_TX / RX7 to PCIECARD_EDGE to verify the EP function of PCIe, and the interconnection test of the two working modes can be completed through the adapter cable to complete the application verification of PCIe design function.

[0056] In a possible implementation manner, the Nand FLASH device of the IFC application verification module is a 1GB 8-BITNAND FLASH device MT29F8G08ABBCAH4:C, the Nor FLASH device is a 128MB 16-BIT NOR FLASH device JS28F00AM29EWHA, and the SRAM device is an SRAM device IS62WV51216BLL-55TLI.

[0057] For details, see Fig.14 According to the characteristics of IFC controller being compatible with memories of different timings, an IFC controller module application verification module was designed. According to the function of LT1022's IFC controller being compatible with different memory timings, 1GB 8-BIT NAND FLASH device MT29F8G08ABBCAH4:C, 128MB 16-BIT NOR FLASH device JS28F00AM29EWHA and SRAM device IS62WV51216BLL-55TLI were designed to complete the functional verification of memory compatibility with different timing requirements, and then led out to the connector to complete the application verification and application development of the remaining multiplexing functions.

[0058] The high-performance communication processor application verification system of the present invention can connect different types of high-speed DDR SDRAM to replace the design of the low-speed memory controller interface of the ordinary processor to connect the low-speed memory; a USB application verification module, an Ethernet application verification module and a high-speed serial communication interface application verification module with multiple functions are designed to replace the low-speed communication interface application verification module in the application verification of the ordinary processor or integrated circuit, thereby realizing the verification and performance test of the high-speed communication interface design function; Nand FLASH, Nor FLASH, SRAM and connector interfaces are designed respectively to replace the low-speed dedicated memory controller interface application verification module in the application verification of the ordinary processor or integrated circuit, thereby completing the application verification and application development of the IFC controller function compatible with multiple interface timings integrated by the high-performance communication processor.

[0059] In another embodiment of the present invention, a high-performance communication processor application verification method is provided, which can be implemented based on the above-mentioned high-performance communication processor application verification system, and includes the following steps: The DDR controller interface application verification module is used to verify the design function of the communication processor's 72-bit DDR controller interface that is compatible with DDR3 and DDR4; the USB application verification module is used to verify the design function of the communication processor's USB interface; the Ethernet application verification module is used to verify the three different working modes of the communication processor's Ethernet module design; the display control application verification module is used to verify the 24-bit display control module of the communication processor; the SDHC application verification module is used to verify the design function of the communication processor's high-speed memory controller interface; the IFC application verification module is used to verify the compatibility of the communication processor's IFC controller with different memory timings; the function verification module of the high-speed serial communication interface with function multiplexing is used to verify the high-speed interface of the communication processor with 8-channel function multiplexing.

[0060] According to the functional and performance requirements of LT1022 design, the high-performance communication processor application verification system and method of the present invention can be used to apply and develop all the functions integrated in LT1022, provide a development platform and application examples for potential users of LT1022, and lay the foundation for the wide application of LT1022. Through the application verification and development based on the high-performance communication processor LT1022, the proposed technical indicators and parameters are fully covered, and according to the needs of existing applications and subsequent updates and upgrades, a solid foundation is laid for the smooth application of LT1022.

[0061] The high-performance communication processor application verification system and method of the present invention can be applied in the application verification and development of high-performance dual-core communication processors. After the high-performance dual-core communication processor is packaged, the high-performance communication processor application verification system and method of the present invention can be used to complete its application verification and application development, and can also provide a reference for the application verification of processors with integrated high-speed memory interfaces and high-speed communication modules in other fields, laying a foundation for user application and development. Among them, the application verification design for the DDR interface of the high-performance communication processor can be directly applied to system integration; through the design of the USB and Ethernet application verification modules of the high-performance communication processor, design examples can be provided for system integration of different application scenarios. The designed LCD display control application verification module can be directly applied to the development of embedded systems while completing functional verification. The application verification module of the high-speed SerDes interface not only provides a design reference for the application verification and development of a variety of high-speed interfaces, but also provides ideas for the application verification of the multi-functional pin multiplexing of the high-speed module.

[0062] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0063] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0064] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0065] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A high-performance communication processor application verification system, characterized in that: It includes DDR controller interface application verification module, USB application verification module, Ethernet application verification module, display control application verification module, SDHC application verification module, IFC application verification module and function-reused high-speed serial communication interface application verification module; The DDR controller interface application verification module adopts a DIMM module connector; the USB application verification module includes 2 USB3.0 application verification circuits that are backward compatible with the USB2.0 working mode; the Ethernet application verification module includes 2 Ethernet application verification units, one for the GMII / MII compatible working mode and the other for the RGMII working mode; the display control application verification module includes a differential signal converter, a connector and a display control adapter connected in sequence; the SDHC application verification module includes a connector and an SD card, eSDHC memory card and eMMC device card connected to the connector; the IFC application verification module includes a NandFLASH device, a Nor FLASH device, a SRAM device and a connector, and the Nand FLASH device, Nor FLASH devices and SRAM devices are used to complete the functional verification of memory compatibility with different timing requirements and lead out to the connector; the functionally reused high-speed serial communication interface application verification module includes the high-speed connector FMC and the FMC_SGMII daughter board, FMC_QSGMII daughter board, FMC_SATA daughter board, FMC_EYE_AURORA daughter board and FMC_PCIe daughter board connected to the high-speed connector FMC; the FMC_SGMII daughter board is used for the application verification design of 8-way high-speed Ethernet and the application verification of the high-speed SerDes interface multiplexing into 8-way SGMII working mode; the FMC_QSGMII daughter board is used for the application verification of the QSGMII multiplexing function; the FMC_SATA daughter board is used for the application verification of 2 groups of SATA interfaces; the FMC_EYE_AURORA daughter board is used for eye diagram testing and interface interconnection testing with corresponding devices; the FMC_PCIe daughter board is used for the application verification of PCIe design functions.

2. The high performance communication processor application verification system according to claim 1, characterized in that: The DIMM module connector includes 5 DDR3 SDRAM and 5 DDR4 SDRAM memory cards, and is used for application verification of the design function of a 72-bits wide DDR controller interface being compatible with DDR3 and DDR4.

3. The high performance communication processor application verification system according to claim 1, characterized in that: The USB3.0 application verification circuit that is backward compatible with the USB2.0 working mode includes a USB3.0 Type-A Female connector, a PUSB3FR4 front-end protector, a differential reference crystal oscillator module, a SY6280AAC power module, and an ESD05V14T-LC ESD protection device; The PUSB3FR4 front-end protector is used to connect to the USB interface of the communication processor; The differential reference crystal oscillator module is used to provide a 100MHz differential reference clock for the USB interface of the communication processor; The SY6280AAC power module is used to enable the output of its power conversion through the communication processor USB interface and to supply power to the VBUS of the USB3.0 Type-A Female connector; The ESD05V14T-LC ESD protection device is used to connect to the USB interface of the communication processor.

4. The high performance communication processor application verification system according to claim 1, characterized in that: The 2-way Ethernet application verification unit includes an Ethernet controller 88E1111 designed in a GMII / MII compatible working mode, and an Ethernet controller DP83867IRPAP designed in a RGMII working mode.

5. The high performance communication processor application verification system according to claim 1, characterized in that: The connector of the display control application verification module adopts the connector DF14-20P- 1.25H, the connector and the display control adapter are connected through the connector QSH060-01-FDA, and the differential signal converter uses the differential signal converter DS90C387R to connect the LCD function pins of the communication processor.

6. The high performance communication processor application verification system according to claim 5, characterized in that: The display control application verification module also includes a signal extraction device; the signal extraction device is used to extract the signal of the communication processor that is not multiplexed with the LCD function pin and use it as a trigger signal.

7. The high performance communication processor application verification system according to claim 1, characterized in that: The Nand FLASH device of the IFC application verification module is a 1GB 8-BIT NAND FLASH device MT29F8G08ABBCAH4:C, the NorFLASH device is a 128MB 16-BIT NOR FLASH device JS28F00AM29EWHA, and the SRAM device is an SRAM device IS62WV51216BLL-55TLI.

8. The high performance communication processor application verification system according to claim 1, characterized in that: The FMC_SGMII daughter board includes a power module, a high-speed SerDes interface module, an Ethernet PHY chip 88E1145-1 and an Ethernet PHY chip 88E1145-2; the power module is connected to the power supply through the FMC connector and converted into the voltage required on the FMC_SGMII daughter board, and the high-speed SerDes interface module is configured as an 8-way SGMII working mode, of which 4 are connected to the Ethernet PHY chip 88E1145-1, and the other 4 are connected to the Ethernet PHY chip 88E1145-2, for realizing the application verification of 8-way high-speed Ethernet and the application verification of the function of multiplexing the high-speed SerDes interface into the SGMII working mode; The FMC_QSGMII daughter board includes a power module, a high-speed SerDes interface, two Ethernet switch chips F104S8A, an ICS843004-01 clock generator, eight H5008 network transformers and an RJ45_LED_8 indicator light module; the power supply and four pairs of high-speed differential signals are received through the FMC connector; the power module is used to convert the voltage, the high-speed SerDes interface is configured as a two-way QSGMII mode, which is respectively connected to the two Ethernet switch chips F104S8A, each Ethernet switch chip F104S8A extends four QSGMII ports, the ICS843004-01 clock generator generates two differential reference clocks, which are respectively supplied to the two Ethernet switch chips F104S8A, and the eight QSGMII ports are respectively connected to the RJ45_LED_8 indicator light module through eight H5008 network transformers for application verification of the QSGMII multiplexing function.

9. The high performance communication processor application verification system according to claim 1, characterized in that: The FMC_SATA daughter board includes a SATA interface connector SATA_CONN0, a SATA interface connector SATA_CONN1 and two SATA devices; two groups of differential signals of the communication processor are transmitted to the SATA interface connector SATA_CONN0 and the SATA interface connector SATA_CONN1 respectively through the FMC connector; the two SATA devices are connected to the SATA interface connector SATA_CONN0 and the SATA interface connector SATA_CONN1 respectively; The FMC_EYE_AURORA daughter board includes a SATA interface connector SATA_CONN0, a first SMA connector and a second SMA connector; the three groups of differential signals SATA0, SATA1 and AURORA of the communication processor are transmitted to the SATA interface connector SATA_CONN0, the first SMA connector and the second SMA connector respectively through the FMC connector, and the SATA interface connector SATA_CONN0 is used to connect a standard SATA interface device; the first SMA connector is used for eye diagram testing, and the SATA1 wiring is consistent with SATA0; the second SMA connector is used for interface interconnection testing with the corresponding device; The FMC_PCIe daughter board includes a 4X PCIe connector PCIE-064-02-FD-TH, a PCIECARD_EDGE connector and a transfer cable; 8 groups of differential signals SD_TX / RX0~SD_TX / RX7 of the communication processor and 4 groups of differential signals SD_TX / RX0~SD_TX / RX3 and a pair of differential reference clocks are connected to the 4X PCIe connector PCIE-064-02-FD-TH through the FMC connector, and 4 groups of differential signals SD_TX / RX4~SD_TX / RX7 are connected to the PCIECARD_EDGE connector; the PCIe connector PCIE-064-02-FD-TH and the PCIECARD_EDGE connector are interconnected through a transfer cable.

10. A high-performance communication processor application verification method based on the high-performance communication processor application verification system according to any one of claims 1 to 9, characterized in that: include: The DDR controller interface application verification module is used to verify the design function of the communication processor's 72-bit DDR controller interface that is compatible with DDR3 and DDR4. Use the USB application verification module to verify the application function of the USB interface of the communication processor; The Ethernet application verification module is used to verify the application of three different working modes of the communication processor Ethernet module design; The display control application verification module is used to verify the application of the communication processor 24-bit display control module; The SDHC application verification module is used to verify the design function of the communication processor high-speed memory controller interface; The IFC application verification module is used to verify the application of the communication processor IFC controller's compatibility with different memory timings; The application verification of the high-speed serial communication interface with 8 channels of functional multiplexing of the communication processor is carried out through the application verification module of the high-speed serial communication interface with functional multiplexing.

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